[PATCH 0/3] arm64: dts: qcom: eliza: Add ADSP and USB support

[PATCH 0/3] arm64: dts: qcom: eliza: Add ADSP and USB support

[Abel Vesa]

The following patchsets document all necessary bindings:

https://lore.kernel.org/all/20260327-eliza-bindings-mailbox-ipcc-v1-1-3f1c89bdf72e@oss.qualcomm.com/
https://lore.kernel.org/all/20260327-eliza-remoteproc-adsp-v1-1-1c46c5e5f809@oss.qualcomm.com/
https://lore.kernel.org/all/20260327-eliza-bindings-phy-eusb2-v1-1-1f8a9ad6a033@oss.qualcomm.com/
https://lore.kernel.org/all/20260318-eliza-bindings-qmp-phy-v1-1-96a0d529ad2d@oss.qualcomm.com/
https://lore.kernel.org/all/20260327-eliza-bindings-dwc3-v2-1-28439482ebce@oss.qualcomm.com/
https://lore.kernel.org/all/20260327-eliza-bindings-aoss-v1-1-70df76adc69b@oss.qualcomm.com/
https://lore.kernel.org/all/20260327-eliza-bindings-pmic-glink-v1-1-f9a65495f599@oss.qualcomm.com/

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (3):
      arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes
      arm64: dts: qcom: Add Eliza-specific PM7750BA dtsi
      arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support

 arch/arm64/boot/dts/qcom/eliza-mtp.dts       |  83 +++++++++
 arch/arm64/boot/dts/qcom/eliza.dtsi          | 261 +++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi |  69 +++++++
 3 files changed, 413 insertions(+)
---
base-commit: 5e59a51e3378f5d31e1f4f8efcb9763db3e322cf
change-id: 20260330-eliza-adsp-usb-8ef2b1b0fc13

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Abel Vesa]

Describe the ADSP remoteproc node along with its dependencies, including
the IPCC mailbox, AOSS QMP and SMP2P links used for communication.

The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
combo PHY and an SNPS eUSB2 PHY. Describe them.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/eliza.dtsi | 261 ++++++++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a7a0ac40ce6..37baa4b240d6 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -6,10 +6,13 @@
 #include <dt-bindings/clock/qcom,eliza-gcc.h>
 #include <dt-bindings/clock/qcom,eliza-tcsr.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,eliza-rpmh.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/power/qcom,rpmhpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -596,6 +599,30 @@ llcc_lpi_mem: llcc-lpi@ff800000 {
 		};
 	};
 
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 
@@ -624,6 +651,17 @@ gcc: clock-controller@100000 {
 			#power-domain-cells = <1>;
 		};
 
+		ipcc: mailbox@406000 {
+			compatible = "qcom,eliza-ipcc", "qcom,ipcc";
+			reg = <0x0 0x00406000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			#mbox-cells = <2>;
+		};
+
 		qupv3_2: geniqup@8c0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0x0 0x008c0000 0x0 0x2000>;
@@ -862,6 +900,55 @@ tcsr: clock-controller@1fbf000 {
 			#reset-cells = <1>;
 		};
 
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,eliza-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack",
+					  "shutdown-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+			};
+		};
+
 		lpass_ag_noc: interconnect@7e40000 {
 			compatible = "qcom,eliza-lpass-ag-noc";
 			reg = <0x0 0x07e40000 0x0 0xe080>;
@@ -883,6 +970,167 @@ lpass_lpicx_noc: interconnect@7420000 {
 			#interconnect-cells = <2>;
 		};
 
+		usb_hsphy: phy@88e3000 {
+			compatible = "qcom,eliza-snps-eusb2-phy",
+				     "qcom,sm8550-snps-eusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x154>;
+			#phy-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			status = "disabled";
+		};
+
+		usb_dp_qmpphy: phy@88e8000 {
+			compatible = "qcom,eliza-qmp-usb3-dp-phy",
+				     "qcom,sm8650-qmp-usb3-dp-phy";
+			reg = <0x0 0x088e8000 0x0 0x4000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&tcsr TCSR_USB3_CLKREF_EN>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "com_aux",
+				      "usb3_pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+			reset-names = "phy",
+				      "common";
+
+			power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+
+			orientation-switch;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dp_qmpphy_out: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dp_qmpphy_usb_ss_in: endpoint {
+						remote-endpoint = <&usb_dwc3_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_dp_qmpphy_dp_in: endpoint {
+					};
+				};
+			};
+		};
+
+		usb: usb@a600000 {
+			compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
+			reg = <0x0 0x0a600000 0x0 0xfc100>;
+
+			interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>,
+					       <200000000>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			phys = <&usb_hsphy>,
+			       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+			phy-names = "usb2-phy",
+				    "usb3-phy";
+
+			interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			iommus = <&apps_smmu 0x40 0x0>;
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,usb3_lpm_capable;
+			snps,usb2-lpm-disable;
+			snps,has-lpm-erratum;
+			tx-fifo-resize;
+
+			dma-coherent;
+			usb-role-switch;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dwc3_hs: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dwc3_ss: endpoint {
+						remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+					};
+				};
+			};
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,eliza-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x40000>,
@@ -957,6 +1205,19 @@ tsens2: thermal-sensor@c22a000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,eliza-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+
+			interrupt-parent = <&ipcc>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+						     IRQ_TYPE_EDGE_RISING>;
+
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			#clock-cells = <0>;
+		};
+
 		spmi: arbiter@c400000 {
 			compatible = "qcom,eliza-spmi-pmic-arb",
 				     "qcom,x1e80100-spmi-pmic-arb";

-- 
2.48.1

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Krzysztof Kozlowski]

On 31/03/2026 12:37, Abel Vesa wrote:
> Describe the ADSP remoteproc node along with its dependencies, including
> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> 
> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> combo PHY and an SNPS eUSB2 PHY. Describe them.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/eliza.dtsi | 261 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 261 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Konrad Dybcio]

On 3/31/26 12:37 PM, Abel Vesa wrote:
> Describe the ADSP remoteproc node along with its dependencies, including
> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> 
> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> combo PHY and an SNPS eUSB2 PHY. Describe them.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

[...]

> +		usb_hsphy: phy@88e3000 {
> +			compatible = "qcom,eliza-snps-eusb2-phy",
> +				     "qcom,sm8550-snps-eusb2-phy";
> +			reg = <0x0 0x088e3000 0x0 0x154>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;

This is TCSR_USB2_CLKREF_EN


> +		usb: usb@a600000 {
> +			compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";

Does the device suspend and resume successfully?

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Abel Vesa]

On 26-03-31 15:37:08, Konrad Dybcio wrote:
> On 3/31/26 12:37 PM, Abel Vesa wrote:
> > Describe the ADSP remoteproc node along with its dependencies, including
> > the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> > 
> > The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> > combo PHY and an SNPS eUSB2 PHY. Describe them.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> > +		usb_hsphy: phy@88e3000 {
> > +			compatible = "qcom,eliza-snps-eusb2-phy",
> > +				     "qcom,sm8550-snps-eusb2-phy";
> > +			reg = <0x0 0x088e3000 0x0 0x154>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> 
> This is TCSR_USB2_CLKREF_EN

Good point. Will fix.

> 
> 
> > +		usb: usb@a600000 {
> > +			compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> 
> Does the device suspend and resume successfully?

Well, tested with pm_test devices and it does suspend and resume
successfully, but there is this:

[   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2

But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
all platforms that have them.

Please correct me if I'm wrong.

Sorry for the late reply.

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Konrad Dybcio]

On 4/22/26 11:41 AM, Abel Vesa wrote:
> On 26-03-31 15:37:08, Konrad Dybcio wrote:
>> On 3/31/26 12:37 PM, Abel Vesa wrote:
>>> Describe the ADSP remoteproc node along with its dependencies, including
>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
>>>
>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +		usb_hsphy: phy@88e3000 {
>>> +			compatible = "qcom,eliza-snps-eusb2-phy",
>>> +				     "qcom,sm8550-snps-eusb2-phy";
>>> +			reg = <0x0 0x088e3000 0x0 0x154>;
>>> +			#phy-cells = <0>;
>>> +
>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
>>
>> This is TCSR_USB2_CLKREF_EN
> 
> Good point. Will fix.
> 
>>
>>
>>> +		usb: usb@a600000 {
>>> +			compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
>>
>> Does the device suspend and resume successfully?
> 
> Well, tested with pm_test devices and it does suspend and resume
> successfully, but there is this:
> 
> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> 
> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> all platforms that have them.

Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
some DWC quirk in the list, although it seems pretty long already. Perhaps
Wesley would know more.

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Abel Vesa]

On 26-04-22 12:09:31, Konrad Dybcio wrote:
> On 4/22/26 11:41 AM, Abel Vesa wrote:
> > On 26-03-31 15:37:08, Konrad Dybcio wrote:
> >> On 3/31/26 12:37 PM, Abel Vesa wrote:
> >>> Describe the ADSP remoteproc node along with its dependencies, including
> >>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> >>>
> >>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> >>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> >>>
> >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> +		usb_hsphy: phy@88e3000 {
> >>> +			compatible = "qcom,eliza-snps-eusb2-phy",
> >>> +				     "qcom,sm8550-snps-eusb2-phy";
> >>> +			reg = <0x0 0x088e3000 0x0 0x154>;
> >>> +			#phy-cells = <0>;
> >>> +
> >>> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> >>
> >> This is TCSR_USB2_CLKREF_EN
> > 
> > Good point. Will fix.
> > 
> >>
> >>
> >>> +		usb: usb@a600000 {
> >>> +			compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> >>
> >> Does the device suspend and resume successfully?
> > 
> > Well, tested with pm_test devices and it does suspend and resume
> > successfully, but there is this:
> > 
> > [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> > 
> > But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> > all platforms that have them.
> 
> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> some DWC quirk in the list, although it seems pretty long already. Perhaps
> Wesley would know more.

+ Wesley

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Krishna Kurapati PSSNV]

On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>
> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> > On 4/22/26 11:41 AM, Abel Vesa wrote:
> > > On 26-03-31 15:37:08, Konrad Dybcio wrote:
> > >> On 3/31/26 12:37 PM, Abel Vesa wrote:
> > >>> Describe the ADSP remoteproc node along with its dependencies, including
> > >>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> > >>>
> > >>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> > >>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> > >>>
> > >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > >>> ---
> > >>
> > >> [...]
> > >>
> > >>> +         usb_hsphy: phy@88e3000 {
> > >>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
> > >>> +                              "qcom,sm8550-snps-eusb2-phy";
> > >>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
> > >>> +                 #phy-cells = <0>;
> > >>> +
> > >>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
> > >>
> > >> This is TCSR_USB2_CLKREF_EN
> > >
> > > Good point. Will fix.
> > >
> > >>
> > >>
> > >>> +         usb: usb@a600000 {
> > >>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> > >>
> > >> Does the device suspend and resume successfully?
> > >
> > > Well, tested with pm_test devices and it does suspend and resume
> > > successfully, but there is this:
> > >
> > > [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> > >
> > > But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> > > all platforms that have them.
> >
> > Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> > some DWC quirk in the list, although it seems pretty long already. Perhaps
> > Wesley would know more.
>
> + Wesley
>

As per HPG and downstream, this is what needs to be done while entering suspend:

1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
3. Set the following bits in the pwr_evnt_irq_stat_reg:
 a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
4. Wait for 3ms for PWR_EVNT_LPM_IN_L2_MASK to be set
5. If it is not set, then we can print the error
6. If its set, then we need to clear the bits.

Regards,
Krishna,

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Konrad Dybcio]

On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>>
>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
>>>>>>
>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
>>>>>>
>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>>>> ---
>>>>>
>>>>> [...]
>>>>>
>>>>>> +         usb_hsphy: phy@88e3000 {
>>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
>>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
>>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
>>>>>> +                 #phy-cells = <0>;
>>>>>> +
>>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
>>>>>
>>>>> This is TCSR_USB2_CLKREF_EN
>>>>
>>>> Good point. Will fix.
>>>>
>>>>>
>>>>>
>>>>>> +         usb: usb@a600000 {
>>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
>>>>>
>>>>> Does the device suspend and resume successfully?
>>>>
>>>> Well, tested with pm_test devices and it does suspend and resume
>>>> successfully, but there is this:
>>>>
>>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
>>>>
>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
>>>> all platforms that have them.
>>>
>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
>>> Wesley would know more.
>>
>> + Wesley
>>
> 
> As per HPG and downstream, this is what needs to be done while entering suspend:
> 
> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
>  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY

In case that's related, most platforms (including this one), set
snps,dis_enblslpm_quirk which prevents the first bit from being set

Likewise, snps,dis_u2_susphy_quirk for the second one

(although it looks like setting these bits is currently
unconditional upon suspend in HOST mode?)


As for the sequence you mentioned, I believe the diff below should be
OK - although it _really_ just adds some delay vs the current state,
since the bits are cleared in the resume call

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index f43f73ac36ff..e7b1775b7207 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/interconnect.h>
+#include <linux/iopoll.h>
 #include <linux/platform_device.h>
 #include <linux/phy/phy.h>
 #include <linux/usb/of.h>
@@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
                return 0;
 
        for (i = 0; i < qcom->num_ports; i++) {
-               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
-               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+               /* Wait for the PHYs to go into L2 */
+               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
+                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
+                                        10, 3 * USEC_PER_MSEC);
+
+               if (ret == -ETIMEDOUT)
                        dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
        }
+
+       /* Clear L2 event bit */
+       writel(PWR_EVNT_LPM_IN_L2_MASK, qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
+
        clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
 
        ret = dwc3_qcom_interconnect_disable(qcom);
@@ -752,6 +761,13 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
        bool wakeup = device_may_wakeup(dev);
        int ret;
 
+       /* Clear previous L2 events */
+       for (int i = 0; i < qcom->num_ports; i++) {
+               writel(PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK,
+                      qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
+       }
+
        ret = dwc3_pm_suspend(&qcom->dwc);
        if (ret)
                return ret;


Konrad

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Krishna Kurapati PSSNV]

On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
> > On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
> >>
> >> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> >>> On 4/22/26 11:41 AM, Abel Vesa wrote:
> >>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
> >>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
> >>>>>> Describe the ADSP remoteproc node along with its dependencies, including
> >>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> >>>>>>
> >>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> >>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> >>>>>>
> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>>>>> ---
> >>>>>
> >>>>> [...]
> >>>>>
> >>>>>> +         usb_hsphy: phy@88e3000 {
> >>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
> >>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
> >>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
> >>>>>> +                 #phy-cells = <0>;
> >>>>>> +
> >>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
> >>>>>
> >>>>> This is TCSR_USB2_CLKREF_EN
> >>>>
> >>>> Good point. Will fix.
> >>>>
> >>>>>
> >>>>>
> >>>>>> +         usb: usb@a600000 {
> >>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> >>>>>
> >>>>> Does the device suspend and resume successfully?
> >>>>
> >>>> Well, tested with pm_test devices and it does suspend and resume
> >>>> successfully, but there is this:
> >>>>
> >>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> >>>>
> >>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> >>>> all platforms that have them.
> >>>
> >>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> >>> some DWC quirk in the list, although it seems pretty long already. Perhaps
> >>> Wesley would know more.
> >>
> >> + Wesley
> >>
> >
> > As per HPG and downstream, this is what needs to be done while entering suspend:
> >
> > 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
> > 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
> > 3. Set the following bits in the pwr_evnt_irq_stat_reg:
> >  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
>
> In case that's related, most platforms (including this one), set
> snps,dis_enblslpm_quirk which prevents the first bit from being set
>
> Likewise, snps,dis_u2_susphy_quirk for the second one
>
> (although it looks like setting these bits is currently
> unconditional upon suspend in HOST mode?)
>
>
> As for the sequence you mentioned, I believe the diff below should be
> OK - although it _really_ just adds some delay vs the current state,
> since the bits are cleared in the resume call
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index f43f73ac36ff..e7b1775b7207 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -12,6 +12,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/interconnect.h>
> +#include <linux/iopoll.h>
>  #include <linux/platform_device.h>
>  #include <linux/phy/phy.h>
>  #include <linux/usb/of.h>
> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>                 return 0;
>
>         for (i = 0; i < qcom->num_ports; i++) {
> -               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> -               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> +               /* Wait for the PHYs to go into L2 */
> +               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
> +                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
> +                                        10, 3 * USEC_PER_MSEC);
> +
> +               if (ret == -ETIMEDOUT)
>                         dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
>         }
> +


I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
for the irq_stat register.

Regards,
Krishna,

> +       /* Clear L2 event bit */
> +       writel(PWR_EVNT_LPM_IN_L2_MASK, qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> +
>         clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>
>         ret = dwc3_qcom_interconnect_disable(qcom);
> @@ -752,6 +761,13 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
>         bool wakeup = device_may_wakeup(dev);
>         int ret;
>
> +       /* Clear previous L2 events */
> +       for (int i = 0; i < qcom->num_ports; i++) {
> +               writel(PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK,
> +                      qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> +       }
> +
>         ret = dwc3_pm_suspend(&qcom->dwc);
>         if (ret)
>                 return ret;
>
>

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Konrad Dybcio]

On 4/29/26 3:57 AM, Krishna Kurapati PSSNV wrote:
> On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
>>> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>>>>
>>>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
>>>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
>>>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
>>>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
>>>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
>>>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
>>>>>>>>
>>>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
>>>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
>>>>>>>>
>>>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>>>>>> ---
>>>>>>>
>>>>>>> [...]
>>>>>>>
>>>>>>>> +         usb_hsphy: phy@88e3000 {
>>>>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
>>>>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
>>>>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
>>>>>>>> +                 #phy-cells = <0>;
>>>>>>>> +
>>>>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
>>>>>>>
>>>>>>> This is TCSR_USB2_CLKREF_EN
>>>>>>
>>>>>> Good point. Will fix.
>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> +         usb: usb@a600000 {
>>>>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
>>>>>>>
>>>>>>> Does the device suspend and resume successfully?
>>>>>>
>>>>>> Well, tested with pm_test devices and it does suspend and resume
>>>>>> successfully, but there is this:
>>>>>>
>>>>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
>>>>>>
>>>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
>>>>>> all platforms that have them.
>>>>>
>>>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
>>>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
>>>>> Wesley would know more.
>>>>
>>>> + Wesley
>>>>
>>>
>>> As per HPG and downstream, this is what needs to be done while entering suspend:
>>>
>>> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
>>> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
>>> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
>>>  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
>>
>> In case that's related, most platforms (including this one), set
>> snps,dis_enblslpm_quirk which prevents the first bit from being set
>>
>> Likewise, snps,dis_u2_susphy_quirk for the second one
>>
>> (although it looks like setting these bits is currently
>> unconditional upon suspend in HOST mode?)
>>
>>
>> As for the sequence you mentioned, I believe the diff below should be
>> OK - although it _really_ just adds some delay vs the current state,
>> since the bits are cleared in the resume call
>>
>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
>> index f43f73ac36ff..e7b1775b7207 100644
>> --- a/drivers/usb/dwc3/dwc3-qcom.c
>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
>> @@ -12,6 +12,7 @@
>>  #include <linux/module.h>
>>  #include <linux/kernel.h>
>>  #include <linux/interconnect.h>
>> +#include <linux/iopoll.h>
>>  #include <linux/platform_device.h>
>>  #include <linux/phy/phy.h>
>>  #include <linux/usb/of.h>
>> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>>                 return 0;
>>
>>         for (i = 0; i < qcom->num_ports; i++) {
>> -               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
>> -               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
>> +               /* Wait for the PHYs to go into L2 */
>> +               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
>> +                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
>> +                                        10, 3 * USEC_PER_MSEC);
>> +
>> +               if (ret == -ETIMEDOUT)
>>                         dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
>>         }
>> +
> 
> 
> I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
> DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
> for the irq_stat register.

Hm, it seems like the dwc3 core layer only does so in the suspend
path if dr_mode = "host"?

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Abel Vesa]

On 26-04-29 11:45:10, Konrad Dybcio wrote:
> On 4/29/26 3:57 AM, Krishna Kurapati PSSNV wrote:
> > On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >>
> >> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
> >>> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
> >>>>
> >>>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> >>>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
> >>>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
> >>>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
> >>>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
> >>>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> >>>>>>>>
> >>>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> >>>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>>>>>>> ---
> >>>>>>>
> >>>>>>> [...]
> >>>>>>>
> >>>>>>>> +         usb_hsphy: phy@88e3000 {
> >>>>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
> >>>>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
> >>>>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
> >>>>>>>> +                 #phy-cells = <0>;
> >>>>>>>> +
> >>>>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
> >>>>>>>
> >>>>>>> This is TCSR_USB2_CLKREF_EN
> >>>>>>
> >>>>>> Good point. Will fix.
> >>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>>> +         usb: usb@a600000 {
> >>>>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> >>>>>>>
> >>>>>>> Does the device suspend and resume successfully?
> >>>>>>
> >>>>>> Well, tested with pm_test devices and it does suspend and resume
> >>>>>> successfully, but there is this:
> >>>>>>
> >>>>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> >>>>>>
> >>>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> >>>>>> all platforms that have them.
> >>>>>
> >>>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> >>>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
> >>>>> Wesley would know more.
> >>>>
> >>>> + Wesley
> >>>>
> >>>
> >>> As per HPG and downstream, this is what needs to be done while entering suspend:
> >>>
> >>> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
> >>>  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
> >>
> >> In case that's related, most platforms (including this one), set
> >> snps,dis_enblslpm_quirk which prevents the first bit from being set
> >>
> >> Likewise, snps,dis_u2_susphy_quirk for the second one
> >>
> >> (although it looks like setting these bits is currently
> >> unconditional upon suspend in HOST mode?)
> >>
> >>
> >> As for the sequence you mentioned, I believe the diff below should be
> >> OK - although it _really_ just adds some delay vs the current state,
> >> since the bits are cleared in the resume call
> >>
> >> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> >> index f43f73ac36ff..e7b1775b7207 100644
> >> --- a/drivers/usb/dwc3/dwc3-qcom.c
> >> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> >> @@ -12,6 +12,7 @@
> >>  #include <linux/module.h>
> >>  #include <linux/kernel.h>
> >>  #include <linux/interconnect.h>
> >> +#include <linux/iopoll.h>
> >>  #include <linux/platform_device.h>
> >>  #include <linux/phy/phy.h>
> >>  #include <linux/usb/of.h>
> >> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >>                 return 0;
> >>
> >>         for (i = 0; i < qcom->num_ports; i++) {
> >> -               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> >> -               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> >> +               /* Wait for the PHYs to go into L2 */
> >> +               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
> >> +                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
> >> +                                        10, 3 * USEC_PER_MSEC);
> >> +
> >> +               if (ret == -ETIMEDOUT)
> >>                         dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
> >>         }
> >> +
> > 
> > 
> > I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
> > DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
> > for the irq_stat register.
> 
> Hm, it seems like the dwc3 core layer only does so in the suspend
> path if dr_mode = "host"?

OK, so I guess the quirk list is complete then, right ?

Lets unblock this.

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Konrad Dybcio]

On 5/4/26 12:06 PM, Abel Vesa wrote:
> On 26-04-29 11:45:10, Konrad Dybcio wrote:
>> On 4/29/26 3:57 AM, Krishna Kurapati PSSNV wrote:
>>> On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
>>> <konrad.dybcio@oss.qualcomm.com> wrote:
>>>>
>>>> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
>>>>> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>>>>>>
>>>>>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
>>>>>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
>>>>>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
>>>>>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
>>>>>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
>>>>>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
>>>>>>>>>>
>>>>>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
>>>>>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>>>>>>>> ---
>>>>>>>>>
>>>>>>>>> [...]
>>>>>>>>>
>>>>>>>>>> +         usb_hsphy: phy@88e3000 {
>>>>>>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
>>>>>>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
>>>>>>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
>>>>>>>>>> +                 #phy-cells = <0>;
>>>>>>>>>> +
>>>>>>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
>>>>>>>>>
>>>>>>>>> This is TCSR_USB2_CLKREF_EN
>>>>>>>>
>>>>>>>> Good point. Will fix.
>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>> +         usb: usb@a600000 {
>>>>>>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
>>>>>>>>>
>>>>>>>>> Does the device suspend and resume successfully?
>>>>>>>>
>>>>>>>> Well, tested with pm_test devices and it does suspend and resume
>>>>>>>> successfully, but there is this:
>>>>>>>>
>>>>>>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
>>>>>>>>
>>>>>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
>>>>>>>> all platforms that have them.
>>>>>>>
>>>>>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
>>>>>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
>>>>>>> Wesley would know more.
>>>>>>
>>>>>> + Wesley
>>>>>>
>>>>>
>>>>> As per HPG and downstream, this is what needs to be done while entering suspend:
>>>>>
>>>>> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
>>>>> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
>>>>> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
>>>>>  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
>>>>
>>>> In case that's related, most platforms (including this one), set
>>>> snps,dis_enblslpm_quirk which prevents the first bit from being set
>>>>
>>>> Likewise, snps,dis_u2_susphy_quirk for the second one
>>>>
>>>> (although it looks like setting these bits is currently
>>>> unconditional upon suspend in HOST mode?)
>>>>
>>>>
>>>> As for the sequence you mentioned, I believe the diff below should be
>>>> OK - although it _really_ just adds some delay vs the current state,
>>>> since the bits are cleared in the resume call
>>>>
>>>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
>>>> index f43f73ac36ff..e7b1775b7207 100644
>>>> --- a/drivers/usb/dwc3/dwc3-qcom.c
>>>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
>>>> @@ -12,6 +12,7 @@
>>>>  #include <linux/module.h>
>>>>  #include <linux/kernel.h>
>>>>  #include <linux/interconnect.h>
>>>> +#include <linux/iopoll.h>
>>>>  #include <linux/platform_device.h>
>>>>  #include <linux/phy/phy.h>
>>>>  #include <linux/usb/of.h>
>>>> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>>>>                 return 0;
>>>>
>>>>         for (i = 0; i < qcom->num_ports; i++) {
>>>> -               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
>>>> -               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
>>>> +               /* Wait for the PHYs to go into L2 */
>>>> +               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
>>>> +                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
>>>> +                                        10, 3 * USEC_PER_MSEC);
>>>> +
>>>> +               if (ret == -ETIMEDOUT)
>>>>                         dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
>>>>         }
>>>> +
>>>
>>>
>>> I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
>>> DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
>>> for the irq_stat register.
>>
>> Hm, it seems like the dwc3 core layer only does so in the suspend
>> path if dr_mode = "host"?
> 
> OK, so I guess the quirk list is complete then, right ?

Yeah, seems that way

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

[Abel Vesa]

On 26-05-04 12:25:36, Konrad Dybcio wrote:
> On 5/4/26 12:06 PM, Abel Vesa wrote:
> > On 26-04-29 11:45:10, Konrad Dybcio wrote:
> >> On 4/29/26 3:57 AM, Krishna Kurapati PSSNV wrote:
> >>> On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
> >>> <konrad.dybcio@oss.qualcomm.com> wrote:
> >>>>
> >>>> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
> >>>>> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
> >>>>>>
> >>>>>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> >>>>>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
> >>>>>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
> >>>>>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
> >>>>>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
> >>>>>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> >>>>>>>>>>
> >>>>>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> >>>>>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> >>>>>>>>>>
> >>>>>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>>>>>>>>> ---
> >>>>>>>>>
> >>>>>>>>> [...]
> >>>>>>>>>
> >>>>>>>>>> +         usb_hsphy: phy@88e3000 {
> >>>>>>>>>> +                 compatible = "qcom,eliza-snps-eusb2-phy",
> >>>>>>>>>> +                              "qcom,sm8550-snps-eusb2-phy";
> >>>>>>>>>> +                 reg = <0x0 0x088e3000 0x0 0x154>;
> >>>>>>>>>> +                 #phy-cells = <0>;
> >>>>>>>>>> +
> >>>>>>>>>> +                 clocks = <&rpmhcc RPMH_CXO_CLK>;
> >>>>>>>>>
> >>>>>>>>> This is TCSR_USB2_CLKREF_EN
> >>>>>>>>
> >>>>>>>> Good point. Will fix.
> >>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>> +         usb: usb@a600000 {
> >>>>>>>>>> +                 compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> >>>>>>>>>
> >>>>>>>>> Does the device suspend and resume successfully?
> >>>>>>>>
> >>>>>>>> Well, tested with pm_test devices and it does suspend and resume
> >>>>>>>> successfully, but there is this:
> >>>>>>>>
> >>>>>>>> [   54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> >>>>>>>>
> >>>>>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> >>>>>>>> all platforms that have them.
> >>>>>>>
> >>>>>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> >>>>>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
> >>>>>>> Wesley would know more.
> >>>>>>
> >>>>>> + Wesley
> >>>>>>
> >>>>>
> >>>>> As per HPG and downstream, this is what needs to be done while entering suspend:
> >>>>>
> >>>>> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>>>> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>>>> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
> >>>>>  a)  DWC3_GUSB2PHYCFG_ENBLSLPM  and  DWC3_GUSB2PHYCFG_SUSPHY
> >>>>
> >>>> In case that's related, most platforms (including this one), set
> >>>> snps,dis_enblslpm_quirk which prevents the first bit from being set
> >>>>
> >>>> Likewise, snps,dis_u2_susphy_quirk for the second one
> >>>>
> >>>> (although it looks like setting these bits is currently
> >>>> unconditional upon suspend in HOST mode?)
> >>>>
> >>>>
> >>>> As for the sequence you mentioned, I believe the diff below should be
> >>>> OK - although it _really_ just adds some delay vs the current state,
> >>>> since the bits are cleared in the resume call
> >>>>
> >>>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> >>>> index f43f73ac36ff..e7b1775b7207 100644
> >>>> --- a/drivers/usb/dwc3/dwc3-qcom.c
> >>>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> >>>> @@ -12,6 +12,7 @@
> >>>>  #include <linux/module.h>
> >>>>  #include <linux/kernel.h>
> >>>>  #include <linux/interconnect.h>
> >>>> +#include <linux/iopoll.h>
> >>>>  #include <linux/platform_device.h>
> >>>>  #include <linux/phy/phy.h>
> >>>>  #include <linux/usb/of.h>
> >>>> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >>>>                 return 0;
> >>>>
> >>>>         for (i = 0; i < qcom->num_ports; i++) {
> >>>> -               val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> >>>> -               if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> >>>> +               /* Wait for the PHYs to go into L2 */
> >>>> +               ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
> >>>> +                                        val, val & PWR_EVNT_LPM_IN_L2_MASK,
> >>>> +                                        10, 3 * USEC_PER_MSEC);
> >>>> +
> >>>> +               if (ret == -ETIMEDOUT)
> >>>>                         dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
> >>>>         }
> >>>> +
> >>>
> >>>
> >>> I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
> >>> DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
> >>> for the irq_stat register.
> >>
> >> Hm, it seems like the dwc3 core layer only does so in the suspend
> >> path if dr_mode = "host"?
> > 
> > OK, so I guess the quirk list is complete then, right ?
> 
> Yeah, seems that way

Ok, will respin with your other comment addressed.

Thanks.

[PATCH 2/3] arm64: dts: qcom: Add Eliza-specific PM7750BA dtsi

[Abel Vesa]

On Eliza, the SPMI arbiter supports multiple bus masters, requiring
explicit selection of the master for each PMIC.

The existing PM7750BA dtsi does not provide a way to describe this,
so introduce an Eliza-specific variant with the appropriate bus
configuration.

This duplication is required due to hardware differences in how the
SPMI bus is exposed on this platform.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi | 69 ++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi
new file mode 100644
index 000000000000..2c386f16eca4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm7550ba-eliza.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pm7550ba-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm7550ba_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus0 {
+	pm7550ba: pmic@7 {
+		compatible = "qcom,pm7550ba", "qcom,spmi-pmic";
+		reg = <7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm7550ba_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm7550ba_gpios: gpio@8800 {
+			compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm7550ba_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm7550ba_eusb2_repeater: phy@fd00 {
+			compatible = "qcom,pm7550ba-eusb2-repeater", "qcom,pm8550b-eusb2-repeater";
+			reg = <0xfd00>;
+			#phy-cells = <0>;
+		};
+	};
+};

-- 
2.48.1

[PATCH 3/3] arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support

[Abel Vesa]

The Eliza MTP features a single USB Type-C port. Its USB 2.0 lines are
routed through an eUSB2 repeater provided by the PM7750BA PMIC.

Describe the port and repeater, and enable the USB controller and PHYs.

Also specify the ADSP firmware and enable the remoteproc.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/eliza-mtp.dts | 83 ++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index 90f629800cb0..c31f00e36eee 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -6,9 +6,12 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "eliza.dtsi"
 
+#include "pm7550ba-eliza.dtsi"
+
 / {
 	model = "Qualcomm Technologies, Inc. Eliza MTP";
 	compatible = "qcom,eliza-mtp", "qcom,eliza";
@@ -54,6 +57,44 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
 		};
 	};
 
+	pmic-glink {
+		compatible = "qcom,eliza-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>;
+
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&usb_dp_qmpphy_out>;
+					};
+				};
+			};
+		};
+	};
+
 	vph_pwr: regulator-vph-pwr {
 		compatible = "regulator-fixed";
 
@@ -376,6 +417,18 @@ vreg_l7k: ldo7 {
 	};
 };
 
+&pm7550ba_eusb2_repeater {
+	vdd18-supply = <&vreg_l7b>;
+	vdd3-supply = <&vreg_l17b>;
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/eliza/adsp.mbn",
+			"qcom/eliza/adsp_dtb.mbn";
+
+	status = "okay";
+};
+
 &tlmm {
 	gpio-reserved-ranges = <20 4>,   /* NFC SPI */
 			       <111 2>,  /* WCN UART1 */
@@ -405,3 +458,33 @@ &ufs_mem_phy {
 
 	status = "okay";
 };
+
+&usb {
+	dr_mode = "otg";
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3g>;
+	vdda-pll-supply = <&vreg_l7k>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_hsphy {
+	vdd-supply = <&vreg_l2b>;
+	vdda12-supply = <&vreg_l4b>;
+
+	phys = <&pm7550ba_eusb2_repeater>;
+
+	status = "okay";
+};

-- 
2.48.1

Re: [PATCH 3/3] arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support

[Konrad Dybcio]

On 3/31/26 12:37 PM, Abel Vesa wrote:
> The Eliza MTP features a single USB Type-C port. Its USB 2.0 lines are
> routed through an eUSB2 repeater provided by the PM7750BA PMIC.
> 
> Describe the port and repeater, and enable the USB controller and PHYs.
> 
> Also specify the ADSP firmware and enable the remoteproc.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

[...]

> +&usb {
> +	dr_mode = "otg";

That's the default if dr_mode is absent, drop 

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/3] arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support

[Krzysztof Kozlowski]

On 31/03/2026 12:37, Abel Vesa wrote:
> The Eliza MTP features a single USB Type-C port. Its USB 2.0 lines are
> routed through an eUSB2 repeater provided by the PM7750BA PMIC.
> 
> Describe the port and repeater, and enable the USB controller and PHYs.
> 
> Also specify the ADSP firmware and enable the remoteproc.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/eliza-mtp.dts | 83 ++++++++++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)
> 

With fix as pointed out by Konrad:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof