From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width
Date: Thu, 10 Sep 2026 13:40:15 +0530 [thread overview]
Message-ID: <3dbb0310-c2d3-4b81-9197-8c275242eb47@oss.qualcomm.com> (raw)
In-Reply-To: <aqEbvx0Q8X33XE-O@QCOM-aGQu4IUr3Y>
On 9/9/2026 2:11 PM, Shawn Guo wrote:
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index 60173b076cc5f16bb55343a1d1136eb07f3c050f..981f973da02f379832fdc0cded3f2b4cae5879e4 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -382,8 +382,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>> #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
>>
>> #define pll_alpha_width(p) \
>> - ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
>> - ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
>> + ((p)->alpha_width ? (p)->alpha_width : \
>> + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
>> + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH))
> The inner ternary kept its original indentation, so the two continuation
> lines are now misaligned relative to the new outer ternary. Worth
> re-wrapping.
>
I will re-wrap.
>>
>> #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
>>
>> @@ -2290,7 +2291,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>> if (ret < 0)
>> return ret;
>>
>> - if (a & PLL_ALPHA_MSB)
> PLL_ALPHA_MSB becomes dead code then.
>
Yes, I can remove the macro.
--
Thanks,
Taniya Das
next prev parent reply other threads:[~2026-09-10 8:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 8:26 [PATCH 0/3] clk: qcom: Add Nord DPRX clock controller support Taniya Das
2026-09-07 8:26 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Taniya Das
2026-09-07 8:38 ` sashiko-bot
2026-09-07 10:30 ` Abel Vesa
2026-09-09 8:41 ` Shawn Guo
2026-09-10 8:10 ` Taniya Das [this message]
2026-09-07 8:26 ` [PATCH 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Taniya Das
2026-09-07 8:35 ` sashiko-bot
2026-09-07 10:38 ` Abel Vesa
2026-09-09 8:31 ` Shawn Guo
2026-09-10 8:55 ` Taniya Das
2026-09-07 8:26 ` [PATCH 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support Taniya Das
2026-09-07 8:55 ` sashiko-bot
2026-09-07 10:43 ` Abel Vesa
2026-09-09 9:06 ` Shawn Guo
2026-09-10 9:08 ` Taniya Das
2026-09-09 8:34 ` [PATCH 0/3] clk: qcom: " Shawn Guo
2026-09-10 8:14 ` Taniya Das
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