Re: [PATCH 0/3] clk: qcom: Add Nord DPRX clock controller support

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Mon, Sep 07, 2026 at 01:56:12PM +0530, Taniya Das wrote:
> Add support for the DisplayPort Receiver (DPRX) clock controllers found
> on Qualcomm Nord devices. There are two identical DPRX clock controller
> instances (DPRX0 and DPRX1), each providing clocks for the DPRX core,
> audio, AHB and video memory paths, along with their core PLLs.
> 
> The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has
> been widened to 28 bits to carry the fractional word at a finer
> resolution. The existing alpha-PLL core derives the ALPHA_VAL width
> solely from the register-map layout and can only express 16 or 40 bits,
> so the first patch adds an optional per-PLL alpha_width override that,
> when set, feeds the recalc_rate/round_rate scaling and the Zonda
> set_rate L-adjust MSB check. This is a prerequisite for the DPRX PLLs to
> lock to and report the correct rate.
> 
> The series is organised as follows:
> 
>   - Patch 1 - alpha-PLL 28-bit ALPHA_VAL width.
>   - Patch 2 - documents the Nord DPRX clock controller device tree
>     bindings.
>   - Patch 3 - adds the two DPRX clock controller drivers.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
> Taniya Das (3):
>       clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width
>       dt-bindings: clock: qcom: document the Nord DPRX Clock Controller
>       clk: qcom: dprxcc: Add Nord DPRX clock controller support

Hi Taniya,

May I ask to be copied on all Nord patches? Thanks!

Shawn