From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support
Date: Thu, 10 Sep 2026 14:38:46 +0530 [thread overview]
Message-ID: <c0b0ff51-e514-4483-aa37-a313755851c1@oss.qualcomm.com> (raw)
In-Reply-To: <aqEheWi6OaJtJfDu@QCOM-aGQu4IUr3Y>
On 9/9/2026 2:36 PM, Shawn Guo wrote:
>> --- /dev/null
>> +++ b/drivers/clk/qcom/dprxcc0-nord.c
>> @@ -0,0 +1,436 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
> This include can be dropped.
>
Okay.
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,nord-dprxcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-pll.h"
> This include doesn't seem to be needed.
>
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
> Ditto
>
Actually our generators are common across clock controllers, so they add
all get added as our templates. I will remove for now.
>> +#include "common.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + DT_BI_TCXO,
>> + DT_AHB_CLK,
> The binding requires the DPRX CFG AHB clock in clocks.
>
> - description: DPRX CFG AHB clock from NWGCC
This change ensures that NWGCC is probed before DPRX, allowing the
critical NW_GCC_DPRX0/1_CFG_AHB_CLK clocks to remain enabled during the
DPRX probe.
>
> But nothing in the driver references index 1 — not in any parent_data,
> not via devm_clk_get_enabled().
--
Thanks,
Taniya Das
next prev parent reply other threads:[~2026-09-10 9:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 8:26 [PATCH 0/3] clk: qcom: Add Nord DPRX clock controller support Taniya Das
2026-09-07 8:26 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Taniya Das
2026-09-07 8:38 ` sashiko-bot
2026-09-07 10:30 ` Abel Vesa
2026-09-09 8:41 ` Shawn Guo
2026-09-10 8:10 ` Taniya Das
2026-09-07 8:26 ` [PATCH 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Taniya Das
2026-09-07 8:35 ` sashiko-bot
2026-09-07 10:38 ` Abel Vesa
2026-09-09 8:31 ` Shawn Guo
2026-09-10 8:55 ` Taniya Das
2026-09-07 8:26 ` [PATCH 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support Taniya Das
2026-09-07 8:55 ` sashiko-bot
2026-09-07 10:43 ` Abel Vesa
2026-09-09 9:06 ` Shawn Guo
2026-09-10 9:08 ` Taniya Das [this message]
2026-09-09 8:34 ` [PATCH 0/3] clk: qcom: " Shawn Guo
2026-09-10 8:14 ` Taniya Das
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