Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The DisplayPort controller (`dp`) is not enabled and not routed to the VOP2, breaking the advertised Type-C DP alt-mode.
- [Medium] The `sai6` CPU DAI node is not enabled, which prevents the HDMI sound card from probing.
--

--- Patch [2]: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO ---
commit 6aa295a8cc84993de39b6dae02d2c7333d9385bb
Author: Jiaxing Hu <gahing@gahingwoo.com>

arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO
    
This commit adds device tree files for the ArmSoM CM5, an RK3576 compute
module, and its CM5-IO carrier board. It configures peripherals such as
the RK806 PMIC, GMAC0, eMMC, HDMI, USB, and an M.2 PCIe slot.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
[ ... ]
> @@ -174,6 +174,10 @@ hdmi_out_con: endpoint {
>  	};
>  };
>  
> +&hdmi_sound {
> +	status = "okay";
> +};

[Severity: Medium]
Will the HDMI sound card fail to probe without the sai6 CPU DAI enabled?

Since hdmi_sound relies on sai6 as its CPU endpoint (defined in the base
SoC dtsi), leaving &sai6 disabled in this board file might prevent ALSA
from registering the sound card, resulting in broken HDMI audio.

> +
>  &hdptxphy {
>  	status = "okay";
>  };
[ ... ]
> @@ -317,6 +321,21 @@ &usb_drd1_dwc3 {
>  	status = "okay";
>  };
>  
> +&usbdp_phy {
> +	status = "okay";
> +	mode-switch;
> +	orientation-switch;
> +	sbu1-dc-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
> +	sbu2-dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;

[Severity: Medium]
Does the DisplayPort controller also need to be enabled for DP alt-mode to
function properly?

The usbdp_phy is configured for mode switching here, but the corresponding
&dp node and its VOP2 display pipeline endpoint appear to be missing or
disabled. Without the controller generating video data, will the Type-C
port fail to output a video signal?

> +
> +	port {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716095101.2498464-1-gahing@gahingwoo.com?part=2

Re: [PATCH v3 0/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[Heiko Stuebner]

Am Donnerstag, 16. Juli 2026, 11:50:59 Mitteleuropäische Sommerzeit schrieb Jiaxing Hu:
> Add mainline support for the ArmSoM CM5, an RK3576 compute module, and
> its CM5-IO carrier board.
> 
> Patch 1 adds the binding, patch 2 the module dtsi and the carrier dts.
> 
> The on-module YT8531 PHY has no crystal and needs the SoC 25 MHz
> reference clock (clk_mac_refout). Ungating it for RGMII needs a small
> dwmac-rk change sent separately to netdev [1]; the clock is optional so
> this DTS applies without it.
> 
> Tested on a CM5-IO: the YT8531 is probed by the motorcomm driver and the
> link comes up at 1000 Mbit/s; RK806, HYM8563, eMMC, microSD, the USB3
> hub and the PCIe root complex all probe. dtbs_check is clean.
> 
> Changes in v3:
> - Remove the ES8388 codec from the file header and the i2c0 block
>   comment. The node was dropped in v2 but the comments still named it
>   (sashiko-bot on v2).
> - Use gpios instead of gpio in the vcc_3v3_pcie fixed regulator, to
>   match the other regulators in the file.
> - Pick up Krzysztof's Acked-by on patch 1.
> - The other v2 review notes need no change: the always-on plus
>   off-in-suspend state on vdd_cpu_lit_s0 and vdd_gpu_s0 matches every
>   rk3576 board upstream, and the eMMC full-pwr-cycle-in-suspend with no
>   vmmc-supply is the same pattern used across rk3576. dtbs_check stays
>   clean.
> 
> Changes in v2:
> - Type-C DP alt-mode: name the altmodes child "displayport" and make
>   svid a /bits/ 16 value; drop the undocumented svid from &usbdp_phy and
>   add the missing mode-switch.
> - Move the FUSB302 role-switch endpoint into the connector's ports; the
>   fusb302 binding does not allow a port on the device node. Rename the
>   node to usb-typec@22.
> - Drop the ES8388 node (disabled, wrong compatible) and the unreferenced
>   gmac0_rst, bt_reg_on and wifi_host_wake_irq pinctrls.
> - Rename the wifi-poweren-gpio pinctrl node, it collided with
>   gpio-consumer.yaml.
> - Describe the PHY reset at the MDIO bus level rather than with the
>   deprecated snps,reset-gpios; a per-PHY reset-gpios is applied only
>   after the ID scan, too late for a PHY that boots held in reset.
> 
> [1] net: stmmac: dwmac-rk: enable the reference clock for output mode
> 
> Jiaxing Hu (2):
>   dt-bindings: arm: rockchip: Add ArmSoM CM5 and CM5-IO
>   arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

As Rob said in the v2 bindings, please slow down.
Additionally that is the 2nd "v3" today?

If something is a resend ... please mark it as such, i.e.
[PATCH RESENT x/y] ... and provide an explanation what went
wrong in the cover-letter.


Thanks
Heiko

Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[Andrew Lunn]

> +&gmac0 {
> +	/* The RX delay is added by the PHY, the TX delay by the MAC below. */
> +	phy-mode = "rgmii-rxid";

Please read.

https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287

> +	clock_in_out = "output";
> +	clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
> +		 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
> +		 <&cru CLK_GMAC0_PTP_REF>, <&cru REFCLKO25M_GMAC0_OUT>;
> +	clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac",
> +		      "ptp_ref", "clk_mac_refout";
> +	tx_delay = <0x21>;
> +	rx_delay = <0x00>;

Try setting phy-mode to rgmii-id, and these delays to 0, or removing
them.

	Andrew