Re: [PATCH v4 1/2] dt-bindings: memory-controllers: Add MediaTek DRAM controller interface

["Crystal Guo (郭晶)" <Crystal.Guo@mediatek.com>]

On Wed, 2025-04-09 at 09:33 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 09/04/2025 09:16, Crystal Guo (郭晶) wrote:
> > On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
> > > > +maintainers:
> > > > +  - Crystal Guo <crystal.guo@mediatek.com>
> > > > +
> > > > +description:
> > > > +  A MediaTek DRAM controller interface to provide the current
> > > > data
> > > > rate of DRAM.
> > > 
> > > DRAM controller does not offer scaling? Or PHY/timing
> > > configuration?
> > > This binding looks pretty incomplete.
> > > 
> > 
> > The PHY/timing configuration is completed during the bootloader
> > stage.
> > In the kernel, we currently only need to provide an interface to
> > retrieve the current DDR data rate.
> 
> Not really, that's what you currently want to do in kernel, but not
> what
> you for example will want next days. Binding is supposed to be
> complete,
> so if you do not have any scaling/interconnect then extend the
> description of hardware and explain that memory controller is non
> configurable, cannot scale and it exposes only read interface. Or
> something similar.
> 
> Best regards,
> Krzysztof

Okay, the following instructions will be added in the next version:
'A MediaTek DRAM controller interface that provides the current data
rate of DRAM.

This controller is designed solely to provide a read interface for
retrieving the DDR data rate. It does not support scaling or PHY/timing
configuration during the kernel stage, as these configurations are
already completed during the bootloader stage.'

Best regards,
Crystal Guo