Re: [PATCH v4 1/2] dt-bindings: memory-controllers: Add MediaTek DRAM controller interface

["Crystal Guo (郭晶)" <Crystal.Guo@mediatek.com>]

On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
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> 
> 
> On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
> > +maintainers:
> > +  - Crystal Guo <crystal.guo@mediatek.com>
> > +
> > +description:
> > +  A MediaTek DRAM controller interface to provide the current data
> > rate of DRAM.
> 
> DRAM controller does not offer scaling? Or PHY/timing configuration?
> This binding looks pretty incomplete.
> 

The PHY/timing configuration is completed during the bootloader stage.
In the kernel, we currently only need to provide an interface to
retrieve the current DDR data rate.

> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8196-dramc
> > +
> > +  reg:
> > +    items:
> > +      - description: anaphy registers
> > +      - description: ddrphy registers
> > +
> > +additionalProperties: false
> 
> If there is going to be any resend then this goes after required:
> block.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> 
> Best regards,
> Krzysztof
> 

Okay, thanks for the suggestion.
I will adjust the order in the next version.

Best regards,
Crystal Guo