[PATCH v3 0/3] arm64: dts: qcom: ipq5018: Add MDIO pinctrl and enable MDIO/PHY on RDP432-c2

[PATCH v3 0/3] arm64: dts: qcom: ipq5018: Add MDIO pinctrl and enable MDIO/PHY on RDP432-c2

[Luo Jie]

This is v2 of the series enabling the two MDIO buses on the IPQ5018
platform. v1 (this series' patch 1) added TLMM pinctrl for the
external MDIO bus (mdio1) and is still under review upstream; it is
carried into this v2 with a clarified commit message noting that the
MDIO pin configuration is identical across all IPQ5018 RDP boards.

v2 adds a second patch that actually makes use of the MDIO buses on
the RDP432-c2 board: it enables mdio0, used by the SoC-integrated
EPHY, and mdio1, used by an external QCA8081 PHY, and describes the
QCA8081 PHY node on mdio1.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
Changes in v3:
- Enable the SoC-integrated EPHY MDIO bus by default in the SoC-level
  DTSI, and move this change into a separate patch.
- Add a blank line before the `status` property for improved formatting.
- Link to v2: https://patch.msgid.link/20260814-qcom_ipq5018_mdio_pinctrl-v2-0-ff90d6605d61@oss.qualcomm.com

Changes in v2:
- Patch 1 (pinctrl for MDIO bus): no functional change; commit message
  clarified to note the MDIO pin configuration is identical across all
  IPQ5018 RDP boards.
- Patch 2 (enable MDIO buses and add ethernet PHY) is new in v2.
- Link to v1: https://patch.msgid.link/20260811-qcom_ipq5018_mdio_pinctrl-v1-1-14ae9dc62a3f@oss.qualcomm.com

To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---
Luo Jie (3):
      arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus
      arm64: dts: qcom: ipq5018: Enable mdio0 for SoC-integrated EPHY
      arm64: dts: qcom: ipq5018: Enable mdio1 and add QCA8081 PHY on rdp432-c2

 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 10 ++++++++++
 arch/arm64/boot/dts/qcom/ipq5018.dtsi          | 21 +++++++++++++++++++--
 2 files changed, 29 insertions(+), 2 deletions(-)
---
base-commit: 8b72f6626dc39b9e7e82b2721d4f7c3b86286012
change-id: 20260811-qcom_ipq5018_mdio_pinctrl-f9e609e97c3d

Best regards,
--  
Luo Jie <jie.luo@oss.qualcomm.com>

[PATCH v3 1/3] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Luo Jie]

The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
TLMM pinctrl; without this the pins are left in their default state and
the bus does not function on boards that enable it.

The MDIO pin configuration is identical across all IPQ5018 RDP boards,
so add it to the shared SoC dtsi.

Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with
8mA drive strength and pull-up, and reference it from the mdio1 node
via pinctrl-0/pinctrl-names.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 4fc627b47fe7..cb3e1202b582 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -241,6 +241,8 @@ mdio1: mdio@90000 {
 			reg = <0x00090000 0x64>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			pinctrl-0 = <&mdio_pins>;
+			pinctrl-names = "default";
 
 			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
 			clock-names = "gcc_mdio_ahb_clk";
@@ -421,6 +423,22 @@ tlmm: pinctrl@1000000 {
 			interrupt-controller;
 			#interrupt-cells = <2>;
 
+			mdio_pins: mdio-state {
+				mdc-pins {
+					pins = "gpio36";
+					function = "mdc";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+
+				mdio-pins {
+					pins = "gpio37";
+					function = "mdio";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
 			uart1_pins: uart1-state {
 				pins = "gpio31", "gpio32", "gpio33", "gpio34";
 				function = "blsp1_uart1";

-- 
2.43.0

[PATCH v3 2/3] arm64: dts: qcom: ipq5018: Enable mdio0 for SoC-integrated EPHY

[Luo Jie]

mdio0 is the internal MDIO bus used to access the SoC-integrated
EPHY (ge_phy), which is present on every IPQ5018 RDP board. Enable
mdio0 with a 6.25MHz MDIO clock in the SoC dtsi so all boards can
reach the EPHY, instead of enabling it per board.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index cb3e1202b582..fe1ed240de59 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -222,8 +222,7 @@ mdio0: mdio@88000 {
 
 			clocks = <&gcc GCC_MDIO0_AHB_CLK>;
 			clock-names = "gcc_mdio_ahb_clk";
-
-			status = "disabled";
+			clock-frequency = <6250000>;
 
 			ge_phy: ethernet-phy@7 {
 				compatible = "ethernet-phy-id004d.d0c0";

-- 
2.43.0

[PATCH v3 3/3] arm64: dts: qcom: ipq5018: Enable mdio1 and add QCA8081 PHY on rdp432-c2

[Luo Jie]

The RDP432-c2 board uses an external QCA8081 PHY on mdio1 for one
of its Ethernet connections, but mdio1 is left disabled at the
board level. Enable mdio1 with a 6.25MHz MDIO clock and describe
the QCA8081 PHY at address 0x1c.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 33eef92b19b1..34d4a0886356 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -30,6 +30,16 @@ &blsp1_uart1 {
 	status = "okay";
 };
 
+&mdio1 {
+	clock-frequency = <6250000>;
+
+	status = "okay";
+
+	ethernet-phy@1c {
+		reg = <0x1c>;
+	};
+};
+
 &pcie0 {
 	pinctrl-0 = <&pcie0_default>;
 	pinctrl-names = "default";

-- 
2.43.0

Re: [PATCH v3 2/3] arm64: dts: qcom: ipq5018: Enable mdio0 for SoC-integrated EPHY

[Konrad Dybcio]

On 9/2/26 12:22 PM, Luo Jie wrote:
> mdio0 is the internal MDIO bus used to access the SoC-integrated
> EPHY (ge_phy), which is present on every IPQ5018 RDP board. Enable
> mdio0 with a 6.25MHz MDIO clock in the SoC dtsi so all boards can
> reach the EPHY, instead of enabling it per board.
> 
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 3/3] arm64: dts: qcom: ipq5018: Enable mdio1 and add QCA8081 PHY on rdp432-c2

[Konrad Dybcio]

On 9/2/26 12:22 PM, Luo Jie wrote:
> The RDP432-c2 board uses an external QCA8081 PHY on mdio1 for one
> of its Ethernet connections, but mdio1 is left disabled at the
> board level. Enable mdio1 with a 6.25MHz MDIO clock and describe
> the QCA8081 PHY at address 0x1c.
> 
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad