Re: [PATCH v1 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement

["Kathpalia, Tanmay" <tanmay.kathpalia@altera.com>]

Hi K

Thanks for your feedback.

On 5/15/2026 2:08 PM, Krzysztof Kozlowski wrote:
> On Mon, May 11, 2026 at 01:21:25PM -0700, Tanmay Kathpalia wrote:
>> The Agilex5 SoC device tree gains an SD/MMC controller node backed by
>> the Cadence SD6HC, with IOMMU integration via the system SMMU. Card
>> power is supplied by a fixed 3.3V regulator and I/O voltage switching
>> between 1.8V and 3.3V is handled by a GPIO-controlled regulator.
>>
>> The SOCDK board enables the controller for SD-only operation in 4-bit
>> bus width with high-speed and SDR104 UHS-I modes at 200 MHz maximum
>> clock. SDHCI capability overrides clear the SDR50 tuning flag and
>> override the clock base mask to report 200 MHz.
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 38 +++++++++++++++++++
>>   .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 26 +++++++++++++
>>   2 files changed, 64 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index 352c96d144a8..7e080f13166f 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -300,6 +300,44 @@ portb: gpio-controller@0 {
>>   			};
>>   		};
>>   
>> +		sd_emmc_power: regulator-fixed-3p3v {
> NAK, this fails basic rules of organizing DTS/DTSI and the nodes. This
> is simple-bus, so how could you have here a regulator which is non MMIO?
>
> Plus, explain me how these regulators managed to appear on the SoC
> die/silicon?
>
> Best regards,
> Krzysztof


Apologies, you are right on both counts.

In v2 this will be fixed:
1. sd_emmc_power and sd_io_1v8_reg will be moved to the root level
of socfpga_agilex5_socdk.dts where they belong.
2. emmc_io_1v8_reg will be moved to the root level of
socfpga_agilex5_socdk_emmc.dts.
3. The shared socfpga_agilex5.dtsi will carry only the SoC-level
emmc controller node with no board-specific regulators.

Regards,
Tanmay