From: Krzysztof Kozlowski <krzk@kernel.org>
To: wangjia@ultrarisc.com, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: Re: [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings
Date: Thu, 21 May 2026 22:56:45 +0200 [thread overview]
Message-ID: <6c320ea2-e169-4c97-a183-b0d5ec3d7aa9@kernel.org> (raw)
In-Reply-To: <20260515-ultrarisc-pinctrl-v1-4-bf559589ea8a@ultrarisc.com>
On 15/05/2026 03:18, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
>
> Add bindings for the pin controllers on the UltraRISC DP1000 RISC-V SoC.
A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
> .../bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml | 168 +++++++++++++++++++++
> MAINTAINERS | 7 +
> .../dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h | 65 ++++++++
> 3 files changed, 240 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
> new file mode 100644
> index 000000000000..c7ed1f96382a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
> @@ -0,0 +1,168 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 Pin Controller
Missing blank line.
Please organize your bindings to match expected style. See example-schema.
> +maintainers:
> + - Jia Wang <wangjia@ultrarisc.com>
> +
> +description: |
> + UltraRISC RISC-V SoC DP1000 pin controller.
> +
> + The binding supports two child node styles under the same controller
> + compatible:
> +
> + - legacy DP1000-specific nodes using phandle-array properties
New bindings CANNOT introduce legacy. It's contradictory.
> + `pinctrl-pins` and `pinconf-pins`
> + - generic pinctrl nodes using `pins`, `function` and generic pin
> + configuration properties
> +
> +properties:
> + compatible:
> + const: ultrarisc,dp1000-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + "#pinctrl-cells":
Use consistent quotes, either ' or "
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> +patternProperties:
> + '.*-pins$':
> + type: object
> + allOf:
> + - $ref: /schemas/pinctrl/pincfg-node.yaml#
> + - $ref: /schemas/pinctrl/pinmux-node.yaml#
> + additionalProperties: false
> + properties:
> + pinctrl-pins:
> + description: |
> + The list of pins and their mux settings that properties in the node
> + apply to. The format: `PORT PIN FUNCTION`.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 32
> + pinconf-pins:
> + description: |
> + The list of pins and their pad configuration that properties in the
> + node apply to. The format: `PORT PIN CONF`.
> + CONF is a DP1000-specific encoding of pull and drive strength as
> + defined in dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 32
> + pins:
> + description: List of pins affected by this state node.
> + minItems: 1
> + uniqueItems: true
> + items:
> + type: string
> + pattern: '^(PA([0-9]|1[0-5])|P[BCD][0-7]|LPC([0-9]|1[0-2]))$'
> +
> + function:
> + description: |
> + Mux function to select for the listed pins.
> + gpio maps to the hardware default mode. The default mode is
> + GPIO for PA/PB/PC/PD pins and LPC for LPC pins.
> + func1 is not supported on LPC pins.
> + enum:
> + - gpio
> + - func0
> + - func1
> +
> + bias-disable: true
> + bias-high-impedance: true
> + bias-pull-up: true
> + bias-pull-down: true
> +
> + drive-strength:
> + description: Output drive strength in mA.
> + enum: [20, 27, 33, 40]
> +
> + oneOf:
> + - allOf:
> + - anyOf:
> + - required: [pinctrl-pins]
> + - required: [pinconf-pins]
> + - not:
> + required: [pins]
> + - allOf:
> + - required: [pins]
> + - not:
> + anyOf:
> + - required: [pinctrl-pins]
> + - required: [pinconf-pins]
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pinmux@11081000 {
> + compatible = "ultrarisc,dp1000-pinctrl";
> + reg = <0x0 0x11081000 0x0 0x1000>;
> + #pinctrl-cells = <2>;
> +
> + i2c0-pins {
> + pins = "PA12", "PA13";
> + function = "func0";
> + bias-pull-up;
> + drive-strength = <33>;
> + };
> +
> + uart0-pins {
> + pins = "PA8", "PA9";
> + function = "func1";
> + bias-pull-up;
> + drive-strength = <33>;
> + };
> + };
> + };
> +
> + - |
> + /* Legacy example */
We do not take new code which is already legacy. Why would we want a legacy?
> + #include <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pinmux@11081000 {
> + compatible = "ultrarisc,dp1000-pinctrl";
> + reg = <0x0 0x11081000 0x0 0x1000>;
> + #pinctrl-cells = <2>;
> +
> + i2c0-pins {
> + pinctrl-pins = <
> + UR_DP1000_IOMUX_A 12 UR_DP1000_FUNC0
> + UR_DP1000_IOMUX_A 13 UR_DP1000_FUNC0
> + >;
> +
> + pinconf-pins = <
> + UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_DP1000_PULL_UP,
> + UR_DP1000_DRIVE_DEF)
> + UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_DP1000_PULL_UP,
> + UR_DP1000_DRIVE_DEF)
> + >;
> + };
> +
> + uart0-pins {
> + pinctrl-pins = <
> + UR_DP1000_IOMUX_A 8 UR_DP1000_FUNC1
> + UR_DP1000_IOMUX_A 9 UR_DP1000_FUNC1
> + >;
> +
> + pinconf-pins = <
> + UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_DP1000_PULL_UP,
> + UR_DP1000_DRIVE_DEF)
> + UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_DP1000_PULL_UP,
> + UR_DP1000_DRIVE_DEF)
> + >;
> + };
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5bf971ff48b2..baaaa46b1a56 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -27358,6 +27358,13 @@ S: Maintained
> F: drivers/usb/common/ulpi.c
> F: include/linux/ulpi/
>
> +ULTRARISC DP1000 PINCTRL DRIVER
> +M: Jia Wang <wangjia@ultrarisc.com>
> +L: linux-gpio@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
> +F: include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h
> +
> ULTRATRONIK BOARD SUPPORT
> M: Goran Rađenović <goran.radni@gmail.com>
> M: Börge Strümpfel <boerge.struempfel@gmail.com>
> diff --git a/include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h
> new file mode 100644
> index 000000000000..bef28115898d
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * UltraRISC DP1000 pinctrl header.
> + *
> + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H
> +#define _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H
> +
> +/**
> + * UltraRISC DP1000 IO pad configuration
> + * port: A, B, C, D, LPC
> + * Pin in the port
> + * pin:
> + * PA: 0 - 15
> + * PB-PD: 0 - 7
> + * LPC: 0 - 12
> + * func:
> + * UR_DP1000_FUNC_DEF: default
> + * UR_DP1000_FUNC0: func0
> + * UR_DP1000_FUNC1: func1
> + */
> +#define UR_DP1000_IOMUX_A 0x0
> +#define UR_DP1000_IOMUX_B 0x1
> +#define UR_DP1000_IOMUX_C 0x2
> +#define UR_DP1000_IOMUX_D 0x3
> +#define UR_DP1000_IOMUX_LPC 0x4
Not bindings, drop.
> +
> +#define UR_DP1000_FUNC_DEF 0
> +#define UR_DP1000_FUNC0 1
> +#define UR_DP1000_FUNC1 0x10000
Not a binding.
> +
> +/**
> + * Configure pull up/down resistor of the IO pin
> + * UR_DP1000_PULL_DIS: disable pull-up and pull-down
> + * UR_DP1000_PULL_UP: enable pull-up
> + * UR_DP1000_PULL_DOWN: enable pull-down
> + */
> +#define UR_DP1000_PULL_DIS 0
> +#define UR_DP1000_PULL_UP 1
> +#define UR_DP1000_PULL_DOWN 2
I don't see usage in the driver, so not a binding.
> +/**
> + * Configure drive strength of the IO pin
> + * UR_DP1000_DRIVE_DEF: default value, reset value is 2
> + * UR_DP1000_DRIVE_0: 20mA
> + * UR_DP1000_DRIVE_1: 27mA
> + * UR_DP1000_DRIVE_2: 33mA
> + * UR_DP1000_DRIVE_3: 40mA
> + */
> +#define UR_DP1000_DRIVE_DEF 2
> +#define UR_DP1000_DRIVE_0 0
> +#define UR_DP1000_DRIVE_1 1
> +#define UR_DP1000_DRIVE_2 2
> +#define UR_DP1000_DRIVE_3 3
Not a binding, use actual mA values in the DTS.
> +
> +/**
> + * Combine the pull-up/down resistor and drive strength
> + * pull: UR_DP1000_PULL_DIS, UR_DP1000_PULL_UP, UR_DP1000_PULL_DOWN
> + * drive: UR_DP1000_DRIVE_DEF, UR_DP1000_DRIVE_0, UR_DP1000_DRIVE_1,
> + * UR_DP1000_DRIVE_2, UR_DP1000_DRIVE_3
> + */
> +#define UR_DP1000_BIAS(pull, drive) (((pull) << 2) | (drive))
> +
> +#endif /* _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H */
>
Also not used in the driver. Drop entire header or move out of bindings.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-05-21 20:56 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 1:17 [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Jia Wang via B4 Relay
2026-05-15 1:17 ` [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Jia Wang via B4 Relay
2026-05-15 1:20 ` sashiko-bot
2026-05-15 1:25 ` Jia Wang
2026-05-21 20:51 ` Krzysztof Kozlowski
2026-05-15 1:17 ` [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-05-15 10:06 ` Conor Dooley
2026-05-15 1:17 ` [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Jia Wang via B4 Relay
2026-05-15 10:08 ` Conor Dooley
2026-05-18 3:06 ` Jia Wang
2026-05-15 1:18 ` [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Jia Wang via B4 Relay
2026-05-15 1:49 ` sashiko-bot
2026-05-15 8:43 ` Jia Wang
2026-05-15 10:12 ` Conor Dooley
2026-05-18 6:03 ` Jia Wang
2026-05-21 20:56 ` Krzysztof Kozlowski [this message]
2026-05-15 1:18 ` [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-05-15 2:02 ` sashiko-bot
2026-05-19 6:55 ` Jia Wang
2026-05-15 10:26 ` Conor Dooley
2026-05-20 2:51 ` Jia Wang
2026-05-21 21:05 ` Krzysztof Kozlowski
2026-05-15 1:18 ` [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Jia Wang via B4 Relay
2026-05-15 2:28 ` sashiko-bot
2026-05-20 7:15 ` Jia Wang
2026-05-21 21:09 ` Krzysztof Kozlowski
2026-05-15 1:18 ` [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Jia Wang via B4 Relay
2026-05-15 2:37 ` sashiko-bot
2026-05-20 8:26 ` Jia Wang
2026-05-15 10:28 ` Conor Dooley
2026-05-20 8:40 ` Jia Wang
2026-05-21 20:59 ` Krzysztof Kozlowski
2026-05-15 1:18 ` [PATCH 8/9] riscv: dts: ultrarisc: add Milk-V Titan " Jia Wang via B4 Relay
2026-05-15 2:50 ` sashiko-bot
2026-05-20 9:39 ` Jia Wang
2026-05-15 1:18 ` [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Jia Wang via B4 Relay
2026-05-15 2:59 ` sashiko-bot
2026-05-20 9:49 ` Jia Wang
2026-05-21 20:57 ` Krzysztof Kozlowski
2026-05-15 10:05 ` [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Conor Dooley
2026-05-21 9:52 ` Jia Wang
2026-05-21 10:23 ` Conor Dooley
2026-05-22 1:41 ` Jia Wang
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