From: "Benoît Monin" <benoit.monin@bootlin.com>
To: sashiko-reviews@lists.linux.dev
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v8 5/9] clk: eyeq: Prefix the PLL registers with the PLL type
Date: Tue, 09 Jun 2026 11:12:48 +0200 [thread overview]
Message-ID: <8-0jFbatSUKRA5pG2l_1wA@bootlin.com> (raw)
In-Reply-To: <20260604133615.56C5D1F00893@smtp.kernel.org>
On Thursday, 4 June 2026 at 15:36:13 CEST, sashiko-bot@kernel.org wrote:
> This is a pre-existing issue, but will this readq() trigger a hardware
> alignment fault on ARM64?
>
> The PLL registers passed as the base address (such as 0x02C, 0x034, 0x03C,
> and 0x044) are 4-byte aligned, but not 8-byte aligned. On ARM64 platforms
> like EyeQ6, performing a 64-bit load instruction via readq() on unaligned
> device memory violates architectural rules and typically causes a
> synchronous external abort.
>
> Would it be safer to replace this with two readl() calls to avoid
> alignment issues?
The clk-eyeq driver is specific to Mobileye EyeQ SoCs which are _not_ ARM64;
readq() works without error.
Best regards,
--
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2026-06-09 9:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-04 13:26 [PATCH v8 0/9] Add clock and reset support for Mobileye EyeQ7H Benoît Monin
2026-06-04 13:26 ` [PATCH v8 1/9] dt-bindings: soc: mobileye: Add EyeQ7H OLB Benoît Monin
2026-06-04 13:26 ` [PATCH v8 2/9] reset: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-06-04 13:26 ` [PATCH v8 3/9] clk: fixed-factor: Rework initialization with parent clocks Benoît Monin
2026-06-04 13:26 ` [PATCH v8 4/9] clk: fixed-factor: Export __clk_hw_register_fixed_factor() Benoît Monin
2026-06-04 13:26 ` [PATCH v8 5/9] clk: eyeq: Prefix the PLL registers with the PLL type Benoît Monin
2026-06-04 13:36 ` sashiko-bot
2026-06-09 9:12 ` Benoît Monin [this message]
2026-06-04 13:26 ` [PATCH v8 6/9] clk: eyeq: Introduce a generic clock type Benoît Monin
2026-06-04 13:51 ` sashiko-bot
2026-06-12 9:12 ` Benoît Monin
2026-06-04 13:26 ` [PATCH v8 7/9] clk: eyeq: Convert clocks declaration to eqc_clock Benoît Monin
2026-06-04 13:44 ` sashiko-bot
2026-06-12 9:12 ` Benoît Monin
2026-06-04 13:26 ` [PATCH v8 8/9] clk: eyeq: Drop PLL, dividers, and fixed factors structs Benoît Monin
2026-06-04 13:26 ` [PATCH v8 9/9] clk: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-06-04 13:43 ` sashiko-bot
2026-06-12 9:12 ` Benoît Monin
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