Re: [PATCH v8 6/9] clk: eyeq: Introduce a generic clock type

["Benoît Monin" <benoit.monin@bootlin.com>]

On Thursday, 4 June 2026 at 15:51:06 CEST, sashiko-bot@kernel.org wrote:
...
> [Severity: High]
> This isn't a bug introduced by this patch, but since multiple writable
> clock dividers share the same physical register (for example, div-ospi-ref
> and div-ospi-sys share the register at 0x090), can concurrent clk_set_rate()
> calls cause read-modify-write races here?
> 
> Because NULL is passed as the lock parameter, the clock divider core will
> perform a lockless read-modify-write sequence. Would it be safer to provide
> a shared spinlock to protect the register state?
> 
This is a fairly theoretical point. For now, the clocks are unused and not
tied to any device in the device tree on the EyeQ6H SoC. Even so, both
clocks are related to the octo-spi controller which uses the
spi-cadence-quadspi driver. In this driver, the clocks are handled by the
clk-bulk API which serialize clock accesses in lk_bulk_prepare_enable() and
clk_bulk_disable_unprepare(). And there are no calls to clk_set_rate() in
this driver.

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com