Re: [PATCH v6 09/16] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support

[Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>]

Hi John

Thank you for the patch

> Add support for the SSIU found on the Renesas RZ/G3E SoC, which
> provides a different BUSIF layout compared to earlier generations:
> 
>  - SSI0-SSI4: 4 BUSIF instances each (BUSIF0-3)
>  - SSI5-SSI8: 1 BUSIF instance each (BUSIF0 only)
>  - SSI9: 4 BUSIF instances (BUSIF0-3)
>  - Total: 28 BUSIFs
> 
> RZ/G3E also differs from Gen2/Gen3 implementations in that only two
> pairs of BUSIF error-status registers are available instead of four,
> and the SSI always operates in BUSIF mode with no PIO fallback.
> 
> Rather than scattering SoC-specific checks across functional code,
> introduce an extra capability flags in the match data:
> 
>  - RSND_SSIU_BUSIF_STATUS_COUNT_2: only two BUSIF error-status
>    register pairs are present. Used in rsnd_ssiu_busif_err_irq_ctrl()
>    and rsnd_ssiu_busif_err_status_clear() to limit register iteration.
> 
> Future SoCs sharing these constraints can set the flags without
> requiring code changes.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---

If my understanding was correct, this patch includes 3 features ?

	- adding busif_status_count
	- adding rag3e_id
	- adding rstc

I guess these can be separated ?

Thank you for your help !!

Best regards
---
Kuninori Morimoto