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From: John Madieu <john.madieu.xa@bp.renesas.com>
To: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>,
	Mark Brown <broonie@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>
Cc: Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Claudiu Beznea <claudiu.beznea@tuxon.dev>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	john.madieu@gmail.com, linux-sound@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	John Madieu <john.madieu.xa@bp.renesas.com>
Subject: [PATCH v6 14/16] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E
Date: Tue, 12 May 2026 18:26:29 +0000	[thread overview]
Message-ID: <20260512182631.3842065-15-john.madieu.xa@bp.renesas.com> (raw)
In-Reply-To: <20260512182631.3842065-1-john.madieu.xa@bp.renesas.com>

The RZ/G3E SoC requires explicit SCU (Sampling Rate Converter Unit)
reset and clock management unlike previous R-Car generations:

 - scu: SCU top-level module clock (CPG_CLKON_15.CLK6_ON)
 - scu_x2: SCU top-level double-rate clock (CPG_CLKON_15.CLK7_ON)
 - scu_supply: SCU register-access / housekeeping clock
   (CPG_CLKON_23.CLK14_ON, described by the HW manual as the system
   clock for "function modules excluding SRC0-9, DVC0-1, CTU0-1 and
   MIX0-1 (including the setting registers, etc.)")

Without every one of them enabled, no SCU register is reachable.
Add support for the shared SCU reset controller used by all SRC
modules on the RZ/G3E SoC and manage scu_supply with the same lifetime
as scu and scu_x2. This matches the hardware description and avoids
unnecessary clock toggling.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v6:
 - Use devm_clk_get_optional_enabled() for scu_supply so it has
   the same lifetime as scu and scu_x2, and drop the manual
   clk_prepare_enable()/clk_disable_unprepare() in
   rsnd_src_init()/rsnd_src_quit(). This matches the HW
   description ("system clock for function modules excluding
   SRC0-9, DVC0-1, CTU0-1 and MIX0-1") and avoids unnecessary
   clock toggling on each stream open/close.
 - Acquire the per-SRC clock via rsnd_devm_clk_get_indexed() from
   patch 04/16, so both "src-N" and the legacy "src.N" work.
 - Drop the per-module name buffer and RSND_SRC_NAME_SIZE.

v5: No changes

v4:
 - Move shared SCU clocks (scu, scu_x2, scu_supply) from
   rsnd_priv variables into new struct rsnd_src_ctrl, following
   the rsnd_dma_ctrl pattern for shared non-per-instance module
   resources.
 - Keep original declaration order for struct device_node *node.

v3: No changes
v2: No changes

 sound/soc/renesas/rcar/rsnd.h |  1 +
 sound/soc/renesas/rcar/src.c  | 50 ++++++++++++++++++++++++++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 186468a584fe..bdc4a99394de 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -698,6 +698,7 @@ struct rsnd_priv {
 	/*
 	 * below value will be filled on rsnd_src_probe()
 	 */
+	void *src_ctrl;
 	void *src;
 	int src_nr;
 
diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c
index 43abe13137bf..0237b5d2e79e 100644
--- a/sound/soc/renesas/rcar/src.c
+++ b/sound/soc/renesas/rcar/src.c
@@ -53,6 +53,14 @@ struct rsnd_src {
 	     ((pos) = (struct rsnd_src *)(priv)->src + i);	\
 	     i++)
 
+struct rsnd_src_ctrl {
+	struct clk *scu;
+	struct clk *scu_x2;
+	struct clk *scu_supply;
+};
+
+#define rsnd_priv_to_src_ctrl(priv) \
+	((struct rsnd_src_ctrl *)(priv)->src_ctrl)
 
 /*
  *		image of SRC (Sampling Rate Converter)
@@ -712,6 +720,8 @@ int rsnd_src_probe(struct rsnd_priv *priv)
 {
 	struct device_node *node;
 	struct device *dev = rsnd_priv_to_dev(priv);
+	struct reset_control *rstc;
+	struct rsnd_src_ctrl *src_ctrl;
 	struct rsnd_src *src;
 	struct clk *clk;
 	int i, nr, ret;
@@ -726,6 +736,12 @@ int rsnd_src_probe(struct rsnd_priv *priv)
 		goto rsnd_src_probe_done;
 	}
 
+	src_ctrl = devm_kzalloc(dev, sizeof(*src_ctrl), GFP_KERNEL);
+	if (!src_ctrl) {
+		ret = -ENOMEM;
+		goto rsnd_src_probe_done;
+	}
+
 	src	= devm_kcalloc(dev, nr, sizeof(*src), GFP_KERNEL);
 	if (!src) {
 		ret = -ENOMEM;
@@ -734,6 +750,28 @@ int rsnd_src_probe(struct rsnd_priv *priv)
 
 	priv->src_nr	= nr;
 	priv->src	= src;
+	priv->src_ctrl	= src_ctrl;
+
+	src_ctrl->scu = devm_clk_get_optional_enabled(dev, "scu");
+	if (IS_ERR(src_ctrl->scu)) {
+		ret = dev_err_probe(dev, PTR_ERR(src_ctrl->scu),
+				    "failed to get scu clock\n");
+		goto rsnd_src_probe_done;
+	}
+
+	src_ctrl->scu_x2 = devm_clk_get_optional_enabled(dev, "scu_x2");
+	if (IS_ERR(src_ctrl->scu_x2)) {
+		ret = dev_err_probe(dev, PTR_ERR(src_ctrl->scu_x2),
+				    "failed to get scu_x2 clock\n");
+		goto rsnd_src_probe_done;
+	}
+
+	src_ctrl->scu_supply = devm_clk_get_optional_enabled(dev, "scu_supply");
+	if (IS_ERR(src_ctrl->scu_supply)) {
+		ret = dev_err_probe(dev, PTR_ERR(src_ctrl->scu_supply),
+				    "failed to get scu_supply clock\n");
+		goto rsnd_src_probe_done;
+	}
 
 	i = 0;
 	for_each_child_of_node_scoped(node, np) {
@@ -754,6 +792,16 @@ int rsnd_src_probe(struct rsnd_priv *priv)
 			goto rsnd_src_probe_done;
 		}
 
+		/*
+		 * RZ/G3E uses a shared SCU reset controller for all SRC modules.
+		 * R-Car platforms typically don't have SRC reset controls.
+		 */
+		rstc = devm_reset_control_get_optional_shared(dev, "scu");
+		if (IS_ERR(rstc)) {
+			ret = PTR_ERR(rstc);
+			goto rsnd_src_probe_done;
+		}
+
 		clk = rsnd_devm_clk_get_indexed(dev, SRC_NAME, i);
 		if (IS_ERR(clk)) {
 			ret = PTR_ERR(clk);
@@ -761,7 +809,7 @@ int rsnd_src_probe(struct rsnd_priv *priv)
 		}
 
 		ret = rsnd_mod_init(priv, rsnd_mod_get(src),
-				    &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i);
+				    &rsnd_src_ops, clk, rstc, RSND_MOD_SRC, i);
 		if (ret)
 			goto rsnd_src_probe_done;
 
-- 
2.25.1


  parent reply	other threads:[~2026-05-12 18:29 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-12 18:26 [PATCH v6 00/16] ASoC: rsnd: Add RZ/G3E audio driver support John Madieu
2026-05-12 18:26 ` [PATCH v6 01/16] ASoC: dt-bindings: sound: Add DT binding for RZ/G3E sound John Madieu
2026-05-12 18:26 ` [PATCH v6 02/16] ASoC: rsnd: Fix RSND_SOC_MASK width to single nibble John Madieu
2026-05-12 18:26 ` [PATCH v6 03/16] ASoC: rsnd: Add reset controller support to rsnd_mod John Madieu
2026-05-12 18:26 ` [PATCH v6 04/16] ASoC: rsnd: Support hyphen or dot in indexed clock and reset names John Madieu
2026-05-12 18:26 ` [PATCH v6 05/16] ASoC: rsnd: Add RZ/G3E SoC probing and register map John Madieu
2026-05-12 18:26 ` [PATCH v6 06/16] ASoC: rsnd: Add audmacpp clock and reset support for RZ/G3E John Madieu
2026-05-12 18:26 ` [PATCH v6 07/16] ASoC: rsnd: Refactor DMA address tables with named structs John Madieu
2026-05-12 18:26 ` [PATCH v6 08/16] ASoC: rsnd: Add RZ/G3E DMA address calculation support John Madieu
2026-05-12 18:26 ` [PATCH v6 09/16] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support John Madieu
2026-05-13  0:35   ` Kuninori Morimoto
2026-05-13  5:04     ` John Madieu
2026-05-13  9:41   ` Geert Uytterhoeven
2026-05-12 18:26 ` [PATCH v6 10/16] ASoC: rsnd: Add SSI reset support for RZ/G3E platform John Madieu
2026-05-12 18:26 ` [PATCH v6 11/16] ASoC: rsnd: Add ADG reset support for RZ/G3E John Madieu
2026-05-12 18:26 ` [PATCH v6 12/16] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management John Madieu
2026-05-12 18:26 ` [PATCH v6 13/16] ASoC: rsnd: adg: Look up RZ/G3E clkin under audio-clk{a,b,c,i} John Madieu
2026-05-12 18:26 ` John Madieu [this message]
2026-05-13  0:44   ` [PATCH v6 14/16] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E Kuninori Morimoto
2026-05-13  5:17     ` John Madieu
2026-05-12 18:26 ` [PATCH v6 15/16] ASoC: rsnd: Support unprefixed DT node names " John Madieu
2026-05-12 18:26 ` [PATCH v6 16/16] ASoC: rsnd: Add system suspend/resume support John Madieu

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