From: Marc Zyngier <maz@kernel.org>
To: sashiko-reviews@lists.linux.dev
Cc: robh@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, "\"Andreas Färber\"" <afaerber@suse.de>,
"Yu-Chun Lin" <eleanor.lin@realtek.com>
Subject: Re: [PATCH v2 14/17] arm64: dts: realtek: Add EL2 virtual timer interrupt
Date: Fri, 15 May 2026 09:23:08 +0100 [thread overview]
Message-ID: <87tss99j4j.wl-maz@kernel.org> (raw)
In-Reply-To: <20260514231804.000CCC2BCB3@smtp.kernel.org>
On Fri, 15 May 2026 00:18:03 +0100,
sashiko-bot@kernel.org wrote:
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Incomplete implementation: missing update for Realtek Kent SoC family which specifies an incorrect EL2 virtual timer interrupt.
> --
>
> commit 3b73638950a28ecc324e1c28fa4fb9fcb13d5567
> Author: Marc Zyngier <maz@kernel.org>
>
> arm64: dts: realtek: Add EL2 virtual timer interrupt
>
> This commit adds the missing EL2 virtual timer interrupt to ARMv8.2-based
> Realtek SoCs. It updates rtd16xx.dtsi by adding the fifth timer interrupt
> with GIC_PPI 12.
>
> > diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> > index 3a7f6e35b7f74..43b13d133c324 100644
> > --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> > +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> > @@ -105,7 +105,8 @@ timer {
> > interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> > };
>
> Does this update miss another Realtek ARMv8.2+ SoC file?
>
> Looking at arch/arm64/boot/dts/realtek/kent.dtsi (used by RTD1501, RTD1861,
> and RTD1920), the fifth timer interrupt is currently defined as
> <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>.
>
> PPI 9 is the GIC vCPU maintenance interrupt, rather than the EL2 virtual
> timer interrupt which should be PPI 12:
>
> arch/arm64/boot/dts/realtek/kent.dtsi:
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> Another patch in this series (clocksource/drivers/arm_arch_timer: Default
> to EL2 virtual timer when running VHE) changes the driver to use the EL2
> virtual timer by default on VHE systems.
>
> If the kernel uses the EL2 virtual timer on these Realtek SoCs, could it
> request the wrong interrupt (PPI 9 instead of PPI 12), causing timer
> interrupts to not be delivered and resulting in a boot hang regression?
That's definitely odd, as PPI9 is present in two interrupt specifiers
(timer and GIC). Obviously, that's not possible.
I'll add a tentative fix for that in the next round. Maybe Andreas or
Yu-Chun can check in the meantime?
M.
--
Jazz isn't dead. It just smells funny.
next prev parent reply other threads:[~2026-05-15 8:19 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-14 15:09 [PATCH v2 00/17] arm64: Use EL2 virtual timer when running VHE Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 01/17] ACPI: GTDT: Account for GTDTv3 size when walking the platform timer descriptors Marc Zyngier
2026-05-14 19:54 ` sashiko-bot
2026-05-15 9:51 ` Sudeep Holla
2026-05-14 15:09 ` [PATCH v2 02/17] ACPI: GTDT: Parse information related to the EL2 virtual timer Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 03/17] clocksource/drivers/arm_arch_timer: Default to EL2 virtual timer when running VHE Marc Zyngier
2026-05-14 21:23 ` sashiko-bot
2026-05-15 8:30 ` Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 04/17] dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description Marc Zyngier
2026-05-14 21:37 ` sashiko-bot
2026-05-15 9:18 ` Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 05/17] arm64: dts: allwinner: Add EL2 virtual timer interrupt Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 06/17] arm64: dts: amlogic: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 07/17] arm64: dts: bst: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 08/17] arm64: dts: exynos: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 09/17] arm64: dts: freescale: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 10/17] arm64: dts: intel: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 11/17] arm64: dts: mediatek: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 12/17] arm64: dts: nvidia: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 13/17] arm64: dts: qcom: " Marc Zyngier
2026-05-14 23:06 ` sashiko-bot
2026-05-15 8:24 ` Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 14/17] arm64: dts: realtek: " Marc Zyngier
2026-05-14 23:18 ` sashiko-bot
2026-05-15 8:23 ` Marc Zyngier [this message]
2026-05-14 15:09 ` [PATCH v2 15/17] arm64: dts: rockchip: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 16/17] arm64: dts: sprd: " Marc Zyngier
2026-05-14 15:09 ` [PATCH v2 17/17] arm64: dts: xilinx: " Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87tss99j4j.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=afaerber@suse.de \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=eleanor.lin@realtek.com \
--cc=krzk+dt@kernel.org \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox