From: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Daniel Lezcano <daniel.lezcano@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Subject: Re: [PATCH 2/3] powercap: qcom: Add SPEL powercap driver
Date: Tue, 9 Jun 2026 18:53:49 +0530 [thread overview]
Message-ID: <8f045340-a6c8-41c7-b1c7-6d9b87b05d90@oss.qualcomm.com> (raw)
In-Reply-To: <7ea2f2cc-ef11-4727-810c-e32e815bd973@oss.qualcomm.com>
Hi Konrad,
On 5/21/2026 4:46 PM, Konrad Dybcio wrote:
> On 5/19/26 12:49 PM, Manaf Meethalavalappu Pallikunhi wrote:
>> The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware
>> based power monitoring and limiting capabilities for various power
>> domains including System, SoC, CPU clusters, GPU, and various other
>> subsystems.
>>
>> The driver integrates with the Linux powercap framework, exposing SPEL
>> capabilities through powercap sysfs interfaces.
>>
>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>> ---
>
> [...]
>
>> +/* SPEL register bitmasks */
>> +#define ENERGY_STATUS_MASK 0xFFFFFFFF
>
> GENMASK(m, n), across the other defines too, please
>
> Then, you can drop the _OFFSET defines as FIELD_PREP/GET/MODIFY
> accessors will derive them from the mask
>
> Please also use lowercase hex, file-wide
ACK
>
> [...]
>
>> +/* Constraint configuration */
>> +static struct spel_constraint_info constraints[] = {
>> + /* SYS domain constraints */
>> + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 },
>> + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 },
>> + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 },
>> + { 0x1C, 0x7C, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 },
>> + /* SOC domain constraints */
>
> "SoC"
ACK
>
>
>> +/* Helper functions */
>> +static bool is_pl_valid(struct spel_domain *sd, int pl)
>> +{
>> + if (pl < POWER_LIMIT1 || pl >= NR_POWER_LIMITS)
>> + return false;
>> + return sd->pl_name[pl] ? true : false;
>
> return !!sd->pl_name[pl]
ACK
>
> [...]
>
>> +static u64 spel_unit_xlate(struct spel_domain *sd, enum unit_type type,
>> + u64 value, int to_raw)
>> +{
>> + struct spel_system *sp = sd->sp;
>> + u64 units = 1;
>> + u64 scale = 1;
>> +
>> + switch (type) {
>> + case POWER_UNIT:
>> + units = sp->power_unit;
>> + break;
>> + case ENERGY_UNIT:
>> + scale = ENERGY_UNIT_SCALE;
>> + units = sp->energy_unit;
>> + break;
>> + case TIME_UNIT:
>> + units = sp->time_unit;
>> + break;
>> + default:
>> + return value;
>
> nit: maybe setting units and scale explicitly in each entry could
> be better for maintainability, but potayto/potahto
ACK
>
>> +static int spel_register_powercap(struct spel_system *sp)
>> +{
>> + struct spel_domain *sd;
>> + struct powercap_zone *power_zone = NULL;
>> + int nr_pl, ret, i;
>> +
>> + /* Register SYS domain as parent zone */
>> + for (sd = sp->domains; sd < sp->domains + SPEL_DOMAIN_MAX; sd++) {
>> + if (sd->id == SPEL_DOMAIN_SYS) {
>> + nr_pl = spel_find_nr_power_limit(sd);
>> +
>> + power_zone = powercap_register_zone(&sd->power_zone,
>> + sp->control_type, sd->name,
>> + NULL, &zone_ops, nr_pl,
>> + &constraint_ops);
>> + if (IS_ERR(power_zone)) {
>> + dev_err(sp->dev, "Failed to register power zone %s\n",
>> + sd->name);
>> + return PTR_ERR(power_zone);
>> + }
>> + sp->power_zone = power_zone;
>> + break;
>> + }
>> + }
>> +
>> + if (!power_zone) {
>
> I believe this is only possible if ARRAY_SIZE(sp->domains) == 0,
> but it's not obivous that it's to protect it from that specifically
It will also catch a case where domains defined without root domain
SPEL_DOMAIN_SYS
>
> [...]
>
>> + /* Map spel domain registers (energy counters) */
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nodes");
>> + if (!res) {
>> + dev_err(dev, "Failed to get nodes resource\n");
>> + return -EINVAL;
>> + }
>> + sp->node_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(sp->node_base))
>> + return PTR_ERR(sp->node_base);
>
> devm_platform_get_and_ioremap_resource()
ACK
>
> [...]
>
>> +static void spel_remove(struct platform_device *pdev)
>> +{
>> + struct spel_system *sp = platform_get_drvdata(pdev);
>> + int i;
>> +
>> + if (!sp)
>> + return;
>> +
>> + /* Unregister in reverse order: children first, then SOC, then SYS */
>> + for (i = SPEL_DOMAIN_MAX - 1; i >= 0; i--)
>> + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone);
>
> Could you try adding a devm_ variant of these register functions?
Powercap framework doesn't support any devm_* API, you meant add this
support in framework in this series ?
>
> [...]
>> +static const struct of_device_id spel_of_match[] = {
>> + { .compatible = "qcom,spel" },
>
> The compatible must contain a SoC name
ACK
Thanks,
Manaf
>
> Konrad
next prev parent reply other threads:[~2026-06-09 13:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 10:49 [PATCH 0/3] Add Qualcomm SPEL powercap driver Manaf Meethalavalappu Pallikunhi
2026-05-19 10:49 ` [PATCH 1/3] dt-bindings: power: limits: Describe Qualcomm SPEL hardware Manaf Meethalavalappu Pallikunhi
2026-05-19 10:57 ` sashiko-bot
2026-05-19 17:40 ` Rob Herring (Arm)
2026-06-09 7:11 ` Manaf Meethalavalappu Pallikunhi
2026-05-30 12:29 ` Krzysztof Kozlowski
2026-06-09 7:35 ` Manaf Meethalavalappu Pallikunhi
2026-05-19 10:49 ` [PATCH 2/3] powercap: qcom: Add SPEL powercap driver Manaf Meethalavalappu Pallikunhi
2026-05-19 11:20 ` sashiko-bot
2026-05-21 11:16 ` Konrad Dybcio
2026-06-09 13:23 ` Manaf Meethalavalappu Pallikunhi [this message]
2026-06-09 13:31 ` Konrad Dybcio
2026-06-15 12:07 ` Daniel Lezcano
2026-06-16 9:45 ` Konrad Dybcio
2026-05-21 11:17 ` Konrad Dybcio
2026-06-09 13:24 ` Manaf Meethalavalappu Pallikunhi
2026-05-21 11:19 ` Konrad Dybcio
2026-06-09 13:26 ` Manaf Meethalavalappu Pallikunhi
2026-05-26 18:36 ` Daniel Lezcano
2026-06-10 19:33 ` Manaf Meethalavalappu Pallikunhi
2026-05-19 10:49 ` [PATCH 3/3] arm64: dts: qcom: glymur: Enable " Manaf Meethalavalappu Pallikunhi
2026-05-19 11:25 ` sashiko-bot
2026-05-30 12:32 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8f045340-a6c8-41c7-b1c7-6d9b87b05d90@oss.qualcomm.com \
--to=manaf.pallikunhi@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=daniel.lezcano@oss.qualcomm.com \
--cc=devicetree@vger.kernel.org \
--cc=gaurav.kohli@oss.qualcomm.com \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox