Re: [PATCH v3 7/9] iio: adc: ti-ads1262: support triggered buffer sampling

["Kurt Borja" <kuurtb@gmail.com>]

On Mon Aug 10, 2026 at 11:31 AM -05, David Lechner wrote:
> On 8/9/26 3:28 AM, Kurt Borja wrote:
>> On Sat Aug 8, 2026 at 1:39 PM -05, David Lechner wrote:
>>> On 8/7/26 10:58 PM, Kurt Borja wrote:
>>>> Add triggered buffer support and a data-ready (DRDY) hardware trigger.
>>>>
>
> ...
>
>>>
>>>> +	u8 tx[11] __aligned(IIO_DMA_MINALIGN);
>>>> +	u8 rx[11] __aligned(IIO_DMA_MINALIGN);
>>>
>>> don't need second one to be aligned, they aren't independent.
>> 
>> Ah, I forgot this observation in the last version. These are used in a
>> full-duplex transfer, wouldn't that require for both to be on its own
>> cache line? I just started learning about DMA.
>
> No. In this case, it works roughly like this...
>
> - We fill the TX buffer before the transfer. (CPU access to memory may
>   just live in the cache at this point and not actually be sent to RAM)
> - We request to start the SPI transfer.
> - The core SPI code flushes (or maybe I should say invalidates) the cache
>   on the TX buffer. This ensures that what we wrote with the CPU available
>   to DMA.
> - The actual SPI transfer happens that uses DMA to access both TX and
>   RX buffers. (Again, could just live in a cache and not be sent to RAM)
> - The SPI core code flushes the cache on the RX buffer. This ensures
>   that when the CPU reads the memory, it will see what the DMA just
>   wrote.

Oh, this makes a lot of sense.

>
> Since there isn't a time when CPU and DMA both write to the cache line
> at the same time before a flush, there is never a time we could have
> an issue with stale data replacing data that had not been flushed.
>
> It does mean that we can't update the tx buffer for the next message
> until after this message is done, but we have to do that anyway.
>
> What does cause problems is if we just had a regular unrelated variable
> after this in the cache line and the driver updated it during a SPI
> transfer. If this new value was just living in the CPU cache, then
> when the RX flush happened, it would write over that new value with
> stale data from the DMA's version of the cache.

Thanks! I'll look deeper into DMA, it's very interesting.

>
>
>> 
>> [...]
>> 
>>>> +static int ads1262_enable_and_read_last(struct ads1262 *st,
>>>> +					const struct iio_chan_spec *spec,
>>>> +					__be32 *val)
>>>> +{
>>>> +	struct ads1262_channel *chan;
>>>> +	int ret;
>>>> +
>>>> +	lockdep_assert_held(&st->xfer_lock);
>>>
>>> What happens if something else (e.g. gpio in the future) decides to do a
>>> register write here. If it wins the race, will it unintentionally read the
>>> data? So do we also need to read the stored data via command here too?
>> 
>> On each trigger, we are holding the lock before we enable the first
>> channel, until after we read the final conversion. So we don't really
>> care if there's concurrent activity in-between triggers. Am I missing
>> something?
>> 
> The datasheet doesn't seem clear on it, so I don't know if you are
> missing something or not, that is why I asked. :-)

I thought I was missing something obvious for a moment :p

>
> It looks to me like the way this is working is that that when data
> is ready, on the very next SPI transfer, the data is placed in the
> RX buffer no matter what is in the TX buffer. So I was imagining that
> if we got a DRDY interrupt, but someone happened to set a gpio output
> at the same time and the gpio request won the race for the lock, then
> when the gpio request was made, it would receive the RX data and trigger
> the next conversion while setting the gpio output, then then what was
> supposed to be receiving the data would receive I don't know what.

There are two conversion data registers: the shift register and the data
holding register. The holding register can only be accessed by command
(RDATA1). The shift register on the other hand is always shifting out
the last conversion in a loop *unless* we are reading a register (RREG)
or we are reading the holding register (RDATA1). This means, even if
there is concurrent activity in-between triggers, this activity will not
get accidentally corrupted.

Additionally, reading data doesn't trigger the next conversion. In
continuous mode it just keeps triggering after the first START signal.
In pulse mode we have to keep sending START signals. So, there is no
risk of concurrent activity from accidentally triggering conversions
either.

To read conversions from the shift register, the requirements are to not
have concurrent activity between the DRDY signal and the data read, and
to finish reading something like 16 clk cycles before the next DRDY.
That's why when reading only one channel we read by command, and when
reading multiple channels we first hold the xfer_lock, then enable the
channel, wait for DRDY and then read from the shift register. This
happens for the whole sequence of channels, so there is no risk of
corruption from concurrent activity happening in-between triggers.

Of course, as you pointed out in the patch, the current implementation
is still racy. That's why the next implementation will read multiple
channels in pulse mode, while still keeping the optimized full-duplex
method.

-- 
Thanks,
 ~ Kurt