Re: [PATCH v12 2/6] dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries

[Bryan O'Donoghue <bryan.odonoghue@linaro.org>]

On 09/07/2026 16:28, Vikram Sharma wrote:
> 
> On 7/9/2026 3:02 AM, Bryan O'Donoghue wrote:
>> On 08/07/2026 16:15, Vikram Sharma wrote:
>>>
>>> On 7/8/2026 5:36 AM, Bryan O'Donoghue wrote:
>>>>                iommus = <&apps_smmu 0x800 0x60>,
>>>> +                     <&apps_smmu 0x820 0x60>,
>>>> +                     <&apps_smmu 0x840 0x60>,
>>>>                         <&apps_smmu 0x860 0x60>,
>>>
>>> I think only "iommus = <&apps_smmu 0x800 0x60>" should be enough as mask which 0x60 is implicitly covering sids like 0x820, 0x840 and 0x860.
>>>
>>> Regards,
>>> Vikram
>>>
>>
>> These all come from the Hamoa iommu defintions in qcom docs.
>>
>> Can you double check for yourself and let me know.
> Hi Bryan,
> 
> Confirmed — all four SIDs (0x800, 0x820, 0x840, 0x860) are valid and documented for IFE/SFE. My point was specifically about how the ARM SMMU SMR matching logic handles these with the given mask.
> 
> In SMR hardware, the mask field marks bits as "don't care" during stream ID comparison. With SID = 0x800 and MASK = 0x60:
> 
> MASK = 0x60 = 0b 0110 0000  →  bits [6:5] are don't-care
> The four SIDs differ only in bits [6:5]:
> 
> 0x800 = 0b 1000 0000 0000  → bits[6:5] = 00
> 0x820 = 0b 1000 0010 0000  → bits[6:5] = 01
> 0x840 = 0b 1000 0100 0000  → bits[6:5] = 10
> 0x860 = 0b 1000 0110 0000  → bits[6:5] = 11
> 
> Since 0x60 masks out exactly those differing bits, a single entry <&apps_smmu 0x800 0x60> will match all four SIDs.
> 
> That said, I'd say this is more of a preference — both forms are functionally correct, and if you prefer keeping the four explicit entries for clarity or to stay aligned with how the Qcom docs enumerate them, that's perfectly fine too.
> 
> Regards,
> Vikram

I rote-copied with my brain switched off.

Your suggestion seems correct to me.

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bod