Re: [PATCH v2 4/6] arm64: dts: qcom: qcs6490-rb3gen2: label BT PMU and M.2 PCI node

[Rahul Samana <rahul.samana@oss.qualcomm.com>]

On 27-07-2026 21:15, Rahul Samana wrote:
> The reworked RB3 Gen 2 Industrial BT UART overlay needs to disable the
> on-board WCN6750 PMU and add a graph endpoint to the M.2 PCI node.
> 
> Label the exact WCN6750 PMU node and PCI child node connected to the M.2
> E-key slot so the overlay can patch them directly instead of using a full
> path or reconstructing the nested PCI hierarchy.
> 
> Signed-off-by: Rahul Samana <rahul.samana@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 37a3b51323ce..b2b6fd29880f 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -325,7 +325,7 @@ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
>  		regulator-enable-ramp-delay = <10000>;
>  	};
>  
> -	wcn6750-pmu {
> +	wcn6750_pmu: wcn6750-pmu {
>  		compatible = "qcom,wcn6750-pmu";
>  		pinctrl-0 = <&bt_en>;
>  		pinctrl-names = "default";
> @@ -901,7 +901,7 @@ pcie1_switch0_dsp1: pcie@1,0 {
>  			bus-range = <0x3 0xff>;
>  		};
>  
> -		pcie@2,0 {
> +		pcie0_m2_e: pcie@2,0 {
>  			reg = <0x21000 0x0 0x0 0x0 0x0>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> 

One correction for this patch:

After re-checking the composed devicetree and the device enumeration, the
QCC2072-facing PCIe path is behind the Industrial mezzanine PCIe0 switch:

    /soc@0/pcie@1c00000/pcie@0/pcie@0,0/pcie@2,0

The pcie@2,0 node labelled in qcs6490-rb3gen2.dts by this patch is under
the base RB3 PCIe1 topology, so it is not the right endpoint for the BT UART
variant.

I will fix this in v3 once the endpoint modelling approach is clarified.

Regards,
Rahul