[PATCH v4 0/2] arm64: dts: qcom: add IMEM and PIL regions for glymur

[PATCH v4 0/2] arm64: dts: qcom: add IMEM and PIL regions for glymur

[Ananthu C V]

This series adds dt binding and node for IMEM on glymur.

changes in v4:
 - picked up acked-by for the dt-binding
 - added dt node for imem on glymur
 - rebased the commits
 - link to v3: https://lore.kernel.org/all/20260129071435.2624252-1-ananthu.cv@oss.qualcomm.com/

changes in v3:
 - moved dt-binding to sram.yaml for mmio-sram fallback
 - link to v2: https://lore.kernel.org/all/20260123101501.2836551-2-ananthu.cv@oss.qualcomm.com/

changes in v2:
 - alphabetically sorted the placement of glymur in the list
 - link to v1: https://lore.kernel.org/all/20260122093319.2124906-1-ananthu.cv@oss.qualcomm.com/

Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
---
Ananthu C V (2):
      dt-bindings: sram: document glymur as compatible
      arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

 Documentation/devicetree/bindings/sram/sram.yaml |  1 +
 arch/arm64/boot/dts/qcom/glymur.dtsi             | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
---
base-commit: 6b346ee225a1747218759fc4846aacf203e1eb35
change-id: 20260327-glymur-imem-bfcf2288e5f8

Best regards,
--  
Ananthu C V <ananthu.cv@oss.qualcomm.com>

[PATCH v4 1/2] dt-bindings: sram: document glymur as compatible

[Ananthu C V]

Add compatible for Qualcomm's glymur IMEM, a block of sram which
can fall back to mmio-sram.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/sram/sram.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index c451140962c8..bd62711dc630 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -34,6 +34,7 @@ properties:
         - nvidia,tegra186-sysram
         - nvidia,tegra194-sysram
         - nvidia,tegra234-sysram
+        - qcom,glymur-imem
         - qcom,kaanapali-imem
         - qcom,rpm-msg-ram
         - rockchip,rk3288-pmu-sram

-- 
2.43.0

Re: [PATCH v4 1/2] dt-bindings: sram: document glymur as compatible

[Dmitry Baryshkov]

On Fri, Mar 27, 2026 at 03:24:35AM -0700, Ananthu C V wrote:
> Add compatible for Qualcomm's glymur IMEM, a block of sram which
> can fall back to mmio-sram.
> 
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/sram/sram.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
> index c451140962c8..bd62711dc630 100644
> --- a/Documentation/devicetree/bindings/sram/sram.yaml
> +++ b/Documentation/devicetree/bindings/sram/sram.yaml
> @@ -34,6 +34,7 @@ properties:
>          - nvidia,tegra186-sysram
>          - nvidia,tegra194-sysram
>          - nvidia,tegra234-sysram
> +        - qcom,glymur-imem

Is it different from the Kaanapali one?

>          - qcom,kaanapali-imem
>          - qcom,rpm-msg-ram
>          - rockchip,rk3288-pmu-sram
> 
> -- 
> 2.43.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH v4 1/2] dt-bindings: sram: document glymur as compatible

[Ananthu C V]

On Sun, Mar 29, 2026 at 02:05:23PM +0300, Dmitry Baryshkov wrote:
> On Fri, Mar 27, 2026 at 03:24:35AM -0700, Ananthu C V wrote:
> > Add compatible for Qualcomm's glymur IMEM, a block of sram which
> > can fall back to mmio-sram.
> > 
> > Acked-by: Rob Herring (Arm) <robh@kernel.org>
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
> >  Documentation/devicetree/bindings/sram/sram.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
> > index c451140962c8..bd62711dc630 100644
> > --- a/Documentation/devicetree/bindings/sram/sram.yaml
> > +++ b/Documentation/devicetree/bindings/sram/sram.yaml
> > @@ -34,6 +34,7 @@ properties:
> >          - nvidia,tegra186-sysram
> >          - nvidia,tegra194-sysram
> >          - nvidia,tegra234-sysram
> > +        - qcom,glymur-imem
> 
> Is it different from the Kaanapali one?

No, it is the same as the kaanapali imem.

> >          - qcom,kaanapali-imem
> >          - qcom,rpm-msg-ram
> >          - rockchip,rk3288-pmu-sram
> > 
> > -- 
> > 2.43.0
> > 
> 
> -- 
> With best wishes
> Dmitry

Best,
Ananthu

[PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

[Ananthu C V]

Add an IMEM on glymur which falls back to mmio-sram and define the
PIL relocation info region as its child, for post mortem tools to
locate the loaded remoteprocs.

Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 4886e87ebd49..21ae05f0ee17 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -6457,6 +6457,22 @@ rx-pins {
 			};
 		};
 
+		sram@14680000 {
+			compatible = "qcom,glymur-imem", "mmio-sram";
+			reg = <0x0 0x14680000 0x0 0x1000>;
+			ranges = <0 0 0x14680000 0x1000>;
+
+			no-memory-wc;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pil-sram@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
+			};
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,glymur-smmu-500",
 				     "qcom,smmu-500",

-- 
2.43.0

Re: [PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

[Konrad Dybcio]

On 3/27/26 11:24 AM, Ananthu C V wrote:
> Add an IMEM on glymur which falls back to mmio-sram and define the
> PIL relocation info region as its child, for post mortem tools to
> locate the loaded remoteprocs.
> 
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 4886e87ebd49..21ae05f0ee17 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -6457,6 +6457,22 @@ rx-pins {
>  			};
>  		};
>  
> +		sram@14680000 {
> +			compatible = "qcom,glymur-imem", "mmio-sram";
> +			reg = <0x0 0x14680000 0x0 0x1000>;
> +			ranges = <0 0 0x14680000 0x1000>;

size=0x2c_000

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

[Ananthu C V]

Hi Konrad,

On Wed, Apr 08, 2026 at 11:42:14AM +0200, Konrad Dybcio wrote:
> On 3/27/26 11:24 AM, Ananthu C V wrote:
> > Add an IMEM on glymur which falls back to mmio-sram and define the
> > PIL relocation info region as its child, for post mortem tools to
> > locate the loaded remoteprocs.
> > 
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 4886e87ebd49..21ae05f0ee17 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -6457,6 +6457,22 @@ rx-pins {
> >  			};
> >  		};
> >  
> > +		sram@14680000 {
> > +			compatible = "qcom,glymur-imem", "mmio-sram";
> > +			reg = <0x0 0x14680000 0x0 0x1000>;
> > +			ranges = <0 0 0x14680000 0x1000>;
> 
> size=0x2c_000

on glymur the imem region is a 4kb region of size 0x1000.

> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Thanks for the review.

> Konrad

Best,
Ananthu

Re: [PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

[Konrad Dybcio]

On 4/21/26 11:47 AM, Ananthu C V wrote:
> Hi Konrad,
> 
> On Wed, Apr 08, 2026 at 11:42:14AM +0200, Konrad Dybcio wrote:
>> On 3/27/26 11:24 AM, Ananthu C V wrote:
>>> Add an IMEM on glymur which falls back to mmio-sram and define the
>>> PIL relocation info region as its child, for post mortem tools to
>>> locate the loaded remoteprocs.
>>>
>>> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
>>>  1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> index 4886e87ebd49..21ae05f0ee17 100644
>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> @@ -6457,6 +6457,22 @@ rx-pins {
>>>  			};
>>>  		};
>>>  
>>> +		sram@14680000 {
>>> +			compatible = "qcom,glymur-imem", "mmio-sram";
>>> +			reg = <0x0 0x14680000 0x0 0x1000>;
>>> +			ranges = <0 0 0x14680000 0x1000>;
>>
>> size=0x2c_000
> 
> on glymur the imem region is a 4kb region of size 0x1000.

No.. that's the "shared" slice of it

Konrad

Re: [PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

[Ananthu C V]

On Wed, Apr 22, 2026 at 01:07:46PM +0200, Konrad Dybcio wrote:
> On 4/21/26 11:47 AM, Ananthu C V wrote:
> > Hi Konrad,
> > 
> > On Wed, Apr 08, 2026 at 11:42:14AM +0200, Konrad Dybcio wrote:
> >> On 3/27/26 11:24 AM, Ananthu C V wrote:
> >>> Add an IMEM on glymur which falls back to mmio-sram and define the
> >>> PIL relocation info region as its child, for post mortem tools to
> >>> locate the loaded remoteprocs.
> >>>
> >>> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> >>> ---
> >>>  arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
> >>>  1 file changed, 16 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> index 4886e87ebd49..21ae05f0ee17 100644
> >>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> @@ -6457,6 +6457,22 @@ rx-pins {
> >>>  			};
> >>>  		};
> >>>  
> >>> +		sram@14680000 {
> >>> +			compatible = "qcom,glymur-imem", "mmio-sram";
> >>> +			reg = <0x0 0x14680000 0x0 0x1000>;
> >>> +			ranges = <0 0 0x14680000 0x1000>;
> >>
> >> size=0x2c_000
> > 
> > on glymur the imem region is a 4kb region of size 0x1000.
> 
> No.. that's the "shared" slice of it

Indeed, I missed out on mentioning the "shared" word. The size of the whole
imem region is indeed 0x2c_000. I used kaanapali, which only mentions the
shared imem region, as a reference before. I'll make a revision to reflect
the whole imem region size. Thanks for the review.

Best,
Ananthu