Re: [PATCH v10 24/26] arm64: dts: mediatek: mt8195: Align ufshci node to dt-bindings changes

["Chaotian Jing (井朝天)" <Chaotian.Jing@mediatek.com>]

On Thu, 2026-07-30 at 11:49 +0200, Louis-Alexis Eyraud wrote:
> The MT8195 UFS host controller dt bindings now describe several extra
> required clocks that were previously missing from clock description
> and deprecates the freq-table-hz property use in favour of
> operating-points-v2 instead.
> 
> Currently, the ufshci node declares the freq-table-hz property but
> all
> values contained in the array are zero, thus converting it to an OPP
> table is not needed.
> 
> So, add in ufshci node the rx_symbol clocks in clock list and remove
> freq-table-hz property.
> Also reorder properties in node.
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Reviewed-by: Chaotian Jing <chaotian.jing@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 ++++++++++-----------
>  1 file changed, 10 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 9aaf8b6edcb5..5ff7b7e543b7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1472,8 +1472,7 @@ mmc2: mmc@11250000 {
>  		ufshci: ufshci@11270000 {
>  			compatible = "mediatek,mt8195-ufshci";
>  			reg = <0 0x11270000 0 0x2300>;
> -			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH
> 0>;
> -			phys = <&ufsphy>;
> +
>  			clocks = <&infracfg_ao
> CLK_INFRA_AO_AES_UFSFDE>,
>  				 <&infracfg_ao CLK_INFRA_AO_AES>,
>  				 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
> @@ -1481,15 +1480,15 @@ ufshci: ufshci@11270000 {
>  				 <&infracfg_ao
> CLK_INFRA_AO_UNIPRO_TICK>,
>  				 <&infracfg_ao
> CLK_INFRA_AO_UFS_MP_SAP_B>,
>  				 <&infracfg_ao
> CLK_INFRA_AO_UFS_TX_SYMBOL>,
> -				 <&infracfg_ao
> CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
> -			clock-names = "ufs", "ufs_aes", "ufs_tick",
> -					"unipro_sysclk", "unipro_tick",
> -					"unipro_mp_bclk",
> "ufs_tx_symbol",
> -					"ufs_mem_sub";
> -			freq-table-hz = <0 0>, <0 0>, <0 0>,
> -					<0 0>, <0 0>, <0 0>,
> -					<0 0>, <0 0>;
> -
> +				 <&infracfg_ao
> CLK_INFRA_AO_PERI_UFS_MEM_SUB>,
> +				 <&topckgen CLK_TOP_UFS_RX_SYMBOL>,
> +				 <&topckgen CLK_TOP_UFS_RX_SYMBOL1>;
> +			clock-names = "main", "aes", "tick",
> "unipro_sysclk",
> +				      "unipro_tick", "unipro_mp_bclk",
> +				      "tx_symbol", "mem_sub",
> "rx_symbol0",
> +				      "rx_symbol1";
> +			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH
> 0>;
> +			phys = <&ufsphy>;
>  			mediatek,ufs-disable-mcq;
>  			status = "disabled";
>  		};
>