[PATCH v4 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator

[PATCH v4 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add support for the ESWIN EIC7700 HSP (high-speed peripherals). The drivers
provide basic functionality to manage and control the clock and reset
signals for EIC7700 HSP, including mmc, USB, ethernet, SATA and DMAC.

The clock and reset registers are mapped to overlapping I/O address ranges.
This causes a resource conflict when two drivers attempt to request the
same region. Use the auxiliary device framework: the main driver
allocates the shared register region and passes it to auxiliary
devices, avoiding resource contention and duplicate remapping.

Features:
Implements support for the ESWIN EIC7700 HSP clock and reset controller.
Provide API to manage clock and reset signals for the EIC7700 HSP.

Supported chips:
ESWIN EIC7700 series SoC.

Test:
Test this patch on the Sifive HiFive Premier P550 (which used the EIC7700
SoC), include USB and other peripherals. All the drivers of these modules
use the clock module and reset module.

Updates:
  Changes in v4:
  - Clock driver:
    - Remove "Reviewed-by: Benoît Monin <benoit.monin@bootlin.com>" and
      "Reviewed-by: Brian Masney <bmasney@redhat.com>", because the clock
      driver has been updated.
    - Remove inclusion of io.h.
    - Add struct regmap to eic7700_hsp_clk_gate.
      Replace 'void __iomem *reg' with 'unsigned int reg'.
      Replace 'void __iomem *ref_reg' with 'unsigned int ref_reg'.
      Replace long with int for 'offset' and 'ref_offset'.
      Remove 'spinlock_t *lock'.
      Apply the same changes to hsp_clk_register_gate().
    - Remove the structure eic7700_hsp_regmap_lock, and the functions
      eic7700_hsp_regmap_lock() and eic7700_hsp_regmap_unlock().
    - Remove the 'guard(spinlock_irqsave)(gate->lock)' in
      hsp_clk_gate_endisable().
    - Replace readl() and writel() with regmap_assign_bits() in
      hsp_clk_gate_endisable().
    - Change the parameter enable from int to bool.
    - Replace readl() with regmap_read() in hsp_clk_gate_is_enabled().
    - Remove the lock_ctx variable.
    - Move eic7700_hsp_regmap_config from inside the probe function to global
      scope.
      Remove '.lock', '.unlock' and 'lock_arg'.
      Add '.fast_io = true' and '.use_raw_spinlock = true'.
  - Reset driver:
    - Add "Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>" for reset.
    - Drop the temporary variable, just return regmap_assign_bits(...) directly.
    - Replace -EINVAL with -ENODEV for dev_get_regmap() check.
    - Drop the '_dt'.

  - Link to v3: https://lore.kernel.org/all/20260423090904.2108-1-dongxuyang@eswincomputing.com/

  Changes in v3:
  - Bindings:
    - Added "Acked-by: Conor Dooley <conor.dooley@microchip.com>" for bindings.
  - Clock driver:
    - Remove 'gate_flags'.
    - Add __acquires for eic7700_hsp_regmap_lock() and add __releases for
      eic7700_hsp_regmap_unlock().
    - Move writel(USB_REF_XTAL24M, gate->ref_reg) into enable. Because this
      is only used for USB gate clock on the enable path. And modify the
      comments.
    - Simplify to: 'return !!(readl(gate->reg) & BIT(gate->bit_idx));'.
    - Drop const from eic7700_hsp_regmap_config.
    - Declare eic7700_hsp_regmap_config as a regular variable at the top.

  - Link to v2: https://lore.kernel.org/all/20260420093929.1895-1-dongxuyang@eswincomputing.com/

  Changes in v2:
  - Bindings:
    - Remove "hsp_" from clock-names.
    - Replace "eswin,eic7700-clock.yaml" and "eswin,eic7700-hspcrg.yaml" with
      "eswin,eic7700*".
    - Replace "eswin,eic7700-clock.h" and "eswin,eic7700-hspcrg.h" with
      "eswin,eic7700*".
  - Clock driver:
    - Use guard(spinlock_irqsave)(gate->lock) instead of spin_lock_irqsave()
      and remove spin_unlock_irqrestore().
    - Remove the newline in function hsp_clk_gate_is_enabled().
    - Use struct clk_init_data init = {}.
    - Replace 'static struct clk_parent_data' with
      'static const struct clk_parent_data'.
    - Change '.fw_name' to '.index', because the function
      eswin_clk_register_fixed_factor() uses .index.
    - The structures of clocks should use static struct. When registering a clock,
      the 'hw' field in the structure will be assigned.
    - Remove __force.
    - Create the regmap in the clock driver and remove (__force void*)data->base.
      The reset driver uses dev_get_regmap() to get the regmap from the clock.
    - Move 'const struct regmap_config eic7700_hsp_regmap_config' from reset
      driver to clock driver.
    - The USB clock gate (hsp_clk_gate_endisable) and the reset driver both
      perform read-modify-write cycles on registers 0x800 and 0x900. Use
      custom regmap lock callbacks so that regmap operations hold data->lock
      with IRQs disabled, the same lock the clock gate path uses, preventing
      concurrent RMW races on those shared registers.
    - Change to 'ret = eswin_clk_register_fixed_factor(dev, eic7700_hsp_factor_clks,'.
      The next line will be over 80 characters and under 100 characters.
  - Reset driver:
    - Remove 'depends on COMMON_CLK_EIC7700_HSP' and 'default COMMON_CLK_EIC7700_HSP'.
    - Use regmap_assign_bits() in assert and deassert functions.
    - Remove eic7700_hsp_reset_reset().
    - The clock driver creates the regmap, and the reset driver uses dev_get_regmap().
    - Remove of_reset_n_cells.

  - Link to v1: https://lore.kernel.org/all/20260403093459.612-1-dongxuyang@eswincomputing.com/

Xuyang Dong (3):
  dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator
  clk: eswin: Add eic7700 HSP clock driver
  reset: eswin: Add eic7700 HSP reset driver

 .../bindings/clock/eswin,eic7700-hspcrg.yaml  |  63 ++++
 MAINTAINERS                                   |   5 +-
 drivers/clk/eswin/Kconfig                     |  12 +
 drivers/clk/eswin/Makefile                    |   1 +
 drivers/clk/eswin/clk-eic7700-hsp.c           | 338 ++++++++++++++++++
 drivers/reset/Kconfig                         |  11 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-eic7700-hsp.c             | 112 ++++++
 .../dt-bindings/clock/eswin,eic7700-hspcrg.h  |  33 ++
 .../dt-bindings/reset/eswin,eic7700-hspcrg.h  |  21 ++
 10 files changed, 595 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
 create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c
 create mode 100644 drivers/reset/reset-eic7700-hsp.c
 create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
 create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h

--
2.34.1

[PATCH v4 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add bindings for the high-speed peripherals clock and reset generator
on the ESWIN EIC7700 HSP.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../bindings/clock/eswin,eic7700-hspcrg.yaml  | 63 +++++++++++++++++++
 MAINTAINERS                                   |  5 +-
 .../dt-bindings/clock/eswin,eic7700-hspcrg.h  | 33 ++++++++++
 .../dt-bindings/reset/eswin,eic7700-hspcrg.h  | 21 +++++++
 4 files changed, 120 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
 create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
 create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h

diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
new file mode 100644
index 000000000000..43df689ae647
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 HSP Clock and Reset Generator
+
+maintainers:
+  - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+  Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
+
+properties:
+  compatible:
+    const: eswin,eic7700-hspcrg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: HSP configuration top clock
+      - description: MMC top clock
+      - description: SATA top clock
+
+  clock-names:
+    items:
+      - const: cfg
+      - const: mmc
+      - const: sata
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
+
+  '#reset-cells':
+    const: 1
+    description:
+      See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@50440000 {
+        compatible = "eswin,eic7700-hspcrg";
+        reg = <0x50440000 0x2000>;
+        clocks = <&clock 171>, <&clock 254>, <&clock 187>;
+        clock-names = "cfg", "mmc", "sata";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index b2040011a386..b7180863310c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9548,9 +9548,10 @@ ESWIN EIC7700 CLOCK DRIVER
 M:	Yifeng Huang <huangyifeng@eswincomputing.com>
 M:	Xuyang Dong <dongxuyang@eswincomputing.com>
 S:	Maintained
-F:	Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+F:	Documentation/devicetree/bindings/clock/eswin,eic7700*
 F:	drivers/clk/eswin/
-F:	include/dt-bindings/clock/eswin,eic7700-clock.h
+F:	include/dt-bindings/clock/eswin,eic7700*
+F:	include/dt-bindings/reset/eswin,eic7700-hspcrg.h
 
 ET131X NETWORK DRIVER
 M:	Mark Einon <mark.einon@gmail.com>
diff --git a/include/dt-bindings/clock/eswin,eic7700-hspcrg.h b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..1d1ff15c1154
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP clock controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+
+#define EIC7700_HSP_CLK_FAC_CFG_DIV2		0
+#define EIC7700_HSP_CLK_FAC_CFG_DIV4		1
+#define EIC7700_HSP_CLK_FAC_MMC_DIV10		2
+#define EIC7700_HSP_CLK_MUX_EMMC_3MUX1		3
+#define EIC7700_HSP_CLK_MUX_SD0_3MUX1		4
+#define EIC7700_HSP_CLK_MUX_SD1_3MUX1		5
+#define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1	6
+#define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1	7
+#define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1	8
+#define EIC7700_HSP_CLK_GATE_MSHC0_TMR		9
+#define EIC7700_HSP_CLK_GATE_EMMC		10
+#define EIC7700_HSP_CLK_GATE_MSHC1_TMR		11
+#define EIC7700_HSP_CLK_GATE_SD0		12
+#define EIC7700_HSP_CLK_GATE_MSHC2_TMR		13
+#define EIC7700_HSP_CLK_GATE_SD1		14
+#define EIC7700_HSP_CLK_GATE_USB0		15
+#define EIC7700_HSP_CLK_GATE_USB1		16
+#define EIC7700_HSP_CLK_GATE_SATA		17
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */
diff --git a/include/dt-bindings/reset/eswin,eic7700-hspcrg.h b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..413fcd08c701
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP reset controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+
+#define EIC7700_HSP_RST_SATA_P0		0
+#define EIC7700_HSP_RST_SATA_PHY	1
+#define EIC7700_HSP_RST_USB0		2
+#define EIC7700_HSP_RST_USB1		3
+#define EIC7700_HSP_RST_USB0_PHY	4
+#define EIC7700_HSP_RST_USB1_PHY	5
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_ */
-- 
2.34.1

[PATCH v4 2/3] clk: eswin: Add eic7700 HSP clock driver

[Xuyang Dong]

Add driver for the ESWIN EIC7700 high-speed peripherals system
clock controller and register an auxiliary device for system
reset controller which is named as "hsp-reset".

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 drivers/clk/eswin/Kconfig           |  12 +
 drivers/clk/eswin/Makefile          |   1 +
 drivers/clk/eswin/clk-eic7700-hsp.c | 338 ++++++++++++++++++++++++++++
 3 files changed, 351 insertions(+)
 create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c

diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig
index 0406ec499ec9..e6cc2a407bac 100644
--- a/drivers/clk/eswin/Kconfig
+++ b/drivers/clk/eswin/Kconfig
@@ -13,3 +13,15 @@ config COMMON_CLK_EIC7700
 	  SoC. The clock controller generates and supplies clocks to various
 	  peripherals within the SoC.
 	  Say yes here to support the clock controller on the EIC7700 SoC.
+
+config COMMON_CLK_EIC7700_HSP
+	tristate "EIC7700 HSP Clock Driver"
+	depends on ARCH_ESWIN || COMPILE_TEST
+	select AUXILIARY_BUS
+	select COMMON_CLK_EIC7700
+	select RESET_EIC7700_HSP if RESET_CONTROLLER
+	help
+	  This driver provides support for clock controller on ESWIN EIC7700
+	  HSP. The clock controller generates and supplies clocks to high
+	  speed peripherals within the SoC.
+	  Say yes here to support the clock controller on the EIC7700 HSP.
diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile
index 4a7c2af82164..21a09a3396df 100644
--- a/drivers/clk/eswin/Makefile
+++ b/drivers/clk/eswin/Makefile
@@ -6,3 +6,4 @@
 obj-$(CONFIG_COMMON_CLK_ESWIN)		+= clk.o
 
 obj-$(CONFIG_COMMON_CLK_EIC7700)	+= clk-eic7700.o
+obj-$(CONFIG_COMMON_CLK_EIC7700_HSP)	+= clk-eic7700-hsp.o
diff --git a/drivers/clk/eswin/clk-eic7700-hsp.c b/drivers/clk/eswin/clk-eic7700-hsp.c
new file mode 100644
index 000000000000..0d5bd5b705dc
--- /dev/null
+++ b/drivers/clk/eswin/clk-eic7700-hsp.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * ESWIN EIC7700 HSP Clock Driver
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/eswin,eic7700-hspcrg.h>
+
+#include "common.h"
+
+#define EIC7700_HSP_SATA_REG		0x300
+#define EIC7700_HSP_MSHC0_REG		0x510
+#define EIC7700_HSP_MSHC1_REG		0x610
+#define EIC7700_HSP_MSHC2_REG		0x710
+#define EIC7700_HSP_USB0_REG		0x800
+#define EIC7700_HSP_USB0_REF_REG	0x83c
+#define EIC7700_HSP_USB1_REG		0x900
+#define EIC7700_HSP_USB1_REF_REG	0x93c
+
+#define USB_REF_XTAL24M			0x2a
+#define EIC7700_HSP_NR_CLKS		(EIC7700_HSP_CLK_GATE_SATA + 1)
+
+struct eic7700_hsp_clk_gate {
+	struct clk_hw hw;
+	unsigned int id;
+	struct regmap *regmap;
+	unsigned int reg;
+	unsigned int ref_reg;
+	const char *name;
+	const struct clk_parent_data *parent_data;
+	unsigned long flags;
+	unsigned int offset;
+	unsigned int ref_offset;
+	u8 bit_idx;
+};
+
+static const struct regmap_config eic7700_hsp_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.max_register = 0x1ffc,
+	.reg_stride = 4,
+	.fast_io = true,
+	.use_raw_spinlock = true,
+};
+
+static inline struct eic7700_hsp_clk_gate *to_gate_clk(struct clk_hw *hw)
+{
+	return container_of(hw, struct eic7700_hsp_clk_gate, hw);
+}
+
+#define EIC7700_HSP_GATE(_id, _name, _pdata, _flags, _offset, _idx,	\
+			 _ref_offset)					\
+	{								\
+		.id		= _id,					\
+		.name		= _name,				\
+		.parent_data	= _pdata,				\
+		.flags		= _flags,				\
+		.offset		= _offset,				\
+		.ref_offset	= _ref_offset,				\
+		.bit_idx	= _idx,					\
+	}
+
+static void hsp_clk_gate_endisable(struct clk_hw *hw, bool enable)
+{
+	struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
+
+	if (enable) {
+		/*
+		 * Hardware bug: The USB reference clock must be 24MHz.
+		 * The default register value after reset is invalid.
+		 * Workaround: Rewrite the correct value before enabling
+		 * the USB gate clock.
+		 */
+		regmap_update_bits(gate->regmap, gate->ref_reg, 0x3f,
+				   USB_REF_XTAL24M);
+	}
+	regmap_assign_bits(gate->regmap, gate->reg, BIT(gate->bit_idx), enable);
+}
+
+static int hsp_clk_gate_enable(struct clk_hw *hw)
+{
+	hsp_clk_gate_endisable(hw, true);
+
+	return 0;
+}
+
+static void hsp_clk_gate_disable(struct clk_hw *hw)
+{
+	hsp_clk_gate_endisable(hw, false);
+}
+
+static int hsp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+	struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
+	unsigned int val;
+
+	regmap_read(gate->regmap, gate->reg, &val);
+
+	return !!(val & BIT(gate->bit_idx));
+}
+
+static const struct clk_ops hsp_clk_gate_ops = {
+	.enable = hsp_clk_gate_enable,
+	.disable = hsp_clk_gate_disable,
+	.is_enabled = hsp_clk_gate_is_enabled,
+};
+
+static struct clk_hw *
+hsp_clk_register_gate(struct device *dev, unsigned int id, const char *name,
+		      const struct clk_parent_data *parent_data,
+		      unsigned long flags, struct regmap *regmap,
+		      unsigned int reg, unsigned int ref_reg, u8 bit_idx)
+{
+	struct eic7700_hsp_clk_gate *gate;
+	struct clk_init_data init = {};
+	struct clk_hw *hw;
+	int ret;
+
+	gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &hsp_clk_gate_ops;
+	init.flags = flags;
+	init.parent_data = parent_data;
+	init.num_parents = 1;
+
+	gate->id = id;
+	gate->regmap = regmap;
+	gate->reg = reg;
+	gate->ref_reg = ref_reg;
+	gate->bit_idx = bit_idx;
+	gate->hw.init = &init;
+
+	hw = &gate->hw;
+	ret = devm_clk_hw_register(dev, hw);
+	if (ret)
+		hw = ERR_PTR(ret);
+
+	return hw;
+}
+
+static const struct clk_parent_data hsp_cfg[] = {
+	{ .index = 0 }
+};
+
+static const struct clk_parent_data hsp_mmc[] = {
+	{ .index = 1 }
+};
+
+static const struct clk_parent_data hsp_usb_sata[] = {
+	{ .index = 2 }
+};
+
+static struct eswin_fixed_factor_clock eic7700_hsp_factor_clks[] = {
+	ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV2, "factor_hsp_cfg_div2",
+		     hsp_cfg, 1, 2, 0),
+	ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV4, "factor_hsp_cfg_div4",
+		     hsp_cfg, 1, 4, 0),
+	ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_MMC_DIV10, "factor_hsp_mmc_div10",
+		     hsp_mmc, 1, 10, 0),
+};
+
+static struct eswin_gate_clock eic7700_hsp_gate_clks[] = {
+	ESWIN_GATE(EIC7700_HSP_CLK_GATE_SATA, "gate_clk_hsp_sata", hsp_usb_sata,
+		   CLK_SET_RATE_PARENT, EIC7700_HSP_SATA_REG, 28, 0),
+	ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC0_TMR, "gate_clk_hsp_mshc0_tmr",
+		   hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 8, 0),
+	ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC1_TMR, "gate_clk_hsp_mshc1_tmr",
+		   hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 8, 0),
+	ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC2_TMR, "gate_clk_hsp_mshc2_tmr",
+		   hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 8, 0),
+};
+
+static struct eic7700_hsp_clk_gate eic7700_hsp_spec_gate_clks[] = {
+	EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB0, "gate_clk_hsp_usb0",
+			 hsp_usb_sata, CLK_SET_RATE_PARENT,
+			 EIC7700_HSP_USB0_REG, 28, EIC7700_HSP_USB0_REF_REG),
+	EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB1, "gate_clk_hsp_usb1",
+			 hsp_usb_sata, CLK_SET_RATE_PARENT,
+			 EIC7700_HSP_USB1_REG, 28, EIC7700_HSP_USB1_REF_REG),
+};
+
+static const struct clk_parent_data mux_mmc_3mux1_p[] = {
+	{ .fw_name = "cfg" },
+	{ .hw = &eic7700_hsp_factor_clks[0].hw },
+	{ .hw = &eic7700_hsp_factor_clks[1].hw },
+};
+
+static const struct clk_parent_data mux_mmc_2mux1_p[] = {
+	{ .fw_name = "mmc" },
+	{ .hw = &eic7700_hsp_factor_clks[2].hw },
+};
+
+static u32 mux_mmc_3mux1_tbl[] = { 0x0, 0x1, 0x3 };
+
+static struct eswin_mux_clock eic7700_hsp_mux_clks[] = {
+	ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_EMMC_3MUX1, "mux_hsp_emmc_3mux1",
+		      mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+		      CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 16, 2, 0,
+		      mux_mmc_3mux1_tbl),
+	ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD0_3MUX1, "mux_hsp_sd0_3mux1",
+		      mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+		      CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 16, 2, 0,
+		      mux_mmc_3mux1_tbl),
+	ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD1_3MUX1, "mux_hsp_sd1_3mux1",
+		      mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+		      CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 16, 2, 0,
+		      mux_mmc_3mux1_tbl),
+	ESWIN_MUX(EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1, "mux_hsp_emmc_cqe_2mux1",
+		  mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+		  CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 0, 1, 0),
+	ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1, "mux_hsp_sd0_cqe_2mux1",
+		  mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+		  CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 0, 1, 0),
+	ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1, "mux_hsp_sd1_cqe_2mux1",
+		  mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+		  CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 0, 1, 0),
+};
+
+static struct eswin_clk_info eic7700_hsp_clks[] = {
+	ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_EMMC, "gate_clk_hsp_emmc",
+			EIC7700_HSP_CLK_MUX_EMMC_3MUX1,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			EIC7700_HSP_MSHC0_REG, 24, 0),
+	ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD0, "gate_clk_hsp_sd0",
+			EIC7700_HSP_CLK_MUX_SD0_3MUX1,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			EIC7700_HSP_MSHC1_REG, 24, 0),
+	ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD1, "gate_clk_hsp_sd1",
+			EIC7700_HSP_CLK_MUX_SD1_3MUX1,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			EIC7700_HSP_MSHC2_REG, 24, 0),
+};
+
+static int eic7700_hsp_clk_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct auxiliary_device *adev;
+	struct eswin_clock_data *data;
+	struct regmap *regmap;
+	struct clk_hw *hw;
+	int i, ret;
+
+	data = eswin_clk_init(pdev, EIC7700_HSP_NR_CLKS);
+	if (IS_ERR(data))
+		return dev_err_probe(dev, PTR_ERR(data),
+				     "failed to get clk data!\n");
+
+	regmap = devm_regmap_init_mmio(dev, data->base,
+				       &eic7700_hsp_regmap_config);
+	if (IS_ERR(regmap))
+		return dev_err_probe(dev, PTR_ERR(regmap),
+				     "failed to get regmap!\n");
+
+	ret = eswin_clk_register_fixed_factor(dev, eic7700_hsp_factor_clks,
+					      ARRAY_SIZE(eic7700_hsp_factor_clks),
+					      data);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to register fixed factor clock\n");
+
+	ret = eswin_clk_register_gate(dev, eic7700_hsp_gate_clks,
+				      ARRAY_SIZE(eic7700_hsp_gate_clks), data);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to register gate clock\n");
+
+	ret = eswin_clk_register_mux(dev, eic7700_hsp_mux_clks,
+				     ARRAY_SIZE(eic7700_hsp_mux_clks),
+				     data);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to register mux clock\n");
+
+	ret = eswin_clk_register_clks(dev, eic7700_hsp_clks,
+				      ARRAY_SIZE(eic7700_hsp_clks), data);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to register clock\n");
+
+	for (i = 0; i < ARRAY_SIZE(eic7700_hsp_spec_gate_clks); i++) {
+		struct eic7700_hsp_clk_gate *gate;
+
+		gate = &eic7700_hsp_spec_gate_clks[i];
+		hw = hsp_clk_register_gate(dev, gate->id, gate->name,
+					   gate->parent_data, gate->flags,
+					   regmap, gate->offset,
+					   gate->ref_offset, gate->bit_idx);
+		if (IS_ERR(hw))
+			return dev_err_probe(dev, PTR_ERR(hw),
+					     "failed to register gate clock\n");
+
+		data->clk_data.hws[gate->id] = hw;
+	}
+
+	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+					  &data->clk_data);
+	if (ret)
+		return dev_err_probe(dev, ret, "add clk provider failed\n");
+
+	adev = devm_auxiliary_device_create(dev, "hsp-reset", NULL);
+	if (!adev)
+		return dev_err_probe(dev, -ENODEV,
+				     "register hsp-reset device failed\n");
+
+	return 0;
+}
+
+static const struct of_device_id eic7700_hsp_clock_dt_ids[] = {
+	{ .compatible = "eswin,eic7700-hspcrg", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, eic7700_hsp_clock_dt_ids);
+
+static struct platform_driver eic7700_hsp_clock_driver = {
+	.probe	= eic7700_hsp_clk_probe,
+	.driver = {
+		.name	= "eic7700-hsp-clock",
+		.of_match_table	= eic7700_hsp_clock_dt_ids,
+	},
+};
+
+module_platform_driver(eic7700_hsp_clock_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
+MODULE_DESCRIPTION("ESWIN EIC7700 HSP clock controller driver");
-- 
2.34.1

[PATCH v4 3/3] reset: eswin: Add eic7700 HSP reset driver

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add auxiliary driver to support ESWIN EIC7700 high-speed peripherals
system. The reset controller is created using the auxiliary device
framework and set up in the clock driver.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 drivers/reset/Kconfig             |  11 +++
 drivers/reset/Makefile            |   1 +
 drivers/reset/reset-eic7700-hsp.c | 112 ++++++++++++++++++++++++++++++
 3 files changed, 124 insertions(+)
 create mode 100644 drivers/reset/reset-eic7700-hsp.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d009eb0849a3..f63e89ed6a4e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -83,6 +83,17 @@ config RESET_EIC7700
 	  The driver supports eic7700 series chips and provides functionality for
 	  asserting and deasserting resets on the chip.
 
+config RESET_EIC7700_HSP
+	tristate "EIC7700 HSP Reset controller"
+	depends on ARCH_ESWIN || COMPILE_TEST
+	select AUXILIARY_BUS
+	help
+	  This enables the HSP reset controller driver for ESWIN SoCs. This
+	  driver is specific to ESWIN SoCs and should only be enabled if using
+	  such hardware.
+	  The driver supports EIC7700 series chips and provides functionality
+	  for asserting and deasserting resets on the chip.
+
 config RESET_EYEQ
 	bool "Mobileye EyeQ reset controller"
 	depends on EYEQ || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e52569bd276..a75af831ef58 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
 obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
+obj-$(CONFIG_RESET_EIC7700_HSP) += reset-eic7700-hsp.o
 obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
 obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
diff --git a/drivers/reset/reset-eic7700-hsp.c b/drivers/reset/reset-eic7700-hsp.c
new file mode 100644
index 000000000000..bdd4f5e3d7a7
--- /dev/null
+++ b/drivers/reset/reset-eic7700-hsp.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * ESWIN EIC7700 HSP Reset Driver
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/eswin,eic7700-hspcrg.h>
+
+/**
+ * struct eic7700_hsp_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @regmap: regmap handle containing the memory-mapped reset registers
+ */
+struct eic7700_hsp_reset_data {
+	struct reset_controller_dev rcdev;
+	struct regmap *regmap;
+};
+
+struct eic7700_hsp_reg {
+	u32 reg;
+	u32 bit;
+	bool active_low;
+};
+
+static inline struct eic7700_hsp_reset_data *
+to_eic7700_hsp_reset(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct eic7700_hsp_reset_data, rcdev);
+}
+
+static const struct eic7700_hsp_reg eic7700_hsp_reset[] = {
+	[EIC7700_HSP_RST_SATA_P0]	= {0x340, BIT(0), false},
+	[EIC7700_HSP_RST_SATA_PHY]	= {0x340, BIT(1), false},
+	[EIC7700_HSP_RST_USB0]		= {0x800, BIT(24), true},
+	[EIC7700_HSP_RST_USB1]		= {0x900, BIT(24), true},
+	[EIC7700_HSP_RST_USB0_PHY]	= {0x800, BIT(25), false},
+	[EIC7700_HSP_RST_USB1_PHY]	= {0x900, BIT(25), false},
+};
+
+static int eic7700_hsp_reset_assert(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	struct eic7700_hsp_reset_data *data = to_eic7700_hsp_reset(rcdev);
+
+	return regmap_assign_bits(data->regmap, eic7700_hsp_reset[id].reg,
+				  eic7700_hsp_reset[id].bit,
+				  !eic7700_hsp_reset[id].active_low);
+}
+
+static int eic7700_hsp_reset_deassert(struct reset_controller_dev *rcdev,
+				      unsigned long id)
+{
+	struct eic7700_hsp_reset_data *data = to_eic7700_hsp_reset(rcdev);
+
+	return regmap_assign_bits(data->regmap, eic7700_hsp_reset[id].reg,
+				  eic7700_hsp_reset[id].bit,
+				  eic7700_hsp_reset[id].active_low);
+}
+
+static const struct reset_control_ops eic7700_hsp_reset_ops = {
+	.assert = eic7700_hsp_reset_assert,
+	.deassert = eic7700_hsp_reset_deassert,
+};
+
+static int eic7700_hsp_reset_probe(struct auxiliary_device *adev,
+				   const struct auxiliary_device_id *id)
+{
+	struct eic7700_hsp_reset_data *data;
+	struct device *dev = &adev->dev;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->regmap = dev_get_regmap(dev->parent, NULL);
+	if (!data->regmap)
+		return dev_err_probe(dev, -ENODEV, "failed to get regmap!\n");
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = &eic7700_hsp_reset_ops;
+	data->rcdev.of_node = dev->parent->of_node;
+	data->rcdev.dev = dev;
+	data->rcdev.nr_resets = ARRAY_SIZE(eic7700_hsp_reset);
+
+	return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct auxiliary_device_id eic7700_hsp_reset_ids[] = {
+	{ .name = "clk_eic7700_hsp.hsp-reset", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, eic7700_hsp_reset_ids);
+
+static struct auxiliary_driver eic7700_hsp_reset_driver = {
+	.probe	= eic7700_hsp_reset_probe,
+	.id_table = eic7700_hsp_reset_ids,
+};
+
+module_auxiliary_driver(eic7700_hsp_reset_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
+MODULE_DESCRIPTION("ESWIN EIC7700 HSP Reset Controller Driver");
-- 
2.34.1

Re: [PATCH v4 2/3] clk: eswin: Add eic7700 HSP clock driver

[Brian Masney]

Hi Xuyang,

On Tue, May 12, 2026 at 10:07:47AM +0800, Xuyang Dong wrote:
> Add driver for the ESWIN EIC7700 high-speed peripherals system
> clock controller and register an auxiliary device for system
> reset controller which is named as "hsp-reset".
> 
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> ---
>  drivers/clk/eswin/Kconfig           |  12 +
>  drivers/clk/eswin/Makefile          |   1 +
>  drivers/clk/eswin/clk-eic7700-hsp.c | 338 ++++++++++++++++++++++++++++
>  3 files changed, 351 insertions(+)
>  create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c
> 
> diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig
> index 0406ec499ec9..e6cc2a407bac 100644
> --- a/drivers/clk/eswin/Kconfig
> +++ b/drivers/clk/eswin/Kconfig
> @@ -13,3 +13,15 @@ config COMMON_CLK_EIC7700
>  	  SoC. The clock controller generates and supplies clocks to various
>  	  peripherals within the SoC.
>  	  Say yes here to support the clock controller on the EIC7700 SoC.
> +
> +config COMMON_CLK_EIC7700_HSP
> +	tristate "EIC7700 HSP Clock Driver"
> +	depends on ARCH_ESWIN || COMPILE_TEST
> +	select AUXILIARY_BUS
> +	select COMMON_CLK_EIC7700
> +	select RESET_EIC7700_HSP if RESET_CONTROLLER
> +	help
> +	  This driver provides support for clock controller on ESWIN EIC7700
> +	  HSP. The clock controller generates and supplies clocks to high
> +	  speed peripherals within the SoC.
> +	  Say yes here to support the clock controller on the EIC7700 HSP.
> diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile
> index 4a7c2af82164..21a09a3396df 100644
> --- a/drivers/clk/eswin/Makefile
> +++ b/drivers/clk/eswin/Makefile
> @@ -6,3 +6,4 @@
>  obj-$(CONFIG_COMMON_CLK_ESWIN)		+= clk.o
>  
>  obj-$(CONFIG_COMMON_CLK_EIC7700)	+= clk-eic7700.o
> +obj-$(CONFIG_COMMON_CLK_EIC7700_HSP)	+= clk-eic7700-hsp.o
> diff --git a/drivers/clk/eswin/clk-eic7700-hsp.c b/drivers/clk/eswin/clk-eic7700-hsp.c
> new file mode 100644
> index 000000000000..0d5bd5b705dc
> --- /dev/null
> +++ b/drivers/clk/eswin/clk-eic7700-hsp.c
> @@ -0,0 +1,338 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
> + * All rights reserved.
> + *
> + * ESWIN EIC7700 HSP Clock Driver
> + *
> + * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
> + */
> +
> +#include <linux/auxiliary_bus.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/eswin,eic7700-hspcrg.h>
> +
> +#include "common.h"
> +
> +#define EIC7700_HSP_SATA_REG		0x300
> +#define EIC7700_HSP_MSHC0_REG		0x510
> +#define EIC7700_HSP_MSHC1_REG		0x610
> +#define EIC7700_HSP_MSHC2_REG		0x710
> +#define EIC7700_HSP_USB0_REG		0x800
> +#define EIC7700_HSP_USB0_REF_REG	0x83c
> +#define EIC7700_HSP_USB1_REG		0x900
> +#define EIC7700_HSP_USB1_REF_REG	0x93c
> +
> +#define USB_REF_XTAL24M			0x2a
> +#define EIC7700_HSP_NR_CLKS		(EIC7700_HSP_CLK_GATE_SATA + 1)
> +
> +struct eic7700_hsp_clk_gate {
> +	struct clk_hw hw;
> +	unsigned int id;
> +	struct regmap *regmap;
> +	unsigned int reg;
> +	unsigned int ref_reg;
> +	const char *name;
> +	const struct clk_parent_data *parent_data;
> +	unsigned long flags;
> +	unsigned int offset;
> +	unsigned int ref_offset;
> +	u8 bit_idx;
> +};
> +
> +static const struct regmap_config eic7700_hsp_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.max_register = 0x1ffc,
> +	.reg_stride = 4,
> +	.fast_io = true,
> +	.use_raw_spinlock = true,
> +};
> +
> +static inline struct eic7700_hsp_clk_gate *to_gate_clk(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct eic7700_hsp_clk_gate, hw);
> +}
> +
> +#define EIC7700_HSP_GATE(_id, _name, _pdata, _flags, _offset, _idx,	\
> +			 _ref_offset)					\
> +	{								\
> +		.id		= _id,					\
> +		.name		= _name,				\
> +		.parent_data	= _pdata,				\
> +		.flags		= _flags,				\
> +		.offset		= _offset,				\
> +		.ref_offset	= _ref_offset,				\
> +		.bit_idx	= _idx,					\
> +	}
> +
> +static void hsp_clk_gate_endisable(struct clk_hw *hw, bool enable)
> +{
> +	struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
> +
> +	if (enable) {
> +		/*
> +		 * Hardware bug: The USB reference clock must be 24MHz.
> +		 * The default register value after reset is invalid.
> +		 * Workaround: Rewrite the correct value before enabling
> +		 * the USB gate clock.
> +		 */
> +		regmap_update_bits(gate->regmap, gate->ref_reg, 0x3f,
> +				   USB_REF_XTAL24M);
> +	}
> +	regmap_assign_bits(gate->regmap, gate->reg, BIT(gate->bit_idx), enable);
> +}
> +
> +static int hsp_clk_gate_enable(struct clk_hw *hw)
> +{
> +	hsp_clk_gate_endisable(hw, true);
> +
> +	return 0;
> +}
> +
> +static void hsp_clk_gate_disable(struct clk_hw *hw)
> +{
> +	hsp_clk_gate_endisable(hw, false);
> +}
> +
> +static int hsp_clk_gate_is_enabled(struct clk_hw *hw)
> +{
> +	struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
> +	unsigned int val;
> +
> +	regmap_read(gate->regmap, gate->reg, &val);
> +
> +	return !!(val & BIT(gate->bit_idx));

If the regmap_read() fails, then val will be uninitialized.

With that fixed:

Reviewed-by: Brian Masney <bmasney@redhat.com>

Re: [PATCH v4 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator

[Brian Masney]

Hi Xuyang,

On Tue, May 12, 2026 at 10:05:11AM +0800, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> Add bindings for the high-speed peripherals clock and reset generator
> on the ESWIN EIC7700 HSP.
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> ---
>  .../bindings/clock/eswin,eic7700-hspcrg.yaml  | 63 +++++++++++++++++++
>  MAINTAINERS                                   |  5 +-
>  .../dt-bindings/clock/eswin,eic7700-hspcrg.h  | 33 ++++++++++
>  .../dt-bindings/reset/eswin,eic7700-hspcrg.h  | 21 +++++++
>  4 files changed, 120 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
>  create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
>  create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h

Does the MAINTAINERS file need to be updated for these paths? The entry
in linux-next currently looks like this:

ESWIN EIC7700 CLOCK DRIVER
M:      Yifeng Huang <huangyifeng@eswincomputing.com>
M:      Xuyang Dong <dongxuyang@eswincomputing.com>
S:      Maintained
F:      Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
F:      drivers/clk/eswin/
F:      include/dt-bindings/clock/eswin,eic7700-clock.h

Brian

Re: [PATCH v4 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator

[Conor Dooley]

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On Tue, May 12, 2026 at 11:48:09AM -0400, Brian Masney wrote:
> Hi Xuyang,
> 
> On Tue, May 12, 2026 at 10:05:11AM +0800, dongxuyang@eswincomputing.com wrote:
> > From: Xuyang Dong <dongxuyang@eswincomputing.com>
> > 
> > Add bindings for the high-speed peripherals clock and reset generator
> > on the ESWIN EIC7700 HSP.
> > 
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> > ---
> >  .../bindings/clock/eswin,eic7700-hspcrg.yaml  | 63 +++++++++++++++++++
> >  MAINTAINERS                                   |  5 +-
> >  .../dt-bindings/clock/eswin,eic7700-hspcrg.h  | 33 ++++++++++
> >  .../dt-bindings/reset/eswin,eic7700-hspcrg.h  | 21 +++++++
> >  4 files changed, 120 insertions(+), 2 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
> >  create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
> >  create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h
> 
> Does the MAINTAINERS file need to be updated for these paths? The entry
> in linux-next currently looks like this:
> 
> ESWIN EIC7700 CLOCK DRIVER
> M:      Yifeng Huang <huangyifeng@eswincomputing.com>
> M:      Xuyang Dong <dongxuyang@eswincomputing.com>
> S:      Maintained
> F:      Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> F:      drivers/clk/eswin/
> F:      include/dt-bindings/clock/eswin,eic7700-clock.h

diff --git a/MAINTAINERS b/MAINTAINERS
index b2040011a386..b7180863310c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9548,9 +9548,10 @@ ESWIN EIC7700 CLOCK DRIVER
 M:     Yifeng Huang <huangyifeng@eswincomputing.com>
 M:     Xuyang Dong <dongxuyang@eswincomputing.com>
 S:     Maintained
-F:     Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+F:     Documentation/devicetree/bindings/clock/eswin,eic7700*
 F:     drivers/clk/eswin/
-F:     include/dt-bindings/clock/eswin,eic7700-clock.h
+F:     include/dt-bindings/clock/eswin,eic7700*
+F:     include/dt-bindings/reset/eswin,eic7700-hspcrg.h


Is this not sufficient for what you're looking for?

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Re: [PATCH v4 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator

[Brian Masney]

On Tue, May 12, 2026 at 05:40:16PM +0100, Conor Dooley wrote:
> On Tue, May 12, 2026 at 11:48:09AM -0400, Brian Masney wrote:
> > Hi Xuyang,
> > 
> > On Tue, May 12, 2026 at 10:05:11AM +0800, dongxuyang@eswincomputing.com wrote:
> > > From: Xuyang Dong <dongxuyang@eswincomputing.com>
> > > 
> > > Add bindings for the high-speed peripherals clock and reset generator
> > > on the ESWIN EIC7700 HSP.
> > > 
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> > > ---
> > >  .../bindings/clock/eswin,eic7700-hspcrg.yaml  | 63 +++++++++++++++++++
> > >  MAINTAINERS                                   |  5 +-
> > >  .../dt-bindings/clock/eswin,eic7700-hspcrg.h  | 33 ++++++++++
> > >  .../dt-bindings/reset/eswin,eic7700-hspcrg.h  | 21 +++++++
> > >  4 files changed, 120 insertions(+), 2 deletions(-)
> > >  create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
> > >  create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
> > >  create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h
> > 
> > Does the MAINTAINERS file need to be updated for these paths? The entry
> > in linux-next currently looks like this:
> > 
> > ESWIN EIC7700 CLOCK DRIVER
> > M:      Yifeng Huang <huangyifeng@eswincomputing.com>
> > M:      Xuyang Dong <dongxuyang@eswincomputing.com>
> > S:      Maintained
> > F:      Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> > F:      drivers/clk/eswin/
> > F:      include/dt-bindings/clock/eswin,eic7700-clock.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b2040011a386..b7180863310c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9548,9 +9548,10 @@ ESWIN EIC7700 CLOCK DRIVER
>  M:     Yifeng Huang <huangyifeng@eswincomputing.com>
>  M:     Xuyang Dong <dongxuyang@eswincomputing.com>
>  S:     Maintained
> -F:     Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> +F:     Documentation/devicetree/bindings/clock/eswin,eic7700*
>  F:     drivers/clk/eswin/
> -F:     include/dt-bindings/clock/eswin,eic7700-clock.h
> +F:     include/dt-bindings/clock/eswin,eic7700*
> +F:     include/dt-bindings/reset/eswin,eic7700-hspcrg.h
> 
> 
> Is this not sufficient for what you're looking for?

I completely missed that. Sorry

Brian

Re: [PATCH v4 2/3] clk: eswin: Add eic7700 HSP clock driver

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The variable `val` is used uninitialized if `regmap_read()` fails in `hsp_clk_gate_is_enabled()`.
--

commit d3ad8b72eab107c1eceac1316c7d04ee9daab08d
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

clk: eswin: Add eic7700 HSP clock driver

Add driver for the ESWIN EIC7700 high-speed peripherals system
clock controller and register an auxiliary device for system
reset controller which is named as "hsp-reset".

> diff --git a/drivers/clk/eswin/clk-eic7700-hsp.c b/drivers/clk/eswin/clk-eic7700-hsp.c
> new file mode 100644
> index 0000000000000..0d5bd5b705dc5
> --- /dev/null
> +++ b/drivers/clk/eswin/clk-eic7700-hsp.c

[ ... ]

> +static int hsp_clk_gate_is_enabled(struct clk_hw *hw)
> +{
> +	struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
> +	unsigned int val;
> +
> +	regmap_read(gate->regmap, gate->reg, &val);

If regmap_read() fails and returns an error code, does it leave the val
variable uninitialized?

> +
> +	return !!(val & BIT(gate->bit_idx));

Could the clock framework evaluate this uninitialized stack memory as the
clock's state?

If a random garbage value is returned, could it lead to subsequent
synchronization or power-management issues, such as improperly disabling
an active clock?

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260512020432.671-1-dongxuyang@eswincomputing.com?part=2