[PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[Han Gao]

The SG2042 hardware design supports cache-coherent PCIe.

With recent firmware updates [1], it allows to use DMA coherent.

[1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36

Han Gao (2):
  dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
  riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

 .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml      | 3 +++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi                        | 4 ++++
 2 files changed, 7 insertions(+)

-- 
2.47.3

[PATCH 1/2] dt-bindings: pci: sophgo: Add dma-coherent property for SG2042

[Han Gao]

Add dma-coherent as an allowed property in the SG2042 PCIe host
controller binding. SG2042's PCIe root complexes are cache-coherent
with the CPU.

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
 .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
index f8b7ca57fff1..ab482488b047 100644
--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -30,6 +30,8 @@ properties:
   device-id:
     const: 0x2042
 
+  dma-coherent: true
+
   msi-parent: true
 
 allOf:
@@ -60,5 +62,6 @@ examples:
       vendor-id = <0x1f1c>;
       device-id = <0x2042>;
       cdns,no-bar-match-nbits = <48>;
+      dma-coherent;
       msi-parent = <&msi>;
     };
-- 
2.47.3

Re: [PATCH 1/2] dt-bindings: pci: sophgo: Add dma-coherent property for SG2042

[Rob Herring (Arm)]

On Wed, 01 Apr 2026 01:12:47 +0800, Han Gao wrote:
> Add dma-coherent as an allowed property in the SG2042 PCIe host
> controller binding. SG2042's PCIe root complexes are cache-coherent
> with the CPU.
> 
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>  .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml       | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

[Han Gao]

SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
so the kernel uses coherent DMA mappings instead of non-coherent bounce
buffering.

Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 9fddf3f0b3b9..3af770549742 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
+			dma-coherent;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
+			dma-coherent;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
+			dma-coherent;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
+			dma-coherent;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
-- 
2.47.3

Re: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

[Conor Dooley]

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On Wed, Apr 01, 2026 at 01:12:48AM +0800, Han Gao wrote:
> SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
> four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
> so the kernel uses coherent DMA mappings instead of non-coherent bounce
> buffering.

Worth pointing out I guess that this property is needed, despite riscv
being coherent by default, because the whole bus is marked
dma-noncoherent.

> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 9fddf3f0b3b9..3af770549742 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> -- 
> 2.47.3
> 

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Re: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

[Chen Wang]

On 4/1/2026 1:12 AM, Han Gao wrote:
> SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
> four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
> so the kernel uses coherent DMA mappings instead of non-coherent bounce
> buffering.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 9fddf3f0b3b9..3af770549742 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
>   			vendor-id = <0x1f1c>;
>   			device-id = <0x2042>;
>   			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>   			msi-parent = <&msi>;
>   			status = "disabled";
>   		};
> @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
>   			vendor-id = <0x1f1c>;
>   			device-id = <0x2042>;
>   			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>   			msi-parent = <&msi>;
>   			status = "disabled";
>   		};
> @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
>   			vendor-id = <0x1f1c>;
>   			device-id = <0x2042>;
>   			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>   			msi-parent = <&msi>;
>   			status = "disabled";
>   		};
> @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
>   			vendor-id = <0x1f1c>;
>   			device-id = <0x2042>;
>   			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>   			msi-parent = <&msi>;
>   			status = "disabled";
>   		};
For binding changes, LGTM. But I have a question regarding this change 
in dtsi.

 From your patch description, I understand that enabling the 
`dma-coherent` attribute requires upgrading the firmware `fip.bin`. If a 
user only updates the kernel (which is relatively easy) but forgets or 
doesn't know how to upgrade the firmware, enabling `coherent` might 
cause the kernel to skip all explicit cache maintenance operations. 
Could this pose a subtle risk?

Wouldn't it be safer to leave the upstream unchanged in dtsi and allow 
users to add the `dma-coherent` attribute themselves after they upgrade 
the firmware?

I would greatly appreciate your guidance.

Thanks,

Chen

Re: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

[Han Gao]

On Thu, Apr 2, 2026 at 4:44 PM Chen Wang <unicorn_wang@outlook.com> wrote:
>
>
> On 4/1/2026 1:12 AM, Han Gao wrote:
> > SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
> > four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
> > so the kernel uses coherent DMA mappings instead of non-coherent bounce
> > buffering.
> >
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> > ---
> >   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index 9fddf3f0b3b9..3af770549742 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
> >                       vendor-id = <0x1f1c>;
> >                       device-id = <0x2042>;
> >                       cdns,no-bar-match-nbits = <48>;
> > +                     dma-coherent;
> >                       msi-parent = <&msi>;
> >                       status = "disabled";
> >               };
> > @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
> >                       vendor-id = <0x1f1c>;
> >                       device-id = <0x2042>;
> >                       cdns,no-bar-match-nbits = <48>;
> > +                     dma-coherent;
> >                       msi-parent = <&msi>;
> >                       status = "disabled";
> >               };
> > @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
> >                       vendor-id = <0x1f1c>;
> >                       device-id = <0x2042>;
> >                       cdns,no-bar-match-nbits = <48>;
> > +                     dma-coherent;
> >                       msi-parent = <&msi>;
> >                       status = "disabled";
> >               };
> > @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
> >                       vendor-id = <0x1f1c>;
> >                       device-id = <0x2042>;
> >                       cdns,no-bar-match-nbits = <48>;
> > +                     dma-coherent;
> >                       msi-parent = <&msi>;
> >                       status = "disabled";
> >               };
> For binding changes, LGTM. But I have a question regarding this change
> in dtsi.
>
>  From your patch description, I understand that enabling the
> `dma-coherent` attribute requires upgrading the firmware `fip.bin`. If a
> user only updates the kernel (which is relatively easy) but forgets or
> doesn't know how to upgrade the firmware, enabling `coherent` might
> cause the kernel to skip all explicit cache maintenance operations.
> Could this pose a subtle risk?
>
> Wouldn't it be safer to leave the upstream unchanged in dtsi and allow
> users to add the `dma-coherent` attribute themselves after they upgrade
> the firmware?

In the firmware, fip.bin and devicetree are distributed together.
So matching issues are unlikely.

>
> I would greatly appreciate your guidance.
>
> Thanks,
>
> Chen
>
>

Thanks,
Han

Re: (subset) [PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[Manivannan Sadhasivam]

On Wed, 01 Apr 2026 01:12:46 +0800, Han Gao wrote:
> The SG2042 hardware design supports cache-coherent PCIe.
> 
> With recent firmware updates [1], it allows to use DMA coherent.
> 
> [1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36
> 
> Han Gao (2):
>   dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
>   riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
      commit: 50c94a2351458ee6cb6e52c5678f099534366830

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>

Re: (subset) [PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[Inochi Amaoto]

On Wed, 01 Apr 2026 01:12:46 +0800, Han Gao wrote:
> The SG2042 hardware design supports cache-coherent PCIe.
> 
> With recent firmware updates [1], it allows to use DMA coherent.
> 
> [1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36
> 
> Han Gao (2):
>   dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
>   riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
> 
> [...]

Applied to for-next, thanks!

[2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
      https://github.com/sophgo/linux/commit/e728a57834d06b9bbf9bbed69e3ea16416d257d5

Thanks,
Inochi

Re: (subset) [PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[Inochi Amaoto]

On Mon, Jun 01, 2026 at 10:57:24AM +0800, Inochi Amaoto wrote:
> On Wed, 01 Apr 2026 01:12:46 +0800, Han Gao wrote:
> > The SG2042 hardware design supports cache-coherent PCIe.
> > 
> > With recent firmware updates [1], it allows to use DMA coherent.
> > 
> > [1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36
> > 
> > Han Gao (2):
> >   dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
> >   riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
> > 
> > [...]
> 
> Applied to for-next, thanks!
> 
> [2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
>       https://github.com/sophgo/linux/commit/e728a57834d06b9bbf9bbed69e3ea16416d257d5
> 
> Thanks,
> Inochi
> 

Revoke this apply due to https://lore.kernel.org/sophgo/ahu57vcS0oOFmCI9@mertle/

Regards,
Inochi

Re: (subset) [PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence

[Inochi Amaoto]

On Tue, Jun 02, 2026 at 05:21:32PM +0800, Inochi Amaoto wrote:
> On Mon, Jun 01, 2026 at 10:57:24AM +0800, Inochi Amaoto wrote:
> > On Wed, 01 Apr 2026 01:12:46 +0800, Han Gao wrote:
> > > The SG2042 hardware design supports cache-coherent PCIe.
> > > 
> > > With recent firmware updates [1], it allows to use DMA coherent.
> > > 
> > > [1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36
> > > 
> > > Han Gao (2):
> > >   dt-bindings: pci: sophgo: Add dma-coherent property for SG2042
> > >   riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
> > > 
> > > [...]
> > 
> > Applied to for-next, thanks!
> > 
> > [2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
> >       https://github.com/sophgo/linux/commit/e728a57834d06b9bbf9bbed69e3ea16416d257d5
> > 
> > Thanks,
> > Inochi
> > 
> 
> Revoke this apply due to https://lore.kernel.org/sophgo/ahu57vcS0oOFmCI9@mertle/
> 

Reapply this as this error is resolved.

Regards,
Inochi