[PATCH 0/3] arm64: dts: qcom: Introduce Asus Zenbook A14 (UX3407NA)

[PATCH 0/3] arm64: dts: qcom: Introduce Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
Glymur platform.

In addition to the same dependencies that other Glymur patches on the
list carries (audio, gpu, remoteproc, etc), this also depends on the eDP
PHY patches available here:
https://lore.kernel.org/linux-arm-msm/20260622-glymur-edp-phy-v1-0-814b45089ac9@oss.qualcomm.com/

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
Bjorn Andersson (3):
      dt-bindings: arm: qcom: Add Asus Zenbook A14 (UX3407NA)
      arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)
      firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14 (UX3407NA)

 Documentation/devicetree/bindings/arm/qcom.yaml    |    1 +
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts  | 1099 ++++++++++++++++++++
 drivers/firmware/qcom/qcom_scm.c                   |    1 +
 4 files changed, 1102 insertions(+)
---
base-commit: 948efecf22e49aa4bf55bb73ec79a0ddcfd38571
change-id: 20260623-zenbook-dts-b69019671266

Best regards,
--  
Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

[PATCH 1/3] dt-bindings: arm: qcom: Add Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, NVMe
storage, a WUXGA OLED screen, and the other typical Glymur platform
capabilities.

Add a compatible for this machine.

[1] https://www.asus.com/us/laptops/for-home/zenbook/asus-zenbook-a14-ux3407/techspec/

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 50cc18a6ec5e..1a1cd5b0bf21 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -68,6 +68,7 @@ properties:
 
       - items:
           - enum:
+              - asus,zenbook-a14-ux3407na
               - qcom,glymur-crd
           - const: qcom,glymur
 

-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: arm: qcom: Add Asus Zenbook A14 (UX3407NA)

[Krzysztof Kozlowski]

On 23/06/2026 03:31, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> 
> UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, NVMe
> storage, a WUXGA OLED screen, and the other typical Glymur platform
> capabilities.
> 
> Add a compatible for this machine.
> 
> [1] https://www.asus.com/us/laptops/for-home/zenbook/asus-zenbook-a14-ux3407/techspec/
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
the other typical Glymur platform capabilities.

The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts  | 1099 ++++++++++++++++++++
 2 files changed, 1100 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6f33c4e2f09c..61e8518a8243 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= apq8096sg-db820c.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= eliza-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= glymur-asus-zenbook-a14-ux3407na.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= glymur-crd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= hamoa-iot-evk.dtb
 
diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts
new file mode 100644
index 000000000000..734fd3aea5d0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts
@@ -0,0 +1,1099 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+/dts-v1/;
+
+#include "glymur.dtsi"
+
+#include "pmcx0102.dtsi"
+#include "pmh0101.dtsi"
+#include "pmh0110-glymur.dtsi"
+#include "pmh0104-glymur.dtsi"
+#include "pmk8850.dtsi"
+#include "smb2370.dtsi"
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+	compatible = "asus,zenbook-a14-ux3407na", "qcom,glymur";
+	model = "ASUS Zenbook A14 (UX3407NA)";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c8 = &i2c8;
+		i2c10 = &i2c10;
+		i2c19 = &i2c19;
+		serial0 = &uart14;
+	};
+
+	chosen {
+	};
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			label = "lid";
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
+	hdmi-bridge {
+		compatible = "parade,ps185hdm";
+
+		pinctrl-0 = <&usb2_dp_hot_plug_detect>;
+		pinctrl-names = "default";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				hdmi_bridge_in: endpoint {
+					remote-endpoint = <&usb_2_qmpphy_out_dp>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				hdmi_bridge_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&hdmi_bridge_out>;
+			};
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,glymur-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Left side display-adjacent port */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&usb_0_qmpphy_out>;
+					};
+				};
+			};
+		};
+
+		/* Left side user-adjacent port */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in1: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in1: endpoint {
+						remote-endpoint = <&usb_1_qmpphy_out>;
+					};
+				};
+			};
+		};
+	};
+
+	vreg_edp: regulator-edp {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_EDP_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&edp_pwr_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_MISC_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&misc_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_NVME_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_wcn_0p95: regulator-wcn-0p95 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_0P95";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+
+		vin-supply = <&vreg_wcn_3p3>;
+	};
+
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wcn_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	sound {
+		compatible = "qcom,glymur-sndcard";
+		model = "GLYMUR-ASUS-Zenbook-A14-UX3407NA";
+
+		audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+				"TweeterLeft IN", "WSA WSA_SPK2 OUT",
+				"WooferRight IN", "WSA2 WSA_SPK1 OUT",
+				"TweeterRight IN", "WSA2 WSA_SPK2 OUT",
+				"VA DMIC0", "vdd-micb",
+				"VA DMIC1", "vdd-micb",
+				"VA DMIC2", "vdd-micb",
+				"VA DMIC3", "vdd-micb";
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			codec {
+				sound-dai = <&left_woofer>, <&left_tweeter>,
+					    <&swr0 0>, <&lpass_wsamacro 0>,
+					    <&right_woofer>, <&right_tweeter>,
+					    <&swr3 0>, <&lpass_wsa2macro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		vdd-supply = <&vreg_wcn_0p95>;
+		vddio-supply = <&vreg_l15b_e0>;
+		vddaon-supply = <&vreg_l15b_e0>;
+		vdddig-supply = <&vreg_l15b_e0>;
+		vddrfa1p2-supply = <&vreg_l15b_e0>;
+		vddrfa1p8-supply = <&vreg_l15b_e0>;
+
+		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&wcn_wlan_bt_en>;
+		pinctrl-names = "default";
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmh0101-rpmh-regulators";
+		qcom,pmic-id = "B_E0";
+
+		vreg_l1b_e0: ldo1 {
+			regulator-name = "vreg_l1b_e0";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_e0: ldo7 {
+			regulator-name = "vreg_l7b_e0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_e0: ldo15 {
+			regulator-name = "vreg_l15b_e0";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l18b_e0: ldo18 {
+			regulator-name = "vreg_l18b_e0";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+
+			/*
+			 * This is also reference voltage for &pcie3b wake and
+			 * reset signals.
+			 */
+			regulator-always-on;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmcx0102-rpmh-regulators";
+		qcom,pmic-id = "C_E1";
+
+		vreg_l1c_e1: ldo1 {
+			regulator-name = "vreg_l1c_e1";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_e1: ldo2 {
+			regulator-name = "vreg_l2c_e1";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_e1: ldo3 {
+			regulator-name = "vreg_l3c_e1";
+			regulator-min-microvolt = <936000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmh0110-rpmh-regulators";
+		qcom,pmic-id = "F_E0";
+
+		vreg_l2f_e0: ldo2 {
+			regulator-name = "vreg_l2f_e0";
+			regulator-min-microvolt = <936000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_e0: ldo3 {
+			regulator-name = "vreg_l3f_e0";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmh0110-rpmh-regulators";
+		qcom,pmic-id = "F_E1";
+
+		vreg_l1f_e1: ldo1 {
+			regulator-name = "vreg_l1f_e1";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_e1: ldo2 {
+			regulator-name = "vreg_l2f_e1";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4f_e1: ldo4 {
+			regulator-name = "vreg_l4f_e1";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmh0110-rpmh-regulators";
+		qcom,pmic-id = "H_E0";
+
+		vreg_l1h_e0: ldo1 {
+			regulator-name = "vreg_l1h_e0";
+			regulator-min-microvolt = <936000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2h_e0: ldo2 {
+			regulator-name = "vreg_l2h_e0";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4h_e0: ldo4 {
+			regulator-name = "vreg_l4h_e0";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gmu {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchpad@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-0 = <&ts_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c10 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	hid@17 {
+		compatible = "hid-over-i2c";
+		reg = <0x17>;
+		interrupts-extended = <&tlmm 43 IRQ_TYPE_LEVEL_LOW>;
+		hid-descr-addr = <0x1>;
+		wakeup-source;
+
+		pinctrl-0 = <&hid_app_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c19 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	keyboard@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+		wakeup-source;
+
+		pinctrl-0 = <&kybd_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&pmh0110_f_e0_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-disable;
+		input-disable;
+		output-enable;
+		drive-push-pull;
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+	};
+};
+
+&lpass_vamacro {
+	vdd-micb-supply = <&vreg_l1b_e0>;
+
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp3 {
+	/delete-property/ #sound-dai-cells;
+
+	pinctrl-0 = <&edp0_hpd_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	aux-bus {
+		panel {
+			compatible = "samsung,atna40ct06", "samsung,atna33xc20";
+			enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+			power-supply = <&vreg_edp>;
+
+			pinctrl-0 = <&edp_bl_en>;
+			pinctrl-names = "default";
+
+			port {
+				edp_panel_in: endpoint {
+					remote-endpoint = <&mdss_dp3_out>;
+				};
+			};
+		};
+	};
+};
+
+&mdss_dp3_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+	remote-endpoint = <&edp_panel_in>;
+};
+
+&mdss_dp3_phy {
+	vdda-phy-supply = <&vreg_l2f_e1>;
+	vdda-pll-supply = <&vreg_l4f_e1>;
+
+	status = "okay";
+};
+
+&pcie3b {
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie3b_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+/* This will become &pcie3_phy, which may result in an ABI breakage */
+&pcie3b_phy {
+	vdda-phy-supply = <&vreg_l3c_e1>;
+	vdda-pll-supply = <&vreg_l2c_e1>;
+
+	status = "okay";
+};
+
+&pcie3b_port0 {
+	reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>;
+};
+
+&pcie4 {
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l1c_e1>;
+	vdda-pll-supply = <&vreg_l4f_e1>;
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
+};
+
+&pmh0101_gpios {
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio14";
+		function = "normal";
+		bias-disable;
+	};
+};
+
+&pmk8850_rtc {
+	qcom,no-alarm;
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/glymur/ASUSTeK/UX3407NA/qcadsp8480.mbn",
+			"qcom/glymur/ASUSTeK/UX3407NA/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/glymur/ASUSTeK/UX3407NA/qccdsp8480.mbn",
+			"qcom/glymur/ASUSTeK/UX3407NA/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_soccp {
+	status = "okay";
+};
+
+&smb2370_k_e2_eusb2_repeater {
+	vdd18-supply = <&vreg_l15b_e0>;
+	vdd3-supply = <&vreg_l7b_e0>;
+};
+
+&swr0 {
+	status = "okay";
+
+	/* WSA8845, left woofer */
+	left_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferLeft";
+		vdd-1p8-supply = <&vreg_l15b_e0>;
+		vdd-io-supply = <&vreg_l18b_e0>;
+		qcom,port-mapping = <1 2 3 7 12 14>;
+	};
+
+	/* WSA8845, left tweeter */
+	left_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TweeterLeft";
+		vdd-1p8-supply = <&vreg_l15b_e0>;
+		vdd-io-supply = <&vreg_l18b_e0>;
+		qcom,port-mapping = <4 5 6 7 13 15>;
+	};
+};
+
+&swr3 {
+	status = "okay";
+
+	/* WSA8845, right woofer */
+	right_woofer: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "WooferRight";
+		vdd-1p8-supply = <&vreg_l15b_e0>;
+		vdd-io-supply = <&vreg_l18b_e0>;
+		qcom,port-mapping = <1 2 3 7 12 14>;
+	};
+
+	/* WSA8845, right tweeter */
+	right_tweeter: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TweeterRight";
+		vdd-1p8-supply = <&vreg_l15b_e0>;
+		vdd-io-supply = <&vreg_l18b_e0>;
+		qcom,port-mapping = <4 5 6 7 13 15>;
+	};
+};
+
+&tcsr {
+	vdda-refgen-0p9-supply = <&vreg_l1f_e1>;
+	vdda-refgen-1p2-supply = <&vreg_l4f_e1>;
+
+	vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0>;
+	vdda-qreftx0-0p9-supply = <&vreg_l3f_e0>;
+	vdda-qreftx0-1p2-supply = <&vreg_l4h_e0>;
+	vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0>;
+	vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0>;
+	vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1>;
+	vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0>;
+	vdda-qreftx1-0p9-supply = <&vreg_l1f_e1>;
+};
+
+&tlmm {
+	gpio-reserved-ranges = <4 4>, /* EC Secure */
+			       <10 2>, /* OOB UART */
+			       <44 4>, /* TPM */
+			       <90 2>; /* TPM */
+
+	tpad_default: tpad-default-state {
+		pins = "gpio3";
+		function = "gpio";
+		bias-disable;
+	};
+
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	hid_app_default: hid-app-default-state {
+		pins = "gpio43";
+		function = "gpio";
+		bias-disable;
+	};
+
+	ts_default: ts-default-state {
+		reset-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			bias-disable;
+			output-high;
+		};
+
+		int-pins {
+			pins = "gpio51";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	kybd_default: kybd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		bias-disable;
+	};
+
+	edp_pwr_en: edp-pwr-en-state {
+		pins = "gpio70";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
+	wcn_sw_en: wcn-sw-en-state {
+		pins = "gpio94";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+		pins = "gpio116", "gpio117";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	edp0_hpd_default: edp0-hpd-default-state {
+		pins = "gpio119";
+		function = "edp0_hot";
+		bias-disable;
+	};
+
+	usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state {
+		pins = "gpio126";
+		function = "usb2_dp";
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk_req_n";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie3b_default: pcie3b-default-state {
+		clkreq-n-pins {
+			pins = "gpio156";
+			function = "pcie3b_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio155";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio157";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+		max-speed = <3200000>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+	};
+};
+
+&uart21 {
+	status = "disabled";
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_0_hsphy {
+	vdd-supply = <&vreg_l3f_e0>;
+	vdda12-supply = <&vreg_l4h_e0>;
+
+	phys = <&smb2370_j_e2_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l4h_e0>;
+	vdda-pll-supply = <&vreg_l3f_e0>;
+	refgen-supply = <&vreg_l2f_e0>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in1>;
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l3f_e0>;
+	vdda12-supply = <&vreg_l4h_e0>;
+
+	phys = <&smb2370_k_e2_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l4h_e0>;
+	vdda-pll-supply = <&vreg_l1h_e0>;
+	refgen-supply = <&vreg_l2f_e0>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy_out {
+	remote-endpoint = <&pmic_glink_ss_in1>;
+};
+
+&usb_2_qmpphy {
+	vdda-phy-supply = <&vreg_l4h_e0>;
+	vdda-pll-supply = <&vreg_l3f_e0>;
+	refgen-supply = <&vreg_l2f_e0>;
+
+	/delete-property/ mode-switch;
+	/delete-property/ orientation-switch;
+
+	status = "okay";
+
+	ports {
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/delete-node/ endpoint;
+
+			usb_2_qmpphy_out_dp: endpoint@0 {
+				reg = <0>;
+
+				data-lanes = <3 2 1 0>;
+				remote-endpoint = <&hdmi_bridge_in>;
+			};
+		};
+	};
+};
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2h_e0>;
+	vdda12-supply = <&vreg_l4h_e0>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2h_e0>;
+	vdda12-supply = <&vreg_l4h_e0>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l4h_e0>;
+	vdda-pll-supply = <&vreg_l2h_e0>;
+	refgen-supply = <&vreg_l1f_e1>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l4h_e0>;
+	vdda-pll-supply = <&vreg_l2h_e0>;
+	refgen-supply = <&vreg_l1f_e1>;
+
+	status = "okay";
+};

-- 
2.53.0

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing regulator configuration for `&smb2370_j_e2_eusb2_repeater` causing potential USB port failure.
--

commit 8c025a2ed8f0bc5c7861b62d7eff8a38ae127ae5
Author: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

This commit adds device tree support for the Asus Zenbook A14 (UX3407NA),
built on the Qualcomm Glymur platform. It configures the typical platform
capabilities, including NVMe storage, screen, USB, and HDMI.

> diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts
> new file mode 100644
> index 0000000000000..734fd3aea5d02
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a14-ux3407na.dts

[ ... ]

> +&smb2370_k_e2_eusb2_repeater {
> +	vdd18-supply = <&vreg_l15b_e0>;
> +	vdd3-supply = <&vreg_l7b_e0>;
> +};

[ ... ]

> +&usb_0_hsphy {
> +	vdd-supply = <&vreg_l3f_e0>;
> +	vdda12-supply = <&vreg_l4h_e0>;
> +
> +	phys = <&smb2370_j_e2_eusb2_repeater>;
> +
> +	status = "okay";
> +};

[Severity: High]
Does this configuration miss the supplies for &smb2370_j_e2_eusb2_repeater?

The usb_0_hsphy node references &smb2370_j_e2_eusb2_repeater, but unlike the
k instance (&smb2370_k_e2_eusb2_repeater) shown above, the j instance does
not have its vdd18-supply and vdd3-supply configured in this file.

Without these configured, the driver falls back to dummy regulators. Since
vreg_l7b_e0 is not regulator-always-on and is only requested by the k
repeater, usb_0 might lose power and fail whenever usb_1 is suspended or
unused.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260623-zenbook-dts-v1-0-3f80f680381d@oss.qualcomm.com?part=2

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Konrad Dybcio]

On 6/23/26 3:31 AM, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> 
> UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> the other typical Glymur platform capabilities.
> 
> The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
> OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---

[...]

> +/ {
> +	compatible = "asus,zenbook-a14-ux3407na", "qcom,glymur";
> +	model = "ASUS Zenbook A14 (UX3407NA)";

unusual order!

> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c8 = &i2c8;
> +		i2c10 = &i2c10;
> +		i2c19 = &i2c19;
> +		serial0 = &uart14;
> +	};
> +
> +	chosen {
> +	};

Do we need this node?

[...]

> +&i2c10 {
> +	clock-frequency = <400000>;
> +
> +	status = "okay";
> +
> +	hid@17 {

We've already got touchscreen, touchpad, the keyboard's below - what's
this one?

[...]

> +&tlmm {
> +	gpio-reserved-ranges = <4 4>, /* EC Secure */
> +			       <10 2>, /* OOB UART */
> +			       <44 4>, /* TPM */
> +			       <90 2>; /* TPM */

Is there no EC reset pin? I wouldn't want others to have to open up
a laptop after trying to find out what it does..

[...]

> +	ts_default: ts-default-state {
> +		reset-n-pins {
> +			pins = "gpio48";
> +			function = "gpio";
> +			bias-disable;
> +			output-high;

You can drop this property

[...]

> +&uart21 {
> +	status = "disabled";

hm?

Konrad

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

On Tue, Jun 23, 2026 at 09:06:51AM +0200, Konrad Dybcio wrote:
> On 6/23/26 3:31 AM, Bjorn Andersson wrote:
> > From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > 
> > UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> > Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> > the other typical Glymur platform capabilities.
> > 
> > The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
> > OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> > +/ {
> > +	compatible = "asus,zenbook-a14-ux3407na", "qcom,glymur";
> > +	model = "ASUS Zenbook A14 (UX3407NA)";
> 
> unusual order!
> 

While I don't see this case documented in dts-coding-style.rst, this
order seems better...

[..]
> > +&tlmm {
> > +	gpio-reserved-ranges = <4 4>, /* EC Secure */
> > +			       <10 2>, /* OOB UART */
> > +			       <44 4>, /* TPM */
> > +			       <90 2>; /* TPM */
> 
> Is there no EC reset pin? I wouldn't want others to have to open up
> a laptop after trying to find out what it does..
> 

These are the ones needed to allow the thing to boot, I don't know what
the EC reset pin does, but I guess we can add some more for convenience.

[..]
> > +&uart21 {
> > +	status = "disabled";
> 
> hm?
> 

The debug-uart is left enabled in glymur.dtsi. Perhaps we should change
that instead?

Regards,
Bjorn

> Konrad

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Dmitry Baryshkov]

On Sat, Jun 27, 2026 at 09:41:38PM -0500, Bjorn Andersson wrote:
> On Tue, Jun 23, 2026 at 09:06:51AM +0200, Konrad Dybcio wrote:
> > On 6/23/26 3:31 AM, Bjorn Andersson wrote:
> > > From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > > 
> > > UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> > > Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> > > the other typical Glymur platform capabilities.
> > > 
> > > The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
> > > OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.
> > > 
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > > ---
> > > +&tlmm {
> > > +	gpio-reserved-ranges = <4 4>, /* EC Secure */
> > > +			       <10 2>, /* OOB UART */
> > > +			       <44 4>, /* TPM */
> > > +			       <90 2>; /* TPM */
> > 
> > Is there no EC reset pin? I wouldn't want others to have to open up
> > a laptop after trying to find out what it does..

:-)

> > 
> 
> These are the ones needed to allow the thing to boot, I don't know what
> the EC reset pin does, but I guess we can add some more for convenience.
> 
> [..]
> > > +&uart21 {
> > > +	status = "disabled";
> > 
> > hm?
> > 
> 
> The debug-uart is left enabled in glymur.dtsi. Perhaps we should change
> that instead?

I think that would match other platforms. But, is it actually not wired
up? No debug connector or TPs?

-- 
With best wishes
Dmitry

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

On Sun, Jun 28, 2026 at 04:20:22PM +0300, Dmitry Baryshkov wrote:
> On Sat, Jun 27, 2026 at 09:41:38PM -0500, Bjorn Andersson wrote:
> > On Tue, Jun 23, 2026 at 09:06:51AM +0200, Konrad Dybcio wrote:
> > > On 6/23/26 3:31 AM, Bjorn Andersson wrote:
> > > > From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > > > 
> > > > UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> > > > Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> > > > the other typical Glymur platform capabilities.
> > > > 
> > > > The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
> > > > OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.
> > > > 
> > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > > > ---
> > > > +&tlmm {
> > > > +	gpio-reserved-ranges = <4 4>, /* EC Secure */
> > > > +			       <10 2>, /* OOB UART */
> > > > +			       <44 4>, /* TPM */
> > > > +			       <90 2>; /* TPM */
> > > 
> > > Is there no EC reset pin? I wouldn't want others to have to open up
> > > a laptop after trying to find out what it does..
> 
> :-)
> 
> > > 
> > 
> > These are the ones needed to allow the thing to boot, I don't know what
> > the EC reset pin does, but I guess we can add some more for convenience.
> > 
> > [..]
> > > > +&uart21 {
> > > > +	status = "disabled";
> > > 
> > > hm?
> > > 
> > 
> > The debug-uart is left enabled in glymur.dtsi. Perhaps we should change
> > that instead?
> 
> I think that would match other platforms. But, is it actually not wired
> up? No debug connector or TPs?
> 

It might very well be, but like most other users I don't intend to ever
use them...

Regards,
Bjorn

> -- 
> With best wishes
> Dmitry

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Nicko van Someren]

On Jun 22, 2026, at 19:31, Bjorn Andersson <andersson@kernel.org> wrote:

> From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> 
> UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> the other typical Glymur platform capabilities.

Firstly, many thanks for this. I recently acquired one of these machines
for some firmware work I'm doing and having a working Linux system on it
makes my life much easier!

I tested this patch set, along with the others it depends on. I have it
mostly working now but ran into some issues that might indicate a few
changes.

WIFI:

> + wifi@0 {
> + compatible = "pci17cb,1107";
> ...
> + };

ASUS don't specify what WiFi7 chip they use, which is fairly normal since
ASUS tends to swap the parts depending on supply. As a result, my machine
has a QCC2072 (17cb:1112) WiFi/BT module not the WCN7850 (17cb:1107) device
that you listed. Inspection of the hardware shows that the WiFi/BT module
is a solder-down M.2 LGA module, but electrically that's still an M.2
interface. Photos that I can find of the Zenbook A16 show it does the same.
I think it might be more reliable to define a wlan-connector, like Konrad
Dybcio did in the Asus Zenbook A16 (UX3607OA) (2/3) from 2026-07-21,
rather than specify the chip.


SOUND:

Regarding sound definitions, the dts declares four WSA8845s -- a woofer
and tweeter per side, two on swr0 and two on swr3. 

> +&swr0 {
> + status = "okay";
> +
> + /* WSA8845, left woofer */
> ...
> +
> + /* WSA8845, left tweeter */
> ...
> +};
> +
> +&swr3 {
> + status = "okay";
> ...
> + /* WSA8845, right woofer */
> ...
> +
> + /* WSA8845, right tweeter */
> ...
> +};

This machine only has two speakers (again confirmed by physical inspection).
Only swr0 shows attached on /sys/bus/soundwire/devices/sdw:*/status:

  sdw:1:0:0217:0204:00:0   Attached
  sdw:1:0:0217:0204:00:1   Attached
  sdw:4:0:0217:0204:00:0   UNATTACHED
  sdw:4:0:0217:0204:00:1   UNATTACHED

I don't think that's a config fault either; the swr0 and swr3 reset lines are
both claimed and in identical state of (out, 0, 2mA, no pull). It's not really
a surprise that the cheaper model from ASUS would not use the full spec audio
offered on the Qualcomm reference designs, but without a suitable
UX3407NA-tplg.bin topology file I can't really tell more.

It appears that the audio setup is blocked further up the audio stack anyway.
I hacked some dts changes, purloined blobs from Windows and got a stereo speaker
setup configured. SoundWire is healthy, but no audio is possible because the DSP
does not respond. The ADSP boots and the audio PD is reported up:

  remoteproc remoteproc1: remote processor adsp is now up
  PDR: Indication received from msm/adsp/audio_pd, state: 0x1fffffff
  qcom,apr ...: Adding APR/GPR dev: gprsvc:service:2:1

then, on every boot:

  qcom-apm gprsvc:service:2:1: CMD timeout for [1001021] opcode

I'm curious as to if you tested this (or if this even known to work on the
Zenbook A16, Yoga Slim 7x or EliteBook X G2q with the other submissions). Do
you know if/when the required firmware blobs will be forthcoming and
upstreamed?


HDMI:

The built-in HDMI cannot read EDID: the connector reports "connected" with
a monitor attached but the EDID is 0 bytes and there are no modes. Less than
2 seconds into every boot, before any cable is involved:

  gcc_usb3_tert_phy_com_aux_clk status stuck at 'off'
  Failed to enable clk 'com_aux': -16
  phy phy-88e1000.phy.5: phy init failed --> -16

I have not really investigated this in detail.


eDP:

eDP link training intermittently times out on resume, leaving visible flicker
until another suspend/resume retrains it:

  [drm:msm_dp_ctrl_link_train_1_2] *ERROR* link training #2 on phy 0 failed. ret=-110

I am carrying the (unmerged) "phy: qcom: edp: update v8 power-on
programming sequence" series, so this may be feedback for that rather than
a report against mainline.


Anyway, thank you again for this patch series. It got me to the point of
having a very usable machine for my limited needs. If you have updates the
need testing I'm happy to help.

Nicko

[PATCH 3/3] firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14 (UX3407NA)

[Bjorn Andersson]

From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

In line with other Glymur-based machines, the Asus Zenbook A14
(UX3407NA) exposes EFI variables through the "uefisecapp". Add it to the
QSEECOM allowlist to enable this access.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 drivers/firmware/qcom/qcom_scm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 6b601a4b89db..96607ac5c10d 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -2289,6 +2289,7 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send);
 static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
 	{ .compatible = "asus,vivobook-s15" },
 	{ .compatible = "asus,vivobook-s15-x1p4" },
+	{ .compatible = "asus,zenbook-a14-ux3407na" },
 	{ .compatible = "asus,zenbook-a14-ux3407qa" },
 	{ .compatible = "asus,zenbook-a14-ux3407ra" },
 	{ .compatible = "dell,inspiron-14-plus-7441" },

-- 
2.53.0

Re: [PATCH 3/3] firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14 (UX3407NA)

[Dmitry Baryshkov]

On Tue, Jun 23, 2026 at 01:31:51AM +0000, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> 
> In line with other Glymur-based machines, the Asus Zenbook A14
> (UX3407NA) exposes EFI variables through the "uefisecapp". Add it to the
> QSEECOM allowlist to enable this access.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
>  drivers/firmware/qcom/qcom_scm.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 2/3] arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)

[Chris Pouliot]

Hi Nicko,

I have an ASUS Zenbook A14 UX3407NA as well and have been investigating the audio issue further.

On my unit I see the same basic hardware layout you described: the two WSA8845 devices on swr0 attach, while the two devices described on swr3 remain unattached. I now have working stereo speakers and internal microphone on NixOS.

The currently working setup is:

keep the stock 4-channel GLYMUR-CRD AudioReach topology
remove the nonexistent WSA2/swr3 speaker path from the board/UCM configuration
constrain the WSA codec-DMA backend to 2 channels in the x1e80100 machine driver
map the frontend channel order so physical left/right, which land in PCM slots 0 and 2, are exposed as normal stereo

I have also started turning this into cleaner, distribution-independent patches for the DTS, AudioReach topology, and alsa-ucm-conf here:

https://github.com/chrispouliot/ux3407na-linux-audio

Those exact upstream-style patches have not been tested yet; they are currently intended as RFC material. In particular, I am not yet sure whether the correct upstream solution is a board-specific 2-channel AudioReach topology, or whether Glymur should retain the 4-channel frontend and express the 2-channel speaker constraint elsewhere.

I would appreciate any guidance on where that constraint is expected to live upstream.

Thanks,
Chris

On Mon, Aug 03, 2026 at 10:19:33AM -0600, Nicko van Someren wrote:
> On Jun 22, 2026, at 19:31, Bjorn Andersson <andersson@kernel.org> wrote:
> 
> > From: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > 
> > UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
> > Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
> > the other typical Glymur platform capabilities.
> 
> Firstly, many thanks for this. I recently acquired one of these machines
> for some firmware work I'm doing and having a working Linux system on it
> makes my life much easier!
> 
> I tested this patch set, along with the others it depends on. I have it
> mostly working now but ran into some issues that might indicate a few
> changes.
> 
> WIFI:
> 
> > + wifi@0 {
> > + compatible = "pci17cb,1107";
> > ...
> > + };
> 
> ASUS don't specify what WiFi7 chip they use, which is fairly normal since
> ASUS tends to swap the parts depending on supply. As a result, my machine
> has a QCC2072 (17cb:1112) WiFi/BT module not the WCN7850 (17cb:1107) device
> that you listed. Inspection of the hardware shows that the WiFi/BT module
> is a solder-down M.2 LGA module, but electrically that's still an M.2
> interface. Photos that I can find of the Zenbook A16 show it does the same.
> I think it might be more reliable to define a wlan-connector, like Konrad
> Dybcio did in the Asus Zenbook A16 (UX3607OA) (2/3) from 2026-07-21,
> rather than specify the chip.
> 
> 
> SOUND:
> 
> Regarding sound definitions, the dts declares four WSA8845s -- a woofer
> and tweeter per side, two on swr0 and two on swr3. 
> 
> > +&swr0 {
> > + status = "okay";
> > +
> > + /* WSA8845, left woofer */
> > ...
> > +
> > + /* WSA8845, left tweeter */
> > ...
> > +};
> > +
> > +&swr3 {
> > + status = "okay";
> > ...
> > + /* WSA8845, right woofer */
> > ...
> > +
> > + /* WSA8845, right tweeter */
> > ...
> > +};
> 
> This machine only has two speakers (again confirmed by physical inspection).
> Only swr0 shows attached on /sys/bus/soundwire/devices/sdw:*/status:
> 
>   sdw:1:0:0217:0204:00:0   Attached
>   sdw:1:0:0217:0204:00:1   Attached
>   sdw:4:0:0217:0204:00:0   UNATTACHED
>   sdw:4:0:0217:0204:00:1   UNATTACHED
> 
> I don't think that's a config fault either; the swr0 and swr3 reset lines are
> both claimed and in identical state of (out, 0, 2mA, no pull). It's not really
> a surprise that the cheaper model from ASUS would not use the full spec audio
> offered on the Qualcomm reference designs, but without a suitable
> UX3407NA-tplg.bin topology file I can't really tell more.
> 
> It appears that the audio setup is blocked further up the audio stack anyway.
> I hacked some dts changes, purloined blobs from Windows and got a stereo speaker
> setup configured. SoundWire is healthy, but no audio is possible because the DSP
> does not respond. The ADSP boots and the audio PD is reported up:
> 
>   remoteproc remoteproc1: remote processor adsp is now up
>   PDR: Indication received from msm/adsp/audio_pd, state: 0x1fffffff
>   qcom,apr ...: Adding APR/GPR dev: gprsvc:service:2:1
> 
> then, on every boot:
> 
>   qcom-apm gprsvc:service:2:1: CMD timeout for [1001021] opcode
> 
> I'm curious as to if you tested this (or if this even known to work on the
> Zenbook A16, Yoga Slim 7x or EliteBook X G2q with the other submissions). Do
> you know if/when the required firmware blobs will be forthcoming and
> upstreamed?
> 
> 
> HDMI:
> 
> The built-in HDMI cannot read EDID: the connector reports "connected" with
> a monitor attached but the EDID is 0 bytes and there are no modes. Less than
> 2 seconds into every boot, before any cable is involved:
> 
>   gcc_usb3_tert_phy_com_aux_clk status stuck at 'off'
>   Failed to enable clk 'com_aux': -16
>   phy phy-88e1000.phy.5: phy init failed --> -16
> 
> I have not really investigated this in detail.
> 
> 
> eDP:
> 
> eDP link training intermittently times out on resume, leaving visible flicker
> until another suspend/resume retrains it:
> 
>   [drm:msm_dp_ctrl_link_train_1_2] *ERROR* link training #2 on phy 0 failed. ret=-110
> 
> I am carrying the (unmerged) "phy: qcom: edp: update v8 power-on
> programming sequence" series, so this may be feedback for that rather than
> a report against mainline.
> 
> 
> Anyway, thank you again for this patch series. It got me to the point of
> having a very usable machine for my limited needs. If you have updates the
> need testing I'm happy to help.
> 
> Nicko
> 
>