* [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:22 ` sashiko-bot
2026-07-17 12:06 ` [PATCH v3 02/11] arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi Ioana Ciornei
` (10 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
Explicitly enable the serdes_1 node in all board DT files. This is
needed in order to be able to change the default status of the node to
"disabled" from the SoC DT file.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- new patch
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 4 ++++
4 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 4bc151d721dd..1f946d3a4ec0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -135,6 +135,10 @@ &sata3 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
index d16e27307275..954b9955b1b3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -805,6 +805,10 @@ &rgmii_phy1 {
status = "disabled";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 935f421475ac..39b2b04be532 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -325,6 +325,10 @@ &sata3 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 99ee2b1c0f13..df2568ec7f1a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -367,6 +367,10 @@ &pcs_mdio18 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node
2026-07-17 12:06 ` [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node Ioana Ciornei
@ 2026-07-17 12:22 ` sashiko-bot
2026-07-17 12:49 ` Ioana Ciornei
0 siblings, 1 reply; 15+ messages in thread
From: sashiko-bot @ 2026-07-17 12:22 UTC (permalink / raw)
To: Ioana Ciornei; +Cc: Frank.Li, imx, robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incomplete device tree update: the patch claims to explicitly enable the `serdes_1` node in "all board DT files" to prepare for an SoC default change, but misses several LX2160A and LX2162A board files.
--
--- Patch [1]: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node ---
commit d3826fcfc7d054169418a33dbec45e352c709bff
Author: Ioana Ciornei <ioana.ciornei@nxp.com>
arm64: dts: lx2160a: explicitly enable serdes_1 node
This commit enables the serdes_1 node in board-specific device tree files.
This change prepares for a subsequent update that will set the default
status of the serdes_1 node to disabled in the main SoC device tree.
> Explicitly enable the serdes_1 node in all board DT files. This is
> needed in order to be able to change the default status of the node to
> "disabled" from the SoC DT file.
[Severity: High]
Does this commit miss updating several other lx2160a and lx2162a board
files?
If the default status in the SoC device tree file is changed to disabled,
it appears boards that rely on serdes_1 for high-speed IO (PCIe,
networking, SATA) might be left without functional interfaces.
Could the following board files also need the serdes_1 node enabled:
- arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
- arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
- arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
Is there a reason these files were omitted from this patch?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717120635.2118610-1-ioana.ciornei@nxp.com?part=1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node
2026-07-17 12:22 ` sashiko-bot
@ 2026-07-17 12:49 ` Ioana Ciornei
0 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:49 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Frank.Li, imx, robh, conor+dt, devicetree
On Fri, Jul 17, 2026 at 12:22:24PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Incomplete device tree update: the patch claims to explicitly enable the `serdes_1` node in "all board DT files" to prepare for an SoC default change, but misses several LX2160A and LX2162A board files.
> --
>
> --- Patch [1]: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node ---
> commit d3826fcfc7d054169418a33dbec45e352c709bff
> Author: Ioana Ciornei <ioana.ciornei@nxp.com>
>
> arm64: dts: lx2160a: explicitly enable serdes_1 node
>
> This commit enables the serdes_1 node in board-specific device tree files.
> This change prepares for a subsequent update that will set the default
> status of the serdes_1 node to disabled in the main SoC device tree.
>
> > Explicitly enable the serdes_1 node in all board DT files. This is
> > needed in order to be able to change the default status of the node to
> > "disabled" from the SoC DT file.
>
> [Severity: High]
> Does this commit miss updating several other lx2160a and lx2162a board
> files?
>
> If the default status in the SoC device tree file is changed to disabled,
> it appears boards that rely on serdes_1 for high-speed IO (PCIe,
> networking, SATA) might be left without functional interfaces.
>
> Could the following board files also need the serdes_1 node enabled:
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
>
> Is there a reason these files were omitted from this patch?
This is not a valid concern.
The above listed board files were not updated because they are not
active users of the serdes_1 node (no MAC node is currently referencing
it), thus enabling it is not necessary.
Ioana
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 02/11] arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 03/11] arm64: dts: lx2160a: extract the SerDes " Ioana Ciornei
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
One of the major differences between LX2160A Rev1 and Rev2 is the PCIe
controller used. With the final goal of removing any usage of
delete-node or delete-property from the current LX2160A related dts
files, move the PCIe nodes found on the LX2160A Rev1 into a separate
dtsi file. This will make it easier to include the appropriate dtsi
file describing the PCIe controller depending on the SoC revision in a
follow-up patch.
No actual change in the DT nodes found in the final DTBs is intended.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- New patch
---
.../dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi | 176 ++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 170 +----------------
2 files changed, 178 insertions(+), 168 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi
new file mode 100644
index 000000000000..871f5d5d8f75
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file describing the PCIe Mobiveil's GPEX 4.0 IP
+// found on LX2160A Rev1
+//
+// Copyright 2026 NXP
+
+&soc {
+ pcie1: pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie2: pcie@3500000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie3: pcie@3600000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <256>;
+ ppio-wins = <24>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie4: pcie@3700000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie5: pcie@3800000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
+ <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <256>;
+ ppio-wins = <24>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
+ pcie6: pcie@3900000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
+ <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 1d73abffa6b7..387cd677cdc7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1177,174 +1177,6 @@ sata3: sata@3230000 {
status = "disabled";
};
- pcie1: pcie@3400000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
- <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
- pcie2: pcie@3500000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
- <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
- pcie3: pcie@3600000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
- <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
- pcie4: pcie@3700000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
- <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
- pcie5: pcie@3800000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
- <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
- pcie6: pcie@3900000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
- <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "aer", "pme", "intr";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
- bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its 0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- status = "disabled";
- };
-
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
@@ -2021,3 +1853,5 @@ optee: optee {
};
};
};
+
+#include "fsl-lx2160a-pcie-mbvl.dtsi"
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 03/11] arm64: dts: lx2160a: extract the SerDes nodes into a separate dtsi
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 02/11] arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 04/11] arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file Ioana Ciornei
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
In terms of its SerDes blocks, the LX2162A is not properly described
since it just inherits the LX2160A SerDes nodes, which is not correct.
In order to fix this but also avoid the usage of delete-node, we need to
first extract the SerDes nodes currently found in fsl-lx2160a.dtsi into a
separate dtsi.
This patch does not intend to do any actual changes in the final dtb
files, only a dt node move.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- New patch
---
.../dts/freescale/fsl-lx2160a-serdes.dtsi | 21 +++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 14 +------------
2 files changed, 22 insertions(+), 13 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
new file mode 100644
index 000000000000..307824eda6d6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2160A
+// Rev1 and Rev2
+//
+// Copyright 2026 NXP
+
+&soc {
+ serdes_1: phy@1ea0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ };
+
+ serdes_2: phy@1eb0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 387cd677cdc7..da139e7fa30c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -621,19 +621,6 @@ soc: soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
- serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
- reg = <0x0 0x1ea0000 0x0 0x1e30>;
- #phy-cells = <1>;
- };
-
- serdes_2: phy@1eb0000 {
- compatible = "fsl,lynx-28g";
- reg = <0x0 0x1eb0000 0x0 0x1e30>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
@@ -1855,3 +1842,4 @@ optee: optee {
};
#include "fsl-lx2160a-pcie-mbvl.dtsi"
+#include "fsl-lx2160a-serdes.dtsi"
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 04/11] arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (2 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 03/11] arm64: dts: lx2160a: extract the SerDes " Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 05/11] arm64: dts: lx2160a: split the dtsi to avoid delete-property Ioana Ciornei
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
The LX2160A Rev2 SoC changed the PCIe controllers used. This difference
is reflected in the fsl-lx2160a-rev2.dtsi file which modifies the
relevant dt nodes so that they match the actual HW.
Extract these modifications into a separate dtsi file as a first step
into a complete overhaul of the LX216xA related dts files with the
intent to not use delete-node or delete-property. No final dtb changes
are expected with this patch.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- New patch
---
.../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 185 +----------------
.../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 187 ++++++++++++++++++
2 files changed, 188 insertions(+), 184 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
index 3d2637fee2d3..c2a18cfd8efc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
@@ -7,187 +7,4 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
-
-&pcie1 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie2 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie3 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-
-&pcie4 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie5 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie6 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&soc {
- pcie_ep1: pcie-ep@3400000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x80 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <8>;
- num-ib-windows = <8>;
- status = "disabled";
- };
-
- pcie_ep2: pcie-ep@3500000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x88 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <8>;
- num-ib-windows = <8>;
- status = "disabled";
- };
-
- pcie_ep3: pcie-ep@3600000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x90 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <256>;
- num-ib-windows = <24>;
- status = "disabled";
- };
-
- pcie_ep4: pcie-ep@3700000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03700000 0x0 0x00100000
- 0x98 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <8>;
- num-ib-windows = <8>;
- status = "disabled";
- };
-
-
- pcie_ep5: pcie-ep@3800000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03800000 0x0 0x00100000
- 0xa0 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <256>;
- num-ib-windows = <24>;
- status = "disabled";
- };
-
- pcie_ep6: pcie-ep@3900000 {
- compatible = "fsl,lx2160ar2-pcie-ep";
- reg = <0x00 0x03900000 0x0 0x00100000
- 0xa8 0x00000000 0x8 0x00000000>;
- reg-names = "regs", "addr_space";
- num-ob-windows = <8>;
- num-ib-windows = <8>;
- status = "disabled";
- };
-};
+#include "fsl-lx216xa-pcie-gen3.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
new file mode 100644
index 000000000000..f405b21e68fc
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file describing the PCIe IPs found on the LX2160A Rev2 and LX2162A SoCs
+//
+// Copyright 2026 NXP
+
+&pcie1 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&pcie2 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&pcie3 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&pcie4 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&pcie5 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&pcie6 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ /delete-property/ apio-wins;
+ /delete-property/ ppio-wins;
+};
+
+&soc {
+ pcie_ep1: pcie-ep@3400000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
+ pcie_ep2: pcie-ep@3500000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
+ pcie_ep3: pcie-ep@3600000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
+ pcie_ep4: pcie-ep@3700000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
+ pcie_ep5: pcie-ep@3800000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
+ pcie_ep6: pcie-ep@3900000 {
+ compatible = "fsl,lx2160ar2-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 05/11] arm64: dts: lx2160a: split the dtsi to avoid delete-property
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (3 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 04/11] arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 06/11] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Ioana Ciornei
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
This patch reorganizes the LX216XA related dts/dtsi files with the
intent to avoid any delete-property usage.
Taken into consideration the differences between the LX2160A Rev1,
LX2160A Rev2 and LX2162A SoCs, the following structure is created:
fsl-lx216x.dtsi ---> fsl-lx2160a-rev1.dtsi (PCIe gen4, 3 SerDes blocks)
(no PCIe, no SerDes) ---> fsl-lx2160a-rev2.dtsi (PCIe gen3, 3 SerDes blocks)
---> fsl-lx2162a.dtsi (PCIe gen3, 2 SerDes blocks)
Each PCIe integration or SerDes block instantiation has its own dtsi
file which gets to be included only by the necessary SoC level dtsi
file.
The dtsi file describing the PCIe controllers found on LX2160A Rev2 is
also changed so that it does not work on a already defined node but
rather it describes it entirely.
In order to decouple the LX2162A from LX2160A, a new dtsi
fsl-lx2162a-serdes.dtsi file is added which, for the moment, only
duplicates the SerDes related nodes found already for LX2160A.
Any dts which previously included fsl-lx2160a.dtsi now includes the
-rev1 version and any dts which is clearly intended for LX2162A based
board now includes the fsl-lx2162a.dtsi. This patch does not intent any
changes into the final dtbs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- New patch
- The only changes in the final dtbs are phandle related ones.
---
.../dts/freescale/fsl-lx2160a-bluebox3.dts | 2 +-
.../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 +-
.../dts/freescale/fsl-lx2160a-honeycomb.dts | 2 +-
.../boot/dts/freescale/fsl-lx2160a-rev1.dtsi | 9 +
.../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 3 +-
.../dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi | 2 +-
.../dts/freescale/fsl-lx2162a-clearfog.dts | 2 +-
.../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
.../dts/freescale/fsl-lx2162a-serdes.dtsi | 21 ++
.../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 9 +
.../{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} | 3 -
.../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 304 +++++++++++-------
12 files changed, 234 insertions(+), 127 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
rename arch/arm64/boot/dts/freescale/{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} (99%)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
index 042c486bdda2..e035e4456867 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev1.dtsi"
/ {
model = "NXP Layerscape LX2160ABLUEBOX3";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
index 802d7611c647..4e47bb389af6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
index 2b1e13053422..1a603decd034 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi
new file mode 100644
index 000000000000..7538dbdc8093
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A Rev1 SoC.
+//
+// Copyright 2026 NXP
+
+#include "fsl-lx216x.dtsi"
+#include "fsl-lx2160a-pcie-mbvl.dtsi"
+#include "fsl-lx2160a-serdes.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
index c2a18cfd8efc..47a42347c230 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
@@ -6,5 +6,6 @@
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx216x.dtsi"
#include "fsl-lx216xa-pcie-gen3.dtsi"
+#include "fsl-lx2160a-serdes.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
index 89a4765737b4..cc6b6427ec8a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
@@ -5,7 +5,7 @@
* Author: Gregor Herburger
*/
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev1.dtsi"
/ {
reg_vcc3v3: regulator-vcc3v3 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index df2568ec7f1a..63f161610caa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -8,7 +8,7 @@
#include <dt-bindings/leds/common.h>
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 7a595fddc027..0ba56b9819ac 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
new file mode 100644
index 000000000000..23f05a138eac
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A
+// SoC
+//
+// Copyright 2026 NXP
+
+&soc {
+ serdes_1: phy@1ea0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ };
+
+ serdes_2: phy@1eb0000 {
+ compatible = "fsl,lynx-28g";
+ reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
new file mode 100644
index 000000000000..b710f6a8eb48
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2162 SoC
+//
+// Copyright 2026 NXP
+
+#include "fsl-lx216x.dtsi"
+#include "fsl-lx216xa-pcie-gen3.dtsi"
+#include "fsl-lx2162a-serdes.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
rename to arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
index da139e7fa30c..ae6e37870c5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
@@ -1840,6 +1840,3 @@ optee: optee {
};
};
};
-
-#include "fsl-lx2160a-pcie-mbvl.dtsi"
-#include "fsl-lx2160a-serdes.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
index f405b21e68fc..068fbf9bf04f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
@@ -4,127 +4,39 @@
//
// Copyright 2026 NXP
-&pcie1 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie2 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie3 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie4 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie5 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
-
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
-
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
-
-&pcie6 {
- compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
+&soc {
+ pcie1: pcie@3400000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
- ranges = /* 16-Bit IO Window */
- <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
- /* 32-Bit - non-prefetchable */
- <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
- /* 64-Bit - prefetchable - 16GB */
- <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr";
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
- /delete-property/ apio-wins;
- /delete-property/ ppio-wins;
-};
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
-&soc {
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
@@ -135,6 +47,37 @@ pcie_ep1: pcie-ep@3400000 {
status = "disabled";
};
+ pcie2: pcie@3500000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
@@ -145,6 +88,38 @@ pcie_ep2: pcie-ep@3500000 {
status = "disabled";
};
+ pcie3: pcie@3600000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
@@ -155,6 +130,37 @@ pcie_ep3: pcie-ep@3600000 {
status = "disabled";
};
+ pcie4: pcie@3700000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
pcie_ep4: pcie-ep@3700000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
@@ -165,6 +171,38 @@ pcie_ep4: pcie-ep@3700000 {
status = "disabled";
};
+ pcie5: pcie@3800000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
pcie_ep5: pcie-ep@3800000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
@@ -175,6 +213,38 @@ pcie_ep5: pcie-ep@3800000 {
status = "disabled";
};
+ pcie6: pcie@3900000 {
+ compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+
+ ranges = /* 16-Bit IO Window */
+ <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
+ /* 32-Bit - non-prefetchable */
+ <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
+ /* 64-Bit - prefetchable - 16GB */
+ <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
+
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ msi-parent = <&its 0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ status = "disabled";
+ };
+
pcie_ep6: pcie-ep@3900000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 06/11] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (4 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 05/11] arm64: dts: lx2160a: split the dtsi to avoid delete-property Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 07/11] arm64: dts: lx2162a: " Ioana Ciornei
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
instance is present in the compatible string, to allow reliable per-lane
capability detection and per-lane customization of electrical properties.
The modern bindings are backward-incompatible with old kernels, due
to the consumer phandles being either in one form or in another, as
explained here:
https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
Also mark the serdes_1 node as disabled by default since any dts using
it enables it explicitly now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- Split the enabling of serdes_1 into a separate patch
- Split the LX2162A changes to another patch
- Move the status property to be the last for serdes_3
- Move the changes to the new fsl-lx2160a-serdes.dtsi file
Changes in v2:
- Enable serdes_1 on all board DTs that has consumers for it.
- Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
- Remove paragraph from commit message which mentioned some consumer
changes that are no longer needed nor part of the commit.
---
.../dts/freescale/fsl-lx2160a-serdes.dtsi | 150 +++++++++++++++++-
1 file changed, 148 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
index 307824eda6d6..d482920f4d17 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
@@ -6,16 +6,162 @@
// Copyright 2026 NXP
&soc {
+ /* Note on the interpretation of SerDes lane numbering from
+ * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
+ * The letters (A-H) correspond to logical lane numbers in the
+ * SerDes register map (lane A's registers start with LNAGCR0),
+ * while the numbers (0-7) correspond to physical lanes as
+ * routed to pins. SerDes block #1 is flipped in the LX2160A
+ * floorplan (logical lane A goes to physical lane 7's pins),
+ * while SerDes blocks #2 and #3 are not. The lanes below are
+ * listed right to left when looking at that table.
+ * Both the numbers and the letters are according to the logical
+ * numbering scheme, and do not account for the flipping.
+ */
serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+ status = "disabled";
+
+ serdes_1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
serdes_2: phy@1eb0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
+
+ serdes_2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes_3: phy@1ec0000 {
+ compatible = "fsl,lx2160a-serdes3";
+ reg = <0x0 0x1ec0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes_3_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 07/11] arm64: dts: lx2162a: transition to device-specific SerDes compatible strings
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (5 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 06/11] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 08/11] arm64: dts: ls1028a: describe the Lynx 10G SerDes Ioana Ciornei
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
Align to the modern fsl,lynx-28g.yaml binding for the LX2162A SoC, where
the SoC and SerDes instance is present in the compatible string, to
allow reliable per-lane capability detection and per-lane customization
of electrical properties.
Since one of the major differences between LX2162A and LX2160A is the
SerDes, add the necessary nodes to its own fsl-lx2162a-serdes.dtsi file.
Also mark the serdes_1 node as disabled by default since any dts using
it enables it explicitly now.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- New patch
---
.../dts/freescale/fsl-lx2162a-serdes.dtsi | 69 ++++++++++++++++++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
index 23f05a138eac..1ab18f0c67c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
@@ -7,15 +7,80 @@
&soc {
serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+ status = "disabled";
+
+ serdes_1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
serdes_2: phy@1eb0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
+
+ serdes_2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 08/11] arm64: dts: ls1028a: describe the Lynx 10G SerDes
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (6 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 07/11] arm64: dts: lx2162a: " Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 09/11] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Ioana Ciornei
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the
LS1028A SoC. The node is left disabled at the SoC level; board DTs will
be expected to enable it once the consumer Ethernet nodes use it.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- None
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index f4ba3d16ab86..ef62968590fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
};
};
+ serdes: phy@1ea0000 {
+ compatible = "fsl,ls1028a-serdes";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
scfg: syscon@1fc0000 {
compatible = "fsl,ls1028a-scfg", "syscon";
reg = <0x0 0x1fc0000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 09/11] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (7 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 08/11] arm64: dts: ls1028a: describe the Lynx 10G SerDes Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 10/11] arm64: dts: ls208xa: " Ioana Ciornei
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1046A SoC. The nodes are left disabled at the SoC level; board
DTs will be expected to enable them once the consumer Ethernet nodes
appear.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- None
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 6fefe837f434..270a97711a69 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1046a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1046a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 10/11] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (8 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 09/11] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 12:06 ` [PATCH v3 11/11] arm64: dts: ls1088a: " Ioana Ciornei
2026-07-17 15:53 ` [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Frank Li
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS208xA SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- None
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 6073e426774a..cc1a64e63ed5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -280,6 +280,104 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls2088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls2088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls2080a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 11/11] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (9 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 10/11] arm64: dts: ls208xa: " Ioana Ciornei
@ 2026-07-17 12:06 ` Ioana Ciornei
2026-07-17 15:53 ` [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Frank Li
11 siblings, 0 replies; 15+ messages in thread
From: Ioana Ciornei @ 2026-07-17 12:06 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx, linux
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1088A SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Note that the SerDes block #2 is non-networking, meaning that it will
not get probed by the Lynx10G SerDes PHY driver and it's only added for
a complete hardware description.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- None
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 99016768b73f..e02f34329988 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -239,6 +239,64 @@ reset: syscon@1e60000 {
reg = <0x0 0x1e60000 0x0 0x10000>;
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs
2026-07-17 12:06 [PATCH v3 00/11] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (10 preceding siblings ...)
2026-07-17 12:06 ` [PATCH v3 11/11] arm64: dts: ls1088a: " Ioana Ciornei
@ 2026-07-17 15:53 ` Frank Li
11 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2026-07-17 15:53 UTC (permalink / raw)
To: Ioana Ciornei
Cc: Frank.Li, robh, krzk+dt, conor+dt, devicetree, vladimir.oltean,
linux-arm-kernel, linux-kernel, imx, linux
On Fri, Jul 17, 2026 at 03:06:24PM +0300, Ioana Ciornei wrote:
> This patch set adds the device tree nodes for the Lynx10G SerDes blocks
> found on the LS1028A, LS1046A, LS1088A and LS2088A SoCs.
>
> The first 5 patches slowly change the LX2160A DTS support to a new
> structure which does not use any delete-node or delete-property
> directives. This is a direct result of the discussion with Frank in the
> v2 of this set:
> https://lore.kernel.org/all/akwAmzAbtg0Ejey0@SMW015318/
>
> Patches 5 and 6 transition the LX2160A and LX2162 SoC dtsi to use the
> device-specific Lynx28G SerDes compatible while the remainder of the set
> adds the SerDes block descriptions for the LS1028A, LS1046A, LS2088A and
> LS1088A SoCs.
>
> Changes in v3:
> - Changes how the LX216XA based SoC dtsi files are structured.
> - Split the enabling of serdes_1 into a separate patch
> - Split the LX2162A changes to another patch
> - Move the status property to be the last for serdes_3
> - Move the changes to the new fsl-lx2160a-serdes.dtsi file
Overall look good, let wait for some days for other reviewers.
Frank
>
> Changes in v2:
> - Enable serdes_1 on all board DTs that has consumers for it.
> - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> - Remove paragraph from commit message which mentioned some consumer
> changes that are no longer needed nor part of the commit.
> - Change the size of the SerDes region to 0x2000
>
> Ioana Ciornei (8):
> arm64: dts: lx2160a: explicitly enable serdes_1 node
> arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi
> arm64: dts: lx2160a: extract the SerDes nodes into a separate dtsi
> arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a
> separate file
> arm64: dts: lx2160a: split the dtsi to avoid delete-property
> arm64: dts: lx2160a: transition to device-specific SerDes compatible
> strings
> arm64: dts: lx2162a: transition to device-specific SerDes compatible
> strings
> arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
>
> Vladimir Oltean (3):
> arm64: dts: ls1028a: describe the Lynx 10G SerDes
> arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
> arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
>
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 ++
> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 ++++
> .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 ++++
> .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++
> .../dts/freescale/fsl-lx2160a-bluebox3.dts | 2 +-
> .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 +-
> .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
> .../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
> .../dts/freescale/fsl-lx2160a-honeycomb.dts | 2 +-
> .../dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi | 176 ++++++++++++
> .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
> .../boot/dts/freescale/fsl-lx2160a-rev1.dtsi | 9 +
> .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 188 +------------
> .../dts/freescale/fsl-lx2160a-serdes.dtsi | 167 ++++++++++++
> .../dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi | 2 +-
> .../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
> .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
> .../dts/freescale/fsl-lx2162a-serdes.dtsi | 86 ++++++
> .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 9 +
> .../{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} | 181 ------------
> .../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 257 ++++++++++++++++++
> 21 files changed, 974 insertions(+), 372 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> rename arch/arm64/boot/dts/freescale/{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} (86%)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread