* [PATCH 0/4] arm64: dts: qcom: nord: Add display support
@ 2026-09-18 1:37 Shawn Guo
2026-09-18 1:37 ` [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Shawn Guo
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 1:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
Nord has two independent display subsystems, MDSS0 at 0xae00000 and
MDSS1 at 0x8c00000, each with a DPU, two DP controllers and two eDP
PHYs. The SoC is DP-only, so there are no DSI blocks.
This series adds the display and remaining clock controller nodes for
the Nord SoC, and enables the eDP outputs on the Ride Embedded (eDP0-3)
and RRD (eDP0/1) boards.
Dependencies:
- Display and PHY: https://lore.kernel.org/all/20260911-nord-drv-dt-v1-0-e25c073cf1b6@oss.qualcomm.com/
- Prerequisite DTS: https://lore.kernel.org/all/20260904081619.593602-1-shengchao.guo@oss.qualcomm.com/
Ritesh Kumar (3):
arm64: dts: qcom: nord: Add display subsystem nodes
arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output
arm64: dts: qcom: nord-rrd: Enable eDP0/1 display output
Taniya Das (1):
arm64: dts: qcom: nord: Add more clock controller nodes
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 615 ++++++++++++++++++
.../boot/dts/qcom/nord-ride-embedded.dts | 128 ++++
arch/arm64/boot/dts/qcom/nord-rrd.dts | 62 ++
arch/arm64/boot/dts/qcom/nord.dtsi | 266 ++++++++
4 files changed, 1071 insertions(+)
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes
2026-09-18 1:37 [PATCH 0/4] arm64: dts: qcom: nord: Add display support Shawn Guo
@ 2026-09-18 1:37 ` Shawn Guo
2026-09-20 7:58 ` Shawn Guo
2026-09-18 1:37 ` [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes Shawn Guo
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 1:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add the GPU, camera, video, and display clock controller nodes for
the Qualcomm Nord SoC, along with their required dt-bindings includes.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 108 ++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index c7ac2e66632e..6dc4c871f41e 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -3,7 +3,11 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,glymur-videocc.h>
+#include <dt-bindings/clock/qcom,nord-camcc.h>
+#include <dt-bindings/clock/qcom,nord-dispcc.h>
#include <dt-bindings/clock/qcom,nord-gcc.h>
+#include <dt-bindings/clock/qcom,nord-gpucc.h>
#include <dt-bindings/clock/qcom,nord-negcc.h>
#include <dt-bindings/clock/qcom,nord-nwgcc.h>
#include <dt-bindings/clock/qcom,nord-segcc.h>
@@ -835,6 +839,17 @@ hscnoc: interconnect@2000000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,nord-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&nwgcc NW_GCC_GPU_GPLL0_CLK_SRC>,
+ <&nwgcc NW_GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
hpass_ag_noc: interconnect@5fc0000 {
compatible = "qcom,nord-hpass-ag-noc";
reg = <0x0 0x05fc0000 0x0 0x37080>;
@@ -877,6 +892,99 @@ nwgcc: clock-controller@8b00000 {
#power-domain-cells = <1>;
};
+ dispcc1: clock-controller@8d00000 {
+ compatible = "qcom,nord-dispcc1";
+ reg = <0x0 0x08d00000 0x0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&nwgcc NW_GCC_DISP_1_AHB_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpu2cc: clock-controller@9890000 {
+ compatible = "qcom,nord-gpu2cc";
+ reg = <0x0 0x09890000 0x0 0xa000>;
+ clocks = <&bi_tcxo_div2>,
+ <&negcc NE_GCC_GPU_2_GPLL0_CLK_SRC>,
+ <&negcc NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@9ce0000 {
+ compatible = "qcom,nord-camcc";
+ reg = <0x0 0x09ce0000 0x0 0x20000>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ clocks = <&nwgcc NW_GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,nord-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&nwgcc NW_GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc0: clock-controller@af00000 {
+ compatible = "qcom,nord-dispcc0";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&nwgcc NW_GCC_DISP_0_AHB_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
tcsrcc: clock-controller@f1d9000 {
compatible = "qcom,nord-tcsrcc",
"syscon";
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes
2026-09-18 1:37 [PATCH 0/4] arm64: dts: qcom: nord: Add display support Shawn Guo
2026-09-18 1:37 ` [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Shawn Guo
@ 2026-09-18 1:37 ` Shawn Guo
2026-09-18 7:36 ` Shawn Guo
2026-09-18 1:37 ` [PATCH 3/4] arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output Shawn Guo
2026-09-18 1:37 ` [PATCH 4/4] arm64: dts: qcom: nord-rrd: Enable eDP0/1 " Shawn Guo
3 siblings, 1 reply; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 1:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Add the MDSS, DPU, DP controller and eDP PHY nodes for the Qualcomm Nord
SoC. Nord has two independent display subsystems, MDSS0 at 0xae00000 and
MDSS1 at 0x8c00000, each with two DP controllers and two eDP PHYs. Nord
is DP-only, so no DSI nodes are added. Wire the DP PHY outputs into the
dispcc0 and dispcc1 clock inputs, which were previously stubbed with
zeroes, and add the eDP0-3 hot-plug-detect pinctrl states.
Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 523 +++++++++++++++++++-
arch/arm64/boot/dts/qcom/nord.dtsi | 266 ++++++++++
2 files changed, 781 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 6dc4c871f41e..74f4e6be8652 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -346,6 +346,489 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
pinctrl-names = "default";
};
+&mdss {
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ dp0_phy: phy@fc3a00 {
+ compatible = "qcom,nord-dp-phy";
+ reg = <0x0 0x0fc3a00 0x0 0x1d0>,
+ <0x0 0x0fc3200 0x0 0x128>,
+ <0x0 0x0fc3600 0x0 0x128>,
+ <0x0 0x0fc3000 0x0 0x200>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&tcsrcc TCSR_DP_TX_0_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ status = "disabled";
+ };
+
+ dp1_phy: phy@fc6a00 {
+ compatible = "qcom,nord-dp-phy";
+ reg = <0x0 0x0fc6a00 0x0 0x200>,
+ <0x0 0x0fc6200 0x0 0xd0>,
+ <0x0 0x0fc6600 0x0 0xd0>,
+ <0x0 0x0fc6000 0x0 0x1c8>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&tcsrcc TCSR_DP_TX_1_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ status = "disabled";
+ };
+};
+
+&mdss_mdp {
+ clocks = <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-532000000 {
+ opp-hz = /bits/ 64 <532000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ opp-710000000 {
+ opp-hz = /bits/ 64 <710000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+};
+
+&mdss_dp0 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&dp0_phy 0>,
+ <&dp0_phy 1>,
+ <&dp0_phy 1>,
+ <&dp0_phy 1>,
+ <&dp0_phy 1>;
+
+ phys = <&dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ pinctrl-0 = <&dp0_hot_plug_det>;
+ pinctrl-names = "default";
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+};
+
+&mdss_dp1 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&dp1_phy 0>,
+ <&dp1_phy 1>,
+ <&dp1_phy 1>;
+
+ phys = <&dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp1_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ pinctrl-0 = <&dp1_hot_plug_det>;
+ pinctrl-names = "default";
+
+ dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+};
+
+&mdss1 {
+ power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_1_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ dp2_phy: phy@fc9a00 {
+ compatible = "qcom,nord-dp-phy";
+ reg = <0x0 0x0fc9a00 0x0 0x1d0>,
+ <0x0 0x0fc9200 0x0 0x128>,
+ <0x0 0x0fc9600 0x0 0x128>,
+ <0x0 0x0fc9000 0x0 0x200>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&tcsrcc TCSR_DP_TX_2_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ status = "disabled";
+ };
+
+ dp3_phy: phy@fcca00 {
+ compatible = "qcom,nord-dp-phy";
+ reg = <0x0 0x0fcca00 0x0 0x200>,
+ <0x0 0x0fcc200 0x0 0xd0>,
+ <0x0 0x0fcc600 0x0 0xd0>,
+ <0x0 0x0fcc000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&tcsrcc TCSR_DP_TX_3_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ status = "disabled";
+ };
+};
+
+&mdss1_mdp {
+ clocks = <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp1_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ mdp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-532000000 {
+ opp-hz = /bits/ 64 <532000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-710000000 {
+ opp-hz = /bits/ 64 <710000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+};
+
+&mdss1_dp0 {
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&dp2_phy 0>,
+ <&dp2_phy 1>,
+ <&dp2_phy 1>,
+ <&dp2_phy 1>,
+ <&dp2_phy 1>;
+
+ phys = <&dp2_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp2_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ pinctrl-0 = <&dp2_hot_plug_det>;
+ pinctrl-names = "default";
+
+ dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+};
+
+&mdss1_dp1 {
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&dp3_phy 0>,
+ <&dp3_phy 1>,
+ <&dp3_phy 1>;
+
+ phys = <&dp3_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp3_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ pinctrl-0 = <&dp3_hot_plug_det>;
+ pinctrl-names = "default";
+
+ dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+};
+
&qupv3_0 {
clocks = <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>,
<&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>;
@@ -903,10 +1386,10 @@ dispcc1: clock-controller@8d00000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&dp2_phy 0>,
+ <&dp2_phy 1>,
+ <&dp3_phy 0>,
+ <&dp3_phy 1>,
<0>,
<0>,
<0>,
@@ -970,10 +1453,10 @@ dispcc0: clock-controller@af00000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&dp0_phy 0>,
+ <&dp0_phy 1>,
+ <&dp1_phy 0>,
+ <&dp1_phy 1>,
<0>,
<0>,
<0>,
@@ -1106,6 +1589,30 @@ nsp_data_noc_3: interconnect@1fe00000 {
};
&tlmm {
+ dp0_hot_plug_det: dp0-hot-plug-det-state {
+ pins = "gpio51";
+ function = "edp0_hot";
+ bias-disable;
+ };
+
+ dp1_hot_plug_det: dp1-hot-plug-det-state {
+ pins = "gpio52";
+ function = "edp1_hot";
+ bias-disable;
+ };
+
+ dp2_hot_plug_det: dp2-hot-plug-det-state {
+ pins = "gpio53";
+ function = "edp2_hot";
+ bias-disable;
+ };
+
+ dp3_hot_plug_det: dp3-hot-plug-det-state {
+ pins = "gpio54";
+ function = "edp3_hot";
+ bias-disable;
+ };
+
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio111", "gpio112";
function = "qup0_se0";
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index 926ccf3bbe4e..73136c27bac1 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1727,6 +1727,139 @@ compute-cb@6 {
};
};
+ /* Display subsystem nodes - MDSS1, DP-only (no DSI) */
+ mdss1: display-subsystem@8c00000 {
+ compatible = "qcom,nord-mdss";
+ reg = <0x0 0x08c00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu_1 0x400 0x2>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss1_mdp: display-controller@8c01000 {
+ compatible = "qcom,nord-dpu";
+ reg = <0x0 0x08c01000 0x0 0x8f000>,
+ <0x0 0x08cb0000 0x0 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu1_intf0_out: endpoint {
+ remote-endpoint = <&mdss1_dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu1_intf4_out: endpoint {
+ remote-endpoint = <&mdss1_dp1_in>;
+ };
+ };
+ };
+ };
+
+ mdss1_dp0: displayport-controller@8d54000 {
+ compatible = "qcom,nord-dp";
+ reg = <0x0 0x08d54000 0x0 0x200>,
+ <0x0 0x08d54200 0x0 0x200>,
+ <0x0 0x08d55000 0x0 0xc00>,
+ <0x0 0x08d56000 0x0 0x400>,
+ <0x0 0x08d57000 0x0 0x400>,
+ <0x0 0x08d58000 0x0 0x400>,
+ <0x0 0x08d59000 0x0 0x400>,
+ <0x0 0x08d5a000 0x0 0x600>,
+ <0x0 0x08d5b000 0x0 0x600>;
+
+ interrupts-extended = <&mdss1 12>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp0_in: endpoint {
+ remote-endpoint = <&dpu1_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss1_dp1: displayport-controller@8d5c000 {
+ compatible = "qcom,nord-dp";
+ reg = <0x0 0x08d5c000 0x0 0x200>,
+ <0x0 0x08d5c200 0x0 0x200>,
+ <0x0 0x08d5d000 0x0 0xc00>,
+ <0x0 0x08d5e000 0x0 0x400>,
+ <0x0 0x08d5f000 0x0 0x400>,
+ <0x0 0x08d60000 0x0 0x400>,
+ <0x0 0x08d61000 0x0 0x400>,
+ <0x0 0x08d62000 0x0 0x600>,
+ <0x0 0x08d63000 0x0 0x600>;
+
+ interrupts-extended = <&mdss1 13>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp1_in: endpoint {
+ remote-endpoint = <&dpu1_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp1_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+
ipcc0: mailbox@9007000 {
compatible = "qcom,nord-ipcc",
"qcom,ipcc";
@@ -1737,6 +1870,139 @@ ipcc0: mailbox@9007000 {
#mbox-cells = <2>;
};
+ /* Display subsystem nodes - MDSS 12.1, DP-only (no DSI) */
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,nord-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 930 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu_1 0x3e0 0x2>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,nord-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_intf4_out: endpoint {
+ remote-endpoint = <&mdss_dp1_in>;
+ };
+ };
+ };
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,nord-dp";
+ reg = <0x0 0x0af54000 0x0 0x200>,
+ <0x0 0x0af54200 0x0 0x200>,
+ <0x0 0x0af55000 0x0 0xc00>,
+ <0x0 0x0af56000 0x0 0x400>,
+ <0x0 0x0af57000 0x0 0x400>,
+ <0x0 0x0af58000 0x0 0x400>,
+ <0x0 0x0af59000 0x0 0x400>,
+ <0x0 0x0af5a000 0x0 0x600>,
+ <0x0 0x0af5b000 0x0 0x600>;
+
+ interrupts-extended = <&mdss 12>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dp1: displayport-controller@af5c000 {
+ compatible = "qcom,nord-dp";
+ reg = <0x0 0x0af5c000 0x0 0x200>,
+ <0x0 0x0af5c200 0x0 0x200>,
+ <0x0 0x0af5d000 0x0 0xc00>,
+ <0x0 0x0af5e000 0x0 0x400>,
+ <0x0 0x0af5f000 0x0 0x400>,
+ <0x0 0x0af60000 0x0 0x400>,
+ <0x0 0x0af61000 0x0 0x400>,
+ <0x0 0x0af62000 0x0 0x600>,
+ <0x0 0x0af63000 0x0 0x600>;
+
+ interrupts-extended = <&mdss 13>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp1_in: endpoint {
+ remote-endpoint = <&dpu_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp1_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output
2026-09-18 1:37 [PATCH 0/4] arm64: dts: qcom: nord: Add display support Shawn Guo
2026-09-18 1:37 ` [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Shawn Guo
2026-09-18 1:37 ` [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes Shawn Guo
@ 2026-09-18 1:37 ` Shawn Guo
2026-09-18 1:37 ` [PATCH 4/4] arm64: dts: qcom: nord-rrd: Enable eDP0/1 " Shawn Guo
3 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 1:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Enable both MDSS instances, the four DP controllers and the eDP0-3 PHYs
on the Nord Ride Embedded board and describe the eDP0-3 connectors,
their 4 data lanes and supported link frequencies.
Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
.../boot/dts/qcom/nord-ride-embedded.dts | 128 ++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
index 09ee525764ef..2ad26902ffe6 100644
--- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
+++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
@@ -53,6 +53,54 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ dp0_connector: connector-dp0 {
+ compatible = "dp-connector";
+ label = "eDP0";
+ type = "full-size";
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+
+ dp1_connector: connector-dp1 {
+ compatible = "dp-connector";
+ label = "eDP1";
+ type = "full-size";
+
+ port {
+ dp1_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp1_out>;
+ };
+ };
+ };
+
+ dp2_connector: connector-dp2 {
+ compatible = "dp-connector";
+ label = "eDP2";
+ type = "full-size";
+
+ port {
+ dp2_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp0_out>;
+ };
+ };
+ };
+
+ dp3_connector: connector-dp3 {
+ compatible = "dp-connector";
+ label = "eDP3";
+ type = "full-size";
+
+ port {
+ dp3_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp1_out>;
+ };
+ };
+ };
};
&apps_rsc {
@@ -366,6 +414,86 @@ vreg_l3l_1p8: ldo3 {
};
};
+&dp0_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
+&dp1_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
+&dp2_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
+&dp3_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+/* eDP0 */
+&mdss_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss_dp1 {
+ status = "okay";
+};
+
+/* eDP1 */
+&mdss_dp1_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp1_connector_in>;
+};
+
+&mdss1 {
+ status = "okay";
+};
+
+&mdss1_dp0 {
+ status = "okay";
+};
+
+/* eDP2 */
+&mdss1_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp2_connector_in>;
+};
+
+&mdss1_dp1 {
+ status = "okay";
+};
+
+/* eDP3 */
+&mdss1_dp1_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp3_connector_in>;
+};
+
&qupv3_0 {
firmware-name = "qcom/nord/qupv3fw.elf";
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] arm64: dts: qcom: nord-rrd: Enable eDP0/1 display output
2026-09-18 1:37 [PATCH 0/4] arm64: dts: qcom: nord: Add display support Shawn Guo
` (2 preceding siblings ...)
2026-09-18 1:37 ` [PATCH 3/4] arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output Shawn Guo
@ 2026-09-18 1:37 ` Shawn Guo
3 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 1:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Enable the MDSS, DP0/1 controllers and eDP0/1 PHYs on the Nord RRD
board and describe the eDP0/1 connector, its 4 data lanes and supported
link frequencies.
Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-rrd.dts | 62 +++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts
index c547963371b4..802987da3cfd 100644
--- a/arch/arm64/boot/dts/qcom/nord-rrd.dts
+++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts
@@ -53,6 +53,30 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ dp0_connector: connector-dp0 {
+ compatible = "dp-connector";
+ label = "eDP0";
+ type = "full-size";
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+
+ dp1_connector: connector-dp1 {
+ compatible = "dp-connector";
+ label = "eDP1";
+ type = "full-size";
+
+ port {
+ dp1_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp1_out>;
+ };
+ };
+ };
};
&apps_rsc {
@@ -366,6 +390,20 @@ vreg_l3l_1p8: ldo3 {
};
};
+&dp0_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
+&dp1_phy {
+ vdda-phy-supply = <&vreg_l2h_1p2>;
+ vdda-pll-supply = <&vreg_l1h_0p9>;
+
+ status = "okay";
+};
+
&i2c7 {
clock-frequency = <400000>;
@@ -377,6 +415,30 @@ rtc@32 {
};
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss_dp1 {
+ status = "okay";
+};
+
+&mdss_dp1_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp1_connector_in>;
+};
+
&qupv3_0 {
firmware-name = "qcom/nord/qupv3fw.elf";
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes
2026-09-18 1:37 ` [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes Shawn Guo
@ 2026-09-18 7:36 ` Shawn Guo
0 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2026-09-18 7:36 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel
On Fri, Sep 18, 2026 at 09:37:38AM +0800, Shawn Guo wrote:
> From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
>
> Add the MDSS, DPU, DP controller and eDP PHY nodes for the Qualcomm Nord
> SoC. Nord has two independent display subsystems, MDSS0 at 0xae00000 and
> MDSS1 at 0x8c00000, each with two DP controllers and two eDP PHYs. Nord
> is DP-only, so no DSI nodes are added. Wire the DP PHY outputs into the
> dispcc0 and dispcc1 clock inputs, which were previously stubbed with
> zeroes, and add the eDP0-3 hot-plug-detect pinctrl states.
>
> Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 523 +++++++++++++++++++-
> arch/arm64/boot/dts/qcom/nord.dtsi | 266 ++++++++++
> 2 files changed, 781 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> index 6dc4c871f41e..74f4e6be8652 100644
> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> @@ -346,6 +346,489 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
> pinctrl-names = "default";
> };
>
> +&mdss {
We will rename mdss to mdss0 to maintain consistency across platforms.
Shawn
> + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
> +
> + resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
> +
> + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "cpu-cfg";
> +
> + dp0_phy: phy@fc3a00 {
> + compatible = "qcom,nord-dp-phy";
> + reg = <0x0 0x0fc3a00 0x0 0x1d0>,
> + <0x0 0x0fc3200 0x0 0x128>,
> + <0x0 0x0fc3600 0x0 0x128>,
> + <0x0 0x0fc3000 0x0 0x200>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&tcsrcc TCSR_DP_TX_0_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
> +
> + status = "disabled";
> + };
> +
> + dp1_phy: phy@fc6a00 {
> + compatible = "qcom,nord-dp-phy";
> + reg = <0x0 0x0fc6a00 0x0 0x200>,
> + <0x0 0x0fc6200 0x0 0xd0>,
> + <0x0 0x0fc6600 0x0 0xd0>,
> + <0x0 0x0fc6000 0x0 0x1c8>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&tcsrcc TCSR_DP_TX_1_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
> +
> + status = "disabled";
> + };
> +};
> +
> +&mdss_mdp {
> + clocks = <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-417000000 {
> + opp-hz = /bits/ 64 <417000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-532000000 {
> + opp-hz = /bits/ 64 <532000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + };
> + opp-710000000 {
> + opp-hz = /bits/ 64 <710000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> +};
> +
> +&mdss_dp0 {
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel",
> + "stream_1_pixel",
> + "stream_2_pixel",
> + "stream_3_pixel";
> +
> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
> + assigned-clock-parents = <&dp0_phy 0>,
> + <&dp0_phy 1>,
> + <&dp0_phy 1>,
> + <&dp0_phy 1>,
> + <&dp0_phy 1>;
> +
> + phys = <&dp0_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + pinctrl-0 = <&dp0_hot_plug_det>;
> + pinctrl-names = "default";
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-162000000 {
> + opp-hz = /bits/ 64 <162000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> +
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> +
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +};
> +
> +&mdss_dp1 {
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel",
> + "stream_1_pixel",
> + "stream_2_pixel",
> + "stream_3_pixel";
> +
> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&dp1_phy 0>,
> + <&dp1_phy 1>,
> + <&dp1_phy 1>;
> +
> + phys = <&dp1_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp1_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + pinctrl-0 = <&dp1_hot_plug_det>;
> + pinctrl-names = "default";
> +
> + dp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-162000000 {
> + opp-hz = /bits/ 64 <162000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> +
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> +
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +};
> +
> +&mdss1 {
> + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
> +
> + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
> +
> + interconnects = <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_1_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "cpu-cfg";
> +
> + dp2_phy: phy@fc9a00 {
> + compatible = "qcom,nord-dp-phy";
> + reg = <0x0 0x0fc9a00 0x0 0x1d0>,
> + <0x0 0x0fc9200 0x0 0x128>,
> + <0x0 0x0fc9600 0x0 0x128>,
> + <0x0 0x0fc9000 0x0 0x200>;
> +
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&tcsrcc TCSR_DP_TX_2_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
> +
> + status = "disabled";
> + };
> +
> + dp3_phy: phy@fcca00 {
> + compatible = "qcom,nord-dp-phy";
> + reg = <0x0 0x0fcca00 0x0 0x200>,
> + <0x0 0x0fcc200 0x0 0xd0>,
> + <0x0 0x0fcc600 0x0 0xd0>,
> + <0x0 0x0fcc000 0x0 0x1c8>;
> +
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&tcsrcc TCSR_DP_TX_3_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
> +
> + status = "disabled";
> + };
> +};
> +
> +&mdss1_mdp {
> + clocks = <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp1_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + mdp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-417000000 {
> + opp-hz = /bits/ 64 <417000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-532000000 {
> + opp-hz = /bits/ 64 <532000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + };
> +
> + opp-710000000 {
> + opp-hz = /bits/ 64 <710000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> +};
> +
> +&mdss1_dp0 {
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel",
> + "stream_1_pixel",
> + "stream_2_pixel",
> + "stream_3_pixel";
> +
> + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
> + assigned-clock-parents = <&dp2_phy 0>,
> + <&dp2_phy 1>,
> + <&dp2_phy 1>,
> + <&dp2_phy 1>,
> + <&dp2_phy 1>;
> +
> + phys = <&dp2_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp2_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + pinctrl-0 = <&dp2_hot_plug_det>;
> + pinctrl-names = "default";
> +
> + dp2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-162000000 {
> + opp-hz = /bits/ 64 <162000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> +
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> +
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +};
> +
> +&mdss1_dp1 {
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel",
> + "stream_1_pixel",
> + "stream_2_pixel",
> + "stream_3_pixel";
> +
> + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&dp3_phy 0>,
> + <&dp3_phy 1>,
> + <&dp3_phy 1>;
> +
> + phys = <&dp3_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp3_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + pinctrl-0 = <&dp3_hot_plug_det>;
> + pinctrl-names = "default";
> +
> + dp3_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-162000000 {
> + opp-hz = /bits/ 64 <162000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> +
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> +
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> +
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +};
> +
> &qupv3_0 {
> clocks = <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>,
> <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>;
> @@ -903,10 +1386,10 @@ dispcc1: clock-controller@8d00000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&dp2_phy 0>,
> + <&dp2_phy 1>,
> + <&dp3_phy 0>,
> + <&dp3_phy 1>,
> <0>,
> <0>,
> <0>,
> @@ -970,10 +1453,10 @@ dispcc0: clock-controller@af00000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&dp0_phy 0>,
> + <&dp0_phy 1>,
> + <&dp1_phy 0>,
> + <&dp1_phy 1>,
> <0>,
> <0>,
> <0>,
> @@ -1106,6 +1589,30 @@ nsp_data_noc_3: interconnect@1fe00000 {
> };
>
> &tlmm {
> + dp0_hot_plug_det: dp0-hot-plug-det-state {
> + pins = "gpio51";
> + function = "edp0_hot";
> + bias-disable;
> + };
> +
> + dp1_hot_plug_det: dp1-hot-plug-det-state {
> + pins = "gpio52";
> + function = "edp1_hot";
> + bias-disable;
> + };
> +
> + dp2_hot_plug_det: dp2-hot-plug-det-state {
> + pins = "gpio53";
> + function = "edp2_hot";
> + bias-disable;
> + };
> +
> + dp3_hot_plug_det: dp3-hot-plug-det-state {
> + pins = "gpio54";
> + function = "edp3_hot";
> + bias-disable;
> + };
> +
> qup_i2c0_default: qup-i2c0-default-state {
> pins = "gpio111", "gpio112";
> function = "qup0_se0";
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index 926ccf3bbe4e..73136c27bac1 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -1727,6 +1727,139 @@ compute-cb@6 {
> };
> };
>
> + /* Display subsystem nodes - MDSS1, DP-only (no DSI) */
> + mdss1: display-subsystem@8c00000 {
> + compatible = "qcom,nord-mdss";
> + reg = <0x0 0x08c00000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu_1 0x400 0x2>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss1_mdp: display-controller@8c01000 {
> + compatible = "qcom,nord-dpu";
> + reg = <0x0 0x08c01000 0x0 0x8f000>,
> + <0x0 0x08cb0000 0x0 0x3000>;
> + reg-names = "mdp",
> + "vbif";
> +
> + interrupt-parent = <&mdss1>;
> + interrupts = <0>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dpu1_intf0_out: endpoint {
> + remote-endpoint = <&mdss1_dp0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + dpu1_intf4_out: endpoint {
> + remote-endpoint = <&mdss1_dp1_in>;
> + };
> + };
> + };
> + };
> +
> + mdss1_dp0: displayport-controller@8d54000 {
> + compatible = "qcom,nord-dp";
> + reg = <0x0 0x08d54000 0x0 0x200>,
> + <0x0 0x08d54200 0x0 0x200>,
> + <0x0 0x08d55000 0x0 0xc00>,
> + <0x0 0x08d56000 0x0 0x400>,
> + <0x0 0x08d57000 0x0 0x400>,
> + <0x0 0x08d58000 0x0 0x400>,
> + <0x0 0x08d59000 0x0 0x400>,
> + <0x0 0x08d5a000 0x0 0x600>,
> + <0x0 0x08d5b000 0x0 0x600>;
> +
> + interrupts-extended = <&mdss1 12>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss1_dp0_in: endpoint {
> + remote-endpoint = <&dpu1_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss1_dp0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + mdss1_dp1: displayport-controller@8d5c000 {
> + compatible = "qcom,nord-dp";
> + reg = <0x0 0x08d5c000 0x0 0x200>,
> + <0x0 0x08d5c200 0x0 0x200>,
> + <0x0 0x08d5d000 0x0 0xc00>,
> + <0x0 0x08d5e000 0x0 0x400>,
> + <0x0 0x08d5f000 0x0 0x400>,
> + <0x0 0x08d60000 0x0 0x400>,
> + <0x0 0x08d61000 0x0 0x400>,
> + <0x0 0x08d62000 0x0 0x600>,
> + <0x0 0x08d63000 0x0 0x600>;
> +
> + interrupts-extended = <&mdss1 13>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss1_dp1_in: endpoint {
> + remote-endpoint = <&dpu1_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss1_dp1_out: endpoint {
> + };
> + };
> + };
> + };
> + };
> +
> ipcc0: mailbox@9007000 {
> compatible = "qcom,nord-ipcc",
> "qcom,ipcc";
> @@ -1737,6 +1870,139 @@ ipcc0: mailbox@9007000 {
> #mbox-cells = <2>;
> };
>
> + /* Display subsystem nodes - MDSS 12.1, DP-only (no DSI) */
> + mdss: display-subsystem@ae00000 {
> + compatible = "qcom,nord-mdss";
> + reg = <0x0 0x0ae00000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + interrupts = <GIC_SPI 930 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu_1 0x3e0 0x2>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,nord-dpu";
> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
> + <0x0 0x0aeb0000 0x0 0x3000>;
> + reg-names = "mdp",
> + "vbif";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss_dp0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + dpu_intf4_out: endpoint {
> + remote-endpoint = <&mdss_dp1_in>;
> + };
> + };
> + };
> + };
> +
> + mdss_dp0: displayport-controller@af54000 {
> + compatible = "qcom,nord-dp";
> + reg = <0x0 0x0af54000 0x0 0x200>,
> + <0x0 0x0af54200 0x0 0x200>,
> + <0x0 0x0af55000 0x0 0xc00>,
> + <0x0 0x0af56000 0x0 0x400>,
> + <0x0 0x0af57000 0x0 0x400>,
> + <0x0 0x0af58000 0x0 0x400>,
> + <0x0 0x0af59000 0x0 0x400>,
> + <0x0 0x0af5a000 0x0 0x600>,
> + <0x0 0x0af5b000 0x0 0x600>;
> +
> + interrupts-extended = <&mdss 12>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + mdss_dp1: displayport-controller@af5c000 {
> + compatible = "qcom,nord-dp";
> + reg = <0x0 0x0af5c000 0x0 0x200>,
> + <0x0 0x0af5c200 0x0 0x200>,
> + <0x0 0x0af5d000 0x0 0xc00>,
> + <0x0 0x0af5e000 0x0 0x400>,
> + <0x0 0x0af5f000 0x0 0x400>,
> + <0x0 0x0af60000 0x0 0x400>,
> + <0x0 0x0af61000 0x0 0x400>,
> + <0x0 0x0af62000 0x0 0x600>,
> + <0x0 0x0af63000 0x0 0x600>;
> +
> + interrupts-extended = <&mdss 13>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp1_in: endpoint {
> + remote-endpoint = <&dpu_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp1_out: endpoint {
> + };
> + };
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,nord-pdc",
> "qcom,pdc";
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes
2026-09-18 1:37 ` [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Shawn Guo
@ 2026-09-20 7:58 ` Shawn Guo
0 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2026-09-20 7:58 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Taniya Das, Ritesh Kumar, Mahadevan P,
Nabige Aala, devicetree, linux-arm-msm, linux-kernel
On Fri, Sep 18, 2026 at 09:37:37AM +0800, Shawn Guo wrote:
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Add the GPU, camera, video, and display clock controller nodes for
> the Qualcomm Nord SoC, along with their required dt-bindings includes.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
I will separate this one from this display series, as camss and iris
depends on it as well.
Shawn
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-09-20 7:58 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-18 1:37 [PATCH 0/4] arm64: dts: qcom: nord: Add display support Shawn Guo
2026-09-18 1:37 ` [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Shawn Guo
2026-09-20 7:58 ` Shawn Guo
2026-09-18 1:37 ` [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes Shawn Guo
2026-09-18 7:36 ` Shawn Guo
2026-09-18 1:37 ` [PATCH 3/4] arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output Shawn Guo
2026-09-18 1:37 ` [PATCH 4/4] arm64: dts: qcom: nord-rrd: Enable eDP0/1 " Shawn Guo
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