[PATCH v3 0/7] riscv: dts: tenstorrent: Add Atlantis platform

[PATCH v3 0/7] riscv: dts: tenstorrent: Add Atlantis platform

[Joel Stanley]

Add initial support for the Tenstorrent Atlantis platform, based on the
Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.

The series adds a bare bones device tree with the CPU, interrupt
controllers and a UART.

Patches 1, 2, 3, 5, and 6 add compatibles or extensions to existing
bindings.

Patch 4 adds a binding for the aclint timer device, with a new rationale
for including it following discussion with Conor at Plumbers.

The series has been boot tested on QEMU and internal development
platforms.

v2:
https://lore.kernel.org/linux-riscv/20260604143957.668047-1-joel@jms.id.au/

Changes since v2:
 - Fixes to prcm_rcpu and aplic dt nodes
 - Drop uart1 clock override. UART now depends on a working PRCM driver
 - Drop bootargs console=ttyS0 in favour of stdout-path
 - Justify aclint mtimer bindings

Changes since v1:
 - Rework mtimer bindings, fix reg property, update compatible and use
   priv spec as reference
 - Drop Drew's sob from bindings patches I wrote
 - Add Drew's co-developed-by to dts patch
 - Correct aplic num-sources

Drew Fustini (1):
  dt-bindings: riscv: add Smrnmi extension description

Joel Stanley (6):
  dt-bindings: aplic: Add Tenstorrent Atlantis compatible
  dt-bindings: imsics: Add Tenstorrent Atlantis compatible
  dt-bindings: riscv: cpus: Add Tenstorrent Ascalon
  dt-bindings: timer: Add RISC-V ACLINT mtimer bindings
  dt-bindings: riscv: Add Tenstorrent Atlantis platform
  riscv: dts: tenstorrent: Add Atlantis platform

 MAINTAINERS                                   |   1 +
 .../interrupt-controller/riscv,aplic.yaml     |   1 +
 .../interrupt-controller/riscv,imsics.yaml    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   5 +
 .../devicetree/bindings/riscv/extensions.yaml |   6 +
 .../bindings/riscv/tenstorrent.yaml           |   4 +
 .../bindings/timer/riscv,aclint-mtimer.yaml   |  56 +++
 arch/riscv/boot/dts/tenstorrent/Makefile      |   1 +
 .../boot/dts/tenstorrent/atlantis-evb.dts     |  29 ++
 .../boot/dts/tenstorrent/atlantis-soc.dtsi    | 473 ++++++++++++++++++
 10 files changed, 577 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
 create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi

-- 
2.47.3

[PATCH v3 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible

[Joel Stanley]

Add compatible for APLIC in Tenstorrent Atlantis SoC.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3: No changes, pick up review tag
---
 .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
index 0718071444d2..d4e17861eda4 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -29,6 +29,7 @@ properties:
       - enum:
           - qemu,aplic
           - spacemit,k3-aplic
+          - tenstorrent,atlantis-aplic
       - const: riscv,aplic
 
   reg:
-- 
2.47.3

Re: [PATCH v3 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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[PATCH v3 2/7] dt-bindings: imsics: Add Tenstorrent Atlantis compatible

[Joel Stanley]

Add compatible for IMSICS in Tenstorrent Atlantis SoC.

Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3: No changes, pick up review tags
---
 .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
index feec122bddde..442b8870f9c5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
@@ -49,6 +49,7 @@ properties:
       - enum:
           - qemu,imsics
           - spacemit,k3-imsics
+          - tenstorrent,atlantis-imsics
       - const: riscv,imsics
 
   reg:
-- 
2.47.3

[PATCH v3 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon

[Joel Stanley]

Add Tenstorrent Ascalon microarchitecture and the Tenstorrent Ascalon-XG
core.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3: No changes, pick up review tags
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 0da219ae6769..2d2e4606a53e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -75,6 +75,11 @@ properties:
               - sifive,x280
           - const: sifive,rocket0
           - const: riscv
+      - items:
+          - enum:
+              - tenstorrent,ascalon-xg
+          - const: tenstorrent,ascalon
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
-- 
2.47.3

[PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Joel Stanley]

Document the RISC-V ACLINT mtimer and mtimecmp hardware, as described
by the riscv-aclint specification, commit 4e570bfd3201f2 [2].

Multiple vendors are shipping silicon with the hardware as described
by the specification, which was abandoned[1] as a standalone spec at
v1.0-rc4.  As we have multiple instances of hardware that implement
the spec, the widespread implementation of the spec is de facto
ratification, providing a stationary target for the bindings to document
and an exception to the policy of not accepting things that are
pre-ratification.

[1] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
[2] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
  - Rework commit message following discussion at LPC
  - Add reg-names, rework description, fix example
---
 MAINTAINERS                                   |  1 +
 .../bindings/timer/riscv,aclint-mtimer.yaml   | 56 +++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..403875d5932e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24185,6 +24185,7 @@ S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git
 F:	Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
 F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 F:	arch/riscv/boot/dts/tenstorrent/
 F:	drivers/clk/tenstorrent/
 F:	drivers/reset/reset-tenstorrent-atlantis.c
diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..e6f3d08d4f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Advanced Core Local Interruptor (ACLINT) timer
+
+maintainers:
+  - Joel Stanley <jms@oss.tenstorrent.com>
+
+description:
+  The RISC-V ACLINT specification defines a set of memory mapped devices which
+  provide timer functionality for each hart on a multi-hart RISC-V platform.
+  The mtimer device has a single mtime register and one mtimecmp register per
+  hart. The specification is at https://github.com/riscvarchive/riscv-aclint/
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - tenstorrent,atlantis-aclint-mtimer
+      - const: riscv,aclint-mtimer
+
+  reg:
+    items:
+      - description: mtime register
+      - description: mtimecmp registers
+
+  reg-names:
+    items:
+      - const: mtime
+      - const: mtimecmp
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    timer@a2180000 {
+      compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
+      reg = <0xa2180000 0x8000>, <0xa2188000 0x8000>;
+      reg-names = "mtime", "mtimecmp";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+    };
+...
-- 
2.47.3

Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Krzysztof Kozlowski]

On Mon, Nov 09, 2026 at 03:40:44PM +1030, Joel Stanley wrote:
> Document the RISC-V ACLINT mtimer and mtimecmp hardware, as described
> by the riscv-aclint specification, commit 4e570bfd3201f2 [2].
> 
> Multiple vendors are shipping silicon with the hardware as described
> by the specification, which was abandoned[1] as a standalone spec at
> v1.0-rc4.  As we have multiple instances of hardware that implement
> the spec, the widespread implementation of the spec is de facto
> ratification, providing a stationary target for the bindings to document
> and an exception to the policy of not accepting things that are
> pre-ratification.
> 
> [1] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
> [2] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v3:
>   - Rework commit message following discussion at LPC
>   - Add reg-names, rework description, fix example
> ---
>  MAINTAINERS                                   |  1 +
>  .../bindings/timer/riscv,aclint-mtimer.yaml   | 56 +++++++++++++++++++
>  2 files changed, 57 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93abbb315065..403875d5932e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24185,6 +24185,7 @@ S:	Maintained
>  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git
>  F:	Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
>  F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
> +F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>  F:	arch/riscv/boot/dts/tenstorrent/
>  F:	drivers/clk/tenstorrent/
>  F:	drivers/reset/reset-tenstorrent-atlantis.c
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..e6f3d08d4f93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Advanced Core Local Interruptor (ACLINT) timer
> +
> +maintainers:
> +  - Joel Stanley <jms@oss.tenstorrent.com>
> +
> +description:
> +  The RISC-V ACLINT specification defines a set of memory mapped devices which
> +  provide timer functionality for each hart on a multi-hart RISC-V platform.
> +  The mtimer device has a single mtime register and one mtimecmp register per
> +  hart. The specification is at https://github.com/riscvarchive/riscv-aclint/
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - tenstorrent,atlantis-aclint-mtimer
> +      - const: riscv,aclint-mtimer
> +
> +  reg:
> +    items:
> +      - description: mtime register
> +      - description: mtimecmp registers
> +
> +  reg-names:
> +    items:
> +      - const: mtime
> +      - const: mtimecmp
> +
> +  interrupts-extended:

Use interrupts. git grep gives basically zero results for such syntax in
the binding.

> +    minItems: 1
> +    maxItems: 4095

Best regards,
Krzysztof

Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Conor Dooley]

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On Mon, Nov 09, 2026 at 03:40:44PM +1030, Joel Stanley wrote:
> Document the RISC-V ACLINT mtimer and mtimecmp hardware, as described
> by the riscv-aclint specification, commit 4e570bfd3201f2 [2].
> 
> Multiple vendors are shipping silicon with the hardware as described
> by the specification, which was abandoned[1] as a standalone spec at
> v1.0-rc4.  As we have multiple instances of hardware that implement
> the spec, the widespread implementation of the spec is de facto
> ratification, providing a stationary target for the bindings to document
> and an exception to the policy of not accepting things that are
> pre-ratification.
> 
> [1] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
> [2] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v3:
>   - Rework commit message following discussion at LPC

Since I was one of the folks involved in that chat, I am okay with this
obviously. I was convinced to change my mind about the use of the riscv
vendor prefix because of the widespread adoption.

>   - Add reg-names, rework description, fix example
> ---
>  MAINTAINERS                                   |  1 +
>  .../bindings/timer/riscv,aclint-mtimer.yaml   | 56 +++++++++++++++++++
>  2 files changed, 57 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93abbb315065..403875d5932e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24185,6 +24185,7 @@ S:	Maintained
>  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git
>  F:	Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
>  F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml

> +F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml


>  F:	arch/riscv/boot/dts/tenstorrent/
>  F:	drivers/clk/tenstorrent/
>  F:	drivers/reset/reset-tenstorrent-atlantis.c
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..e6f3d08d4f93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Advanced Core Local Interruptor (ACLINT) timer
> +
> +maintainers:
> +  - Joel Stanley <jms@oss.tenstorrent.com>
> +
> +description:
> +  The RISC-V ACLINT specification defines a set of memory mapped devices which
> +  provide timer functionality for each hart on a multi-hart RISC-V platform.
> +  The mtimer device has a single mtime register and one mtimecmp register per
> +  hart. The specification is at https://github.com/riscvarchive/riscv-aclint/
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - tenstorrent,atlantis-aclint-mtimer
> +      - const: riscv,aclint-mtimer

So, what are we doing about thead,c900-aclint-mtimer.yaml?

> +
> +  reg:
> +    items:
> +      - description: mtime register
> +      - description: mtimecmp registers

For example, I note that you have mtime and mtimecmp in the opposite
order to how the mips folks have had to add the mtime region to that
file:
https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/

> +
> +  reg-names:
> +    items:
> +      - const: mtime
> +      - const: mtimecmp
> +
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +
> +required:
> +  - compatible
> +  - reg

You've also not made reg-names or interrupts-extended required.

I think we should swap the regs around and make these two required at a
minimum, but also "initialise" this file by renaming the existing file.

My ~assumption~hope is that all of the devices in that file have
implemented the aclint spec at the -rc1 revision that we're citing here.

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    timer@a2180000 {
> +      compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
> +      reg = <0xa2180000 0x8000>, <0xa2188000 0x8000>;
> +      reg-names = "mtime", "mtimecmp";
> +      interrupts-extended = <&cpu1intc 7>,
> +                            <&cpu2intc 7>,
> +                            <&cpu3intc 7>,
> +                            <&cpu4intc 7>;
> +    };
> +...
> -- 
> 2.47.3
> 
> 

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Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Joel Stanley]

+cc people who might know more about the various hardware this binding supports.

On Tue, 10 Nov 2026 at 05:59, Conor Dooley <conor@kernel.org> wrote:
> > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - tenstorrent,atlantis-aclint-mtimer
> > +      - const: riscv,aclint-mtimer
>
> So, what are we doing about thead,c900-aclint-mtimer.yaml?

Once we agree on this binding, I planned to submit a change to bring
over the devices that implement the common binding. I can do that up
front instead.

>
> > +
> > +  reg:
> > +    items:
> > +      - description: mtime register
> > +      - description: mtimecmp registers
>
> For example, I note that you have mtime and mtimecmp in the opposite
> order to how the mips folks have had to add the mtime region to that
> file:
> https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/

This is the order OpenSBI has used since v1.0, when support was added
about five years ago. It reads mtime followed by mtimecmp when there
are no reg-names:

 https://github.com/riscv-software-src/opensbi/blob/v1.9/lib/utils/timer/fdt_timer_mtimer.c#L79

QEMU also generates a dt with mtime followed by mtimecmp, and without reg-names.

The MIPS ordering works because it specifies reg-names. OpenSBI uses
reg-names to parse the reg property so it would continue working, but
u-boot takes index 0 as mtime and ignores reg-names.

> > +
> > +  reg-names:
> > +    items:
> > +      - const: mtime
> > +      - const: mtimecmp
> > +
> > +  interrupts-extended:
> > +    minItems: 1
> > +    maxItems: 4095
> > +
> > +required:
> > +  - compatible
> > +  - reg
>
> You've also not made reg-names or interrupts-extended required.

That was intentional. A mtimer device without harts attached won't
have interrupts (opensbi supports this), but I haven't come across a
system that uses it this way. I have no preference here, what do you
think?

> I think we should swap the regs around and make these two required at a
> minimum, but also "initialise" this file by renaming the existing file.

Bringing over the other devices sounds like a good idea to me. And I
appreciate the spelling.

The nuclei/anlogic boards document mtime[1] support:

 - nuclei,ux900-aclint-mtimer
 - anlogic,dr1v90-aclint-mtimer

K3 has a mtime register (at 0xf181bff8, by experimentation on hardware):

 - spacemit,k3-aclint-mtimer

MIPS has it, as per their patch[2]:

 - gf,mips-p8700-aclint-mtimer

Note that MIPS have mips,p8700-aclint-mtimer in opensbi.

T-Head has no mtime[3], just a set of mtimecmp registers. Sophgo are
unknown, can we assume it is the same design as T-Head?

 - thead,c900-aclint-mtimer
 - sophgo,sg2042-aclint-mtimer
 - sophgo,sg2044-aclint-mtimer

There are two options for T-Head:

1) Leave it in its own binding, because it doesn't have mtime registers.

2) Use this binding with an optional reg property for the mtime
region, which means putting the optional part last.

If we go with 1 we can preserve the mtime, mtimecmp ordering, matching
u-boot, opensbi, qemu. If we go with 2 we put mtime last and make
reg-names required.

The current K3 and Anlogic current device trees would need an update
to their reg property to describe mtime when adding the riscv
compatible.

I lean towards 1 because it reduces churn in firmware.

> My ~assumption~hope is that all of the devices in that file have
> implemented the aclint spec at the -rc1 revision that we're citing here.

(-rc4). Yep, we can move the majority of the compatibles into this
binding. The T-Head family might be the exception.

Cheers,

Joel

[1] https://doc.nucleisys.com/nuclei_spec/isa/timer.html
[2] https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
[3] https://lore.kernel.org/all/IA1PR20MB4953D36ABE26822B62415500BBBBA@IA1PR20MB4953.namprd20.prod.outlook.com/

Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Inochi Amaoto]

On Wed, Nov 11, 2026 at 03:34:26PM +1030, Joel Stanley wrote:
> +cc people who might know more about the various hardware this binding supports.
> 
> On Tue, 10 Nov 2026 at 05:59, Conor Dooley <conor@kernel.org> wrote:
> > > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> 
> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> > > +          - tenstorrent,atlantis-aclint-mtimer
> > > +      - const: riscv,aclint-mtimer
> >
> > So, what are we doing about thead,c900-aclint-mtimer.yaml?
> 
> Once we agree on this binding, I planned to submit a change to bring
> over the devices that implement the common binding. I can do that up
> front instead.
> 
> >
> > > +
> > > +  reg:
> > > +    items:
> > > +      - description: mtime register
> > > +      - description: mtimecmp registers
> >
> > For example, I note that you have mtime and mtimecmp in the opposite
> > order to how the mips folks have had to add the mtime region to that
> > file:
> > https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> 
> This is the order OpenSBI has used since v1.0, when support was added
> about five years ago. It reads mtime followed by mtimecmp when there
> are no reg-names:
> 
>  https://github.com/riscv-software-src/opensbi/blob/v1.9/lib/utils/timer/fdt_timer_mtimer.c#L79
> 
> QEMU also generates a dt with mtime followed by mtimecmp, and without reg-names.
> 
> The MIPS ordering works because it specifies reg-names. OpenSBI uses
> reg-names to parse the reg property so it would continue working, but
> u-boot takes index 0 as mtime and ignores reg-names.
> 
> > > +
> > > +  reg-names:
> > > +    items:
> > > +      - const: mtime
> > > +      - const: mtimecmp
> > > +
> > > +  interrupts-extended:
> > > +    minItems: 1
> > > +    maxItems: 4095
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> >
> > You've also not made reg-names or interrupts-extended required.
> 
> That was intentional. A mtimer device without harts attached won't
> have interrupts (opensbi supports this), but I haven't come across a
> system that uses it this way. I have no preference here, what do you
> think?
> 

I think reg-names is required. The spec archive does not requrire the core
implement both MTIME and MTIMECMP. So using reg-name will let the DT parser
does not reply on the order and leave the room for MTIMECMP only devices.

interrupts-extended should also be required, it is kind of weird for 
a zero-interrupt timer.

> > I think we should swap the regs around and make these two required at a
> > minimum, but also "initialise" this file by renaming the existing file.
> 
> Bringing over the other devices sounds like a good idea to me. And I
> appreciate the spelling.
> 
> The nuclei/anlogic boards document mtime[1] support:
> 
>  - nuclei,ux900-aclint-mtimer
>  - anlogic,dr1v90-aclint-mtimer
> 
> K3 has a mtime register (at 0xf181bff8, by experimentation on hardware):
> 
>  - spacemit,k3-aclint-mtimer
> 
> MIPS has it, as per their patch[2]:
> 
>  - gf,mips-p8700-aclint-mtimer
> 
> Note that MIPS have mips,p8700-aclint-mtimer in opensbi.
> 
> T-Head has no mtime[3], just a set of mtimecmp registers. Sophgo are
> unknown, can we assume it is the same design as T-Head?
> 
>  - thead,c900-aclint-mtimer
>  - sophgo,sg2042-aclint-mtimer
>  - sophgo,sg2044-aclint-mtimer
> 

For T-HEAD, IIRC all the design share the same layout. C9XX use the same
layout for both C906/C910/C920. Sophgo is just a SoC vendor, not the
core vendor.

> There are two options for T-Head:
> 
> 1) Leave it in its own binding, because it doesn't have mtime registers.
> 
> 2) Use this binding with an optional reg property for the mtime
> region, which means putting the optional part last.
> 
> If we go with 1 we can preserve the mtime, mtimecmp ordering, matching
> u-boot, opensbi, qemu. If we go with 2 we put mtime last and make
> reg-names required.
> 
> The current K3 and Anlogic current device trees would need an update
> to their reg property to describe mtime when adding the riscv
> compatible.
> 
> I lean towards 1 because it reduces churn in firmware.
> 

I prefer 2. as the ACLINT is designed for modularity, it should 
tolerate one that does not have MTIME.

> > My ~assumption~hope is that all of the devices in that file have
> > implemented the aclint spec at the -rc1 revision that we're citing here.
> 
> (-rc4). Yep, we can move the majority of the compatibles into this
> binding. The T-Head family might be the exception.
> 
> Cheers,
> 
> Joel
> 
> [1] https://doc.nucleisys.com/nuclei_spec/isa/timer.html
> [2] https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> [3] https://lore.kernel.org/all/IA1PR20MB4953D36ABE26822B62415500BBBBA@IA1PR20MB4953.namprd20.prod.outlook.com/

Regards,
Inochi

Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 6358 bytes --]

+CC Aleska,

On Wed, Nov 11, 2026 at 02:21:44PM +0800, Inochi Amaoto wrote:
> On Wed, Nov 11, 2026 at 03:34:26PM +1030, Joel Stanley wrote:
> > +cc people who might know more about the various hardware this binding supports.
> > 
> > On Tue, 10 Nov 2026 at 05:59, Conor Dooley <conor@kernel.org> wrote:
> > > > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> > 
> > > > +properties:
> > > > +  compatible:
> > > > +    items:
> > > > +      - enum:
> > > > +          - tenstorrent,atlantis-aclint-mtimer
> > > > +      - const: riscv,aclint-mtimer
> > >
> > > So, what are we doing about thead,c900-aclint-mtimer.yaml?
> > 
> > Once we agree on this binding, I planned to submit a change to bring
> > over the devices that implement the common binding. I can do that up
> > front instead.
> > 
> > >
> > > > +
> > > > +  reg:
> > > > +    items:
> > > > +      - description: mtime register
> > > > +      - description: mtimecmp registers
> > >
> > > For example, I note that you have mtime and mtimecmp in the opposite
> > > order to how the mips folks have had to add the mtime region to that
> > > file:
> > > https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> > 
> > This is the order OpenSBI has used since v1.0, when support was added
> > about five years ago. It reads mtime followed by mtimecmp when there
> > are no reg-names:
> > 
> >  https://github.com/riscv-software-src/opensbi/blob/v1.9/lib/utils/timer/fdt_timer_mtimer.c#L79
> > 
> > QEMU also generates a dt with mtime followed by mtimecmp, and without reg-names.
> > 
> > The MIPS ordering works because it specifies reg-names. OpenSBI uses
> > reg-names to parse the reg property so it would continue working, but
> > u-boot takes index 0 as mtime and ignores reg-names.
> > 
> > > > +
> > > > +  reg-names:
> > > > +    items:
> > > > +      - const: mtime
> > > > +      - const: mtimecmp
> > > > +
> > > > +  interrupts-extended:
> > > > +    minItems: 1
> > > > +    maxItems: 4095
> > > > +
> > > > +required:
> > > > +  - compatible
> > > > +  - reg
> > >
> > > You've also not made reg-names or interrupts-extended required.
> > 
> > That was intentional. A mtimer device without harts attached won't
> > have interrupts (opensbi supports this), but I haven't come across a
> > system that uses it this way. I have no preference here, what do you
> > think?
> > 
> 
> I think reg-names is required. The spec archive does not requrire the core
> implement both MTIME and MTIMECMP. So using reg-name will let the DT parser
> does not reply on the order and leave the room for MTIMECMP only devices.
> 
> interrupts-extended should also be required, it is kind of weird for 
> a zero-interrupt timer.
> 
> > > I think we should swap the regs around and make these two required at a
> > > minimum, but also "initialise" this file by renaming the existing file.
> > 
> > Bringing over the other devices sounds like a good idea to me. And I
> > appreciate the spelling.
> > 
> > The nuclei/anlogic boards document mtime[1] support:
> > 
> >  - nuclei,ux900-aclint-mtimer
> >  - anlogic,dr1v90-aclint-mtimer
> > 
> > K3 has a mtime register (at 0xf181bff8, by experimentation on hardware):
> > 
> >  - spacemit,k3-aclint-mtimer
> > 
> > MIPS has it, as per their patch[2]:
> > 
> >  - gf,mips-p8700-aclint-mtimer
> > 
> > Note that MIPS have mips,p8700-aclint-mtimer in opensbi.

/sigh. Aleksa, can we sort this out please as part of whatever revision
is made to the mtimer patch in your series?

> > 
> > T-Head has no mtime[3], just a set of mtimecmp registers. Sophgo are
> > unknown, can we assume it is the same design as T-Head?
> > 
> >  - thead,c900-aclint-mtimer
> >  - sophgo,sg2042-aclint-mtimer
> >  - sophgo,sg2044-aclint-mtimer
> > 
> 
> For T-HEAD, IIRC all the design share the same layout. C9XX use the same
> layout for both C906/C910/C920. Sophgo is just a SoC vendor, not the
> core vendor.
> 
> > There are two options for T-Head:
> > 
> > 1) Leave it in its own binding, because it doesn't have mtime registers.
> > 
> > 2) Use this binding with an optional reg property for the mtime
> > region, which means putting the optional part last.
> > 
> > If we go with 1 we can preserve the mtime, mtimecmp ordering, matching
> > u-boot, opensbi, qemu. If we go with 2 we put mtime last and make
> > reg-names required.
> > 
> > The current K3 and Anlogic current device trees would need an update
> > to their reg property to describe mtime when adding the riscv
> > compatible.
> > 
> > I lean towards 1 because it reduces churn in firmware.
> > 
> 
> I prefer 2. as the ACLINT is designed for modularity, it should 
> tolerate one that does not have MTIME.

I think we need to make reg-names mandatory and permit free ordering of
the reg entries and make reg-names mandatory.
QEMU will need to be changed to add reg-names and U-Boot changed to use
reg-names - I think neither should be controversial, since no hardware
actually implementing this device follows the qemu/opensbi ordering.

Maybe the right thing to do is:
| items:
|  - enum [mtime, mtimecmp]
|  - const: mtimecmp
which forces mtime to be first when there are two items, not really
problematic given there's currently no devices with two with a binding
that need modification given the mips thing is not yet merged so we can
update it to be like this.

Maybe for safety we abstain from retrofitting riscv,aclint-mtimer to the
existing devices (although I still think they should be merged into one
file) so that they don't run into U-Boot failures.

Cheers,
Conor.

> 
> > > My ~assumption~hope is that all of the devices in that file have
> > > implemented the aclint spec at the -rc1 revision that we're citing here.
> > 
> > (-rc4). Yep, we can move the majority of the compatibles into this
> > binding. The T-Head family might be the exception.
> > 
> > Cheers,
> > 
> > Joel
> > 
> > [1] https://doc.nucleisys.com/nuclei_spec/isa/timer.html
> > [2] https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> > [3] https://lore.kernel.org/all/IA1PR20MB4953D36ABE26822B62415500BBBBA@IA1PR20MB4953.namprd20.prod.outlook.com/
> 
> Regards,
> Inochi

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[PATCH v3 5/7] dt-bindings: riscv: add Smrnmi extension description

[Joel Stanley]

From: Drew Fustini <fustini@kernel.org>

Add description for the Smrnmi extension (Resumable Non-Maskable
Interrupts) as ratified in 35eb3948bf0b ("Merge pull request #1492 from
riscv/smrnmi-ratified") of the riscv-isa-manual.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3: No changes
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 79491ef8f86a..7f5d85c64f83 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -214,6 +214,12 @@ properties:
             ratified at commit d70011dde6c2 ("Update to ratified state")
             of riscv-j-extension.
 
+        - const: smrnmi
+          description: |
+            The standard Smrnmi extension for Resumable Non-Maskable Interrupts
+            as ratified in commit 35eb3948bf0b ("Merge pull request #1492 from
+            riscv/smrnmi-ratified") of the riscv-isa-manual.
+
         - const: smstateen
           description: |
             The standard Smstateen extension for controlling access to CSRs
-- 
2.47.3

[PATCH v3 6/7] dt-bindings: riscv: Add Tenstorrent Atlantis platform

[Joel Stanley]

Add compatible for the Tenstorrent Atlantis platform.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3: No changes, pick up review tags
---
 Documentation/devicetree/bindings/riscv/tenstorrent.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/tenstorrent.yaml b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml
index e15359b2aab6..7fb640e38455 100644
--- a/Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+++ b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml
@@ -22,6 +22,10 @@ properties:
         items:
           - const: tenstorrent,blackhole-card
           - const: tenstorrent,blackhole
+      - description: Tenstorrent Atlantis
+        items:
+          - const: tenstorrent,atlantis-evb
+          - const: tenstorrent,atlantis
 
 additionalProperties: true
 
-- 
2.47.3

[PATCH v3 7/7] riscv: dts: tenstorrent: Add Atlantis platform

[Joel Stanley]

Add initial support for the Tenstorrent Atlantis platform, based on the
Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.

The evb machine represents an internal bringup vehicle with just the
interrupt controllers and a UART. This will be updated in time with a
full featured machine once details are available.

The chosen node sets bootargs to earlycon=sbi to aid debugging early
boot, as the platform may not have a bootloader to fill out the chosen
node.

The m-mode IMSIC setting riscv,guest-index-bits looks strange, as m-mode
devices don't have guest interrupt files. The spacing (stride) between
m-mode files is the same 256KB as s-mode on Atlantis, so we set the
property so software (eg OpenSBI) can derive the layout.

The SoC has a 8-way 64KB L1I, 4-way 256KB L1D, and a 24-way 12MB last
level cache shared across all cores.

Co-developed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
 - Fix prcm_rcpu parent
 - Delegate all aplic irqs
 - Drop uart1 clock override
 - Use earlycon=sbi, document rationale
 - Fix mistakes in cache info

v2:
 - Update mtimer compatible
 - Add Drew's co-developed-by
 - Correct aplic num-sources count
---
 arch/riscv/boot/dts/tenstorrent/Makefile      |   1 +
 .../boot/dts/tenstorrent/atlantis-evb.dts     |  29 ++
 .../boot/dts/tenstorrent/atlantis-soc.dtsi    | 473 ++++++++++++++++++
 3 files changed, 503 insertions(+)
 create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
 create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi

diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
index 2c81faaba462..92d8bb1a683f 100644
--- a/arch/riscv/boot/dts/tenstorrent/Makefile
+++ b/arch/riscv/boot/dts/tenstorrent/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
+dtb-$(CONFIG_ARCH_TENSTORRENT) += atlantis-evb.dtb
diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
new file mode 100644
index 000000000000..839a63dc9507
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright 2026 Tenstorrent
+/dts-v1/;
+
+#include "atlantis-soc.dtsi"
+
+/ {
+	model = "Tenstorrent Atlantis development platform";
+	compatible = "tenstorrent,atlantis-evb", "tenstorrent,atlantis";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x80000000>,
+		      <0x1 0x80000000 0x0 0x80000000>;
+	};
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		bootargs = "earlycon=sbi";
+		stdout-path = "serial0:115200";
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
new file mode 100644
index 000000000000..085b0ab90bbe
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright 2026 Tenstorrent
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h>
+
+/ {
+	model = "Tenstorrent Atlantis";
+	compatible = "tenstorrent,atlantis";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000000>;
+
+		cpu0: cpu@0 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <0>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <1>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <2>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <3>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu4: cpu@4 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <4>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu5: cpu@5 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <5>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu6: cpu@6 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <6>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu7: cpu@7 {
+			compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+			reg = <7>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+					       "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+					       "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintntl", "zihintpause", "zihpm",
+					       "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+					       "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+					       "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+					       "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+					       "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+					       "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+					       "smrnmi", "smstateen", "ssaia", "ssccptr",
+					       "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+					       "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+					       "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x40000>;
+			d-cache-sets = <1024>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv57";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <0xc00000>;
+			cache-sets = <8192>;
+			cache-unified;
+		};
+	};
+
+	clocks {
+		osc_24m: clock-24m {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc_24m";
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&aplic_s>;
+		ranges;
+
+		imsic_m: interrupt-controller@a0000000 {
+			compatible = "tenstorrent,atlantis-imsics", "riscv,imsics";
+			reg = <0x0 0xa0000000 0x0 0x200000>;
+			riscv,num-ids = <255>;
+			riscv,guest-index-bits = <6>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+					      <&cpu2_intc 11>, <&cpu3_intc 11>,
+					      <&cpu4_intc 11>, <&cpu5_intc 11>,
+					      <&cpu6_intc 11>, <&cpu7_intc 11>;
+			msi-controller;
+			#msi-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <0>;
+		};
+
+		mtimer: timer@a2180000 {
+			compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
+			reg = <0x0 0xa2180000 0x0 0x8000>, <0x0 0xa2188000 0x0 0x8000>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>,
+					      <&cpu2_intc 7>, <&cpu3_intc 7>,
+					      <&cpu4_intc 7>, <&cpu5_intc 7>,
+					      <&cpu6_intc 7>, <&cpu7_intc 7>;
+		};
+
+		imsic_s: interrupt-controller@a4000000 {
+			compatible = "tenstorrent,atlantis-imsics", "riscv,imsics";
+			reg = <0x0 0xa4000000 0x0 0x200000>;
+			riscv,num-ids = <255>;
+			riscv,guest-index-bits = <6>;
+			interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+					      <&cpu2_intc 9>, <&cpu3_intc 9>,
+					      <&cpu4_intc 9>, <&cpu5_intc 9>,
+					      <&cpu6_intc 9>, <&cpu7_intc 9>;
+			msi-controller;
+			#msi-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <0>;
+		};
+
+		aplic_m: interrupt-controller@cc000000 {
+			compatible = "tenstorrent,atlantis-aplic", "riscv,aplic";
+			reg = <0x0 0xcc000000 0x0 0x4000000>;
+			msi-parent = <&imsic_m>;
+			riscv,delegation = <&aplic_s 1 128>;
+			riscv,children = <&aplic_s>;
+			riscv,num-sources = <128>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+		};
+
+		prcm_rcpu: clock-controller@d0000000 {
+			compatible = "tenstorrent,atlantis-prcm-rcpu";
+			reg = <0x0 0xd0000000 0x0 0x10000>;
+			clocks = <&osc_24m>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			assigned-clocks = <&prcm_rcpu CLK_RCPU_ROOT>, <&prcm_rcpu CLK_NOCC_CLK>;
+			assigned-clock-parents = <&prcm_rcpu CLK_RCPU_PLL>,
+						 <&prcm_rcpu CLK_NOC_PLL>;
+		};
+
+		uart0: serial@d4100000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xd4100000 0x0 0x10000>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&prcm_rcpu CLK_UART0_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@d4110000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xd4110000 0x0 0x10000>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&prcm_rcpu CLK_UART1_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@d4120000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xd4120000 0x0 0x10000>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&prcm_rcpu CLK_UART2_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@d4130000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xd4130000 0x0 0x10000>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&prcm_rcpu CLK_UART3_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@d4140000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xd4140000 0x0 0x10000>;
+			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&prcm_rcpu CLK_UART4_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		aplic_s: interrupt-controller@e8000000 {
+			compatible = "tenstorrent,atlantis-aplic", "riscv,aplic";
+			reg = <0x0 0xe8000000 0x0 0x4000000>;
+			msi-parent = <&imsic_s>;
+			riscv,num-sources = <128>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+		};
+	};
+};
-- 
2.47.3

Re: [PATCH v3 7/7] riscv: dts: tenstorrent: Add Atlantis platform

[Anirudh Srinivasan]

On Sun, Nov 8, 2026 at 11:11 PM Joel Stanley <joel@jms.id.au> wrote:
>
> Add initial support for the Tenstorrent Atlantis platform, based on the
> Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.
>
> The evb machine represents an internal bringup vehicle with just the
> interrupt controllers and a UART. This will be updated in time with a
> full featured machine once details are available.
>
> The chosen node sets bootargs to earlycon=sbi to aid debugging early
> boot, as the platform may not have a bootloader to fill out the chosen
> node.
>
> The m-mode IMSIC setting riscv,guest-index-bits looks strange, as m-mode
> devices don't have guest interrupt files. The spacing (stride) between
> m-mode files is the same 256KB as s-mode on Atlantis, so we set the
> property so software (eg OpenSBI) can derive the layout.
>
> The SoC has a 8-way 64KB L1I, 4-way 256KB L1D, and a 24-way 12MB last
> level cache shared across all cores.
>
> Co-developed-by: Drew Fustini <fustini@kernel.org>
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v3:
>  - Fix prcm_rcpu parent
>  - Delegate all aplic irqs
>  - Drop uart1 clock override
>  - Use earlycon=sbi, document rationale
>  - Fix mistakes in cache info
>
> v2:
>  - Update mtimer compatible
>  - Add Drew's co-developed-by
>  - Correct aplic num-sources count
> ---
>  arch/riscv/boot/dts/tenstorrent/Makefile      |   1 +
>  .../boot/dts/tenstorrent/atlantis-evb.dts     |  29 ++
>  .../boot/dts/tenstorrent/atlantis-soc.dtsi    | 473 ++++++++++++++++++
>  3 files changed, 503 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
>  create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
>
> diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
> index 2c81faaba462..92d8bb1a683f 100644
> --- a/arch/riscv/boot/dts/tenstorrent/Makefile
> +++ b/arch/riscv/boot/dts/tenstorrent/Makefile
> @@ -1,2 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
> +dtb-$(CONFIG_ARCH_TENSTORRENT) += atlantis-evb.dtb
> diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
> new file mode 100644
> index 000000000000..839a63dc9507
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +// Copyright 2026 Tenstorrent
> +/dts-v1/;
> +
> +#include "atlantis-soc.dtsi"
> +
> +/ {
> +       model = "Tenstorrent Atlantis development platform";
> +       compatible = "tenstorrent,atlantis-evb", "tenstorrent,atlantis";
> +
> +       memory@0 {
> +               device_type = "memory";
> +               reg = <0x0 0x00000000 0x0 0x80000000>,
> +                     <0x1 0x80000000 0x0 0x80000000>;
> +       };
> +
> +       aliases {
> +               serial0 = &uart1;
> +       };
> +
> +       chosen {
> +               bootargs = "earlycon=sbi";
> +               stdout-path = "serial0:115200";
> +       };
> +};
> +
> +&uart1 {
> +       status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
> new file mode 100644
> index 000000000000..085b0ab90bbe
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
> @@ -0,0 +1,473 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +// Copyright 2026 Tenstorrent
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h>
> +
> +/ {
> +       model = "Tenstorrent Atlantis";
> +       compatible = "tenstorrent,atlantis";
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       cpus {

Please add a cpus: label here (like below). It'll be useful if we need
to refer to this node in the u-boot DT.

            cpus: cpus {

            };

> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               timebase-frequency = <1000000000>;
> +
> +               cpu0: cpu@0 {
> +                       compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
> +                       reg = <0>;

Re: [PATCH v3 7/7] riscv: dts: tenstorrent: Add Atlantis platform

[Emil Renner Berthing]

Quoting Joel Stanley (2026-11-09 06:10:47)
> Add initial support for the Tenstorrent Atlantis platform, based on the
> Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.
>
> The evb machine represents an internal bringup vehicle with just the
> interrupt controllers and a UART. This will be updated in time with a
> full featured machine once details are available.
>
> The chosen node sets bootargs to earlycon=sbi to aid debugging early
> boot, as the platform may not have a bootloader to fill out the chosen
> node.

Does this mean OpenSBI uses a different uart from uart1?

If not that means both Linux in S-mode and OpenSBI in M-mode will
both try to use uart1 at the same time. It might work by chance,
but a much better solution would be to just use "earlycon".
You already define chosen/stdout-path to point at uart1 and the
driver for 'snps,dw-apb-uart' implements earlycon so it should
work much the same.

/Emil