[PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Tushar Nimkar]

From: Anirudha Sarangi <anirudha.sarangi@amd.com>

Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
(Control and Status Register) interrupt controller.

The SMMU CSR block acts as a vendor-specific interrupt controller
in front of the ARM SMMUv3, providing registers to enable and clear
standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
Interrupts must be acknowledged in this block before being forwarded
to the parent interrupt controller (e.g. GIC).

Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
---
 .../xlnx,versal-net-smmu-csr.yaml             | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
new file mode 100644
index 000000000000..3387deabb5be
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/xlnx,versal-net-smmu-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal NET SMMU CSR Interrupt Controller
+
+maintainers:
+  - Anirudha Sarangi <anirudha.sarangi@amd.com>
+  - Tushar Nimkar <tushar.nimkar@amd.com>
+
+description: |
+  The Versal NET platform includes a Xilinx-specific SMMU CSR (Control and
+  Status Register) block that acts as an intermediate interrupt controller
+  for ARM SMMUv3.
+
+  The block provides registers to enable, disable and clear the
+  standard SMMUv3 interrupt sources (EVENTQ, CMDQ_SYNC, GERROR and PRIQ)
+  before forwarding them to the parent interrupt controller,
+  typically a GIC.
+
+  The controller receives one parent interrupt and demultiplexes CSR
+  status bits into the following child interrupt identifiers
+    0 - EVENTQ
+    1 - CMDQ_SYNC
+    2 - GERROR (GLOBAL)
+    3 - PRIQ
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    const: xlnx,versal-net-smmu-csr
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+    description: |
+     Single cell containing the child interrupt identifier
+      0 - EVENTQ
+      1 - CMDQ_SYNC
+      2 - GERROR (GLOBAL)
+      3 - PRIQ
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - "#interrupt-cells"
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    iommu@ec000000 {
+        compatible = "arm,smmu-v3";
+        reg = <0xec000000 0x40000>;
+        #iommu-cells = <1>;
+        dma-coherent;
+        interrupt-names = "eventq", "gerror", "priq";
+        interrupt-parent = <&smmu_irq_csr>;
+        interrupts = <0>, <2>, <3>;
+    };
+
+    smmu_irq_csr: interrupt-controller@eca10000 {
+        compatible = "xlnx,versal-net-smmu-csr";
+        reg = <0xeca10000 0x1000>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+    };
-- 
2.34.1

Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Krzysztof Kozlowski]

On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
> From: Anirudha Sarangi <anirudha.sarangi@amd.com>
> 
> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
> (Control and Status Register) interrupt controller.
> 
> The SMMU CSR block acts as a vendor-specific interrupt controller
> in front of the ARM SMMUv3, providing registers to enable and clear
> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
> Interrupts must be acknowledged in this block before being forwarded
> to the parent interrupt controller (e.g. GIC).
> 
> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
> Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
> ---

b4 got only this one patch, where is the rest?

Can finally people in AMD start using b4 to send patches? How many times
I need to ask for that?


>  .../xlnx,versal-net-smmu-csr.yaml             | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
> 
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    iommu@ec000000 {
> +        compatible = "arm,smmu-v3";
> +        reg = <0xec000000 0x40000>;
> +        #iommu-cells = <1>;
> +        dma-coherent;
> +        interrupt-names = "eventq", "gerror", "priq";
> +        interrupt-parent = <&smmu_irq_csr>;
> +        interrupts = <0>, <2>, <3>;
> +    };

Drop node irrelevant.

> +
> +    smmu_irq_csr: interrupt-controller@eca10000 {

Drop unused label

> +        compatible = "xlnx,versal-net-smmu-csr";
> +        reg = <0xeca10000 0x1000>;
> +        interrupt-controller;
> +        #interrupt-cells = <1>;
> +        interrupt-parent = <&gic>;
> +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> -- 
> 2.34.1
> 
> 

Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Krzysztof Kozlowski]

On 18/08/2026 09:03, Krzysztof Kozlowski wrote:
> On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
>> From: Anirudha Sarangi <anirudha.sarangi@amd.com>
>>
>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
>> (Control and Status Register) interrupt controller.
>>
>> The SMMU CSR block acts as a vendor-specific interrupt controller
>> in front of the ARM SMMUv3, providing registers to enable and clear
>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
>> Interrupts must be acknowledged in this block before being forwarded
>> to the parent interrupt controller (e.g. GIC).
>>
>> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
>> Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> ---
> 
> b4 got only this one patch, where is the rest?
> 
> Can finally people in AMD start using b4 to send patches? How many times
> I need to ask for that?
> 
> 
>>  .../xlnx,versal-net-smmu-csr.yaml             | 85 +++++++++++++++++++
>>  1 file changed, 85 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
>>
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupt-controller
>> +  - "#interrupt-cells"
>> +  - interrupts
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    iommu@ec000000 {
>> +        compatible = "arm,smmu-v3";
>> +        reg = <0xec000000 0x40000>;
>> +        #iommu-cells = <1>;
>> +        dma-coherent;
>> +        interrupt-names = "eventq", "gerror", "priq";
>> +        interrupt-parent = <&smmu_irq_csr>;
>> +        interrupts = <0>, <2>, <3>;
>> +    };
> 
> Drop node irrelevant.
> 
>> +
>> +    smmu_irq_csr: interrupt-controller@eca10000 {
> 
> Drop unused label

Ah and:

drop second/last, redundant "bindings". The "dt-bindings" prefix is
already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Michal Simek]

On 8/18/26 09:03, Krzysztof Kozlowski wrote:
> On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
>> From: Anirudha Sarangi <anirudha.sarangi@amd.com>
>>
>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
>> (Control and Status Register) interrupt controller.
>>
>> The SMMU CSR block acts as a vendor-specific interrupt controller
>> in front of the ARM SMMUv3, providing registers to enable and clear
>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
>> Interrupts must be acknowledged in this block before being forwarded
>> to the parent interrupt controller (e.g. GIC).
>>
>> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
>> Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> ---
> 
> b4 got only this one patch, where is the rest?
> 
> Can finally people in AMD start using b4 to send patches? How many times
> I need to ask for that?

Not sure what you want me to say about it. I don't think that this is related to 
AMD but only individual developers.

There are also other tools for doing it not just b4. Everybody got these 
instructions but it is up to everybody to follow them. When something is sent 
out I can't do anything with it. (And internally this was sent as threaded 
multiple times).

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Tushar Nimkar]

On 8/18/2026 12:48 PM, Michal Simek wrote:
>
>
> On 8/18/26 09:03, Krzysztof Kozlowski wrote:
>> On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
>>> From: Anirudha Sarangi <anirudha.sarangi@amd.com>
>>>
>>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
>>> (Control and Status Register) interrupt controller.
>>>
>>> The SMMU CSR block acts as a vendor-specific interrupt controller
>>> in front of the ARM SMMUv3, providing registers to enable and clear
>>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
>>> Interrupts must be acknowledged in this block before being forwarded
>>> to the parent interrupt controller (e.g. GIC).
>>>
>>> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
>>> Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
>>> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
>>> ---
>>
>> b4 got only this one patch, where is the rest?
>>
>> Can finally people in AMD start using b4 to send patches? How many times
>> I need to ask for that?
>
> Not sure what you want me to say about it. I don't think that this is 
> related to AMD but only individual developers.
>
> There are also other tools for doing it not just b4. Everybody got 
> these instructions but it is up to everybody to follow them. When 
> something is sent out I can't do anything with it. (And internally 
> this was sent as threaded multiple times).
>

My bad !!
Something went bad while sending outside.

Krzysztof,
The other patch link - 
https://lore.kernel.org/all/20260817105251.1557770-1-tushar.nimkar@amd.com/
and I will fix this.

I apologize.

> Thanks,
> Michal
>