[PATCH v2 0/6] Shikra: Add DT support for ICE, RNG and QCE

[PATCH v2 0/6] Shikra: Add DT support for ICE, RNG and QCE

[Kuldeep Singh]

This patch series enables SDHC ICE, RNG and QCE support on Shikra,
aligned with how similar support is modeled on other Qualcomm platforms.

These DT and dt-bindings updates were previously posted as three
separate series. Based on review feedback, they are grouped here as one
crypto-focused series.

Previous threads:
QCE: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-0-80f07b345c29@oss.qualcomm.com/
RNG: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-0-4ea721a1429a@oss.qualcomm.com/
ICE: https://lore.kernel.org/lkml/20260515-shikra_ice_ufs-v2-0-2724a54339db@oss.qualcomm.com/

Prerequisite series:
- https://lore.kernel.org/all/20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com/
- https://lore.kernel.org/lkml/20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com/,

Validation:
- ICE: driver probe at boot
- QCE: kcapi tests and driver probe
- RNG: validated using rngutils
- DT: validated shikra-cqs-evk.dtb with dt_binding_check and CHECK_DTBS=y

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
Changes in v2:
- Add fix in ice bindings to specify 2 clocks defauly for non-legacy Soc
  compatibles.
- Update commit messages.
- Link to v1: https://patch.msgid.link/20260521-shikra_crypto_changse-v1-0-0154cc9cc0de@oss.qualcomm.com/

To: Herbert Xu <herbert@gondor.apana.org.au>
To: "David S. Miller" <davem@davemloft.net>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
To: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
To: Harshal Dev <harshal.dev@oss.qualcomm.com>
To: Vinod Koul <vkoul@kernel.org>
To: Bartosz Golaszewski <brgl@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Frank Li <Frank.Li@kernel.org>
To: Andy Gross <agross@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: dmaengine@vger.kernel.org

---
Kuldeep Singh (6):
      dt-bindings: crypto: qcom,inline-crypto-engine: Fix legacy/new SoC strictness split
      dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE
      dt-bindings: crypto: qcom,prng: Document Shikra TRNG
      dt-bindings: crypto: qcom-qce: Document the Shikra crypto engine
      dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven
      arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes

 .../bindings/crypto/qcom,inline-crypto-engine.yaml | 24 +++++++---
 .../devicetree/bindings/crypto/qcom,prng.yaml      |  1 +
 .../devicetree/bindings/crypto/qcom-qce.yaml       |  1 +
 .../devicetree/bindings/dma/qcom,bam-dma.yaml      |  2 +-
 arch/arm64/boot/dts/qcom/shikra.dtsi               | 52 ++++++++++++++++++++++
 5 files changed, 73 insertions(+), 7 deletions(-)
---
base-commit: 9ac84344d36457c598806f7d8ed1369a8b0c5c45
change-id: 20260701-b4-shikra_crypto_changse-f2d6d5bf04b5
prerequisite-message-id: <20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com>
prerequisite-patch-id: 3a689e8dda5fd2755b689d94d095806b3f2e6eed
prerequisite-patch-id: ac83151a889855498d36288ddd36216d451340c8
prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405
prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc
prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8
prerequisite-message-id: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com>
prerequisite-patch-id: 0118397958b85e4297b47d6553ba4bf5b84024bb
prerequisite-patch-id: b6724798e8b73fb2182d11bda2a7aaa58976c7ea
prerequisite-patch-id: 4101033ee8eb0bc79c8dbc4a6c636cd527bf3bd0

Best regards,
--  
Kuldeep Singh <kuldsing@qti.qualcomm.com>

[PATCH v2 1/6] dt-bindings: crypto: qcom,inline-crypto-engine: Fix legacy/new SoC strictness split

[Kuldeep Singh]

Couple of already merged SoCs describe ICE as single clock historically
which are recently updated with mandatory 2 clocks.

Keep only the known legacy compatibles flexible, and make strict
validation default(of power-domains and 2 clocks) for all other Soc
compatibles.

This ensures old DTs are valid while ensuring any new SoC (not in the
legacy allowlist) must follow latest requirements by default.

Fixes: e27264daac7d ("dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk")
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 .../bindings/crypto/qcom,inline-crypto-engine.yaml | 23 ++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index db895c50e2d2..4f3689a24410 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -55,14 +55,25 @@ required:
 
 additionalProperties: false
 
+# Do not extend the list.
+# Legacy SoCs are allowed for single clock.
+# New SoCs must provide both clocks and power domains.
 allOf:
   - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,eliza-inline-crypto-engine
-              - qcom,milos-inline-crypto-engine
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - qcom,kaanapali-inline-crypto-engine
+                - qcom,qcs8300-inline-crypto-engine
+                - qcom,sa8775p-inline-crypto-engine
+                - qcom,sc7180-inline-crypto-engine
+                - qcom,sc7280-inline-crypto-engine
+                - qcom,sm8450-inline-crypto-engine
+                - qcom,sm8550-inline-crypto-engine
+                - qcom,sm8650-inline-crypto-engine
+                - qcom,sm8750-inline-crypto-engine
 
     then:
       required:

-- 
2.34.1

Re: [PATCH v2 1/6] dt-bindings: crypto: qcom,inline-crypto-engine: Fix legacy/new SoC strictness split

[Krzysztof Kozlowski]

On Thu, Jul 02, 2026 at 01:47:11AM +0530, Kuldeep Singh wrote:
> Couple of already merged SoCs describe ICE as single clock historically
> which are recently updated with mandatory 2 clocks.
> 
> Keep only the known legacy compatibles flexible, and make strict
> validation default(of power-domains and 2 clocks) for all other Soc
> compatibles.
> 
> This ensures old DTs are valid while ensuring any new SoC (not in the
> legacy allowlist) must follow latest requirements by default.
> 
> Fixes: e27264daac7d ("dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk")

Please drop, original codeo was correct, no bug to fix.

> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  .../bindings/crypto/qcom,inline-crypto-engine.yaml | 23 ++++++++++++++++------
>  1 file changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> index db895c50e2d2..4f3689a24410 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> @@ -55,14 +55,25 @@ required:
>  
>  additionalProperties: false
>  
> +# Do not extend the list.
> +# Legacy SoCs are allowed for single clock.
> +# New SoCs must provide both clocks and power domains.
>  allOf:
>    - if:
> -      properties:
> -        compatible:
> -          contains:
> -            enum:
> -              - qcom,eliza-inline-crypto-engine
> -              - qcom,milos-inline-crypto-engine
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - qcom,kaanapali-inline-crypto-engine

Your change is not equivalent in relation to hawi. Please make it
explicit in commit msg - all devices which are fixed by this.

> +                - qcom,qcs8300-inline-crypto-engine
> +                - qcom,sa8775p-inline-crypto-engine
> +                - qcom,sc7180-inline-crypto-engine
> +                - qcom,sc7280-inline-crypto-engine
> +                - qcom,sm8450-inline-crypto-engine
> +                - qcom,sm8550-inline-crypto-engine
> +                - qcom,sm8650-inline-crypto-engine
> +                - qcom,sm8750-inline-crypto-engine

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: crypto: qcom,inline-crypto-engine: Fix legacy/new SoC strictness split

[Kuldeep Singh]

On 03-07-2026 12:21, Krzysztof Kozlowski wrote:
> On Thu, Jul 02, 2026 at 01:47:11AM +0530, Kuldeep Singh wrote:
>> Couple of already merged SoCs describe ICE as single clock historically
>> which are recently updated with mandatory 2 clocks.
>>
>> Keep only the known legacy compatibles flexible, and make strict
>> validation default(of power-domains and 2 clocks) for all other Soc
>> compatibles.
>>
>> This ensures old DTs are valid while ensuring any new SoC (not in the
>> legacy allowlist) must follow latest requirements by default.
>>
>> Fixes: e27264daac7d ("dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk")
> 
> Please drop, original codeo was correct, no bug to fix.

Ok.

> 
>> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
>> ---
>>  .../bindings/crypto/qcom,inline-crypto-engine.yaml | 23 ++++++++++++++++------
>>  1 file changed, 17 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> index db895c50e2d2..4f3689a24410 100644
>> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> @@ -55,14 +55,25 @@ required:
>>  
>>  additionalProperties: false
>>  
>> +# Do not extend the list.
>> +# Legacy SoCs are allowed for single clock.
>> +# New SoCs must provide both clocks and power domains.
>>  allOf:
>>    - if:
>> -      properties:
>> -        compatible:
>> -          contains:
>> -            enum:
>> -              - qcom,eliza-inline-crypto-engine
>> -              - qcom,milos-inline-crypto-engine
>> +      not:
>> +        properties:
>> +          compatible:
>> +            contains:
>> +              enum:
>> +                - qcom,kaanapali-inline-crypto-engine
> 
> Your change is not equivalent in relation to hawi. Please make it
> explicit in commit msg - all devices which are fixed by this.

Sure, eliza/milos/hawi are non-legacy and will adapt 2 clocks model by
default so will update them in commit message.

-- 
Regards
Kuldeep

[PATCH v2 2/6] dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE

[Kuldeep Singh]

Document the Inline Crypto Engine (ICE) on the Qualcomm Shikra platform.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 4f3689a24410..9e6d3af42971 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -21,6 +21,7 @@ properties:
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine
           - qcom,sc7280-inline-crypto-engine
+          - qcom,shikra-inline-crypto-engine
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine

-- 
2.34.1

Re: [PATCH v2 2/6] dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE

[Krzysztof Kozlowski]

On Thu, Jul 02, 2026 at 01:47:12AM +0530, Kuldeep Singh wrote:
> Document the Inline Crypto Engine (ICE) on the Qualcomm Shikra platform.
> 
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 2/6] dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE

[Bartosz Golaszewski]

On Wed, 1 Jul 2026 22:17:12 +0200, Kuldeep Singh
<kuldeep.singh@oss.qualcomm.com> said:
> Document the Inline Crypto Engine (ICE) on the Qualcomm Shikra platform.
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> index 4f3689a24410..9e6d3af42971 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> @@ -21,6 +21,7 @@ properties:
>            - qcom,sa8775p-inline-crypto-engine
>            - qcom,sc7180-inline-crypto-engine
>            - qcom,sc7280-inline-crypto-engine
> +          - qcom,shikra-inline-crypto-engine
>            - qcom,sm8450-inline-crypto-engine
>            - qcom,sm8550-inline-crypto-engine
>            - qcom,sm8650-inline-crypto-engine
>
> --
> 2.34.1
>
>

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

[PATCH v2 3/6] dt-bindings: crypto: qcom,prng: Document Shikra TRNG

[Kuldeep Singh]

Document shikra compatible for the True Random Number Generator.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index dc270c8aedf3..5de52d7a745c 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -30,6 +30,7 @@ properties:
               - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
+              - qcom,shikra-trng
               - qcom,sm8450-trng
               - qcom,sm8550-trng
               - qcom,sm8650-trng

-- 
2.34.1

Re: [PATCH v2 3/6] dt-bindings: crypto: qcom,prng: Document Shikra TRNG

[Krzysztof Kozlowski]

On Thu, Jul 02, 2026 at 01:47:13AM +0530, Kuldeep Singh wrote:
> Document shikra compatible for the True Random Number Generator.
> 
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 3/6] dt-bindings: crypto: qcom,prng: Document Shikra TRNG

[Bartosz Golaszewski]

On Wed, 1 Jul 2026 22:17:13 +0200, Kuldeep Singh
<kuldeep.singh@oss.qualcomm.com> said:
> Document shikra compatible for the True Random Number Generator.
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> index dc270c8aedf3..5de52d7a745c 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> @@ -30,6 +30,7 @@ properties:
>                - qcom,sa8255p-trng
>                - qcom,sa8775p-trng
>                - qcom,sc7280-trng
> +              - qcom,shikra-trng
>                - qcom,sm8450-trng
>                - qcom,sm8550-trng
>                - qcom,sm8650-trng
>
> --
> 2.34.1
>
>

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

[PATCH v2 4/6] dt-bindings: crypto: qcom-qce: Document the Shikra crypto engine

[Kuldeep Singh]

Document the crypto engine on the Qualcomm Shikra platform.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 08febd66c22b..5a653757ee75 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -54,6 +54,7 @@ properties:
               - qcom,qcs8300-qce
               - qcom,sa8775p-qce
               - qcom,sc7280-qce
+              - qcom,shikra-qce
               - qcom,sm6350-qce
               - qcom,sm8250-qce
               - qcom,sm8350-qce

-- 
2.34.1

Re: [PATCH v2 4/6] dt-bindings: crypto: qcom-qce: Document the Shikra crypto engine

[Krzysztof Kozlowski]

On Thu, Jul 02, 2026 at 01:47:14AM +0530, Kuldeep Singh wrote:
> Document the crypto engine on the Qualcomm Shikra platform.
> 
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 4/6] dt-bindings: crypto: qcom-qce: Document the Shikra crypto engine

[Bartosz Golaszewski]

On Wed, 1 Jul 2026 22:17:14 +0200, Kuldeep Singh
<kuldeep.singh@oss.qualcomm.com> said:
> Document the crypto engine on the Qualcomm Shikra platform.
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index 08febd66c22b..5a653757ee75 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -54,6 +54,7 @@ properties:
>                - qcom,qcs8300-qce
>                - qcom,sa8775p-qce
>                - qcom,sc7280-qce
> +              - qcom,shikra-qce
>                - qcom,sm6350-qce
>                - qcom,sm8250-qce
>                - qcom,sm8350-qce
>
> --
> 2.34.1
>
>

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

[PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Kuldeep Singh]

Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
`iommus` maxItems constraint.

Fix below error:
dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
134, 17], [25, 146, 0], [25, 148, 17], [25, 150, 17], [25, 152, 1], [25,
159, 0]] is too long
      from schema $id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
index 0923fb189ada..e72adc172af1 100644
--- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
@@ -48,7 +48,7 @@ properties:
 
   iommus:
     minItems: 1
-    maxItems: 6
+    maxItems: 7
 
   num-channels:
     $ref: /schemas/types.yaml#/definitions/uint32

-- 
2.34.1

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Krzysztof Kozlowski]

On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
> `iommus` maxItems constraint.
> 
> Fix below error:
> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,

There is no dma-controller@1b04000 in DTS. Please drop all the warnings
which do not exist.

You cannot add incorrect code, cause warnings and then based on that
claim that there is a warning to fix. It's like adding NULL ptr
exception in next patch and therefore now you add some additional checks
for that future NULL ptr exception.

Solution is: do not add NULL ptr exception...

> 134, 17], [25, 146, 0], [25, 148, 17], [25, 150, 17], [25, 152, 1], [25,
> 159, 0]] is too long
>       from schema $id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml

Best regards,
Krzysztof

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Kuldeep Singh]

On 03-07-2026 12:24, Krzysztof Kozlowski wrote:
> On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
>> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
>> `iommus` maxItems constraint.
>>
>> Fix below error:
>> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
> 
> There is no dma-controller@1b04000 in DTS. Please drop all the warnings
> which do not exist.

Kindly check patch 6/6, it is introducing bam node with 7iommus which IP
describes and hence, updated bindings before to accustom this which also
helps in avoiding rob's dt-schema bot error.

The same way we add qcom,shikra* compatible before consuming in DT,
isn't this case also similar where bindings are updated as per the DT
changes?
> You cannot add incorrect code, 

Shikra bam actually has 7 iommus and hence, bindings need an update.

-- 
Regards
Kuldeep

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Konrad Dybcio]

On 7/3/26 10:38 AM, Kuldeep Singh wrote:
> On 03-07-2026 12:24, Krzysztof Kozlowski wrote:
>> On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
>>> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
>>> `iommus` maxItems constraint.
>>>
>>> Fix below error:
>>> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
>>
>> There is no dma-controller@1b04000 in DTS. Please drop all the warnings
>> which do not exist.
> 
> Kindly check patch 6/6, it is introducing bam node with 7iommus which IP
> describes and hence, updated bindings before to accustom this which also
> helps in avoiding rob's dt-schema bot error.

Krzysztof is saying that the error doesn't exist in the tree (because
the offending DTS hunk is not merged), so you shouldn't claim this fixes
an error, rather that Shikra simply needs it

Konrad

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Kuldeep Singh]

On 03-07-2026 14:27, Konrad Dybcio wrote:
> On 7/3/26 10:38 AM, Kuldeep Singh wrote:
>> On 03-07-2026 12:24, Krzysztof Kozlowski wrote:
>>> On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
>>>> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
>>>> `iommus` maxItems constraint.
>>>>
>>>> Fix below error:
>>>> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
>>>
>>> There is no dma-controller@1b04000 in DTS. Please drop all the warnings
>>> which do not exist.
>>
>> Kindly check patch 6/6, it is introducing bam node with 7iommus which IP
>> describes and hence, updated bindings before to accustom this which also
>> helps in avoiding rob's dt-schema bot error.
> 
> Krzysztof is saying that the error doesn't exist in the tree (because
> the offending DTS hunk is not merged), so you shouldn't claim this fixes
> an error, rather that Shikra simply needs it

In previous patchset, krzysztof ask was to add error in commit log and
hence updated that.
Maybe some misunderstanding!

I get the point, in that case I should simply say below and drop errors
in commit message.
"Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
`iommus` maxItems constraint."

Hope this is fine.

-- 
Regards
Kuldeep

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Krzysztof Kozlowski]

On 03/07/2026 11:01, Kuldeep Singh wrote:
> 
> 
> On 03-07-2026 14:27, Konrad Dybcio wrote:
>> On 7/3/26 10:38 AM, Kuldeep Singh wrote:
>>> On 03-07-2026 12:24, Krzysztof Kozlowski wrote:
>>>> On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
>>>>> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
>>>>> `iommus` maxItems constraint.
>>>>>
>>>>> Fix below error:
>>>>> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
>>>>
>>>> There is no dma-controller@1b04000 in DTS. Please drop all the warnings
>>>> which do not exist.
>>>
>>> Kindly check patch 6/6, it is introducing bam node with 7iommus which IP
>>> describes and hence, updated bindings before to accustom this which also
>>> helps in avoiding rob's dt-schema bot error.
>>
>> Krzysztof is saying that the error doesn't exist in the tree (because
>> the offending DTS hunk is not merged), so you shouldn't claim this fixes
>> an error, rather that Shikra simply needs it
> 
> In previous patchset, krzysztof ask was to add error in commit log and
> hence updated that.
> Maybe some misunderstanding!

From that answer you should have understood there are no warnings to be
fixed, no warnings to be mentioned, so that commit msg should have been
fixed.

Solution is not to add fake warnings in such case, like you did here.

Best regards,
Krzysztof

Re: [PATCH v2 5/6] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven

[Krzysztof Kozlowski]

On 04/07/2026 10:37, Krzysztof Kozlowski wrote:
> On 03/07/2026 11:01, Kuldeep Singh wrote:
>>
>>
>> On 03-07-2026 14:27, Konrad Dybcio wrote:
>>> On 7/3/26 10:38 AM, Kuldeep Singh wrote:
>>>> On 03-07-2026 12:24, Krzysztof Kozlowski wrote:
>>>>> On Thu, Jul 02, 2026 at 01:47:15AM +0530, Kuldeep Singh wrote:
>>>>>> Upcoming Shikra BAM DMA uses 7 IOMMU entries and not 6, so increase the
>>>>>> `iommus` maxItems constraint.
>>>>>>
>>>>>> Fix below error:
>>>>>> dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[25, 132, 17], [25,
>>>>>
>>>>> There is no dma-controller@1b04000 in DTS. Please drop all the warnings
>>>>> which do not exist.
>>>>
>>>> Kindly check patch 6/6, it is introducing bam node with 7iommus which IP
>>>> describes and hence, updated bindings before to accustom this which also
>>>> helps in avoiding rob's dt-schema bot error.
>>>
>>> Krzysztof is saying that the error doesn't exist in the tree (because
>>> the offending DTS hunk is not merged), so you shouldn't claim this fixes
>>> an error, rather that Shikra simply needs it
>>
>> In previous patchset, krzysztof ask was to add error in commit log and
>> hence updated that.
>> Maybe some misunderstanding!
> 
> From that answer you should have understood there are no warnings to be
> fixed, no warnings to be mentioned, so that commit msg should have been
> fixed.
> 
> Solution is not to add fake warnings in such case, like you did here.
> 


I even said that to you last time at v1!

"Again, there is no error. Revert this patch and check."

https://lore.kernel.org/all/c6415963-ef68-4422-a7fb-fd23b007de32@kernel.org/

Best regards,
Krzysztof

[PATCH v2 6/6] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes

[Kuldeep Singh]

Add device tree nodes describing the crypto hardware blocks present
on the Qualcomm Shikra platform:

- BAM DMA controller used by the Qualcomm crypto engine
- QCE (crypto) engine with DMA support
- TRNG hardware random number generator
- Inline crypto engine (ICE)

Also connect the SDHC controller to ICE via "qcom,ice" property to
support inline encryption.

On Shikra, different BAM pipe pairs (for example 0x84/0x94 and
0x86/0x96) may still resolve to the same resulting SID due SMMU-side
optimization. They are still distinct pipe pairs and therefore require
separate DT IOMMU entries.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 52 ++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8e..a95e2140416c 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -482,6 +482,41 @@ config_noc: interconnect@1900000 {
 			#interconnect-cells = <2>;
 		};
 
+		cryptobam: dma-controller@1b04000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x0 0x01b04000 0x0 0x24000>;
+			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+			iommus = <&apps_smmu 0x84 0x0011>,
+				 <&apps_smmu 0x86 0x0011>,
+				 <&apps_smmu 0x92 0x0>,
+				 <&apps_smmu 0x94 0x0011>,
+				 <&apps_smmu 0x96 0x0011>,
+				 <&apps_smmu 0x98 0x0001>,
+				 <&apps_smmu 0x9f 0x0>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			num-channels = <16>;
+			qcom,num-ees = <4>;
+		};
+
+		crypto: crypto@1b3a000 {
+			compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce";
+			reg = <0x0 0x01b3a000 0x0 0x6000>;
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x84 0x0011>,
+				 <&apps_smmu 0x86 0x0011>,
+				 <&apps_smmu 0x92 0x0>,
+				 <&apps_smmu 0x94 0x0011>,
+				 <&apps_smmu 0x96 0x0011>,
+				 <&apps_smmu 0x98 0x0001>,
+				 <&apps_smmu 0x9f 0x0>;
+			interconnects = <&system_noc MASTER_CRYPTO_CORE0 0
+					 &mc_virt SLAVE_EBI_CH0 0>;
+			interconnect-names = "memory";
+		};
+
 		qfprom: efuse@1b44000 {
 			compatible = "qcom,shikra-qfprom", "qcom,qfprom";
 			reg = <0x0 0x01b44000 0x0 0x3000>;
@@ -521,6 +556,11 @@ spmi_bus: spmi@1c40000 {
 			qcom,ee = <0>;
 		};
 
+		rng: rng@4454000 {
+			compatible = "qcom,shikra-trng", "qcom,trng";
+			reg = <0x0 0x04454000 0x0 0x1000>;
+		};
+
 		rpm_msg_ram: sram@45f0000 {
 			compatible = "qcom,rpm-msg-ram", "mmio-sram";
 			reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -582,6 +622,7 @@ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
 			mmc-hs400-enhanced-strobe;
 
 			resets = <&gcc GCC_SDCC1_BCR>;
+			qcom,ice = <&sdhc_ice>;
 
 			status = "disabled";
 
@@ -604,6 +645,17 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@4748000 {
+			compatible = "qcom,shikra-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x04748000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&rpmpd RPMHPD_CX>;
+		};
+
 		qupv3_0: geniqup@4ac0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0x0 0x04ac0000 0x0 0x2000>;

-- 
2.34.1

Re: [PATCH v2 6/6] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes

[Bartosz Golaszewski]

On Wed, 1 Jul 2026 22:17:16 +0200, Kuldeep Singh
<kuldeep.singh@oss.qualcomm.com> said:
> Add device tree nodes describing the crypto hardware blocks present
> on the Qualcomm Shikra platform:
>
> - BAM DMA controller used by the Qualcomm crypto engine
> - QCE (crypto) engine with DMA support
> - TRNG hardware random number generator
> - Inline crypto engine (ICE)
>
> Also connect the SDHC controller to ICE via "qcom,ice" property to
> support inline encryption.
>
> On Shikra, different BAM pipe pairs (for example 0x84/0x94 and
> 0x86/0x96) may still resolve to the same resulting SID due SMMU-side
> optimization. They are still distinct pipe pairs and therefore require
> separate DT IOMMU entries.
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>