[PATCH 0/6] arm64: dts: qcom: kaanapali: Add PMIC dependent features

[PATCH 0/6] arm64: dts: qcom: kaanapali: Add PMIC dependent features

[Jingyi Wang]

Add PMIC dependent features on the Kaanapali Platform including:
- spmi-pmic-arb device
- various PMICs along with temp-alarm and GPIO nodes
- Volume Keys, RGB LEDs and flash LEDs
- bluetooth WCN785x and Wi-Fi (enabled on MTP only)
- Display (enabled on MTP only)

dependency:
dts: https://lore.kernel.org/all/20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com/ - reviewed

For display feature, there is a 20~30% probability of crash during the DPU initialization
stage without voltage and frequency alignment. The issue can be fixed by:
https://lore.kernel.org/all/20260309063720.13572-1-yuanjie.yang@oss.qualcomm.com/ - reviewed

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
Jishnu Prakash (3):
      arm64: dts: qcom: kaanapali: Add PMIC devices
      arm64: dts: qcom: kaanapali-mtp: Add PMIC support
      arm64: dts: qcom: kaanapali-qrd: Add PMIC support

Yuanjie Yang (2):
      arm64: dts: qcom: kaanapali: add display hardware devices
      arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices

Zijun Hu (1):
      arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts       | 331 ++++++++++++++++++++++-
 arch/arm64/boot/dts/qcom/kaanapali-qrd.dts       |  92 +++++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi          | 289 +++++++++++++++++++-
 arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi   |  93 +++++++
 arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi  |  62 +++++
 arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi  |  63 +++++
 arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi  | 213 +++++++++++++++
 arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi |  68 +++++
 arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi  |  63 +++++
 9 files changed, 1271 insertions(+), 3 deletions(-)
---
base-commit: 3ef088b0c5772a6f75634e54aa34f5fc0a2c041c
change-id: 20260322-knp-pmic-dt-4873a7d906e6
prerequisite-message-id: <20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com>
prerequisite-patch-id: 46f519528d63c06ae8d46857285f08dbc0178a11
prerequisite-patch-id: 80394c38f46592e7bef58b2670bb18e9253718b0
prerequisite-patch-id: 2b0a4d96d4ce86fc6e56e80316f53f30020abf65
prerequisite-patch-id: 019501eb4a1a36a34c5b90f63bb2f1b521d6d60c
prerequisite-patch-id: 46ef2e848ebe5af55c6e8d6e16c775f4e3db4ed1
prerequisite-patch-id: f24bbf211e6fe18d5a022b1bd31050b0b4056cd4
prerequisite-patch-id: 72c1a9d0eb5c8a94233d47809192e033ba2cb6ab
prerequisite-patch-id: ef3125ac8d8471149ab219b79a90304dd491602f
prerequisite-patch-id: f7fff260ebea331c7faf9be96eae00ceb42f94bf
prerequisite-patch-id: fa0135a52b89f9c5baa8c9fa160d2d927e4e37bc

Best regards,
-- 
Jingyi Wang <jingyi.wang@oss.qualcomm.com>

[PATCH 1/6] arm64: dts: qcom: kaanapali: Add PMIC devices

[Jingyi Wang]

From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>

Add a spmi-pmic-arb device for the SPMI PMIC arbiter found on Kaanapali.
It has two subnodes corresponding to the SPMI0 bus controller and the
SPMI1 bus controller.

Also add dtsi files for PMH0104, PMH0110, PMD8028, PMIH0108, PMR735D
and PM8010 along with temp-alarm and GPIO nodes under them, which are
needed on Kaanapali.

Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi          |  47 +++++
 arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi   |  93 ++++++++++
 arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi  |  62 +++++++
 arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi  |  63 +++++++
 arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi  | 213 +++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi |  68 ++++++++
 arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi  |  63 +++++++
 7 files changed, 609 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 54d6c235e1b1..f0de06b2c20b 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -3316,6 +3316,53 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
 			#clock-cells = <0>;
 		};
 
+		arbiter@c400000 {
+			compatible = "qcom,kaanapali-spmi-pmic-arb", "qcom,glymur-spmi-pmic-arb";
+			reg = <0x0 0x0c400000 0x0 0x3000>,
+			      <0x0 0x0c900000 0x0 0x400000>,
+			      <0x0 0x0c4c0000 0x0 0x400000>,
+			      <0x0 0x0c403000 0x0 0x8000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "chnl_map";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			qcom,channel = <0>;
+			qcom,ee = <0>;
+
+			spmi_bus0: spmi@c426000 {
+				reg = <0x0 0x0c426000 0x0 0x4000>,
+				      <0x0 0x0c8c0000 0x0 0x10000>,
+				      <0x0 0x0c42a000 0x0 0x8000>;
+				reg-names = "cnfg",
+					    "intr",
+					    "chnl_owner";
+				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "periph_irq";
+				interrupt-controller;
+				#interrupt-cells = <4>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+			};
+
+			spmi_bus1: spmi@c437000 {
+				reg = <0x0 0x0c437000 0x0 0x4000>,
+				      <0x0 0x0c8d0000 0x0 0x10000>,
+				      <0x0 0x0c43b000 0x0 0x8000>;
+				reg-names = "cnfg",
+					    "intr",
+					    "chnl_owner";
+				interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "periph_irq";
+				interrupt-controller;
+				#interrupt-cells = <4>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+			};
+		};
+
 		tlmm: pinctrl@f100000 {
 			compatible = "qcom,kaanapali-tlmm";
 			reg = <0x0 0x0f100000 0x0 0x300000>;
diff --git a/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi
new file mode 100644
index 000000000000..bfc58a6589d3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pm8010-m-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8010_m_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pm8010-n-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8010_n_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus1 {
+	pm8010_m_e1: pmic@c {
+		compatible = "qcom,pm8010", "qcom,spmi-pmic";
+		reg = <0xc SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8010_m_e1_temp_alarm: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
+	pm8010_n_e1: pmic@d {
+		compatible = "qcom,pm8010", "qcom,spmi-pmic";
+		reg = <0xd SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8010_n_e1_temp_alarm: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi
new file mode 100644
index 000000000000..db4dc16a66e7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmd8028-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmd8028_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus1 {
+	pmd8028_e1: pmic@4 {
+		compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmd8028_e1_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmd8028_e1_gpios: gpio@8800 {
+			compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmd8028_e1_gpios 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi
new file mode 100644
index 000000000000..d009c9a9f59e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmh0104-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus1 {
+	pmh0104_j_e1: pmic@9 {
+		compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+		reg = <0x9 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmh0104_j_e1_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmh0104_j_e1_gpios: gpio@8800 {
+			compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmh0104_j_e1_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi
new file mode 100644
index 000000000000..15d9cff246b3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmh0110-d-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmh0110-f-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmh0110-g-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmh0110-i-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus0 {
+	pmh0110_d_e0: pmic@3 {
+		compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmh0110_d_e0_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmh0110_d_e0_gpios: gpio@8800 {
+			compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmh0110_d_e0_gpios 0 0 14>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pmh0110_f_e0: pmic@5 {
+		compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmh0110_f_e0_gpios: gpio@8800 {
+			compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pmh0110_g_e0: pmic@6 {
+		compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+		reg = <0x6 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmh0110_g_e0_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmh0110_g_e0_gpios: gpio@8800 {
+			compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmh0110_g_e0_gpios 0 0 14>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pmh0110_i_e0: pmic@8 {
+		compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+		reg = <0x8 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmh0110_i_e0_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmh0110_i_e0_gpios: gpio@8800 {
+			compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmh0110_i_e0_gpios 0 0 14>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi
new file mode 100644
index 000000000000..b73b0e82c3d3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmih0108-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmih0108_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus1 {
+	pmih0108_e1: pmic@7 {
+		compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+		reg = <0x7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmih0108_e1_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmih0108_e1_gpios: gpio@8800 {
+			compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmih0108_e1_gpios 0 0 18>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmih0108_e1_eusb2_repeater: phy@fd00 {
+			compatible = "qcom,pm8550b-eusb2-repeater";
+			reg = <0xfd00>;
+			#phy-cells = <0>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi
new file mode 100644
index 000000000000..d0dd5e078cdc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmr735d-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pmr735d_e1_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus1 {
+	pmr735d_e1: pmic@a {
+		compatible = "qcom,pmr735d", "qcom,spmi-pmic";
+		reg = <0xa SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmr735d_e1_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmr735d_e1_gpios: gpio@8800 {
+			compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmr735d_e1_gpios 0 0 2>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};

-- 
2.25.1

Re: [PATCH 1/6] arm64: dts: qcom: kaanapali: Add PMIC devices

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:41PM -0700, Jingyi Wang wrote:
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> 
> Add a spmi-pmic-arb device for the SPMI PMIC arbiter found on Kaanapali.
> It has two subnodes corresponding to the SPMI0 bus controller and the
> SPMI1 bus controller.
> 
> Also add dtsi files for PMH0104, PMH0110, PMD8028, PMIH0108, PMR735D
> and PM8010 along with temp-alarm and GPIO nodes under them, which are
> needed on Kaanapali.

"Also" usually points out that these should be two separate commits.

> 
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali.dtsi          |  47 +++++
>  arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi   |  93 ++++++++++
>  arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi  |  62 +++++++
>  arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi  |  63 +++++++
>  arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi  | 213 +++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi |  68 ++++++++
>  arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi  |  63 +++++++
>  7 files changed, 609 insertions(+)
> 

-- 
With best wishes
Dmitry

Re: [PATCH 1/6] arm64: dts: qcom: kaanapali: Add PMIC devices

[Jishnu Prakash]

Hi Dmitry,

On 3/24/2026 6:42 AM, Dmitry Baryshkov wrote:
> On Sun, Mar 22, 2026 at 11:19:41PM -0700, Jingyi Wang wrote:
>> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>
>> Add a spmi-pmic-arb device for the SPMI PMIC arbiter found on Kaanapali.
>> It has two subnodes corresponding to the SPMI0 bus controller and the
>> SPMI1 bus controller.
>>
>> Also add dtsi files for PMH0104, PMH0110, PMD8028, PMIH0108, PMR735D
>> and PM8010 along with temp-alarm and GPIO nodes under them, which are
>> needed on Kaanapali.
> 
> "Also" usually points out that these should be two separate commits.
> 

I thought it was slightly better to add new PMIC dtsi files in the same
patch adding the PMIC arbiter (which they are dependent on) in the main
SoC dtsi file, like in here:
https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-3-8ce4e489ebb6@oss.qualcomm.com/.

It looks like this patch has been applied in linux-next now. We can
add the new PMIC dtsi files in a separate patch going forward if
that looks better.

Thanks,
Jishnu

>>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/kaanapali.dtsi          |  47 +++++
>>  arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi   |  93 ++++++++++
>>  arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi  |  62 +++++++
>>  arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi  |  63 +++++++
>>  arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi  | 213 +++++++++++++++++++++++
>>  arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi |  68 ++++++++
>>  arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi  |  63 +++++++
>>  7 files changed, 609 insertions(+)
>>
> 

[PATCH 2/6] arm64: dts: qcom: kaanapali-mtp: Add PMIC support

[Jingyi Wang]

From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>

Include PMIC files used on Kaanapali MTP boards. Add configurations for
keys (volume up and volume down), RGB LEDs and flash LEDs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 92 ++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index bc57935c042c..5054c5933687 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -5,9 +5,21 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "kaanapali.dtsi"
 
+#include "pm8010-kaanapali.dtsi"     /* SPMI1: SID-12/13   */
+#include "pmd8028-kaanapali.dtsi"    /* SPMI1: SID-4       */
+#include "pmh0101.dtsi"              /* SPMI0: SID-1       */
+#include "pmh0104-kaanapali.dtsi"    /* SPMI1: SID-9       */
+#include "pmh0110-kaanapali.dtsi"    /* SPMI0: SID-3/5/6/8 */
+#include "pmih0108-kaanapali.dtsi"   /* SPMI1: SID-7       */
+#include "pmk8850.dtsi"              /* SPMI0: SID-0       */
+#include "pmr735d-kaanapali.dtsi"    /* SPMI1: SID-10      */
+
 / {
 	model = "Qualcomm Technologies, Inc. Kaanapali MTP";
 	compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
@@ -53,6 +65,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
 		};
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_vol_up_default>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
 	sound {
 		compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
 		model = "Kaanapali-MTP";
@@ -801,6 +829,63 @@ &pcie_port0 {
 	reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
 };
 
+&pmh0101_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		function-enumerator = <0>;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		function-enumerator = <1>;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+	};
+};
+
+&pmh0101_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
 &remoteproc_adsp {
 	firmware-name = "qcom/kaanapali/adsp.mbn",
 			"qcom/kaanapali/adsp_dtb.mbn";
@@ -940,6 +1025,13 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
 		bias-disable;
 	};
 
+	key_vol_up_default: key-vol-up-default-state {
+		pins = "gpio101";
+		function = "gpio";
+		output-disable;
+		bias-pull-up;
+	};
+
 	pcie0_default_state: pcie0-default-state {
 		perst-n-pins {
 			pins = "gpio102";

-- 
2.25.1

Re: [PATCH 2/6] arm64: dts: qcom: kaanapali-mtp: Add PMIC support

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:42PM -0700, Jingyi Wang wrote:
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> 
> Include PMIC files used on Kaanapali MTP boards. Add configurations for
> keys (volume up and volume down), RGB LEDs and flash LEDs.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 92 ++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index bc57935c042c..5054c5933687 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -5,9 +5,21 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/leds/common.h>
>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>  #include "kaanapali.dtsi"
>  
> +#include "pm8010-kaanapali.dtsi"     /* SPMI1: SID-12/13   */
> +#include "pmd8028-kaanapali.dtsi"    /* SPMI1: SID-4       */
> +#include "pmh0101.dtsi"              /* SPMI0: SID-1       */
> +#include "pmh0104-kaanapali.dtsi"    /* SPMI1: SID-9       */
> +#include "pmh0110-kaanapali.dtsi"    /* SPMI0: SID-3/5/6/8 */
> +#include "pmih0108-kaanapali.dtsi"   /* SPMI1: SID-7       */
> +#include "pmk8850.dtsi"              /* SPMI0: SID-0       */
> +#include "pmr735d-kaanapali.dtsi"    /* SPMI1: SID-10      */
> +
>  / {
>  	model = "Qualcomm Technologies, Inc. Kaanapali MTP";
>  	compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
> @@ -53,6 +65,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
>  		};
>  	};
>  
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		pinctrl-0 = <&key_vol_up_default>;
> +		pinctrl-names = "default";
> +
> +		key-volume-up {
> +			label = "Volume Up";
> +			linux,code = <KEY_VOLUMEUP>;
> +			gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <15>;
> +			linux,can-disable;
> +			wakeup-source;
> +		};
> +	};
> +

This is not related to PMICs (and doesn't use PMIC gpios).

>  	sound {
>  		compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
>  		model = "Kaanapali-MTP";

-- 
With best wishes
Dmitry

Re: [PATCH 2/6] arm64: dts: qcom: kaanapali-mtp: Add PMIC support

[Jishnu Prakash]

Hi Dmitry,

On 3/24/2026 6:43 AM, Dmitry Baryshkov wrote:
> On Sun, Mar 22, 2026 at 11:19:42PM -0700, Jingyi Wang wrote:
>> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>
>> Include PMIC files used on Kaanapali MTP boards. Add configurations for
>> keys (volume up and volume down), RGB LEDs and flash LEDs.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>

...

>>  	};
>>  
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +
>> +		pinctrl-0 = <&key_vol_up_default>;
>> +		pinctrl-names = "default";
>> +
>> +		key-volume-up {
>> +			label = "Volume Up";
>> +			linux,code = <KEY_VOLUMEUP>;
>> +			gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
>> +			debounce-interval = <15>;
>> +			linux,can-disable;
>> +			wakeup-source;
>> +		};
>> +	};
>> +
> 
> This is not related to PMICs (and doesn't use PMIC gpios).

Usually volume up and down pins are both under PMIC, and it seems best to enable them together,
so we end up enabling these in PMIC patches.

Since this patch is already applied, maybe in the future, we'll add them under the main board
enablement patches, or perhaps should there be a separate patch for input pins ?

Thanks,
Jishnu

> 
>>  	sound {
>>  		compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
>>  		model = "Kaanapali-MTP";
> 

[PATCH 3/6] arm64: dts: qcom: kaanapali-qrd: Add PMIC support

[Jingyi Wang]

From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>

Include PMIC files used on Kaanapali QRD boards. Add configurations for
keys (volume up and volume down), RGB LEDs and flash LEDs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 92 ++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
index 32034eed03eb..da0e8f9091c3 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
@@ -5,9 +5,21 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "kaanapali.dtsi"
 
+#include "pm8010-kaanapali.dtsi"     /* SPMI1: SID-12/13   */
+#include "pmd8028-kaanapali.dtsi"    /* SPMI1: SID-4       */
+#include "pmh0101.dtsi"              /* SPMI0: SID-1       */
+#include "pmh0104-kaanapali.dtsi"    /* SPMI1: SID-9       */
+#include "pmh0110-kaanapali.dtsi"    /* SPMI0: SID-3/5/6/8 */
+#include "pmih0108-kaanapali.dtsi"   /* SPMI1: SID-7       */
+#include "pmk8850.dtsi"              /* SPMI0: SID-0       */
+#include "pmr735d-kaanapali.dtsi"    /* SPMI1: SID-10      */
+
 / {
 	model = "Qualcomm Technologies, Inc. Kaanapali QRD";
 	compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
@@ -52,6 +64,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
 			clock-div = <2>;
 		};
 	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_vol_up_default>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
 };
 
 &apps_rsc {
@@ -665,6 +693,63 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&pmh0101_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		function-enumerator = <0>;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		function-enumerator = <1>;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+	};
+};
+
+&pmh0101_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
 &sdhc_2 {
 	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
 
@@ -701,6 +786,13 @@ &tlmm {
 			       <74 1>, /* eSE */
 			       <119 2>, /* SoCCP */
 			       <144 4>; /* CXM UART */
+
+	key_vol_up_default: key-vol-up-default-state {
+		pins = "gpio101";
+		function = "gpio";
+		output-disable;
+		bias-pull-up;
+	};
 };
 
 &uart7 {

-- 
2.25.1

Re: [PATCH 3/6] arm64: dts: qcom: kaanapali-qrd: Add PMIC support

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:43PM -0700, Jingyi Wang wrote:
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> 
> Include PMIC files used on Kaanapali QRD boards. Add configurations for
> keys (volume up and volume down), RGB LEDs and flash LEDs.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 92 ++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> index 32034eed03eb..da0e8f9091c3 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> @@ -5,9 +5,21 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/leds/common.h>
>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>  #include "kaanapali.dtsi"
>  
> +#include "pm8010-kaanapali.dtsi"     /* SPMI1: SID-12/13   */
> +#include "pmd8028-kaanapali.dtsi"    /* SPMI1: SID-4       */
> +#include "pmh0101.dtsi"              /* SPMI0: SID-1       */
> +#include "pmh0104-kaanapali.dtsi"    /* SPMI1: SID-9       */
> +#include "pmh0110-kaanapali.dtsi"    /* SPMI0: SID-3/5/6/8 */
> +#include "pmih0108-kaanapali.dtsi"   /* SPMI1: SID-7       */
> +#include "pmk8850.dtsi"              /* SPMI0: SID-0       */
> +#include "pmr735d-kaanapali.dtsi"    /* SPMI1: SID-10      */
> +
>  / {
>  	model = "Qualcomm Technologies, Inc. Kaanapali QRD";
>  	compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
> @@ -52,6 +64,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
>  			clock-div = <2>;
>  		};
>  	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		pinctrl-0 = <&key_vol_up_default>;
> +		pinctrl-names = "default";
> +
> +		key-volume-up {
> +			label = "Volume Up";
> +			linux,code = <KEY_VOLUMEUP>;
> +			gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <15>;
> +			linux,can-disable;
> +			wakeup-source;
> +		};
> +	};

Again, this is not related to PMICs.

>  };
>  
>  &apps_rsc {

-- 
With best wishes
Dmitry

[PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Jingyi Wang]

From: Zijun Hu <zijun.hu@oss.qualcomm.com>

Enable bluetooth WCN785x and Wi-Fi on Kaanapali MTP board.

Co-developed-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
Signed-off-by: Zijun Hu <zijun.hu@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 121 +++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 5054c5933687..d0f3909621c9 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -27,6 +27,7 @@ / {
 
 	aliases {
 		serial0 = &uart7;
+		serial1 = &uart18;
 	};
 
 	chosen {
@@ -189,6 +190,68 @@ wcd939x: audio-codec {
 
 		#sound-dai-cells = <1>;
 	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
+		pinctrl-names = "default";
+
+		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
+		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&vreg_s2j_0p8>;
+		vddio-supply = <&vreg_l2g_1p8>;
+		vddio1p2-supply = <&vreg_l3g_1p2>;
+		vddaon-supply = <&vreg_s7g_0p9>;
+		vdddig-supply = <&vreg_s1j_0p8>;
+		vddrfa1p2-supply = <&vreg_s7f_1p2>;
+		vddrfa1p8-supply = <&vreg_s8f_1p8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -827,6 +890,21 @@ &pcie0_phy {
 &pcie_port0 {
 	wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
 	reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
 };
 
 &pmh0101_flash {
@@ -880,6 +958,18 @@ led@3 {
 	};
 };
 
+&pmh0104_j_e1_gpios {
+	bt_default: bt-default-state {
+		pins = "gpio5";
+		function = "normal";
+		input-disable;
+		output-enable;
+		output-low;
+		bias-disable;
+		power-source = <1>;
+	};
+};
+
 &pon_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 
@@ -1011,6 +1101,19 @@ &tlmm {
 			       <119 2>, /* SoCCP */
 			       <144 4>; /* CXM UART */
 
+	wlan_en: wlan-en-state {
+		pins = "gpio16";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	sw_ctrl_default: sw-ctrl-default-state {
+		pins = "gpio18";
+		function = "gpio";
+		bias-pull-down;
+	};
+
 	spkr_0_sd_n_active: spkr-0-sd-n-active-state {
 		pins = "gpio76";
 		function = "gpio";
@@ -1067,6 +1170,24 @@ &uart7 {
 	status = "okay";
 };
 
+&uart18 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+		max-speed = <3200000>;
+	};
+};
+
 &ufs_mem_hc {
 	reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
 

-- 
2.25.1

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:44PM -0700, Jingyi Wang wrote:
> From: Zijun Hu <zijun.hu@oss.qualcomm.com>
> 
> Enable bluetooth WCN785x and Wi-Fi on Kaanapali MTP board.
> 
> Co-developed-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
> Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
> Signed-off-by: Zijun Hu <zijun.hu@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 121 +++++++++++++++++++++++++++++
>  1 file changed, 121 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index 5054c5933687..d0f3909621c9 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -27,6 +27,7 @@ / {
>  
>  	aliases {
>  		serial0 = &uart7;
> +		serial1 = &uart18;
>  	};
>  
>  	chosen {
> @@ -189,6 +190,68 @@ wcd939x: audio-codec {
>  
>  		#sound-dai-cells = <1>;
>  	};
> +
> +	wcn7850-pmu {
> +		compatible = "qcom,wcn7850-pmu";
> +
> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> +		pinctrl-names = "default";
> +
> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;

swctrl-gpios?

> +
> +		vdd-supply = <&vreg_s2j_0p8>;
> +		vddio-supply = <&vreg_l2g_1p8>;
> +		vddio1p2-supply = <&vreg_l3g_1p2>;
> +		vddaon-supply = <&vreg_s7g_0p9>;
> +		vdddig-supply = <&vreg_s1j_0p8>;
> +		vddrfa1p2-supply = <&vreg_s7f_1p2>;
> +		vddrfa1p8-supply = <&vreg_s8f_1p8>;
> +
> +		clocks = <&rpmhcc RPMH_RF_CLK1>;
> +

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
>> +
>> +	wcn7850-pmu {
>> +		compatible = "qcom,wcn7850-pmu";
>> +
>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
>> +		pinctrl-names = "default";
>> +
>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> swctrl-gpios?

it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
the input pin is not used by power sequencing driver.
just give it some default configurations here.

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
> >> +
> >> +	wcn7850-pmu {
> >> +		compatible = "qcom,wcn7850-pmu";
> >> +
> >> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> >> +		pinctrl-names = "default";
> >> +
> >> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> >> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> > swctrl-gpios?
> 
> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
> the input pin is not used by power sequencing driver.
> just give it some default configurations here.

Please don't mix hardware description and the driver. If the pin is
wired, let's describe it in DT.

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
> On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
>> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
>>>> +
>>>> +	wcn7850-pmu {
>>>> +		compatible = "qcom,wcn7850-pmu";
>>>> +
>>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
>>>> +		pinctrl-names = "default";
>>>> +
>>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
>>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
>>> swctrl-gpios?
>>
>> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
>> the input pin is not used by power sequencing driver.
>> just give it some default configurations here.
> 
> Please don't mix hardware description and the driver. If the pin is
> wired, let's describe it in DT.
> 

give comments about that pin in this dts file ?
or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Wed, Mar 25, 2026 at 06:59:41PM +0800, Zijun Hu wrote:
> On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
> > On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
> >> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
> >>>> +
> >>>> +	wcn7850-pmu {
> >>>> +		compatible = "qcom,wcn7850-pmu";
> >>>> +
> >>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> >>>> +		pinctrl-names = "default";
> >>>> +
> >>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> >>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> >>> swctrl-gpios?
> >>
> >> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
> >> the input pin is not used by power sequencing driver.
> >> just give it some default configurations here.
> > 
> > Please don't mix hardware description and the driver. If the pin is
> > wired, let's describe it in DT.
> > 
> 
> give comments about that pin in this dts file ?
> or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?

It is there, as far as I remember.

$ grep swctrl Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
  swctrl-gpios:

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 3/25/2026 7:40 PM, Dmitry Baryshkov wrote:
>> On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
>>> On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
>>>> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
>>>>>> +
>>>>>> +	wcn7850-pmu {
>>>>>> +		compatible = "qcom,wcn7850-pmu";
>>>>>> +
>>>>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
>>>>>> +		pinctrl-names = "default";
>>>>>> +
>>>>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
>>>>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
>>>>> swctrl-gpios?
>>>> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
>>>> the input pin is not used by power sequencing driver.
>>>> just give it some default configurations here.
>>> Please don't mix hardware description and the driver. If the pin is
>>> wired, let's describe it in DT.
>>>
>> give comments about that pin in this dts file ?
>> or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?
> It is there, as far as I remember.
> 
> $ grep swctrl Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
>   swctrl-gpios:

swctrl-gpios may be not applicable for 'qcom,wcn7850-pmu' since there is no 'qcom,wcn7850-pmu' node
which configures 'swctrl-gpios' within upstream DT tree.

 

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Thu, Mar 26, 2026 at 11:19:27AM +0800, Zijun Hu wrote:
> On 3/25/2026 7:40 PM, Dmitry Baryshkov wrote:
> >> On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
> >>> On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
> >>>> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
> >>>>>> +
> >>>>>> +	wcn7850-pmu {
> >>>>>> +		compatible = "qcom,wcn7850-pmu";
> >>>>>> +
> >>>>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> >>>>>> +		pinctrl-names = "default";
> >>>>>> +
> >>>>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> >>>>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> >>>>> swctrl-gpios?
> >>>> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
> >>>> the input pin is not used by power sequencing driver.
> >>>> just give it some default configurations here.
> >>> Please don't mix hardware description and the driver. If the pin is
> >>> wired, let's describe it in DT.
> >>>
> >> give comments about that pin in this dts file ?
> >> or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?
> > It is there, as far as I remember.
> > 
> > $ grep swctrl Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
> >   swctrl-gpios:
> 
> swctrl-gpios may be not applicable for 'qcom,wcn7850-pmu' since there is no 'qcom,wcn7850-pmu' node
> which configures 'swctrl-gpios' within upstream DT tree.

It's a wrong way to check it.
Instead follow these steps:
- Is the pin defined in the datasheet?
- Is the pin defined in the schema?
- Is the pin wired in the hardware?

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 3/26/2026 12:10 PM, Dmitry Baryshkov wrote:
>> 3/25/2026 7:40 PM, Dmitry Baryshkov wrote:
>>>> On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
>>>>> On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
>>>>>> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
>>>>>>>> +
>>>>>>>> +	wcn7850-pmu {
>>>>>>>> +		compatible = "qcom,wcn7850-pmu";
>>>>>>>> +
>>>>>>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
>>>>>>>> +		pinctrl-names = "default";
>>>>>>>> +
>>>>>>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
>>>>>>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
>>>>>>> swctrl-gpios?
>>>>>> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
>>>>>> the input pin is not used by power sequencing driver.
>>>>>> just give it some default configurations here.
>>>>> Please don't mix hardware description and the driver. If the pin is
>>>>> wired, let's describe it in DT.
>>>>>
>>>> give comments about that pin in this dts file ?
>>>> or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?
>>> It is there, as far as I remember.
>>>
>>> $ grep swctrl Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
>>>   swctrl-gpios:
>> swctrl-gpios may be not applicable for 'qcom,wcn7850-pmu' since there is no 'qcom,wcn7850-pmu' node
>> which configures 'swctrl-gpios' within upstream DT tree.
> It's a wrong way to check it.
> Instead follow these steps:
> - Is the pin defined in the datasheet?
datasheet define this pin SW_CTRL with description 
"Switch request to the external PMU between active and sleep mode"

> - Is the pin defined in the schema?

schema define property 'swctrl-gpios' with description
"GPIO line indicating the state of the clock supply to the BT module"

> - Is the pin wired in the hardware?
pin SW_CTRL is wired in hardware.

i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
which WCN7850 pin is 'swctrl-gpios' mean for ?
Why to introduce 'swctrl-gpios' ?
what problem does it solve ?
how to solve the problem ?

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Thu, Mar 26, 2026 at 01:15:44PM +0800, Zijun Hu wrote:
> On 3/26/2026 12:10 PM, Dmitry Baryshkov wrote:
> >> 3/25/2026 7:40 PM, Dmitry Baryshkov wrote:
> >>>> On 3/25/2026 3:08 PM, Dmitry Baryshkov wrote:
> >>>>> On Wed, Mar 25, 2026 at 02:40:19PM +0800, Zijun Hu wrote:
> >>>>>> On 3/24/2026 9:16 AM, Dmitry Baryshkov wrote:
> >>>>>>>> +
> >>>>>>>> +	wcn7850-pmu {
> >>>>>>>> +		compatible = "qcom,wcn7850-pmu";
> >>>>>>>> +
> >>>>>>>> +		pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> >>>>>>>> +		pinctrl-names = "default";
> >>>>>>>> +
> >>>>>>>> +		bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> >>>>>>>> +		wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> >>>>>>> swctrl-gpios?
> >>>>>> it is '<&sw_ctrl_default>' within 'pinctrl-0' above.
> >>>>>> the input pin is not used by power sequencing driver.
> >>>>>> just give it some default configurations here.
> >>>>> Please don't mix hardware description and the driver. If the pin is
> >>>>> wired, let's describe it in DT.
> >>>>>
> >>>> give comments about that pin in this dts file ?
> >>>> or give a seperated patch to describe the pin in DT binding schema of "qcom,wcn7850-pmu"?
> >>> It is there, as far as I remember.
> >>>
> >>> $ grep swctrl Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
> >>>   swctrl-gpios:
> >> swctrl-gpios may be not applicable for 'qcom,wcn7850-pmu' since there is no 'qcom,wcn7850-pmu' node
> >> which configures 'swctrl-gpios' within upstream DT tree.
> > It's a wrong way to check it.
> > Instead follow these steps:
> > - Is the pin defined in the datasheet?
> datasheet define this pin SW_CTRL with description 
> "Switch request to the external PMU between active and sleep mode"
> 
> > - Is the pin defined in the schema?
> 
> schema define property 'swctrl-gpios' with description
> "GPIO line indicating the state of the clock supply to the BT module"
> 
> > - Is the pin wired in the hardware?
> pin SW_CTRL is wired in hardware.

Granted your three answers, it can and should be described in the DT.

> 
> i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
> which WCN7850 pin is 'swctrl-gpios' mean for ?
> Why to introduce 'swctrl-gpios' ?
> what problem does it solve ?
> how to solve the problem ?

Please descibe the hardware in the DT. Problem solving belongs to the
driver.

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 3/30/2026 7:53 PM, Dmitry Baryshkov wrote:
>>> - Is the pin defined in the schema?
>> schema define property 'swctrl-gpios' with description
>> "GPIO line indicating the state of the clock supply to the BT module"
>>
>>> - Is the pin wired in the hardware?
>> pin SW_CTRL is wired in hardware.
> Granted your three answers, it can and should be described in the DT.
> 
>> i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
>> which WCN7850 pin is 'swctrl-gpios' mean for ?
>> Why to introduce 'swctrl-gpios' ?
>> what problem does it solve ?
>> how to solve the problem ?
> Please descibe the hardware in the DT. Problem solving belongs to the
> driver.

sorry for not agreeing with your points here.

it is better to correct or remove 'swctrl-gpios' within DT binding spec at least
for 'qcom,wcn7850-pmu' with below reasons:

1) provided that 'swctrl-gpios' is for pin SW_CTRL of datasheet, binding spec's
   both description and its expected usage are wrong.
2) its driver does not parse and use the property 'swctrl-gpios', moreover, the
   property have no user within upstream DT tree.
3) the property is not mandatory based on binding spec.
4) upstream DT tree have had many such usages as mine which just set default pin
   configuration and not specify 'swctrl-gpios' explicitly.
5) kaanapali-mtp is originally preinstalled with android OS which supports some
   qualcomm specific feature which have not been supported by up-stream kernel.
   so kaanapali-mtp H/W has some wired pins which is not used by up-stream 
   kernel sometimes

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Wed, Apr 01, 2026 at 06:39:19PM +0800, Zijun Hu wrote:
> On 3/30/2026 7:53 PM, Dmitry Baryshkov wrote:
> >>> - Is the pin defined in the schema?
> >> schema define property 'swctrl-gpios' with description
> >> "GPIO line indicating the state of the clock supply to the BT module"
> >>
> >>> - Is the pin wired in the hardware?
> >> pin SW_CTRL is wired in hardware.
> > Granted your three answers, it can and should be described in the DT.
> > 
> >> i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
> >> which WCN7850 pin is 'swctrl-gpios' mean for ?
> >> Why to introduce 'swctrl-gpios' ?
> >> what problem does it solve ?
> >> how to solve the problem ?
> > Please descibe the hardware in the DT. Problem solving belongs to the
> > driver.
> 
> sorry for not agreeing with your points here.
> 
> it is better to correct or remove 'swctrl-gpios' within DT binding spec at least
> for 'qcom,wcn7850-pmu' with below reasons:
> 
> 1) provided that 'swctrl-gpios' is for pin SW_CTRL of datasheet, binding spec's
>    both description and its expected usage are wrong.

Please correct it.

> 2) its driver does not parse and use the property 'swctrl-gpios', moreover, the
>    property have no user within upstream DT tree.

There is no "driver" in the "DT bindings"

> 3) the property is not mandatory based on binding spec.

Which is expected, because on some platforms it might be not wired up
and on the other platforms the pin to which it is wired to might be
unknown (think about all the phones for which the community doesn't have
schematics).

> 4) upstream DT tree have had many such usages as mine which just set default pin
>    configuration and not specify 'swctrl-gpios' explicitly.

I don't understand this part.

> 5) kaanapali-mtp is originally preinstalled with android OS which supports some
>    qualcomm specific feature which have not been supported by up-stream kernel.
>    so kaanapali-mtp H/W has some wired pins which is not used by up-stream 
>    kernel sometimes

Again, what does that have to do with the hardware description?

-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 4/1/2026 7:08 PM, Dmitry Baryshkov wrote:
>>>>> - Is the pin wired in the hardware?
>>>> pin SW_CTRL is wired in hardware.
>>> Granted your three answers, it can and should be described in the DT.
>>>
>>>> i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
>>>> which WCN7850 pin is 'swctrl-gpios' mean for ?
>>>> Why to introduce 'swctrl-gpios' ?
>>>> what problem does it solve ?
>>>> how to solve the problem ?
>>> Please descibe the hardware in the DT. Problem solving belongs to the
>>> driver.
>> sorry for not agreeing with your points here.
>>
>> it is better to correct or remove 'swctrl-gpios' within DT binding spec at least
>> for 'qcom,wcn7850-pmu' with below reasons:
>>
>> 1) provided that 'swctrl-gpios' is for pin SW_CTRL of datasheet, binding spec's
>>    both description and its expected usage are wrong.
> Please correct it.
> 
>> 2) its driver does not parse and use the property 'swctrl-gpios', moreover, the
>>    property have no user within upstream DT tree.
> There is no "driver" in the "DT bindings"
> 

'its driver' i mean here is the driver which drives the device which is generated
by this DT node 'qcom,wcn7850-pmu'.
source code of the driver is drivers/power/sequencing/pwrseq-qcom-wcn.c

>> 3) the property is not mandatory based on binding spec.
> Which is expected, because on some platforms it might be not wired up
> and on the other platforms the pin to which it is wired to might be
> unknown (think about all the phones for which the community doesn't have
> schematics).
> 

got your points and will explain mine at below 2) together.

>> 4) upstream DT tree have had many such usages as mine which just set default pin
>>    configuration and not specify 'swctrl-gpios' explicitly.
> I don't understand this part.
> 

For DT node 'qcom,wcn7850-pmu' of products identified by the following dts file at least:

wcn7850-pmu {
	compatible = "qcom,wcn7850-pmu";

        pinctrl-names = "default";   // config SW_CTRL pin default settings, but
        pinctrl-0 = ....;            // this DT node does not specify property 'swctrl-gpios'.
	....		
}


grep -l -r "qcom,wcn7850-pmu" arch/arm64/boot/dts/qcom/ | xargs grep -l -r "sw[_-]ctrl"
arch/arm64/boot/dts/qcom/sm8550-hdk.dts
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
arch/arm64/boot/dts/qcom/sm8750-mtp.dts
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
arch/arm64/boot/dts/qcom/sm8650-hdk.dts


>> 5) kaanapali-mtp is originally preinstalled with android OS which supports some
>>    qualcomm specific feature which have not been supported by up-stream kernel.
>>    so kaanapali-mtp H/W has some wired pins which is not used by up-stream 
>>    kernel sometimes
> Again, what does that have to do with the hardware description?

kaanapali-mtp hardware supports the feature pin SW_CTRL involved, but we can decide
not to enable the feature based on requirements.

any advise about how to correct DTS to not enable the feature SW_CTRL involved ?

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Dmitry Baryshkov]

On Wed, Apr 01, 2026 at 09:34:16PM +0800, Zijun Hu wrote:
> On 4/1/2026 7:08 PM, Dmitry Baryshkov wrote:
> >>>>> - Is the pin wired in the hardware?
> >>>> pin SW_CTRL is wired in hardware.
> >>> Granted your three answers, it can and should be described in the DT.
> >>>
> >>>> i have below confusions about 'swctrl-gpios' of 'qcom,wcn7850-pmu'
> >>>> which WCN7850 pin is 'swctrl-gpios' mean for ?
> >>>> Why to introduce 'swctrl-gpios' ?
> >>>> what problem does it solve ?
> >>>> how to solve the problem ?
> >>> Please descibe the hardware in the DT. Problem solving belongs to the
> >>> driver.
> >> sorry for not agreeing with your points here.
> >>
> >> it is better to correct or remove 'swctrl-gpios' within DT binding spec at least
> >> for 'qcom,wcn7850-pmu' with below reasons:
> >>
> >> 1) provided that 'swctrl-gpios' is for pin SW_CTRL of datasheet, binding spec's
> >>    both description and its expected usage are wrong.
> > Please correct it.
> > 
> >> 2) its driver does not parse and use the property 'swctrl-gpios', moreover, the
> >>    property have no user within upstream DT tree.
> > There is no "driver" in the "DT bindings"
> > 
> 
> 'its driver' i mean here is the driver which drives the device which is generated
> by this DT node 'qcom,wcn7850-pmu'.
> source code of the driver is drivers/power/sequencing/pwrseq-qcom-wcn.c

DT describes the hardware. The driver behaviour is not that relevant
here.

> 
> >> 3) the property is not mandatory based on binding spec.
> > Which is expected, because on some platforms it might be not wired up
> > and on the other platforms the pin to which it is wired to might be
> > unknown (think about all the phones for which the community doesn't have
> > schematics).
> > 
> 
> got your points and will explain mine at below 2) together.
> 
> >> 4) upstream DT tree have had many such usages as mine which just set default pin
> >>    configuration and not specify 'swctrl-gpios' explicitly.
> > I don't understand this part.
> > 
> 
> For DT node 'qcom,wcn7850-pmu' of products identified by the following dts file at least:
> 
> wcn7850-pmu {
> 	compatible = "qcom,wcn7850-pmu";
> 
>         pinctrl-names = "default";   // config SW_CTRL pin default settings, but
>         pinctrl-0 = ....;            // this DT node does not specify property 'swctrl-gpios'.
> 	....		
> }
> 
> 
> grep -l -r "qcom,wcn7850-pmu" arch/arm64/boot/dts/qcom/ | xargs grep -l -r "sw[_-]ctrl"
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> arch/arm64/boot/dts/qcom/sm8650-qrd.dts
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> arch/arm64/boot/dts/qcom/sm8650-hdk.dts

So, let's fix them too.

> >> 5) kaanapali-mtp is originally preinstalled with android OS which supports some
> >>    qualcomm specific feature which have not been supported by up-stream kernel.
> >>    so kaanapali-mtp H/W has some wired pins which is not used by up-stream 
> >>    kernel sometimes
> > Again, what does that have to do with the hardware description?
> 
> kaanapali-mtp hardware supports the feature pin SW_CTRL involved, but we can decide
> not to enable the feature based on requirements.
> 
> any advise about how to correct DTS to not enable the feature SW_CTRL involved ?

You can enable or disable something in the driver. It doesn't change the
way the chip is wired (that's what DT describes).


-- 
With best wishes
Dmitry

Re: [PATCH 4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi

[Zijun Hu]

On 4/1/2026 10:07 PM, Dmitry Baryshkov wrote:
>>>> 2) its driver does not parse and use the property 'swctrl-gpios', moreover, the
>>>>    property have no user within upstream DT tree.
>>> There is no "driver" in the "DT bindings"
>>>
>> 'its driver' i mean here is the driver which drives the device which is generated
>> by this DT node 'qcom,wcn7850-pmu'.
>> source code of the driver is drivers/power/sequencing/pwrseq-qcom-wcn.c
> DT describes the hardware. The driver behaviour is not that relevant
> here.

agree with your opinion which is right (^^)

> 
>>>> 3) the property is not mandatory based on binding spec.
>>> Which is expected, because on some platforms it might be not wired up
>>> and on the other platforms the pin to which it is wired to might be
>>> unknown (think about all the phones for which the community doesn't have
>>> schematics).
>>>
>> got your points and will explain mine at below 2) together.
>>
>>>> 4) upstream DT tree have had many such usages as mine which just set default pin
>>>>    configuration and not specify 'swctrl-gpios' explicitly.
>>> I don't understand this part.
>>>
>> For DT node 'qcom,wcn7850-pmu' of products identified by the following dts file at least:
>>
>> wcn7850-pmu {
>> 	compatible = "qcom,wcn7850-pmu";
>>
>>         pinctrl-names = "default";   // config SW_CTRL pin default settings, but
>>         pinctrl-0 = ....;            // this DT node does not specify property 'swctrl-gpios'.
>> 	....		
>> }
>>
>>
>> grep -l -r "qcom,wcn7850-pmu" arch/arm64/boot/dts/qcom/ | xargs grep -l -r "sw[_-]ctrl"
>> arch/arm64/boot/dts/qcom/sm8550-hdk.dts
>> arch/arm64/boot/dts/qcom/sm8650-qrd.dts
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
>> arch/arm64/boot/dts/qcom/sm8550-qrd.dts
>> arch/arm64/boot/dts/qcom/sm8650-hdk.dts
> So, let's fix them too.
> 
perhaps. also fix for kaanapali-mtp whose DT have gone into linux-next.
BTW, there may be other 'qcom,wcnxxxx-pmu' which have the same problem to fix besides
'qcom,wcn7850-pmu'.

>>>> 5) kaanapali-mtp is originally preinstalled with android OS which supports some
>>>>    qualcomm specific feature which have not been supported by up-stream kernel.
>>>>    so kaanapali-mtp H/W has some wired pins which is not used by up-stream 
>>>>    kernel sometimes
>>> Again, what does that have to do with the hardware description?
>> kaanapali-mtp hardware supports the feature pin SW_CTRL involved, but we can decide
>> not to enable the feature based on requirements.
>>
>> any advise about how to correct DTS to not enable the feature SW_CTRL involved ?
> You can enable or disable something in the driver. It doesn't change the
> way the chip is wired (that's what DT describes).

got it. thank you. (^^)

[PATCH 5/6] arm64: dts: qcom: kaanapali: add display hardware devices

[Jingyi Wang]

From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>

Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers
are not included.

Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 242 +++++++++++++++++++++++++++++++-
 1 file changed, 240 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index f0de06b2c20b..bf3c6eb496e1 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
 #include <dt-bindings/clock/qcom,kaanapali-camcc.h>
 #include <dt-bindings/clock/qcom,kaanapali-dispcc.h>
@@ -3156,6 +3157,243 @@ camcc: clock-controller@956d000 {
 			#power-domain-cells = <1>;
 		};
 
+		mdss: display-subsystem@9800000 {
+			compatible = "qcom,kaanapali-mdss";
+			reg = <0x0 0x09800000 0x0 0x1000>;
+			reg-names = "mdss";
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&gcc GCC_DISP_HF_AXI_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+				 <&dispcc DISP_CC_MDSS_AHB_SWI_CLK>;
+			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "mdp0-mem",
+					     "cpu-cfg";
+
+			power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+
+			iommus = <&apps_smmu 0x800 0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			mdss_mdp: display-controller@9801000 {
+				compatible = "qcom,kaanapali-dpu";
+				reg = <0x0 0x09801000 0x0 0x1c8000>,
+				      <0x0 0x09b16000 0x0 0x3000>;
+				reg-names = "mdp",
+					    "vbif";
+
+				interrupts-extended = <&mdss 0>;
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "nrt_bus",
+					      "iface",
+					      "lut",
+					      "core",
+					      "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&mdp_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						dpu_intf2_out: endpoint {
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						dpu_intf0_out: endpoint {
+						};
+					};
+				};
+
+				mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-156000000 {
+						opp-hz = /bits/ 64 <156000000>;
+						required-opps = <&rpmhpd_opp_low_svs_d1>;
+					};
+
+					opp-207000000 {
+						opp-hz = /bits/ 64 <207000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-337000000 {
+						opp-hz = /bits/ 64 <337000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-417000000 {
+						opp-hz = /bits/ 64 <417000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-532000000 {
+						opp-hz = /bits/ 64 <532000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+
+					opp-600000000 {
+						opp-hz = /bits/ 64 <600000000>;
+						required-opps = <&rpmhpd_opp_nom_l1>;
+					};
+
+					opp-650000000 {
+						opp-hz = /bits/ 64 <650000000>;
+						required-opps = <&rpmhpd_opp_turbo>;
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@9ac0000 {
+				compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+				reg = <0x0 0x09ac0000 0x0 0x1000>;
+				reg-names = "dsi_ctrl";
+
+				interrupts-extended = <&mdss 4>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+					 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+					 <&dispcc DISP_CC_ESYNC0_CLK>,
+					 <&dispcc DISP_CC_OSC_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus",
+					      "dsi_pll_pixel",
+					      "dsi_pll_byte",
+					      "esync",
+					      "osc",
+					      "byte_src",
+					      "pixel_src";
+
+				operating-points-v2 = <&mdss_dsi_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				phys = <&mdss_dsi0_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+
+				mdss_dsi_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmhpd_opp_low_svs_d1>;
+					};
+
+					opp-250000000 {
+						opp-hz = /bits/ 64 <250000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-312500000 {
+						opp-hz = /bits/ 64 <312500000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-358000000 {
+						opp-hz = /bits/ 64 <358000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@9ac1000 {
+				compatible = "qcom,kaanapali-dsi-phy-3nm";
+				reg = <0x0 0x09ac1000 0x0 0x1cc>,
+				      <0x0 0x09ac1200 0x0 0x280>,
+				      <0x0 0x09ac1500 0x0 0x400>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface",
+					      "ref";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
 		dispcc: clock-controller@9ba2000 {
 			compatible = "qcom,kaanapali-dispcc";
 			reg = <0x0 0x09ba2000 0x0 0x20000>;
@@ -3171,8 +3409,8 @@ dispcc: clock-controller@9ba2000 {
 				 <0>,
 				 <0>,
 				 <0>,
-				 <0>,
-				 <0>,
+				 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+				 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
 				 <0>,
 				 <0>;
 

-- 
2.25.1

Re: [PATCH 5/6] arm64: dts: qcom: kaanapali: add display hardware devices

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:45PM -0700, Jingyi Wang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> 
> Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers
> are not included.

Why?

> 
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 242 +++++++++++++++++++++++++++++++-
>  1 file changed, 240 insertions(+), 2 deletions(-)
> 
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						dpu_intf1_out: endpoint {
> +							remote-endpoint = <&mdss_dsi0_in>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						dpu_intf2_out: endpoint {

Missing DSI1. Please add it back.

> +						};
> +					};
> +
> +					port@2 {
> +						reg = <2>;
> +
> +						dpu_intf0_out: endpoint {
> +						};
> +					};
> +				};
> +

-- 
With best wishes
Dmitry

Re: [PATCH 5/6] arm64: dts: qcom: kaanapali: add display hardware devices

[yuanjiey]

On Tue, Mar 24, 2026 at 03:20:15AM +0200, Dmitry Baryshkov wrote:
> On Sun, Mar 22, 2026 at 11:19:45PM -0700, Jingyi Wang wrote:
> > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > 
> > Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers
> > are not included.
> 
> Why?

DP driver is not ready.

 
> > 
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 242 +++++++++++++++++++++++++++++++-
> >  1 file changed, 240 insertions(+), 2 deletions(-)
> > 
> > +
> > +				ports {
> > +					#address-cells = <1>;
> > +					#size-cells = <0>;
> > +
> > +					port@0 {
> > +						reg = <0>;
> > +
> > +						dpu_intf1_out: endpoint {
> > +							remote-endpoint = <&mdss_dsi0_in>;
> > +						};
> > +					};
> > +
> > +					port@1 {
> > +						reg = <1>;
> > +
> > +						dpu_intf2_out: endpoint {
> 
> Missing DSI1. Please add it back.
OK, will add it.

Thanks,
Yuanjie

> > +						};
> > +					};
> > +
> > +					port@2 {
> > +						reg = <2>;
> > +
> > +						dpu_intf0_out: endpoint {
> > +						};
> > +					};
> > +				};
> > +
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH 5/6] arm64: dts: qcom: kaanapali: add display hardware devices

[Dmitry Baryshkov]

On Thu, Mar 26, 2026 at 10:37:24AM +0800, yuanjiey wrote:
> On Tue, Mar 24, 2026 at 03:20:15AM +0200, Dmitry Baryshkov wrote:
> > On Sun, Mar 22, 2026 at 11:19:45PM -0700, Jingyi Wang wrote:
> > > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > 
> > > Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers
> > > are not included.
> > 
> > Why?
> 
> DP driver is not ready.

=> commit message.

> 
>  
> > > 
> > > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>

-- 
With best wishes
Dmitry

[PATCH 6/6] arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices

[Jingyi Wang]

From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>

Enable MDSS/DPU/DSI0 and add Novatek NT37801 panel on Kaanapali MTP
board.

NT37801 Spec V1.0 chapter "5.7.1 Power On Sequence" states VDDI ranges
1.65V~1.95V, but ldo12 ranges 1.2V~1.8V, so change ldo12 range to
1.65V~1.8V.

pmh0110_d_e0_gpios and pmh0110_f_e0_gpios are configured for
level shifters. Kaanapali need configure these pinctrl for panel
function.

Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 118 ++++++++++++++++++++++++++++-
 1 file changed, 117 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index d0f3909621c9..07247dc98b70 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -375,7 +375,7 @@ vreg_l11b_1p0: ldo11 {
 
 		vreg_l12b_1p8: ldo12 {
 			regulator-name = "vreg_l12b_1p8";
-			regulator-min-microvolt = <1200000>;
+			regulator-min-microvolt = <1650000>;
 			regulator-max-microvolt = <1800000>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
 			regulator-allow-set-load;
@@ -873,6 +873,51 @@ &lpass_vamacro {
 	qcom,dmic-sample-rate = <4800000>;
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&vreg_l1d_1p2>;
+	status = "okay";
+
+	panel@0 {
+		compatible = "novatek,nt37801";
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend
+			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
+			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
+		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend
+			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
+			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
+		pinctrl-names = "default", "sleep";
+
+		vci-supply = <&vreg_l13b_3p0>;
+		vdd-supply = <&vreg_l11b_1p0>;
+		vddio-supply = <&vreg_l12b_1p8>;
+
+		reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&panel0_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	vdds-supply = <&vreg_l3d_0p8>;
+
+	status = "okay";
+};
+
 &pcie0 {
 	pinctrl-0 = <&pcie0_default_state>;
 	pinctrl-names = "default";
@@ -970,6 +1015,42 @@ bt_default: bt-default-state {
 	};
 };
 
+&pmh0110_d_e0_gpios {
+	sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state {
+		pins = "gpio9";
+		function = "paired";
+		input-disable;
+		output-enable;
+		power-source = <2>; /* 1.2v */
+	};
+
+	sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state {
+		pins = "gpio10";
+		function = "paired";
+		input-enable;
+		output-disable;
+		power-source = <1>; /* 1.8v */
+	};
+};
+
+&pmh0110_f_e0_gpios {
+	sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state {
+		pins = "gpio9";
+		function = "paired";
+		input-enable;
+		output-disable;
+		power-source = <2>; /* 1.2v */
+	};
+
+	sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state {
+		pins = "gpio10";
+		function = "paired";
+		input-disable;
+		output-enable;
+		power-source = <1>; /* 1.8v */
+	};
+};
+
 &pon_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 
@@ -1128,6 +1209,41 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
 		bias-disable;
 	};
 
+	sde_te_active: sde-te-active-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_suspend: sde-te-suspend-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_esync0_suspend: sde-esync0-suspend-state {
+		pins = "gpio88";
+		function = "mdp_esync0_out";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_dsi_active: sde-dsi-active-state {
+		pins = "gpio98";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	sde_dsi_suspend: sde-dsi-suspend-state {
+		pins = "gpio98";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	key_vol_up_default: key-vol-up-default-state {
 		pins = "gpio101";
 		function = "gpio";

-- 
2.25.1

Re: [PATCH 6/6] arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices

[Dmitry Baryshkov]

On Sun, Mar 22, 2026 at 11:19:46PM -0700, Jingyi Wang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> 
> Enable MDSS/DPU/DSI0 and add Novatek NT37801 panel on Kaanapali MTP
> board.
> 
> NT37801 Spec V1.0 chapter "5.7.1 Power On Sequence" states VDDI ranges
> 1.65V~1.95V, but ldo12 ranges 1.2V~1.8V, so change ldo12 range to
> 1.65V~1.8V.
> 
> pmh0110_d_e0_gpios and pmh0110_f_e0_gpios are configured for
> level shifters. Kaanapali need configure these pinctrl for panel
> function.
> 
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 118 ++++++++++++++++++++++++++++-
>  1 file changed, 117 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index d0f3909621c9..07247dc98b70 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -375,7 +375,7 @@ vreg_l11b_1p0: ldo11 {
>  
>  		vreg_l12b_1p8: ldo12 {
>  			regulator-name = "vreg_l12b_1p8";
> -			regulator-min-microvolt = <1200000>;
> +			regulator-min-microvolt = <1650000>;

Separate commit, Fixes tag.

>  			regulator-max-microvolt = <1800000>;
>  			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
>  			regulator-allow-set-load;
> @@ -873,6 +873,51 @@ &lpass_vamacro {
>  	qcom,dmic-sample-rate = <4800000>;
>  };
>  
> +&mdss {
> +	status = "okay";
> +};
> +
> +&mdss_dsi0 {
> +	vdda-supply = <&vreg_l1d_1p2>;
> +	status = "okay";
> +
> +	panel@0 {
> +		compatible = "novatek,nt37801";
> +		reg = <0>;
> +
> +		pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend

Why is this esync0_suspend?

> +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> +		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend
> +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> +		pinctrl-names = "default", "sleep";
> +
> +		vci-supply = <&vreg_l13b_3p0>;
> +		vdd-supply = <&vreg_l11b_1p0>;
> +		vddio-supply = <&vreg_l12b_1p8>;
> +
> +		reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
> +
> +		port {
> +			panel0_in: endpoint {
> +				remote-endpoint = <&mdss_dsi0_out>;
> +			};
> +		};
> +	};
> +};
> +
> +&mdss_dsi0_out {
> +	remote-endpoint = <&panel0_in>;
> +	data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> +	vdds-supply = <&vreg_l3d_0p8>;
> +
> +	status = "okay";
> +};
> +
>  &pcie0 {
>  	pinctrl-0 = <&pcie0_default_state>;
>  	pinctrl-names = "default";
> @@ -970,6 +1015,42 @@ bt_default: bt-default-state {
>  	};
>  };
>  
> +&pmh0110_d_e0_gpios {
> +	sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state {

If these are level shifters, should they be configured as a hog? Or
should they be modelled as regulators?

I'm not sure, how do we handle shifters and their supplies.

> +		pins = "gpio9";
> +		function = "paired";
> +		input-disable;
> +		output-enable;
> +		power-source = <2>; /* 1.2v */
> +	};
> +
> +	sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state {
> +		pins = "gpio10";
> +		function = "paired";
> +		input-enable;
> +		output-disable;
> +		power-source = <1>; /* 1.8v */
> +	};
> +};
> +
> +&pmh0110_f_e0_gpios {
> +	sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state {

The same.

> +		pins = "gpio9";
> +		function = "paired";
> +		input-enable;
> +		output-disable;
> +		power-source = <2>; /* 1.2v */
> +	};
> +
> +	sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state {
> +		pins = "gpio10";
> +		function = "paired";
> +		input-disable;
> +		output-enable;
> +		power-source = <1>; /* 1.8v */
> +	};
> +};
> +
>  &pon_resin {
>  	linux,code = <KEY_VOLUMEDOWN>;
>  
> @@ -1128,6 +1209,41 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
>  		bias-disable;
>  	};
>  
> +	sde_te_active: sde-te-active-state {
> +		pins = "gpio86";
> +		function = "mdp_vsync";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
> +	sde_te_suspend: sde-te-suspend-state {
> +		pins = "gpio86";
> +		function = "mdp_vsync";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};

It's the same as _active. Merge them.

> +
> +	sde_esync0_suspend: sde-esync0-suspend-state {
> +		pins = "gpio88";
> +		function = "mdp_esync0_out";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
> +	sde_dsi_active: sde-dsi-active-state {

panel-reset-active-state

> +		pins = "gpio98";
> +		function = "gpio";
> +		drive-strength = <8>;
> +		bias-disable;
> +	};
> +
> +	sde_dsi_suspend: sde-dsi-suspend-state {
> +		pins = "gpio98";
> +		function = "gpio";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
>  	key_vol_up_default: key-vol-up-default-state {
>  		pins = "gpio101";
>  		function = "gpio";
> 
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH 6/6] arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices

[yuanjiey]

On Tue, Mar 24, 2026 at 03:25:49AM +0200, Dmitry Baryshkov wrote:
> On Sun, Mar 22, 2026 at 11:19:46PM -0700, Jingyi Wang wrote:
> > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > 
> > Enable MDSS/DPU/DSI0 and add Novatek NT37801 panel on Kaanapali MTP
> > board.
> > 
> > NT37801 Spec V1.0 chapter "5.7.1 Power On Sequence" states VDDI ranges
> > 1.65V~1.95V, but ldo12 ranges 1.2V~1.8V, so change ldo12 range to
> > 1.65V~1.8V.
> > 
> > pmh0110_d_e0_gpios and pmh0110_f_e0_gpios are configured for
> > level shifters. Kaanapali need configure these pinctrl for panel
> > function.
> > 
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 118 ++++++++++++++++++++++++++++-
> >  1 file changed, 117 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > index d0f3909621c9..07247dc98b70 100644
> > --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > @@ -375,7 +375,7 @@ vreg_l11b_1p0: ldo11 {
> >  
> >  		vreg_l12b_1p8: ldo12 {
> >  			regulator-name = "vreg_l12b_1p8";
> > -			regulator-min-microvolt = <1200000>;
> > +			regulator-min-microvolt = <1650000>;
> 
> Separate commit, Fixes tag.
> 
> >  			regulator-max-microvolt = <1800000>;
> >  			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> >  			regulator-allow-set-load;
> > @@ -873,6 +873,51 @@ &lpass_vamacro {
> >  	qcom,dmic-sample-rate = <4800000>;
> >  };
> >  
> > +&mdss {
> > +	status = "okay";
> > +};
> > +
> > +&mdss_dsi0 {
> > +	vdda-supply = <&vreg_l1d_1p2>;
> > +	status = "okay";
> > +
> > +	panel@0 {
> > +		compatible = "novatek,nt37801";
> > +		reg = <0>;
> > +
> > +		pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend
> 
> Why is this esync0_suspend?

I check downstream sde_esync0_suspend and sde_esync0_active is same config in kaanapali,
maybe I need rename a proper name for these pinctrl.

 
> > +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> > +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> > +		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend
> > +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> > +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> > +		pinctrl-names = "default", "sleep";
> > +
> > +		vci-supply = <&vreg_l13b_3p0>;
> > +		vdd-supply = <&vreg_l11b_1p0>;
> > +		vddio-supply = <&vreg_l12b_1p8>;
> > +
> > +		reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
> > +
> > +		port {
> > +			panel0_in: endpoint {
> > +				remote-endpoint = <&mdss_dsi0_out>;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +&mdss_dsi0_out {
> > +	remote-endpoint = <&panel0_in>;
> > +	data-lanes = <0 1 2 3>;
> > +};
> > +
> > +&mdss_dsi0_phy {
> > +	vdds-supply = <&vreg_l3d_0p8>;
> > +
> > +	status = "okay";
> > +};
> > +
> >  &pcie0 {
> >  	pinctrl-0 = <&pcie0_default_state>;
> >  	pinctrl-names = "default";
> > @@ -970,6 +1015,42 @@ bt_default: bt-default-state {
> >  	};
> >  };
> >  
> > +&pmh0110_d_e0_gpios {
> > +	sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state {
> 
> If these are level shifters, should they be configured as a hog? Or
> should they be modelled as regulators?
> 
> I'm not sure, how do we handle shifters and their supplies.

I think regulator-fixed is OK, but if change these pmh0110_d_e0_gpios
to regulator-fixed, means need to modify the panel driver to accept 
these changes, is that correct?

I see downstream also directly manipulates these paired GPIOs. 

> > +		pins = "gpio9";
> > +		function = "paired";
> > +		input-disable;
> > +		output-enable;
> > +		power-source = <2>; /* 1.2v */
> > +	};
> > +
> > +	sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state {
> > +		pins = "gpio10";
> > +		function = "paired";
> > +		input-enable;
> > +		output-disable;
> > +		power-source = <1>; /* 1.8v */
> > +	};
> > +};
> > +
> > +&pmh0110_f_e0_gpios {
> > +	sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state {
> 
> The same.
OK.
 
> > +		pins = "gpio9";
> > +		function = "paired";
> > +		input-enable;
> > +		output-disable;
> > +		power-source = <2>; /* 1.2v */
> > +	};
> > +
> > +	sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state {
> > +		pins = "gpio10";
> > +		function = "paired";
> > +		input-disable;
> > +		output-enable;
> > +		power-source = <1>; /* 1.8v */
> > +	};
> > +};
> > +
> >  &pon_resin {
> >  	linux,code = <KEY_VOLUMEDOWN>;
> >  
> > @@ -1128,6 +1209,41 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
> >  		bias-disable;
> >  	};
> >  
> > +	sde_te_active: sde-te-active-state {
> > +		pins = "gpio86";
> > +		function = "mdp_vsync";
> > +		drive-strength = <2>;
> > +		bias-pull-down;
> > +	};
> > +
> > +	sde_te_suspend: sde-te-suspend-state {
> > +		pins = "gpio86";
> > +		function = "mdp_vsync";
> > +		drive-strength = <2>;
> > +		bias-pull-down;
> > +	};
> 
> It's the same as _active. Merge them.
OK.

> > +
> > +	sde_esync0_suspend: sde-esync0-suspend-state {
> > +		pins = "gpio88";
> > +		function = "mdp_esync0_out";
> > +		drive-strength = <2>;
> > +		bias-pull-down;
> > +	};
> > +
> > +	sde_dsi_active: sde-dsi-active-state {
> 
> panel-reset-active-state

OK.
 
Thanks,
Yuanjie



> > +		pins = "gpio98";
> > +		function = "gpio";
> > +		drive-strength = <8>;
> > +		bias-disable;
> > +	};
> > +
> > +	sde_dsi_suspend: sde-dsi-suspend-state {
> > +		pins = "gpio98";
> > +		function = "gpio";
> > +		drive-strength = <2>;
> > +		bias-pull-down;
> > +	};
> > +
> >  	key_vol_up_default: key-vol-up-default-state {
> >  		pins = "gpio101";
> >  		function = "gpio";
> > 
> > -- 
> > 2.25.1
> > 
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH 6/6] arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices

[Dmitry Baryshkov]

On Thu, Mar 26, 2026 at 11:13:46AM +0800, yuanjiey wrote:
> On Tue, Mar 24, 2026 at 03:25:49AM +0200, Dmitry Baryshkov wrote:
> > On Sun, Mar 22, 2026 at 11:19:46PM -0700, Jingyi Wang wrote:
> > > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > 
> > > Enable MDSS/DPU/DSI0 and add Novatek NT37801 panel on Kaanapali MTP
> > > board.
> > > 
> > > NT37801 Spec V1.0 chapter "5.7.1 Power On Sequence" states VDDI ranges
> > > 1.65V~1.95V, but ldo12 ranges 1.2V~1.8V, so change ldo12 range to
> > > 1.65V~1.8V.
> > > 
> > > pmh0110_d_e0_gpios and pmh0110_f_e0_gpios are configured for
> > > level shifters. Kaanapali need configure these pinctrl for panel
> > > function.
> > > 
> > > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > > ---
> > >  arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 118 ++++++++++++++++++++++++++++-
> > >  1 file changed, 117 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > > index d0f3909621c9..07247dc98b70 100644
> > > --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > > +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> > > @@ -375,7 +375,7 @@ vreg_l11b_1p0: ldo11 {
> > >  
> > >  		vreg_l12b_1p8: ldo12 {
> > >  			regulator-name = "vreg_l12b_1p8";
> > > -			regulator-min-microvolt = <1200000>;
> > > +			regulator-min-microvolt = <1650000>;
> > 
> > Separate commit, Fixes tag.
> > 
> > >  			regulator-max-microvolt = <1800000>;
> > >  			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> > >  			regulator-allow-set-load;
> > > @@ -873,6 +873,51 @@ &lpass_vamacro {
> > >  	qcom,dmic-sample-rate = <4800000>;
> > >  };
> > >  
> > > +&mdss {
> > > +	status = "okay";
> > > +};
> > > +
> > > +&mdss_dsi0 {
> > > +	vdda-supply = <&vreg_l1d_1p2>;
> > > +	status = "okay";
> > > +
> > > +	panel@0 {
> > > +		compatible = "novatek,nt37801";
> > > +		reg = <0>;
> > > +
> > > +		pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend
> > 
> > Why is this esync0_suspend?
> 
> I check downstream sde_esync0_suspend and sde_esync0_active is same config in kaanapali,
> maybe I need rename a proper name for these pinctrl.

Yes, please.

>  
> > > +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> > > +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> > > +		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend
> > > +			     &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
> > > +			     &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
> > > +		pinctrl-names = "default", "sleep";
> > > +

> > > @@ -970,6 +1015,42 @@ bt_default: bt-default-state {
> > >  	};
> > >  };
> > >  
> > > +&pmh0110_d_e0_gpios {
> > > +	sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state {
> > 
> > If these are level shifters, should they be configured as a hog? Or
> > should they be modelled as regulators?
> > 
> > I'm not sure, how do we handle shifters and their supplies.
> 
> I think regulator-fixed is OK, but if change these pmh0110_d_e0_gpios
> to regulator-fixed, means need to modify the panel driver to accept 
> these changes, is that correct?

The problem is that it is not a panel supply.

The 100% correct, but also 80% (or 95%) overkill solution would be to
define a separate "level-shifter" device sitting between DSI host and
DSI panel and let it consume that regulator.

But, as I wrote, it's a definite overkill, unless we start getting lots
of those and require more precise control.

I'm torn between accepting this solution and asking to stuff those GPIOs
into the GPIO hog.

Probably the current solution is fine, just please add the small comment
before those pins (it's a part of the commit message, but frankly
speaking I missed it when first reviewing the patch).

> 
> I see downstream also directly manipulates these paired GPIOs. 

That's a bad reference. Vendor kernels are frequently full of the
not-well-thought solutions.

> 
-- 
With best wishes
Dmitry

Re: [PATCH 0/6] arm64: dts: qcom: kaanapali: Add PMIC dependent features

[Bjorn Andersson]

On Sun, 22 Mar 2026 23:19:40 -0700, Jingyi Wang wrote:
> Add PMIC dependent features on the Kaanapali Platform including:
> - spmi-pmic-arb device
> - various PMICs along with temp-alarm and GPIO nodes
> - Volume Keys, RGB LEDs and flash LEDs
> - bluetooth WCN785x and Wi-Fi (enabled on MTP only)
> - Display (enabled on MTP only)
> 
> [...]

Applied, thanks!

[1/6] arm64: dts: qcom: kaanapali: Add PMIC devices
      commit: 8914cc8ab0b3dbfef56100aa3bd49c7137d6feb7
[2/6] arm64: dts: qcom: kaanapali-mtp: Add PMIC support
      commit: d5b236e796c4c6922259b801a58831f8f568d31a
[3/6] arm64: dts: qcom: kaanapali-qrd: Add PMIC support
      commit: 141ae09ec1200b548a15e11fc771cbf937d01d36
[4/6] arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi
      commit: 27139dce7291f9ad233c00a72780db318b5b6de8
[5/6] arm64: dts: qcom: kaanapali: add display hardware devices
      commit: 52096f3d3f6caf88686b8cf17911225495cbe5d2
[6/6] arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices
      commit: a1a975530cab22b06c8ee2994c64b36eba193220

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>