Re: [PATCH v8 1/3] dt-bindings: timer: mips,p8700-gcru

[Aleksa Paunovic <aleksa.paunovic@htecgroup.com>]

Hi Krzysztof,


On 6/11/26 08:54, Krzysztof Kozlowski wrote:
> On 11/06/2026 08:51, Krzysztof Kozlowski wrote:
>> On 10/06/2026 10:22, Aleksa Paunovic via B4 Relay wrote:
>>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>
>>> Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
>>> platforms. The GCR.U memory region contains shadow copies of the RISC-V
>>> mtime register and the hrtime Global Configuration Register.
>>>
>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> You keep ignoring reviews you received (14th May!) and sending same mistake.
>>
>> Can you address the emails?
I wasn't really sure what the etiquette was for replying to Sashiko reviews, so I decided to
address the comments for other patches and send a v8 without replying.

As for this patch, the GCR.U itself does start at 0x7F000, but the first 
actual register (mtime) is at 0x7F050 [1]. 
I'm not seeing any warnings when running dt_binding_check.

>>
>> NAK for this patch.
> Hm, maybe it's b4 relay issue, so here is the report:
>
> https://lore.kernel.org/all/20260514055333.A29B8C2BCB7@smtp.kernel.org/
>

It did take a while but I noticed the comments. 
Will have to check more regularly in the future.


Best regards,
Aleksa

[1] https://mips.com/wp-content/uploads/2026/03/MIPS_P8700_P8700-F_Programmers_Reference_Guide_Rev1.86_2-17-2026.pdf#G7.1528502