* Re: [PATCH v2 1/5] clk: sunxi: Add support for USB clock-register reset bits
From: Hans de Goede @ 2014-02-06 16:58 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Emilio Lopez
Cc: Mike Turquette, Maxime Ripard, Philipp Zabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree
In-Reply-To: <52E80746.9020500-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Hi,
On 01/28/2014 08:38 PM, Emilio López wrote:
> Hi Hans,
>
> El 22/01/14 18:36, Hans de Goede escribió:
>> The usb-clk register is special in that it not only contains clk gate bits,
>> but also has a few reset bits. This commit adds support for this by allowing
>> gates type sunxi clks to also register a reset controller.
>>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
> (snip)
>> static const struct gates_data sun4i_axi_gates_data __initconst = {
>> @@ -818,6 +873,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
>> struct gates_data *data)
>> {
>> struct clk_onecell_data *clk_data;
>> + struct gates_reset_data *reset_data;
>> const char *clk_parent;
>> const char *clk_name;
>> void *reg;
>> @@ -861,6 +917,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
>> clk_data->clk_num = i;
>>
>> of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
>> +
>> + /* Register a reset controler for gates with reset bits */
>> + if (data->reset_mask == 0)
>> + return;
>> +
>> + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
>> + if (!reset_data)
>> + return;
>> +
>> + reset_data->reg = reg;
>> + reset_data->lock = &clk_lock;
>> + reset_data->rcdev.nr_resets = hweight32(data->reset_mask);
>
> I know I made you change this, but after having a second look into nr_resets, I think your original implementation makes more sense. This will break if you use a mask with holes on it. Sorry :(
No problem, just changed it back :)
Regards,
Hans
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^ permalink raw reply
* [PATCH 2/2] spi: Add Qualcomm QUP SPI controller support
From: Ivan T. Ivanov @ 2014-02-06 16:57 UTC (permalink / raw)
To: Mark Brown, Grant Likely, Rob Herring
Cc: Ivan T. Ivanov, linux-spi, linux-arm-msm, linux-kernel,
devicetree, Alok Chauhan, Gilad Avidov, Kiran Gunda, Sagar Dharia
In-Reply-To: <1391705868-20091-1-git-send-email-iivanov@mm-sol.com>
From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Qualcomm Universal Peripheral (QUP) core is an AHB slave that
provides a common data path (an output FIFO and an input FIFO)
for serial peripheral interface (SPI) mini-core. SPI in master mode
support up to 50MHz, up to four chip selects, and a programmable
data path from 4 bits to 32 bits; MODE0..3 protocols
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Cc: Alok Chauhan <alokc@codeaurora.org>
Cc: Gilad Avidov <gavidov@codeaurora.org>
Cc: Kiran Gunda <kgunda@codeaurora.org>
Cc: Sagar Dharia <sdharia@codeaurora.org>
---
drivers/spi/Kconfig | 14 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-qup.c | 898 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 913 insertions(+)
create mode 100644 drivers/spi/spi-qup.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ba9310b..bf8ce6b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -381,6 +381,20 @@ config SPI_RSPI
help
SPI driver for Renesas RSPI blocks.
+config SPI_QUP
+ tristate "Qualcomm SPI Support with QUP interface"
+ depends on ARCH_MSM
+ help
+ Qualcomm Universal Peripheral (QUP) core is an AHB slave that
+ provides a common data path (an output FIFO and an input FIFO)
+ for serial peripheral interface (SPI) mini-core. SPI in master
+ mode support up to 50MHz, up to four chip selects, and a
+ programmable data path from 4 bits to 32 bits; supports numerous
+ protocol variants.
+
+ This driver can also be built as a module. If so, the module
+ will be called spi_qup.
+
config SPI_S3C24XX
tristate "Samsung S3C24XX series SPI"
depends on ARCH_S3C24XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d..e598147 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
+obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
spi-s3c24xx-hw-y := spi-s3c24xx.o
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 0000000..5eb5e8f
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,898 @@
+/*
+ * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/spi/spi.h>
+
+#define QUP_CONFIG 0x0000
+#define QUP_STATE 0x0004
+#define QUP_IO_M_MODES 0x0008
+#define QUP_SW_RESET 0x000c
+#define QUP_OPERATIONAL 0x0018
+#define QUP_ERROR_FLAGS 0x001c
+#define QUP_ERROR_FLAGS_EN 0x0020
+#define QUP_OPERATIONAL_MASK 0x0028
+#define QUP_HW_VERSION 0x0030
+#define QUP_MX_OUTPUT_CNT 0x0100
+#define QUP_OUTPUT_FIFO 0x0110
+#define QUP_MX_WRITE_CNT 0x0150
+#define QUP_MX_INPUT_CNT 0x0200
+#define QUP_MX_READ_CNT 0x0208
+#define QUP_INPUT_FIFO 0x0218
+
+#define SPI_CONFIG 0x0300
+#define SPI_IO_CONTROL 0x0304
+#define SPI_ERROR_FLAGS 0x0308
+#define SPI_ERROR_FLAGS_EN 0x030c
+
+/* QUP_CONFIG fields */
+#define QUP_CONFIG_SPI_MODE (1 << 8)
+#define QUP_CONFIG_NO_INPUT BIT(7)
+#define QUP_CONFIG_NO_OUTPUT BIT(6)
+#define QUP_CONFIG_N 0x001f
+
+/* QUP_STATE fields */
+#define QUP_STATE_VALID BIT(2)
+#define QUP_STATE_RESET 0
+#define QUP_STATE_RUN 1
+#define QUP_STATE_PAUSE 3
+#define QUP_STATE_MASK 3
+#define QUP_STATE_CLEAR 2
+
+#define QUP_HW_VERSION_2_1_1 0x20010001
+
+/* QUP_IO_M_MODES fields */
+#define QUP_IO_M_PACK_EN BIT(15)
+#define QUP_IO_M_UNPACK_EN BIT(14)
+#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
+#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
+#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
+#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
+
+#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
+#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
+#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
+#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
+
+#define QUP_IO_M_MODE_FIFO 0
+#define QUP_IO_M_MODE_BLOCK 1
+#define QUP_IO_M_MODE_DMOV 2
+#define QUP_IO_M_MODE_BAM 3
+
+/* QUP_OPERATIONAL fields */
+#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
+#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
+#define QUP_OP_IN_SERVICE_FLAG BIT(9)
+#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
+#define QUP_OP_IN_FIFO_FULL BIT(7)
+#define QUP_OP_OUT_FIFO_FULL BIT(6)
+#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
+#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
+
+/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
+#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
+#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
+#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
+#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
+
+/* SPI_CONFIG fields */
+#define SPI_CONFIG_HS_MODE BIT(10)
+#define SPI_CONFIG_INPUT_FIRST BIT(9)
+#define SPI_CONFIG_LOOPBACK BIT(8)
+
+/* SPI_IO_CONTROL fields */
+#define SPI_IO_C_FORCE_CS BIT(11)
+#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
+#define SPI_IO_C_MX_CS_MODE BIT(8)
+#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
+#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
+#define SPI_IO_C_CS_SELECT_MASK 0x000c
+#define SPI_IO_C_TRISTATE_CS BIT(1)
+#define SPI_IO_C_NO_TRI_STATE BIT(0)
+
+/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
+#define SPI_ERROR_CLK_OVER_RUN BIT(1)
+#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
+
+#define SPI_NUM_CHIPSELECTS 4
+
+/* high speed mode is when bus rate is greater then 26MHz */
+#define SPI_HS_MIN_RATE 26000000
+
+#define SPI_DELAY_THRESHOLD 1
+#define SPI_DELAY_RETRY 10
+
+struct spi_qup_device {
+ int bits_per_word;
+ int chip_select;
+ int speed_hz;
+ u16 mode;
+};
+
+struct spi_qup {
+ void __iomem *base;
+ struct device *dev;
+ struct clk *cclk; /* core clock */
+ struct clk *iclk; /* interface clock */
+ int irq;
+ u32 max_speed_hz;
+ u32 speed_hz;
+
+ int in_fifo_sz;
+ int out_fifo_sz;
+ int in_blk_sz;
+ int out_blk_sz;
+
+ struct spi_transfer *xfer;
+ struct completion done;
+ int error;
+ int bytes_per_word;
+ int tx_bytes;
+ int rx_bytes;
+};
+
+
+static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
+{
+ u32 opstate = readl_relaxed(controller->base + QUP_STATE);
+
+ return opstate & QUP_STATE_VALID;
+}
+
+static int spi_qup_set_state(struct spi_qup *controller, u32 state)
+{
+ unsigned long loop = 0;
+ u32 cur_state;
+
+ cur_state = readl_relaxed(controller->base + QUP_STATE);
+ /*
+ * Per spec: for PAUSE_STATE to RESET_STATE, two writes
+ * of (b10) are required
+ */
+ if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
+ (state == QUP_STATE_RESET)) {
+ writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
+ writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
+ } else {
+ cur_state &= ~QUP_STATE_MASK;
+ cur_state |= state;
+ writel_relaxed(cur_state, controller->base + QUP_STATE);
+ }
+
+ while (!spi_qup_is_valid_state(controller)) {
+
+ usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
+
+ if (++loop > SPI_DELAY_RETRY)
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void spi_qup_deassert_cs(struct spi_qup *controller,
+ struct spi_qup_device *chip)
+{
+ u32 iocontol, mask;
+
+ iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
+
+ /* Disable auto CS toggle and use manual */
+ iocontol &= ~SPI_IO_C_MX_CS_MODE;
+ iocontol |= SPI_IO_C_FORCE_CS;
+
+ iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
+ iocontol |= SPI_IO_C_CS_SELECT(chip->chip_select);
+
+ mask = SPI_IO_C_CS_N_POLARITY_0 << chip->chip_select;
+
+ if (chip->mode & SPI_CS_HIGH)
+ iocontol &= ~mask;
+ else
+ iocontol |= mask;
+
+ writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
+}
+
+static void spi_qup_assert_cs(struct spi_qup *controller,
+ struct spi_qup_device *chip)
+{
+ u32 iocontol, mask;
+
+ iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
+
+ /* Disable auto CS toggle and use manual */
+ iocontol &= ~SPI_IO_C_MX_CS_MODE;
+ iocontol |= SPI_IO_C_FORCE_CS;
+
+ iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
+ iocontol |= SPI_IO_C_CS_SELECT(chip->chip_select);
+
+ mask = SPI_IO_C_CS_N_POLARITY_0 << chip->chip_select;
+
+ if (chip->mode & SPI_CS_HIGH)
+ iocontol |= mask;
+ else
+ iocontol &= ~mask;
+
+ writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
+}
+
+static void spi_qup_fifo_read(struct spi_qup *controller,
+ struct spi_transfer *xfer)
+{
+ u8 *rx_buf = xfer->rx_buf;
+ u32 word, state;
+ int idx, shift;
+
+ while (controller->rx_bytes < xfer->len) {
+
+ state = readl_relaxed(controller->base + QUP_OPERATIONAL);
+ if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
+ break;
+
+ word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
+
+ for (idx = 0; idx < controller->bytes_per_word &&
+ controller->rx_bytes < xfer->len; idx++,
+ controller->rx_bytes++) {
+
+ if (!rx_buf)
+ continue;
+ /*
+ * The data format depends on bytes_per_word:
+ * 4 bytes: 0x12345678
+ * 2 bytes: 0x00001234
+ * 1 byte : 0x00000012
+ */
+ shift = BITS_PER_BYTE;
+ shift *= (controller->bytes_per_word - idx - 1);
+ rx_buf[controller->rx_bytes] = word >> shift;
+ }
+ }
+}
+
+static void spi_qup_fifo_write(struct spi_qup *controller,
+ struct spi_transfer *xfer)
+{
+ const u8 *tx_buf = xfer->tx_buf;
+ u32 word, state, data;
+ int idx;
+
+ while (controller->tx_bytes < xfer->len) {
+
+ state = readl_relaxed(controller->base + QUP_OPERATIONAL);
+ if (state & QUP_OP_OUT_FIFO_FULL)
+ break;
+
+ word = 0;
+ for (idx = 0; idx < controller->bytes_per_word &&
+ controller->tx_bytes < xfer->len; idx++,
+ controller->tx_bytes++) {
+
+ if (!tx_buf)
+ continue;
+
+ data = tx_buf[controller->tx_bytes];
+ word |= data << (BITS_PER_BYTE * (3 - idx));
+ }
+
+ writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
+ }
+}
+
+static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
+{
+ struct spi_qup *controller = dev_id;
+ struct spi_transfer *xfer;
+ u32 opflags, qup_err, spi_err;
+
+ xfer = controller->xfer;
+
+ qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
+ spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
+ opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
+
+ writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
+ writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
+ writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
+
+ if (!xfer)
+ return IRQ_HANDLED;
+
+ if (qup_err) {
+ if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
+ dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
+ if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
+ dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
+ if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
+ dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
+ if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
+ dev_warn(controller->dev, "INPUT_OVER_RUN\n");
+
+ controller->error = -EIO;
+ }
+
+ if (spi_err) {
+ if (spi_err & SPI_ERROR_CLK_OVER_RUN)
+ dev_warn(controller->dev, "CLK_OVER_RUN\n");
+ if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
+ dev_warn(controller->dev, "CLK_UNDER_RUN\n");
+
+ controller->error = -EIO;
+ }
+
+ if (opflags & QUP_OP_IN_SERVICE_FLAG) {
+ writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
+ controller->base + QUP_OPERATIONAL);
+ spi_qup_fifo_read(controller, xfer);
+ }
+
+ if (opflags & QUP_OP_OUT_SERVICE_FLAG) {
+ writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
+ controller->base + QUP_OPERATIONAL);
+ spi_qup_fifo_write(controller, xfer);
+ }
+
+ if (controller->rx_bytes == xfer->len ||
+ controller->error)
+ complete(&controller->done);
+
+ return IRQ_HANDLED;
+}
+
+static int spi_qup_transfer_do(struct spi_qup *controller,
+ struct spi_qup_device *chip,
+ struct spi_transfer *xfer)
+{
+ unsigned long timeout;
+ int ret = -EIO;
+
+ reinit_completion(&controller->done);
+
+ timeout = DIV_ROUND_UP(controller->speed_hz, MSEC_PER_SEC);
+ timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
+ timeout = 100 * msecs_to_jiffies(timeout);
+
+ controller->rx_bytes = 0;
+ controller->tx_bytes = 0;
+ controller->error = 0;
+ controller->xfer = xfer;
+
+ if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
+ dev_warn(controller->dev, "cannot set RUN state\n");
+ goto exit;
+ }
+
+ if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
+ dev_warn(controller->dev, "cannot set PAUSE state\n");
+ goto exit;
+ }
+
+ spi_qup_fifo_write(controller, xfer);
+
+ if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
+ dev_warn(controller->dev, "cannot set EXECUTE state\n");
+ goto exit;
+ }
+
+ if (!wait_for_completion_timeout(&controller->done, timeout))
+ ret = -ETIMEDOUT;
+ else
+ ret = controller->error;
+exit:
+ controller->xfer = NULL;
+ controller->error = 0;
+ controller->rx_bytes = 0;
+ controller->tx_bytes = 0;
+ spi_qup_set_state(controller, QUP_STATE_RESET);
+ return ret;
+}
+
+static int spi_qup_setup(struct spi_device *spi)
+{
+ struct spi_qup *controller = spi_master_get_devdata(spi->master);
+ struct spi_qup_device *chip = spi_get_ctldata(spi);
+
+ if (spi->chip_select >= spi->master->num_chipselect) {
+ dev_err(controller->dev, "invalid chip_select %d\n",
+ spi->chip_select);
+ return -EINVAL;
+ }
+
+ if (spi->max_speed_hz > controller->max_speed_hz) {
+ dev_err(controller->dev, "invalid max_speed_hz %d\n",
+ spi->max_speed_hz);
+ return -EINVAL;
+ }
+
+ if (!chip) {
+ /* First setup */
+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+ if (!chip) {
+ dev_err(controller->dev, "no memory for chip data\n");
+ return -ENOMEM;
+ }
+
+ spi_set_ctldata(spi, chip);
+ }
+
+ return 0;
+}
+
+static void spi_qup_cleanup(struct spi_device *spi)
+{
+ struct spi_qup_device *chip = spi_get_ctldata(spi);
+
+ if (!chip)
+ return;
+
+ spi_set_ctldata(spi, NULL);
+ kfree(chip);
+}
+
+/* set clock freq, clock ramp, bits per work */
+static int spi_qup_io_setup(struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ struct spi_qup *controller = spi_master_get_devdata(spi->master);
+ struct spi_qup_device *chip = spi_get_ctldata(spi);
+ u32 iocontol, config, iomode, mode;
+ int ret, n_words;
+
+ if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
+ dev_err(controller->dev, "too big size for loopback %d > %d\n",
+ xfer->len, controller->in_fifo_sz);
+ return -EIO;
+ }
+
+ chip->mode = spi->mode;
+ chip->speed_hz = spi->max_speed_hz;
+ if (xfer->speed_hz)
+ chip->speed_hz = xfer->speed_hz;
+
+ if (controller->speed_hz != chip->speed_hz) {
+ ret = clk_set_rate(controller->cclk, chip->speed_hz);
+ if (ret) {
+ dev_err(controller->dev, "fail to set frequency %d",
+ chip->speed_hz);
+ return -EIO;
+ }
+ }
+
+ controller->speed_hz = chip->speed_hz;
+
+ chip->bits_per_word = spi->bits_per_word;
+ if (xfer->bits_per_word)
+ chip->bits_per_word = xfer->bits_per_word;
+
+ if (chip->bits_per_word <= 8)
+ controller->bytes_per_word = 1;
+ else if (chip->bits_per_word <= 16)
+ controller->bytes_per_word = 2;
+ else
+ controller->bytes_per_word = 4;
+
+ if (controller->bytes_per_word > xfer->len ||
+ xfer->len % controller->bytes_per_word != 0){
+ /* No partial transfers */
+ dev_err(controller->dev, "invalid len %d for %d bits\n",
+ xfer->len, chip->bits_per_word);
+ return -EIO;
+ }
+
+ n_words = xfer->len / controller->bytes_per_word;
+
+ if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
+ dev_err(controller->dev, "cannot set RESET state\n");
+ return -EIO;
+ }
+
+ if (n_words <= controller->in_fifo_sz) {
+ mode = QUP_IO_M_MODE_FIFO;
+ writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
+ writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
+ /* must be zero for FIFO */
+ writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
+ writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
+ } else {
+ mode = QUP_IO_M_MODE_BLOCK;
+ writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
+ writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
+ /* must be zero for BLOCK and BAM */
+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
+ }
+
+ iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
+ /* Set input and output transfer mode */
+ iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
+ iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
+ iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
+ iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
+
+ writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
+
+ config = readl_relaxed(controller->base + SPI_CONFIG);
+
+ if (chip->mode & SPI_LOOP)
+ config |= SPI_CONFIG_LOOPBACK;
+ else
+ config &= ~SPI_CONFIG_LOOPBACK;
+
+ if (chip->mode & SPI_CPHA)
+ config &= ~SPI_CONFIG_INPUT_FIRST;
+ else
+ config |= SPI_CONFIG_INPUT_FIRST;
+
+ /*
+ * HS_MODE improves signal stability for spi-clk high rates
+ * but is invalid in loop back mode.
+ */
+ if ((controller->speed_hz >= SPI_HS_MIN_RATE) &&
+ !(chip->mode & SPI_LOOP))
+ config |= SPI_CONFIG_HS_MODE;
+ else
+ config &= ~SPI_CONFIG_HS_MODE;
+
+ writel_relaxed(config, controller->base + SPI_CONFIG);
+
+ config = readl_relaxed(controller->base + QUP_CONFIG);
+ config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
+ config |= chip->bits_per_word - 1;
+ config |= QUP_CONFIG_SPI_MODE;
+ writel_relaxed(config, controller->base + QUP_CONFIG);
+
+ iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
+
+ /* Disable auto CS toggle */
+ iocontol &= ~SPI_IO_C_MX_CS_MODE;
+
+ if (chip->mode & SPI_CPOL)
+ iocontol |= SPI_IO_C_CLK_IDLE_HIGH;
+ else
+ iocontol &= ~SPI_IO_C_CLK_IDLE_HIGH;
+
+ writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
+
+ /*
+ * TODO: In BAM mode mask INPUT and OUTPUT service flags in
+ * to prevent IRQs on FIFO status change.
+ */
+ writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
+
+ return 0;
+}
+
+static int spi_qup_transfer_one(struct spi_master *master,
+ struct spi_message *msg)
+{
+ struct spi_qup *controller = spi_master_get_devdata(master);
+ struct spi_qup_device *chip = spi_get_ctldata(msg->spi);
+ struct spi_transfer *xfer;
+ struct spi_device *spi;
+ unsigned cs_change;
+ int status;
+
+ spi = msg->spi;
+ cs_change = 1;
+ status = 0;
+
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+
+ status = spi_qup_io_setup(spi, xfer);
+ if (status)
+ break;
+
+ if (cs_change)
+ spi_qup_assert_cs(controller, chip);
+
+ cs_change = xfer->cs_change;
+
+ /* Do actual transfer */
+ status = spi_qup_transfer_do(controller, chip, xfer);
+ if (status)
+ break;
+
+ msg->actual_length += xfer->len;
+
+ if (xfer->delay_usecs)
+ udelay(xfer->delay_usecs);
+
+ if (cs_change)
+ spi_qup_deassert_cs(controller, chip);
+ }
+
+ if (status || !cs_change)
+ spi_qup_deassert_cs(controller, chip);
+
+ msg->status = status;
+ spi_finalize_current_message(master);
+ return status;
+}
+
+static int spi_qup_probe(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct clk *iclk, *cclk;
+ struct spi_qup *controller;
+ struct resource *res;
+ struct device *dev;
+ void __iomem *base;
+ u32 data, max_freq, iomode;
+ int ret, irq, size;
+
+ dev = &pdev->dev;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ irq = platform_get_irq(pdev, 0);
+
+ if (irq < 0)
+ return irq;
+
+ cclk = devm_clk_get(dev, "core");
+ if (IS_ERR(cclk)) {
+ dev_err(dev, "cannot get core clock\n");
+ return PTR_ERR(cclk);
+ }
+
+ iclk = devm_clk_get(dev, "iface");
+ if (IS_ERR(iclk)) {
+ dev_err(dev, "cannot get iface clock\n");
+ return PTR_ERR(iclk);
+ }
+
+ if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
+ max_freq = 19200000;
+
+ if (!max_freq) {
+ dev_err(dev, "invalid clock frequency %d\n", max_freq);
+ return -ENXIO;
+ }
+
+ ret = clk_set_rate(cclk, max_freq);
+ if (ret)
+ dev_warn(dev, "fail to set SPI frequency %d\n", max_freq);
+
+ ret = clk_prepare_enable(cclk);
+ if (ret) {
+ dev_err(dev, "cannot enable core clock\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(iclk);
+ if (ret) {
+ clk_disable_unprepare(cclk);
+ dev_err(dev, "cannot enable iface clock\n");
+ return ret;
+ }
+
+ data = readl_relaxed(base + QUP_HW_VERSION);
+
+ if (data < QUP_HW_VERSION_2_1_1) {
+ clk_disable_unprepare(cclk);
+ clk_disable_unprepare(iclk);
+ dev_err(dev, "v.%08x is not supported\n", data);
+ return -ENXIO;
+ }
+
+ master = spi_alloc_master(dev, sizeof(struct spi_qup));
+ if (!master) {
+ clk_disable_unprepare(cclk);
+ clk_disable_unprepare(iclk);
+ dev_err(dev, "cannot allocate master\n");
+ return -ENOMEM;
+ }
+
+ master->bus_num = pdev->id;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
+ master->num_chipselect = SPI_NUM_CHIPSELECTS;
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+ master->setup = spi_qup_setup;
+ master->cleanup = spi_qup_cleanup;
+ master->transfer_one_message = spi_qup_transfer_one;
+ master->dev.of_node = pdev->dev.of_node;
+ master->auto_runtime_pm = true;
+
+ platform_set_drvdata(pdev, master);
+
+ controller = spi_master_get_devdata(master);
+
+ controller->dev = dev;
+ controller->base = base;
+ controller->iclk = iclk;
+ controller->cclk = cclk;
+ controller->irq = irq;
+ controller->max_speed_hz = clk_get_rate(cclk);
+ controller->speed_hz = controller->max_speed_hz;
+
+ init_completion(&controller->done);
+
+ iomode = readl_relaxed(base + QUP_IO_M_MODES);
+
+ size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
+ if (size)
+ controller->out_blk_sz = size * 16;
+ else
+ controller->out_blk_sz = 4;
+
+ size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
+ if (size)
+ controller->in_blk_sz = size * 16;
+ else
+ controller->in_blk_sz = 4;
+
+ size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
+ controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
+
+ size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
+ controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
+
+ dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
+ data, controller->in_blk_sz, controller->in_fifo_sz,
+ controller->out_blk_sz, controller->out_fifo_sz);
+
+ writel_relaxed(1, base + QUP_SW_RESET);
+
+ ret = spi_qup_set_state(controller, QUP_STATE_RESET);
+ if (ret) {
+ dev_err(dev, "cannot set RESET state\n");
+ goto error;
+ }
+
+ writel_relaxed(0, base + QUP_OPERATIONAL);
+ writel_relaxed(0, base + QUP_IO_M_MODES);
+ writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
+ writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
+ base + SPI_ERROR_FLAGS_EN);
+
+ writel_relaxed(0, base + SPI_CONFIG);
+ writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
+
+ ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
+ IRQF_TRIGGER_HIGH, pdev->name, controller);
+ if (ret) {
+ dev_err(dev, "cannot request IRQ %d\n", irq);
+ goto error;
+ }
+
+ ret = devm_spi_register_master(dev, master);
+ if (!ret) {
+ pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ return ret;
+ }
+error:
+ clk_disable_unprepare(cclk);
+ clk_disable_unprepare(iclk);
+ spi_master_put(master);
+ return ret;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+static int spi_qup_pm_suspend_runtime(struct device *device)
+{
+ struct spi_master *master = dev_get_drvdata(device);
+ struct spi_qup *controller = spi_master_get_devdata(master);
+
+ disable_irq(controller->irq);
+ clk_disable_unprepare(controller->cclk);
+ clk_disable_unprepare(controller->iclk);
+ dev_dbg(device, "suspend runtime\n");
+ return 0;
+}
+
+static int spi_qup_pm_resume_runtime(struct device *device)
+{
+ struct spi_master *master = dev_get_drvdata(device);
+ struct spi_qup *controller = spi_master_get_devdata(master);
+
+ clk_prepare_enable(controller->cclk);
+ clk_prepare_enable(controller->iclk);
+ enable_irq(controller->irq);
+ dev_dbg(device, "resume runtime\n");
+ return 0;
+}
+#endif /* CONFIG_PM_RUNTIME */
+
+#ifdef CONFIG_PM_SLEEP
+static int spi_qup_suspend(struct device *device)
+{
+ struct spi_master *master = dev_get_drvdata(device);
+ struct spi_qup *controller = spi_master_get_devdata(master);
+ int status;
+
+ status = spi_master_suspend(master);
+ if (!status) {
+ disable_irq(controller->irq);
+ clk_disable_unprepare(controller->cclk);
+ clk_disable_unprepare(controller->iclk);
+ }
+
+ dev_dbg(device, "system suspend %d\n", status);
+ return status;
+}
+
+static int spi_qup_resume(struct device *device)
+{
+ struct spi_master *master = dev_get_drvdata(device);
+ struct spi_qup *controller = spi_master_get_devdata(master);
+ int status;
+
+ clk_prepare_enable(controller->cclk);
+ clk_prepare_enable(controller->iclk);
+
+ status = spi_master_resume(master);
+
+ dev_dbg(device, "system resume %d\n", status);
+ return status;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static int spi_qup_remove(struct platform_device *pdev)
+{
+ struct spi_master *master = dev_get_drvdata(&pdev->dev);
+ struct spi_qup *controller = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(&pdev->dev);
+
+ clk_disable_unprepare(controller->cclk);
+ clk_disable_unprepare(controller->iclk);
+
+ pm_runtime_put_noidle(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static struct of_device_id spi_qup_dt_match[] = {
+ { .compatible = "qcom,spi-qup-v2", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
+
+static const struct dev_pm_ops spi_qup_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
+ SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
+ spi_qup_pm_resume_runtime,
+ NULL)
+};
+
+static struct platform_driver spi_qup_driver = {
+ .driver = {
+ .name = "spi_qup",
+ .owner = THIS_MODULE,
+ .pm = &spi_qup_dev_pm_ops,
+ .of_match_table = spi_qup_dt_match,
+ },
+ .probe = spi_qup_probe,
+ .remove = spi_qup_remove,
+};
+module_platform_driver(spi_qup_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION("0.4");
+MODULE_ALIAS("platform:spi_qup");
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] spi: qup: Add device tree bindings information
From: Ivan T. Ivanov @ 2014-02-06 16:57 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Rob Landley
Cc: Ivan T. Ivanov, devicetree, linux-doc, linux-arm-msm,
linux-kernel
In-Reply-To: <1391705868-20091-1-git-send-email-iivanov@mm-sol.com>
From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
The Qualcomm Universal Peripheral (QUP) core is an
AHB slave that provides a common data path (an output
FIFO and an input FIFO) for serial peripheral interface
(SPI) mini-core.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
.../devicetree/bindings/spi/qcom,spi-qup.txt | 86 ++++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
new file mode 100644
index 0000000..74565f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -0,0 +1,86 @@
+Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
+
+The QUP core is an AHB slave that provides a common data path (an output FIFO
+and an input FIFO) for serial peripheral interface (SPI) mini-core.
+
+SPI in master mode support up to 50MHz, up to four chip selects, and a
+programmable data path from 4 bits to 32 bits; supports numerous protocol
+variants.
+
+Required properties:
+- compatible: Should contain "qcom,spi-qup-v2".
+- reg: Should contain base register location and length
+- interrupts: Interrupt number used by this controller
+
+- clocks: Should contain the core clock and the AHB clock.
+- clock-names: Should be "core" for the core clock and "iface" for the
+ AHB clock.
+
+- #address-cells: Number of cells required to define a chip select
+ address on the SPI bus. Should be set to 1.
+- #size-cells: Should be zero.
+
+Optional properties:
+- spi-max-frequency: Specifies maximum SPI clock frequency, Units - Hz. Definition
+ as per Documentation/devicetree/bindings/spi/spi-bus.txt
+
+SPI slave nodes must be children of the SPI master node and can
+contain properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+ spi_8: spi@f9964000 { /* BLSP2 QUP2 */
+
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf9964000 0x1000>;
+ interrupts = <0 102 0>;
+ spi-max-frequency = <19200000>;
+
+ clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi8_default>;
+
+ device@0 {
+ compatible = "arm,pl022-dummy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <19200000>;
+ spi-cpol;
+ };
+
+ device@1 {
+ compatible = "arm,pl022-dummy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <1>; /* Chip select 1 */
+ spi-max-frequency = <9600000>;
+ spi-cpha;
+ };
+
+ device@2 {
+ compatible = "arm,pl022-dummy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <2>; /* Chip select 2 */
+ spi-max-frequency = <19200000>;
+ spi-cpol;
+ spi-cpha;
+ };
+
+ device@3 {
+ compatible = "arm,pl022-dummy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <3>; /* Chip select 3 */
+ spi-max-frequency = <19200000>;
+ spi-cpol;
+ spi-cpha;
+ spi-cs-high;
+ };
+ };
+
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/2] spi: Add Qualcomm QUP SPI controller support
From: Ivan T. Ivanov @ 2014-02-06 16:57 UTC (permalink / raw)
To: Mark Brown, Grant Likely, Rob Herring
Cc: Ivan T. Ivanov, linux-spi, linux-arm-msm, linux-kernel,
devicetree
From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Hi,
Following two patches are adding initial support for SPI controller
available in Qualcomm SoC's.
Controller initialization is based on spi_qsd driver available in
CAF repository.
Controller supports SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP modes,
up to 3 CS's and from 4 to 32 bits per word. SPI_LOOP mode is limited
to input FIFO buffer size.
Currently driver support only PIO mode, I am hopping to add also DMA
mode support with dmaengine patches developed by Andy.
Regards,
Ivan
Ivan T. Ivanov (2):
spi: qup: Add device tree bindings information
spi: Add Qualcomm QUP SPI controller support
.../devicetree/bindings/spi/qcom,spi-qup.txt | 86 ++
drivers/spi/Kconfig | 14 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-qup.c | 898 ++++++++++++++++++++
4 files changed, 999 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
create mode 100644 drivers/spi/spi-qup.c
--
1.7.9.5
^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Ian Campbell @ 2014-02-06 16:52 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland, devicetree, Ben Peddell, Jason Cooper, pawel.moll,
Kumar Gala, linux ARM
In-Reply-To: <20140206165003.GJ29860@lunn.ch>
On Thu, 2014-02-06 at 17:50 +0100, Andrew Lunn wrote:
> On Thu, Feb 06, 2014 at 04:39:25PM +0000, Ian Campbell wrote:
> > On Thu, 2014-02-06 at 10:39 -0500, Jason Cooper wrote:
> > >
> > > > + pmx_fan_33: pmx-fan-33 {
> > > > + marvell,pins = "mpp33";
> > > > + marvell,function = "gpo";
> > > > + };
> >
> > Typo I think.
>
> Hi Ian
>
> drivers/pinctrl/mvebu/pinctrl-kirkwood.c:
>
> MPP_MODE(33,
> MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)),
> MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
> MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)),
> MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))),
> MPP_MODE(34,
>
> It is output only.
Oops, Sorry for the noise!
>
> I actually had the opposite bug in v1, setup two gpo's as gpio's.
>
> Andrew
>
^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Andrew Lunn @ 2014-02-06 16:50 UTC (permalink / raw)
To: Ian Campbell
Cc: Jason Cooper, Andrew Lunn, linux ARM, Ben Peddell,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
pawel.moll-5wv7dgnIgG8, Mark Rutland, Kumar Gala
In-Reply-To: <1391704765.2162.7.camel-ommiHX4a84BXesXXhkcM7miJhflN2719@public.gmane.org>
On Thu, Feb 06, 2014 at 04:39:25PM +0000, Ian Campbell wrote:
> On Thu, 2014-02-06 at 10:39 -0500, Jason Cooper wrote:
> >
> > > + pmx_fan_33: pmx-fan-33 {
> > > + marvell,pins = "mpp33";
> > > + marvell,function = "gpo";
> > > + };
>
> Typo I think.
Hi Ian
drivers/pinctrl/mvebu/pinctrl-kirkwood.c:
MPP_MODE(33,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(34,
It is output only.
I actually had the opposite bug in v1, setup two gpo's as gpio's.
Andrew
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^ permalink raw reply
* Re: [PATCH 1/4] ARM: STi: add stid127 soc support
From: Arnd Bergmann @ 2014-02-06 16:46 UTC (permalink / raw)
To: srinivas kandagatla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Russell King,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, Linus Walleij, Patrice CHOTARD,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Stuart Menefy, Rob Herring,
Grant Likely, Giuseppe Cavallaro, maxime.coquelin-qxv4g6HH51o,
alexandre.torgue-qxv4g6HH51o
In-Reply-To: <52F22508.7080706-qxv4g6HH51o@public.gmane.org>
On Wednesday 05 February 2014, srinivas kandagatla wrote:
> Currently l2cc bindings has few optional properties like.
>
> - arm,data-latency
> - arm,tag-latency
> - arm,dirty-latency
> - arm,filter-ranges
> - interrupts :
> - cache-id-part:
> - wt-override:
>
> These does not include properties to set "way-size", "associativity",
> "enabling prefetching", "Prefetch drop enable", "prefetch offset",
> "Double linefill" and few more in prefect control register and
> aux-control register.
>
> This is not just a issue with STi SOCs, having a quick look, I can see
> that few more SOCs have similar requirements to set these properties.
>
> We could do two things to get l2 setup automatically on STi SOCS.
>
> 1> Either define these properties case-by-case basic, which might be
> useful for other SOCs too.
>
> 2> Or Add new compatible string for STi SoCs so that they can
> automatically setup these values in cache-l2x0.c
>
> Am Ok with either approaches.
>
I suggested 1 in the past, but the objection that I saw (can't
find the email at the moment) was that the additional settings
are "configuration" rather than "hardware properties". What I'd
really need to know from you is which of properties you listed
as missing above are actually needed for your platform, and whether
they can be classified as hardware specific or just configuration.
Arnd
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^ permalink raw reply
* Re: [PATCH v3 3/6] misc: fuse: Add efuse driver for Tegra
From: Stephen Warren @ 2014-02-06 16:45 UTC (permalink / raw)
To: Peter De Schrijver
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Landley,
Thierry Reding, Grant Likely, Rob Herring, Danny Huang,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20140206091114.GK19389-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
On 02/06/2014 02:11 AM, Peter De Schrijver wrote:
> On Wed, Feb 05, 2014 at 08:15:46PM +0100, Stephen Warren wrote:
>> On 01/28/2014 04:36 PM, Peter De Schrijver wrote:
>>> Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124.
>>> diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse
>>> +What: /sys/devices/*/<our-device>/fuse
>>> +Date: December 2013
>>> +Contact: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>> +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
>>> + and Tegra124 SoC's from NVIDIA. The efuses contain write once
>>> + data programmed at the factory.
>>> +Users: any user space application which wants to read the efuses on
>>> + Tegra SoC's
>>
>> Surely this file should describe the format of the file, since that's
>> part of the ABI too, right?
>>
>
> Part of the fuse data is ODM defined so possibly board specific.
I didn't mean the interpretation of which fuses mean what semantically,
but rather the data format of the file. IIRC looking at the code, it's
just a binary dump of the fuses, but it might be worth spelling out that
it's a byte-oriented binary file, with fuse 0 in bit 0 of byte 0 etc.?
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^ permalink raw reply
* Re: [RFC] dt-bindings: configuration of parent clocks and clock frequency
From: Mike Turquette @ 2014-02-06 16:43 UTC (permalink / raw)
To: Marek Szyprowski, Sylwester Nawrocki, linux-arm-kernel,
devicetree
Cc: Russell King - ARM Linux, Tomasz Figa, Kyungmin Park, Rob Herring,
Mark Rutland, Pawel Moll, Ian Campbell, Kumar Gala
In-Reply-To: <52F0DA07.6050903-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Quoting Marek Szyprowski (2014-02-04 04:16:07)
> Hello,
>
> On 2014-02-01 04:06, Mike Turquette wrote:
> > Quoting Sylwester Nawrocki (2014-01-21 04:48:43)
> > > 5. Similarly to the regulator bindings the clock names could be appended
> > > to name of a DT property:
> > >
> > > [clk_name]-assigned-clock-parent = <...>;
> > > [clk_name]-assigned-clock-rate = <...>;
> >
> > I have always been partial to the way that the reg framework does its
> > [reg_name]-supply. We could shorten it to something like:
> >
> > [clk-name]-asn-parent = ....
> > [clk-name]-asn-rate = ...
> >
> > This is actually the format that was discussed at the ARM kernel summit
> > IIRC.
>
> I think that "[clk-name]-clk-parent" and "[clk-name]-clk-rate" will be a bit
> more descriptive names instead of quite ambiguous "asn".
+1
Regards,
Mike
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>
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^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Ian Campbell @ 2014-02-06 16:39 UTC (permalink / raw)
To: Jason Cooper
Cc: Mark Rutland, Andrew Lunn, Ben Peddell, pawel.moll, devicetree,
Kumar Gala, linux ARM
In-Reply-To: <20140206153939.GD8533@titan.lakedaemon.net>
On Thu, 2014-02-06 at 10:39 -0500, Jason Cooper wrote:
>
> > + pmx_fan_33: pmx-fan-33 {
> > + marvell,pins = "mpp33";
> > + marvell,function = "gpo";
> > + };
Typo I think.
Ian.
^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Arnd Bergmann @ 2014-02-06 16:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, Andrew Lunn, Ben Peddell, Jason Cooper, pawel.moll,
devicetree, Ian Campbell, Kumar Gala
In-Reply-To: <20140206160126.GH29860@lunn.ch>
On Thursday 06 February 2014 17:01:26 Andrew Lunn wrote:
> , but this is, imho,
> > over-fragmenting. I'm sure there's a reason you chose this path, but
> > you haven't explained why in your commit log. So I'm left guessing...
>
> Synology seem to build there devices like lego. They have two
> different RTC blocks. They have three different fan alarm blocks, four
> different led blocks, etc. And to build a product, the just select a
> group of blocks and put them together.
I guess the Armada-370 and newer based ds213j and dsx14 will also be
able to reuse some of the blocks, right?
Arnd
^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Andrew Lunn @ 2014-02-06 16:01 UTC (permalink / raw)
To: Jason Cooper
Cc: Mark Rutland, Andrew Lunn, Ben Peddell, pawel.moll, devicetree,
Kumar Gala, Ian Campbell, linux ARM
In-Reply-To: <20140206153939.GD8533@titan.lakedaemon.net>
On Thu, Feb 06, 2014 at 10:39:39AM -0500, Jason Cooper wrote:
>
> + devicetree ML, DT maintainers
>
> On Wed, Feb 05, 2014 at 10:05:09PM +0100, Andrew Lunn wrote:
> > Add device tree fragments and files to support many of the kirkwood
> > based Synology NAS devices. This is a translation of the board setup
> > file maintained by Ben Peddell <klightspeed@killerwolves.net>
> >
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> > Tested by Ben Peddell <klightspeed@killerwolves.net>
> > cc: Ben Peddell <klightspeed@killerwolves.net>
> > ---
> >
> > v2:
> > Fix gpio's which should be gpo.
> > Rebase onto v3-14-rc1
> > Update RTC nodes with vendor name.
> > Update SPI flash node with vendor name.
> > ---
> > arch/arm/boot/dts/Makefile | 15 ++++
> > arch/arm/boot/dts/kirkwood-ds109.dts | 33 +++++++
> > arch/arm/boot/dts/kirkwood-ds110jv10.dts | 33 +++++++
> > arch/arm/boot/dts/kirkwood-ds111.dts | 33 +++++++
> > arch/arm/boot/dts/kirkwood-ds112.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-ds209.dts | 33 +++++++
> > arch/arm/boot/dts/kirkwood-ds210.dts | 35 ++++++++
> > arch/arm/boot/dts/kirkwood-ds212.dts | 37 ++++++++
> > arch/arm/boot/dts/kirkwood-ds212j.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-ds409.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-ds409slim.dts | 32 +++++++
> > arch/arm/boot/dts/kirkwood-ds411.dts | 35 ++++++++
> > arch/arm/boot/dts/kirkwood-ds411j.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-ds411slim.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-rs212.dts | 34 +++++++
> > arch/arm/boot/dts/kirkwood-rs409.dts | 33 +++++++
> > arch/arm/boot/dts/kirkwood-rs411.dts | 34 +++++++
> > arch/arm/boot/dts/synology/alarm-led-12.dtsi | 28 ++++++
> > arch/arm/boot/dts/synology/common.dtsi | 112 ++++++++++++++++++++++++
> > arch/arm/boot/dts/synology/ethernet-1.dtsi | 15 ++++
> > arch/arm/boot/dts/synology/fan-alarm-18.dtsi | 22 +++++
> > arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi | 22 +++++
> > arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi | 32 +++++++
> > arch/arm/boot/dts/synology/fan-gpios-15.dtsi | 34 +++++++
> > arch/arm/boot/dts/synology/fan-gpios-32.dtsi | 34 +++++++
> > arch/arm/boot/dts/synology/fan-speed-100.dtsi | 20 +++++
> > arch/arm/boot/dts/synology/fan-speed-120.dtsi | 20 +++++
> > arch/arm/boot/dts/synology/fan-speed-150.dtsi | 20 +++++
> > arch/arm/boot/dts/synology/hdd-leds-20.dtsi | 90 +++++++++++++++++++
> > arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi | 36 ++++++++
> > arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi | 52 +++++++++++
> > arch/arm/boot/dts/synology/hdd-leds-36.dtsi | 103 ++++++++++++++++++++++
> > arch/arm/boot/dts/synology/hdd-leds-38.dtsi | 52 +++++++++++
> > arch/arm/boot/dts/synology/hdd-power-29.dtsi | 56 ++++++++++++
> > arch/arm/boot/dts/synology/hdd-power-30-1.dtsi | 40 +++++++++
> > arch/arm/boot/dts/synology/hdd-power-30-2.dtsi | 56 ++++++++++++
> > arch/arm/boot/dts/synology/hdd-power-30-4.dtsi | 89 +++++++++++++++++++
> > arch/arm/boot/dts/synology/hdd-power-31.dtsi | 40 +++++++++
> > arch/arm/boot/dts/synology/hdd-power-34.dtsi | 73 +++++++++++++++
> > arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi | 18 ++++
> > arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi | 18 ++++
> > arch/arm/boot/dts/synology/pcie-2.dtsi | 19 ++++
> > 42 files changed, 1658 insertions(+)
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds109.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds110jv10.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds111.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds112.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds209.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds210.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds212.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds212j.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds409.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds409slim.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds411.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds411j.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ds411slim.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-rs212.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-rs409.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-rs411.dts
> > create mode 100644 arch/arm/boot/dts/synology/alarm-led-12.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/common.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/ethernet-1.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-alarm-18.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-gpios-15.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-gpios-32.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-speed-100.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-speed-120.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/fan-speed-150.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-leds-20.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-leds-36.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-leds-38.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-29.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-1.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-2.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-4.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-31.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/hdd-power-34.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi
> > create mode 100644 arch/arm/boot/dts/synology/pcie-2.dtsi
>
> Holy sh*t! I know we're adding 15 boards
More than 15 actually. Most .dts files support multiple devices. So
there should be about 30 devices supported by these .dts files.
, but this is, imho,
> over-fragmenting. I'm sure there's a reason you chose this path, but
> you haven't explained why in your commit log. So I'm left guessing...
Synology seem to build there devices like lego. They have two
different RTC blocks. They have three different fan alarm blocks, four
different led blocks, etc. And to build a product, the just select a
group of blocks and put them together.
The board setup code which Ben Peddell wrote has a somewhat similar
structure:
http://klightspeed.killerwolves.net/synology/linux-3.4-synology-0.1.patch
It has a set of functions which add platform devices. And a table
driven piece of code which based on the product name calls these
functions to add the needed platform devices. Take a look at the table
to get a better idea of the re-use factor of the blocks.
In this DT version, i have a dtsi file for each function, and a dti
file for each table entry.
I will add to the changelog in the next version.
Andrew
^ permalink raw reply
* [PATCH v10] gpio: add a driver for the Synopsys DesignWare APB GPIO block
From: Alan Tull @ 2014-02-06 15:55 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-kernel, linux-gpio, linux-doc, Jamie Iles,
devicetree@vger.kernel.org, Grant Likely, Rob Herring,
Steffen Trumtrar, Sebastian Hesselbarth, delicious quinoa,
Heiko Stuebner, Alan Tull, Dinh Nguyen, Yves Vandervennet
From: Jamie Iles <jamie@jamieiles.com>
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Alan Tull <atull@altera.com>
Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
v10: - in documentation nr-gpio -> nr-gpios
v9: - cleanup in dt bindings doc
- use of_get_child_count()
v8: - remove socfpga.dtsi changes
- minor cleanup in devicetree documentation
v7: - use irq_generic_chip
- support one irq per gpio line or one irq for many
- s/bank/port/ and other cleanup
v6: - (atull) squash the set of patches
- use linear irq domain
- build fixes. Original driver was reviewed on v3.2.
- Fix setting irq edge type for 'rising' and 'both'.
- Support as a loadable module.
- Use bgpio_chip's spinlock during register access.
- Clean up register names to match spec
- s/bank/port/ because register names use the word 'port'
- s/nr-gpio/nr-gpios/
- don't get/put the of_node
- remove signoffs/acked-by's because of changes
- other cleanup
v5: - handle sparse bank population correctly
v3: - depend on rather than select IRQ_DOMAIN
- split IRQ support into a separate patch
v2: - use Rob Herring's irqdomain in generic irq chip patches
- use reg property to indicate bank index
- support irqs on both edges based on LinusW's u300 driver
---
.../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 59 +++
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-dwapb.c | 415 ++++++++++++++++++++
4 files changed, 484 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
create mode 100644 drivers/gpio/gpio-dwapb.c
diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
new file mode 100644
index 0000000..cb01f9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
@@ -0,0 +1,59 @@
+* Synopsys DesignWare APB GPIO controller
+
+Required properties:
+- compatible : Should contain "snps,dw-apb-gpio"
+- reg : Address and length of the register set for the device
+
+The GPIO controller has a configurable number of ports, each of which are
+represented as child nodes with the following properties:
+
+Required properties:
+- compatible : "snps,dw-apb-gpio-port"
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify optional parameters (currently
+ unused).
+- reg : The integer port index of the port, a single cell.
+- #address-cells : should be 1.
+- #size-cells : should be 0.
+
+Optional properties:
+- interrupt-controller : The first port may be configured to be an interrupt
+controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+interrupt. Shall be set to 2. The first cell defines the interrupt number,
+the second encodes the triger flags encoded as described in
+Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+- interrupts : The interrupts to the parent controller raised when GPIOs
+generate the interrupts.
+- snps,nr-gpios : The number of pins in the port, a single cell.
+
+Example:
+
+gpio: gpio@20000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <8>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&vic1>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+ };
+
+ portb: gpio-controller@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <8>;
+ reg = <1>;
+ };
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0f04444..17760dd 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -121,6 +121,15 @@ config GPIO_GENERIC_PLATFORM
help
Say yes here to support basic platform_device memory-mapped GPIO controllers.
+config GPIO_DWAPB
+ tristate "Synopsys DesignWare APB GPIO driver"
+ select GPIO_GENERIC
+ select GENERIC_IRQ_CHIP
+ depends on OF_GPIO && IRQ_DOMAIN
+ help
+ Say Y or M here to build support for the Synopsys DesignWare APB
+ GPIO block.
+
config GPIO_IT8761E
tristate "IT8761E GPIO support"
depends on X86 # unconditional access to IO space.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7971e36..b4f852e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o
+obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
obj-$(CONFIG_GPIO_EM) += gpio-em.o
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
new file mode 100644
index 0000000..7dff515
--- /dev/null
+++ b/drivers/gpio/gpio-dwapb.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2011 Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/basic_mmio_gpio.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#define GPIO_SWPORTA_DR 0x00
+#define GPIO_SWPORTA_DDR 0x04
+#define GPIO_SWPORTB_DR 0x0c
+#define GPIO_SWPORTB_DDR 0x10
+#define GPIO_SWPORTC_DR 0x18
+#define GPIO_SWPORTC_DDR 0x1c
+#define GPIO_SWPORTD_DR 0x24
+#define GPIO_SWPORTD_DDR 0x28
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK 0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY 0x3c
+#define GPIO_INTSTATUS 0x40
+#define GPIO_PORTA_EOI 0x4c
+#define GPIO_EXT_PORTA 0x50
+#define GPIO_EXT_PORTB 0x54
+#define GPIO_EXT_PORTC 0x58
+#define GPIO_EXT_PORTD 0x5c
+
+#define DWAPB_MAX_PORTS 4
+#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
+#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
+#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
+
+struct dwapb_gpio;
+
+struct dwapb_gpio_port {
+ struct bgpio_chip bgc;
+ bool is_registered;
+ struct dwapb_gpio *gpio;
+};
+
+struct dwapb_gpio {
+ struct device *dev;
+ void __iomem *regs;
+ struct dwapb_gpio_port *ports;
+ unsigned int nr_ports;
+ struct irq_domain *domain;
+};
+
+static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ struct dwapb_gpio_port *port = container_of(bgc, struct
+ dwapb_gpio_port, bgc);
+ struct dwapb_gpio *gpio = port->gpio;
+
+ return irq_create_mapping(gpio->domain, offset);
+}
+
+static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
+{
+ u32 v = readl(gpio->regs + GPIO_INT_POLARITY);
+
+ if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
+ v &= ~BIT(offs);
+ else
+ v |= BIT(offs);
+
+ writel(v, gpio->regs + GPIO_INT_POLARITY);
+}
+
+static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
+{
+ struct dwapb_gpio *gpio = irq_get_handler_data(irq);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
+
+ while (irq_status) {
+ int hwirq = fls(irq_status) - 1;
+ int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
+
+ generic_handle_irq(gpio_irq);
+ irq_status &= ~BIT(hwirq);
+
+ if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
+ == IRQ_TYPE_EDGE_BOTH)
+ dwapb_toggle_trigger(gpio, hwirq);
+ }
+
+ if (chip->irq_eoi)
+ chip->irq_eoi(irq_desc_get_irq_data(desc));
+}
+
+static void dwapb_irq_enable(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = gc->private;
+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&bgc->lock, flags);
+ val = readl(gpio->regs + GPIO_INTEN);
+ val |= BIT(d->hwirq);
+ writel(val, gpio->regs + GPIO_INTEN);
+ spin_unlock_irqrestore(&bgc->lock, flags);
+}
+
+static void dwapb_irq_disable(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = gc->private;
+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&bgc->lock, flags);
+ val = readl(gpio->regs + GPIO_INTEN);
+ val &= ~BIT(d->hwirq);
+ writel(val, gpio->regs + GPIO_INTEN);
+ spin_unlock_irqrestore(&bgc->lock, flags);
+}
+
+static int dwapb_irq_set_type(struct irq_data *d, u32 type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = gc->private;
+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
+ int bit = d->hwirq;
+ unsigned long level, polarity, flags;
+
+ if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
+ IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
+ return -EINVAL;
+
+ spin_lock_irqsave(&bgc->lock, flags);
+ level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
+ polarity = readl(gpio->regs + GPIO_INT_POLARITY);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ level |= BIT(bit);
+ dwapb_toggle_trigger(gpio, bit);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ level |= BIT(bit);
+ polarity |= BIT(bit);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ level |= BIT(bit);
+ polarity &= ~BIT(bit);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ level &= ~BIT(bit);
+ polarity |= BIT(bit);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ level &= ~BIT(bit);
+ polarity &= ~BIT(bit);
+ break;
+ }
+
+ writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
+ writel(polarity, gpio->regs + GPIO_INT_POLARITY);
+ spin_unlock_irqrestore(&bgc->lock, flags);
+
+ return 0;
+}
+
+static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
+ struct dwapb_gpio_port *port)
+{
+ struct gpio_chip *gc = &port->bgc.gc;
+ struct device_node *node = gc->of_node;
+ struct irq_chip_generic *irq_gc;
+ unsigned int hwirq, ngpio = gc->ngpio;
+ struct irq_chip_type *ct;
+ int reg, err, irq;
+
+ if (of_get_property(node, "interrupts", ®) == NULL)
+ return;
+
+ gpio->domain = irq_domain_add_linear(node, ngpio, &irq_generic_chip_ops,
+ gpio);
+ if (!gpio->domain)
+ return;
+
+ err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 1,
+ "gpio-dwapb", handle_level_irq,
+ IRQ_NOREQUEST, 0,
+ IRQ_GC_INIT_NESTED_LOCK);
+ if (err) {
+ dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
+ irq_domain_remove(gpio->domain);
+ gpio->domain = NULL;
+ return;
+ }
+
+ for (hwirq = 0 ; hwirq < ngpio ; hwirq++) {
+ irq_gc = irq_get_domain_generic_chip(gpio->domain, hwirq);
+ if (!irq_gc) {
+ irq_domain_remove(gpio->domain);
+ gpio->domain = NULL;
+ return;
+ }
+
+ irq_gc->reg_base = gpio->regs;
+ irq_gc->private = gpio;
+
+ ct = irq_gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack_set_bit;
+ ct->chip.irq_mask = irq_gc_mask_set_bit;
+ ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+ ct->chip.irq_set_type = dwapb_irq_set_type;
+ ct->chip.irq_enable = dwapb_irq_enable;
+ ct->chip.irq_disable = dwapb_irq_disable;
+ ct->regs.ack = GPIO_PORTA_EOI;
+ ct->regs.mask = GPIO_INTMASK;
+
+ irq_setup_generic_chip(irq_gc, IRQ_MSK(port->bgc.gc.ngpio),
+ IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
+
+ irq = irq_of_parse_and_map(node, hwirq);
+ if (!irq && (hwirq == 0)) {
+ dev_warn(gpio->dev, "no irq for bank %s\n",
+ port->bgc.gc.of_node->full_name);
+ return;
+ } else if (!irq)
+ break;
+
+ irq_set_chained_handler(irq, dwapb_irq_handler);
+ irq_set_handler_data(irq, gpio);
+ }
+ port->bgc.gc.to_irq = dwapb_gpio_to_irq;
+}
+
+static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
+{
+ struct dwapb_gpio_port *port = &gpio->ports[0];
+ struct gpio_chip *gc = &port->bgc.gc;
+ unsigned int ngpio = gc->ngpio;
+ irq_hw_number_t hwirq;
+
+ if (!gpio->domain)
+ return;
+
+ for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
+ irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
+
+ irq_domain_remove(gpio->domain);
+ gpio->domain = NULL;
+}
+
+static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
+ struct device_node *port_np,
+ unsigned int offs)
+{
+ struct dwapb_gpio_port *port;
+ u32 port_idx, ngpio;
+ void __iomem *dat, *set, *dirout;
+ int err;
+
+ if (of_property_read_u32(port_np, "reg", &port_idx) ||
+ port_idx >= DWAPB_MAX_PORTS) {
+ dev_err(gpio->dev, "missing/invalid port index for %s\n",
+ port_np->full_name);
+ return -EINVAL;
+ }
+
+ port = &gpio->ports[offs];
+ port->gpio = gpio;
+
+ if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
+ dev_info(gpio->dev, "failed to get number of gpios for %s\n",
+ port_np->full_name);
+ ngpio = 32;
+ }
+
+ dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
+ set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
+ dirout = gpio->regs + GPIO_SWPORTA_DDR +
+ (port_idx * GPIO_SWPORT_DDR_SIZE);
+
+ err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
+ NULL, false);
+ if (err) {
+ dev_err(gpio->dev, "failed to init gpio chip for %s\n",
+ port_np->full_name);
+ return err;
+ }
+
+ port->bgc.gc.ngpio = ngpio;
+ port->bgc.gc.of_node = port_np;
+
+ /*
+ * Only port A can provide interrupts in all configurations of the IP.
+ */
+ if (port_idx == 0 &&
+ of_property_read_bool(port_np, "interrupt-controller"))
+ dwapb_configure_irqs(gpio, port);
+
+ err = gpiochip_add(&port->bgc.gc);
+ if (err)
+ dev_err(gpio->dev, "failed to register gpiochip for %s\n",
+ port_np->full_name);
+ else
+ port->is_registered = true;
+
+ return err;
+}
+
+static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
+{
+ unsigned int m;
+
+ for (m = 0; m < gpio->nr_ports; ++m)
+ if (gpio->ports[m].is_registered)
+ WARN_ON(gpiochip_remove(&gpio->ports[m].bgc.gc));
+}
+
+static int dwapb_gpio_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct dwapb_gpio *gpio;
+ struct device_node *np;
+ int err;
+ unsigned int offs = 0;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+ gpio->dev = &pdev->dev;
+
+ gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
+ if (!gpio->nr_ports) {
+ err = -EINVAL;
+ goto out_err;
+ }
+ gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
+ sizeof(*gpio->ports), GFP_KERNEL);
+ if (!gpio->ports) {
+ err = -ENOMEM;
+ goto out_err;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ gpio->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(gpio->regs)) {
+ err = PTR_ERR(gpio->regs);
+ goto out_err;
+ }
+
+ for_each_child_of_node(pdev->dev.of_node, np) {
+ err = dwapb_gpio_add_port(gpio, np, offs++);
+ if (err)
+ goto out_unregister;
+ }
+ platform_set_drvdata(pdev, gpio);
+
+ return 0;
+
+out_unregister:
+ dwapb_gpio_unregister(gpio);
+ dwapb_irq_teardown(gpio);
+
+out_err:
+ return err;
+}
+
+static int dwapb_gpio_remove(struct platform_device *pdev)
+{
+ struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
+
+ dwapb_gpio_unregister(gpio);
+ dwapb_irq_teardown(gpio);
+
+ return 0;
+}
+
+static const struct of_device_id dwapb_of_match[] = {
+ { .compatible = "snps,dw-apb-gpio" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dwapb_of_match);
+
+static struct platform_driver dwapb_gpio_driver = {
+ .driver = {
+ .name = "gpio-dwapb",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(dwapb_of_match),
+ },
+ .probe = dwapb_gpio_probe,
+ .remove = dwapb_gpio_remove,
+};
+
+module_platform_driver(dwapb_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jamie Iles");
+MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
From: Lars-Peter Clausen @ 2014-02-06 15:53 UTC (permalink / raw)
To: Srikanth Thokala
Cc: Vinod Koul, dan.j.williams-ral2JQCrhuEAvxtiuMwx3w,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA, Grant Likely,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dmaengine-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CA+mB=1JX5K9Cu=9WGyr_e9tUtVz6ypT9UxhJU9BNJbQA9eaRKA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 02/06/2014 02:34 PM, Srikanth Thokala wrote:
> On Wed, Feb 5, 2014 at 10:00 PM, Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org> wrote:
>> On 02/05/2014 05:25 PM, Srikanth Thokala wrote:
>>>
>>> On Fri, Jan 31, 2014 at 12:21 PM, Srikanth Thokala <sthokal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>>> wrote:
>>>>
>>>> Hi Vinod,
>>>>
>>>> On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote:
>>>>>
>>>>> On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
>>>>>>
>>>>>> Hi Lars/Vinod,
>>>>>>>>
>>>>>>>> The question here i think would be waht this device supports? Is the
>>>>>>>> hardware
>>>>>>>> capable of doing interleaved transfers, then would make sense.
>>>>>>>
>>>>>>>
>>>>>>> The hardware does 2D transfers. The parameters for a transfer are
>>>>>>> height,
>>>>>>> width and stride. That's only a subset of what interleaved transfers
>>>>>>> can be
>>>>>>> (xt->num_frames must be one for 2d transfers). But if I remember
>>>>>>> correctly
>>>>>>> there has been some discussion on this in the past and the result of
>>>>>>> that
>>>>>>> discussion was that using interleaved transfers for 2D transfers is
>>>>>>> preferred over adding a custom API for 2D transfers.
>>>>>>
>>>>>>
>>>>>> I went through the prep_interleaved_dma API and I see only one
>>>>>> descriptor
>>>>>> is prepared per API call (i.e. per frame). As our IP supports upto 16
>>>>>> frame
>>>>>> buffers (can be more in future), isn't it less efficient compared to
>>>>>> the
>>>>>> prep_slave_sg where we get a single sg list and can prepare all the
>>>>>> descriptors
>>>>>> (of non-contiguous buffers) in one go? Correct me, if am wrong and let
>>>>>> me
>>>>>> know your opinions.
>>>>>
>>>>> Well the descriptor maybe one, but that can represent multiple frames,
>>>>> for
>>>>> example 16 as in your case. Can you read up the documentation of how
>>>>> multiple
>>>>> frames are passed. Pls see include/linux/dmaengine.h
>>>>>
>>>>> /**
>>>>> * Interleaved Transfer Request
>>>>> * ----------------------------
>>>>> * A chunk is collection of contiguous bytes to be transfered.
>>>>> * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
>>>>> * ICGs may or maynot change between chunks.
>>>>> * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
>>>>> * that when repeated an integral number of times, specifies the
>>>>> transfer.
>>>>> * A transfer template is specification of a Frame, the number of times
>>>>> * it is to be repeated and other per-transfer attributes.
>>>>> *
>>>>> * Practically, a client driver would have ready a template for each
>>>>> * type of transfer it is going to need during its lifetime and
>>>>> * set only 'src_start' and 'dst_start' before submitting the
>>>>> requests.
>>>>> *
>>>>> *
>>>>> * | Frame-1 | Frame-2 | ~ |
>>>>> Frame-'numf' |
>>>>> * |====....==.===...=...|====....==.===...=...| ~
>>>>> |====....==.===...=...|
>>>>> *
>>>>> * == Chunk size
>>>>> * ... ICG
>>>>> */
>>>>
>>>>
>>>> Yes, it can handle multiple frames specified by 'numf' each of size
>>>> 'frame_size * sgl[0].size'.
>>>> But, I see it only works if all the frames' memory is contiguous and
>>>> in this case we
>>>> can just increment 'src_start' by the total frame size 'numf' number
>>>> of times to fill in
>>>> for each HW descriptor (each frame is one HW descriptor). So, there
>>>> is no issue when the
>>>> memory is contiguous. If the frames are non contiguous, we have to
>>>> call this API for each
>>>> frame (hence for each descriptor), as the src_start for each frame is
>>>> different. Is it correct?
>>>>
>>>> FYI: This hardware has an inbuilt Scatter-Gather engine.
>>>>
>>>
>>> Ping?
>>
>>
>> If you want to submit multiple frames at once I think you should look at how
>> the current dmaengine API can be extended to allow that. And also provide an
>> explanation on how this is superior over submitting them one by one.
>
>
> Sure. I would start with explaning the current implementation of this driver.
>
> Using prep_slave_sg(), we can define multiple segments in a
> async_tx_descriptor where each frame is defined by a segment (a sg
> list entry). So, the slave device could DMA the data (of multiple
> frames) with a descriptor by calling tx_submit in a transaction i.e.,
>
> prep_slave_sg(16) -> tx_submit(1) -> interrupt (16 frames)
>
> Using interleaved_dma(), we could not divide into segments when we
> have scattered memory (for the reasons mentioned in above thread).
> This implies we are restricting the slave device to process frame by
> frame i.e.,
>
> interleaved_dma(1) -> tx_submit(1) -> interrupt -> interleaved_dma(2)
> -> tx_submit (2) -> interrupt -> ........ tx_submit(16) -> interrupt
>
The API allows you to create and submit multiple interleaved descriptors
before you have to issue them.
interleaved_dma(1) -> tx_submit(1) -> interleaved_dma(2) -> tx_submit(2) ->
... -> issue_pending() -> interrupt
> This implementation makes the hardware to wait until the next frame is
> submitted.
>
> To overcome this, I feel it would be a good option if we could extend
> interleaved_dma template to modify src_start/dest_start to be a
> pointer to an array of addresses. Here, number of addresses will be
> defined by numf. The other option would be to include scatterlist in
> the interleaved template. This way we can handle scattered memory
> using this API.
Each "frame" in a interleaved transfer describes a single line in your video
frame (size = width, icg = stride). numf is the number of lines per video
frame. So the suggested change does not make that much sense. If you want to
submit multiple video frames in one batch the best option is in my opinion
to allow to pass an array of dma_interleaved_template structs instead of a
single one.
- Lars
>
> Srikanth
>
>>
>> - Lars
>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at http://www.tux.org/lkml/
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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^ permalink raw reply
* Re: [PATCH v3 1/2] Documentation: Add GPIO reset binding to reset binding documentation
From: Philipp Zabel @ 2014-02-06 15:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Roger Quadros, Mark Rutland,
Maxime Ripard, Stephen Warren
In-Reply-To: <1389353136.5854.13.camel-/rZezPiN1rtR6QfukMTsflXZhhPuCNm+@public.gmane.org>
Hi Arnd,
Am Freitag, den 10.01.2014, 12:25 +0100 schrieb Philipp Zabel:
> Hi Arnd,
>
> Am Mittwoch, den 08.01.2014, 17:08 +0100 schrieb Arnd Bergmann:
> > On Wednesday 08 January 2014, Philipp Zabel wrote:
> > > += GPIO Reset consumers =
> > > +
> > > +For the common case of reset lines controlled by GPIOs, the GPIO binding
> > > +documented in devicetree/bindings/gpio/gpio.txt should be used:
> > > +
> > > +Required properties:
> > > +reset-gpios or Reset GPIO using standard GPIO bindings,
> > > +<name>-reset-gpios: optionally named to specify the reset line
> > > +
> > > +Optional properties:
> > > +reset-boot-asserted or Boolean. If set, the corresponding reset is
> > > +<name>-reset-boot-asserted: initially asserted and should be kept that way
> > > + until released by the driver.
> >
> > I don't get this one. Why would you use a different reset binding for the case
> > where the reset line is connected to the gpio controller rather than a
> > specialized reset controller?
> >
> > I was expecting to see the definition of a generic reset controller that
> > in turn uses gpio lines, like
> >
> >
> > reset {
> > compatible = "gpio-reset";
> > /* provides three reset lines through these GPIOs */
> > gpios = <&gpioA 1 &gpioB 7 <gpioD 17>;
> > #reset-cells = <1>;
> > };
> >
> > foo {
> > ...
> > resets = <&reset 0>; /* uses first reset line of the gpio-reset controller */
> > };
>
> That is what I initially proposed...
>
> > I realize it would be a little more verbose, but it also seems more
> > regular and wouldn't stand out from the rest of the reset interfaces.
>
> ... but it can also be argued that GPIO resets shouldn't stand out from
> other GPIOs.
>
> Mark Rutland spoke out against having a 'GPIO reset device' node in the
> device tree:
>
> http://comments.gmane.org/gmane.linux.drivers.devicetree/41596
>
> and I see his point. Using different bindings for reset controller IPs
> and for single GPIOs better describes the actual hardware and it is less
> Linux specific: it still allows an OS without gpio-reset framework to
> let each driver handle the GPIO itself.
>
> Also Stephen Warren pointed out that we'll have to support the existing
> GPIO bindings anyway: in the meantime there are a lot of GPIO resets in
> various device trees that use the GPIO bindings.
>
> regards
> Philipp
do you have further comments on this?
I'd like to request a pull of the changes in
http://git.pengutronix.de/?p=pza/linux.git;a=shortlog;h=refs/heads/reset/for_v3.15
and I wonder whether I should submit that now without the GPIO patches
or hold it back a bit and add them on top.
regards
Philipp
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^ permalink raw reply
* Re: [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Jason Cooper @ 2014-02-06 15:39 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland, devicetree, Ben Peddell, pawel.moll, Kumar Gala,
Ian Campbell, linux ARM
In-Reply-To: <1391634309-3123-5-git-send-email-andrew@lunn.ch>
+ devicetree ML, DT maintainers
On Wed, Feb 05, 2014 at 10:05:09PM +0100, Andrew Lunn wrote:
> Add device tree fragments and files to support many of the kirkwood
> based Synology NAS devices. This is a translation of the board setup
> file maintained by Ben Peddell <klightspeed@killerwolves.net>
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> Tested by Ben Peddell <klightspeed@killerwolves.net>
> cc: Ben Peddell <klightspeed@killerwolves.net>
> ---
>
> v2:
> Fix gpio's which should be gpo.
> Rebase onto v3-14-rc1
> Update RTC nodes with vendor name.
> Update SPI flash node with vendor name.
> ---
> arch/arm/boot/dts/Makefile | 15 ++++
> arch/arm/boot/dts/kirkwood-ds109.dts | 33 +++++++
> arch/arm/boot/dts/kirkwood-ds110jv10.dts | 33 +++++++
> arch/arm/boot/dts/kirkwood-ds111.dts | 33 +++++++
> arch/arm/boot/dts/kirkwood-ds112.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-ds209.dts | 33 +++++++
> arch/arm/boot/dts/kirkwood-ds210.dts | 35 ++++++++
> arch/arm/boot/dts/kirkwood-ds212.dts | 37 ++++++++
> arch/arm/boot/dts/kirkwood-ds212j.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-ds409.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-ds409slim.dts | 32 +++++++
> arch/arm/boot/dts/kirkwood-ds411.dts | 35 ++++++++
> arch/arm/boot/dts/kirkwood-ds411j.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-ds411slim.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-rs212.dts | 34 +++++++
> arch/arm/boot/dts/kirkwood-rs409.dts | 33 +++++++
> arch/arm/boot/dts/kirkwood-rs411.dts | 34 +++++++
> arch/arm/boot/dts/synology/alarm-led-12.dtsi | 28 ++++++
> arch/arm/boot/dts/synology/common.dtsi | 112 ++++++++++++++++++++++++
> arch/arm/boot/dts/synology/ethernet-1.dtsi | 15 ++++
> arch/arm/boot/dts/synology/fan-alarm-18.dtsi | 22 +++++
> arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi | 22 +++++
> arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi | 32 +++++++
> arch/arm/boot/dts/synology/fan-gpios-15.dtsi | 34 +++++++
> arch/arm/boot/dts/synology/fan-gpios-32.dtsi | 34 +++++++
> arch/arm/boot/dts/synology/fan-speed-100.dtsi | 20 +++++
> arch/arm/boot/dts/synology/fan-speed-120.dtsi | 20 +++++
> arch/arm/boot/dts/synology/fan-speed-150.dtsi | 20 +++++
> arch/arm/boot/dts/synology/hdd-leds-20.dtsi | 90 +++++++++++++++++++
> arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi | 36 ++++++++
> arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi | 52 +++++++++++
> arch/arm/boot/dts/synology/hdd-leds-36.dtsi | 103 ++++++++++++++++++++++
> arch/arm/boot/dts/synology/hdd-leds-38.dtsi | 52 +++++++++++
> arch/arm/boot/dts/synology/hdd-power-29.dtsi | 56 ++++++++++++
> arch/arm/boot/dts/synology/hdd-power-30-1.dtsi | 40 +++++++++
> arch/arm/boot/dts/synology/hdd-power-30-2.dtsi | 56 ++++++++++++
> arch/arm/boot/dts/synology/hdd-power-30-4.dtsi | 89 +++++++++++++++++++
> arch/arm/boot/dts/synology/hdd-power-31.dtsi | 40 +++++++++
> arch/arm/boot/dts/synology/hdd-power-34.dtsi | 73 +++++++++++++++
> arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi | 18 ++++
> arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi | 18 ++++
> arch/arm/boot/dts/synology/pcie-2.dtsi | 19 ++++
> 42 files changed, 1658 insertions(+)
> create mode 100644 arch/arm/boot/dts/kirkwood-ds109.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds110jv10.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds111.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds112.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds209.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds210.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds212.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds212j.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds409.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds409slim.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds411.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds411j.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-ds411slim.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-rs212.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-rs409.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-rs411.dts
> create mode 100644 arch/arm/boot/dts/synology/alarm-led-12.dtsi
> create mode 100644 arch/arm/boot/dts/synology/common.dtsi
> create mode 100644 arch/arm/boot/dts/synology/ethernet-1.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-18.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-gpios-15.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-gpios-32.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-speed-100.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-speed-120.dtsi
> create mode 100644 arch/arm/boot/dts/synology/fan-speed-150.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-20.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-36.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-38.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-29.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-1.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-2.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-4.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-31.dtsi
> create mode 100644 arch/arm/boot/dts/synology/hdd-power-34.dtsi
> create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi
> create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi
> create mode 100644 arch/arm/boot/dts/synology/pcie-2.dtsi
Holy sh*t! I know we're adding 15 boards, but this is, imho,
over-fragmenting. I'm sure there's a reason you chose this path, but
you haven't explained why in your commit log. So I'm left guessing...
thx,
Jason.
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b9d6a8b485e0..6cf3a54ef7f1 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -89,6 +89,18 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
> kirkwood-dns325.dtb \
> kirkwood-dockstar.dtb \
> kirkwood-dreamplug.dtb \
> + kirkwood-ds109.dtb \
> + kirkwood-ds110jv10.dtb \
> + kirkwood-ds111.dtb \
> + kirkwood-ds209.dtb \
> + kirkwood-ds210.dtb \
> + kirkwood-ds212.dtb \
> + kirkwood-ds212j.dtb \
> + kirkwood-ds409.dtb \
> + kirkwood-ds409slim.dtb \
> + kirkwood-ds411.dtb \
> + kirkwood-ds411j.dtb \
> + kirkwood-ds411slim.dtb \
> kirkwood-goflexnet.dtb \
> kirkwood-guruplug-server-plus.dtb \
> kirkwood-ib62x0.dtb \
> @@ -111,6 +123,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
> kirkwood-nsa310a.dtb \
> kirkwood-openblocks_a6.dtb \
> kirkwood-openblocks_a7.dtb \
> + kirkwood-rs212.dtb \
> + kirkwood-rs409.dtb \
> + kirkwood-rs411.dtb \
> kirkwood-sheevaplug.dtb \
> kirkwood-sheevaplug-esata.dtb \
> kirkwood-topkick.dtb \
> diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts
> new file mode 100644
> index 000000000000..bea085ad540a
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds109.dts
> @@ -0,0 +1,33 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-ricoh.dtsi"
> +#include "synology/fan-speed-150.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-1.dtsi"
> +
> +/ {
> + model = "Synology DS109, DS110, DS110jv20";
> + compatible = "synology,ds109", "synology,ds110jv20",
> + "synology,ds110", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
> new file mode 100644
> index 000000000000..d6b746952947
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
> @@ -0,0 +1,33 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-150.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-1.dtsi"
> +
> +/ {
> + model = "Synology DS110j v10 and v30";
> + compatible = "synology,ds110jv10", "synology,ds110jv30",
> + "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts
> new file mode 100644
> index 000000000000..5f51e088903f
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds111.dts
> @@ -0,0 +1,33 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-1.dtsi"
> +
> +/ {
> + model = "Synology DS111";
> + compatible = "synology,ds111", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
> new file mode 100644
> index 000000000000..cda3203a0824
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds112.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35.dtsi"
> +#include "synology/hdd-leds-21-2.dtsi"
> +#include "synology/hdd-power-30.dtsi"
> +
> +/ {
> + model = "Synology DS111";
> + compatible = "synology,ds111", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts
> new file mode 100644
> index 000000000000..b2ebb423e129
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds209.dts
> @@ -0,0 +1,33 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-ricoh.dtsi"
> +#include "synology/fan-speed-150.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-2.dtsi"
> +#include "synology/hdd-power-31.dtsi"
> +
> +/ {
> + model = "Synology DS209";
> + compatible = "synology,ds209", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts
> new file mode 100644
> index 000000000000..8623dd63f44d
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds210.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-150.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-2.dtsi"
> +#include "synology/hdd-power-31.dtsi"
> +
> +/ {
> + model = "Synology DS210 v10, v20, v30, DS211j";
> + compatible = "synology,ds210jv10", "synology,ds210jv20",
> + "synology,ds210jv30", "synology,ds211j",
> + "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts
> new file mode 100644
> index 000000000000..89e091ce2174
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds212.dts
> @@ -0,0 +1,37 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-2.dtsi"
> +#include "synology/hdd-power-30-2.dtsi"
> +
> +/ {
> + model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10";
> + compatible = "synology,ds212", "synology,ds212pv10",
> + "synology,ds212pv10", "synology,ds212pv20",
> + "synology,ds213airv10", "synology,ds213v10",
> + "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts
> new file mode 100644
> index 000000000000..ed14b7bb695e
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-21-2.dtsi"
> +#include "synology/hdd-power-29.dtsi"
> +
> +/ {
> + model = "Synology DS212j v10, v20";
> + compatible = "synology,ds212jv10", "synology,ds212jv20",
> + "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts
> new file mode 100644
> index 000000000000..7000de1add08
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds409.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-ricoh.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-120.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-18.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +#include "synology/alarm-led-12.dtsi"
> +
> +/ {
> + model = "Synology DS409, DS410j";
> + compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts
> new file mode 100644
> index 000000000000..0ba525a594f7
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-ricoh.dtsi"
> +#include "synology/fan-speed-120.dtsi"
> +#include "synology/fan-gpios-32.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-20.dtsi"
> +
> +/ {
> + model = "Synology 409slim";
> + compatible = "synology,ds409slim", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
> new file mode 100644
> index 000000000000..4c1ca8e85559
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds411.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +#include "synology/hdd-power-34.dtsi"
> +
> +/ {
> + model = "Synology DS411, DS413jv10";
> + compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts
> new file mode 100644
> index 000000000000..7f08a46ddabb
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-120.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-18.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +#include "synology/alarm-led-12.dtsi"
> +
> +/ {
> + model = "Synology DS411j";
> + compatible = "synology,ds411j", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts
> new file mode 100644
> index 000000000000..2e6d66f37002
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-1.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +
> +/ {
> + model = "Synology DS411slim";
> + compatible = "synology,ds411slim", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
> new file mode 100644
> index 000000000000..edc797464983
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-rs212.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-3.dtsi"
> +#include "synology/hdd-leds-38.dtsi"
> +#include "synology/hdd-power-30-2.dtsi"
> +
> +/ {
> + model = "Synology RS212";
> + compatible = "synology,rs212", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts
> new file mode 100644
> index 000000000000..906664a99602
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-rs409.dts
> @@ -0,0 +1,33 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6281.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-ricoh.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-120.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-18.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +
> +/ {
> + model = "Synology RS409";
> + compatible = "synology,rs409", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts
> new file mode 100644
> index 000000000000..75c806ea0dc9
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-rs411.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "kirkwood.dtsi"
> +#include "kirkwood-6282.dtsi"
> +#include "synology/pcie-2.dtsi"
> +#include "synology/common.dtsi"
> +#include "synology/i2c-rtc-seiko.dtsi"
> +#include "synology/ethernet-1.dtsi"
> +#include "synology/fan-speed-100.dtsi"
> +#include "synology/fan-gpios-15.dtsi"
> +#include "synology/fan-alarm-35-3.dtsi"
> +#include "synology/hdd-leds-36.dtsi"
> +
> +/ {
> + model = "Synology RS411 RS812";
> + compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8";
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/alarm-led-12.dtsi b/arch/arm/boot/dts/synology/alarm-led-12.dtsi
> new file mode 100644
> index 000000000000..e6ea8f07d1a5
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/alarm-led-12.dtsi
> @@ -0,0 +1,28 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_12: pmx-led-12 {
> + marvell,pins = "mpp12";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_12>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:alarm";
> + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/common.dtsi b/arch/arm/boot/dts/synology/common.dtsi
> new file mode 100644
> index 000000000000..fb078c4f9a62
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/common.dtsi
> @@ -0,0 +1,112 @@
> +/*
> + * Nodes which are common to all Synology devices
> + *
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + mbus {
> + pcie-controller {
> + status = "okay";
> +
> + pcie@1,0 {
> + status = "okay";
> + };
> + };
> + };
> + ocp@f1000000 {
> + i2c@11000 {
> + status = "okay";
> + clock-frequency = <400000>;
> + pinctrl-0 = <&pmx_twsi0>;
> + pinctrl-names = "default";
> + };
> + serial@12000 {
> + status = "okay";
> + pinctrl-0 = <&pmx_uart0>;
> + pinctrl-names = "default";
> + };
> + serial@12100 {
> + status = "okay";
> + pinctrl-0 = <&pmx_uart1>;
> + pinctrl-names = "default";
> + };
> + poweroff@12100 {
> + compatible = "synology,power-off";
> + reg = <0x12000 0x100>;
> + clocks = <&gate_clk 7>;
> + };
> + spi@10600 {
> + status = "okay";
> + pinctrl-0 = <&pmx_spi>;
> + pinctrl-names = "default";
> +
> + m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,m25p80";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + mode = <0>;
> +
> + partition@00000000 {
> + reg = <0x00000000 0x00080000>;
> + label = "RedBoot";
> + };
> +
> + partition@00080000 {
> + reg = <0x00080000 0x00200000>;
> + label = "zImage";
> + };
> +
> + partition@00280000 {
> + reg = <0x00280000 0x00140000>;
> + label = "rd.gz";
> + };
> + partition@003c0000 {
> + reg = <0x003c0000 0x00010000>;
> + label = "vendor";
> + };
> + partition@003d0000 {
> + reg = <0x003d0000 0x00020000>;
> + label = "RedBoot config";
> + };
> + partition@003f0000 {
> + reg = <0x003f0000 0x00010000>;
> + label = "FIS directory";
> + };
> + };
> + };
> + sata@80000 {
> + pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
> + pinctrl-names = "default";
> + status = "okay";
> + nr-ports = <2>;
> + };
> + };
> + gpio_fan {
> + compatible = "gpio-fan";
> + };
> +};
> +
> +&mdio {
> + status = "okay";
> +
> + ethphy0: ethernet-phy {
> + device_type = "ethernet-phy";
> + reg = <8>;
> + };
> +};
> +
> +ð0 {
> + status = "okay";
> + ethernet0-port@0 {
> + phy-handle = <ðphy0>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/ethernet-1.dtsi b/arch/arm/boot/dts/synology/ethernet-1.dtsi
> new file mode 100644
> index 000000000000..bf00eff53bbc
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/ethernet-1.dtsi
> @@ -0,0 +1,15 @@
> +&mdio {
> + status = "okay";
> +
> + ethphy1: ethernet-phy {
> + device_type = "ethernet-phy";
> + reg = <9>;
> + };
> +};
> +
> +ð0 {
> + status = "okay";
> + ethernet1-port@0 {
> + phy-handle = <ðphy1>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-alarm-18.dtsi b/arch/arm/boot/dts/synology/fan-alarm-18.dtsi
> new file mode 100644
> index 000000000000..d323eb0d2109
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-alarm-18.dtsi
> @@ -0,0 +1,22 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_fan_18: pmx-fan-18 {
> + marvell,pins = "mpp18";
> + marvell,function = "gpo";
> + };
> + };
> + };
> + gpio_fan {
> + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi b/arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi
> new file mode 100644
> index 000000000000..12e52fdae870
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi
> @@ -0,0 +1,22 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_fan_35: pmx-fan-35 {
> + marvell,pins = "mpp35";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio_fan {
> + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi b/arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi
> new file mode 100644
> index 000000000000..e2a44f402bf0
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi
> @@ -0,0 +1,32 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_fan_35: pmx-fan-35 {
> + marvell,pins = "mpp35";
> + marvell,function = "gpio";
> + };
> + pmx_fan_44: pmx-fan-44 {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> + pmx_fan_45: pmx-fan-45 {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio_fan {
> + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
> + &gpio1 12 GPIO_ACTIVE_HIGH
> + &gpio1 13 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-gpios-15.dtsi b/arch/arm/boot/dts/synology/fan-gpios-15.dtsi
> new file mode 100644
> index 000000000000..e27cba942eed
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-gpios-15.dtsi
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_fan_15: pmx-fan-15 {
> + marvell,pins = "mpp15";
> + marvell,function = "gpio";
> + };
> + pmx_fan_16: pmx-fan-16 {
> + marvell,pins = "mpp16";
> + marvell,function = "gpio";
> + };
> + pmx_fan_17: pmx-fan-17 {
> + marvell,pins = "mpp17";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio_fan {
> + pinctrl-0 = <&pmx_fan_15 &pmx_fan_16 &pmx_fan_17>;
> + pinctrl-names = "default";
> + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
> + &gpio0 16 GPIO_ACTIVE_HIGH
> + &gpio0 17 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-gpios-32.dtsi b/arch/arm/boot/dts/synology/fan-gpios-32.dtsi
> new file mode 100644
> index 000000000000..d4fd393e71a8
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-gpios-32.dtsi
> @@ -0,0 +1,34 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_fan_32: pmx-fan-32 {
> + marvell,pins = "mpp32";
> + marvell,function = "gpio";
> + };
> + pmx_fan_33: pmx-fan-33 {
> + marvell,pins = "mpp33";
> + marvell,function = "gpo";
> + };
> + pmx_fan_34: pmx-fan-34 {
> + marvell,pins = "mpp34";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio_fan {
> + pinctrl-0 = <&pmx_fan_32 &pmx_fan_33 &pmx_fan_34>;
> + pinctrl-names = "default";
> + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
> + &gpio1 1 GPIO_ACTIVE_HIGH
> + &gpio1 2 GPIO_ACTIVE_HIGH>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/synology/fan-speed-100.dtsi b/arch/arm/boot/dts/synology/fan-speed-100.dtsi
> new file mode 100644
> index 000000000000..5188ba59a9b2
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-speed-100.dtsi
> @@ -0,0 +1,20 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + gpio_fan {
> + gpio-fan,speed-map = < 0 0
> + 2500 1
> + 3100 2
> + 3800 3
> + 4600 4
> + 4800 5
> + 4900 6
> + 5000 7 >;
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/fan-speed-120.dtsi b/arch/arm/boot/dts/synology/fan-speed-120.dtsi
> new file mode 100644
> index 000000000000..90157070492c
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-speed-120.dtsi
> @@ -0,0 +1,20 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + gpio_fan {
> + gpio-fan,speed-map = < 0 0
> + 2500 1
> + 2700 2
> + 3000 4
> + 3600 3
> + 3800 5
> + 3900 6
> + 4300 7 >;
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/fan-speed-150.dtsi b/arch/arm/boot/dts/synology/fan-speed-150.dtsi
> new file mode 100644
> index 000000000000..6abc36915886
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/fan-speed-150.dtsi
> @@ -0,0 +1,20 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + gpio_fan {
> + gpio-fan,speed-map = < 0 0
> + 2200 1
> + 2500 2
> + 3000 4
> + 3300 3
> + 3700 5
> + 3800 6
> + 4200 7 >;
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-leds-20.dtsi b/arch/arm/boot/dts/synology/hdd-leds-20.dtsi
> new file mode 100644
> index 000000000000..e6663ea7014c
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-leds-20.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_20: pmx-led-20 {
> + marvell,pins = "mpp20";
> + marvell,function = "gpio";
> + };
> + pmx_led_21: pmx-led-21 {
> + marvell,pins = "mpp21";
> + marvell,function = "gpio";
> + };
> + pmx_led_22: pmx-led-22 {
> + marvell,pins = "mpp22";
> + marvell,function = "gpio";
> + };
> + pmx_led_23: pmx-led-23 {
> + marvell,pins = "mpp23";
> + marvell,function = "gpio";
> + };
> + pmx_led_24: pmx-led-24 {
> + marvell,pins = "mpp24";
> + marvell,function = "gpio";
> + };
> + pmx_led_25: pmx-led-25 {
> + marvell,pins = "mpp25";
> + marvell,function = "gpio";
> + };
> + pmx_led_26: pmx-led-26 {
> + marvell,pins = "mpp26";
> + marvell,function = "gpio";
> + };
> + pmx_led_27: pmx-led-27 {
> + marvell,pins = "mpp27";
> + marvell,function = "gpio";
> + };
> + pmx_led_28: pmx-led-28 {
> + marvell,pins = "mpp28";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_20 &pmx_led_21 &pmx_led_22
> + &pmx_led_23 &pmx_led_24 &pmx_led_25
> + &pmx_led_26 &pmx_led_27>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:green:hdd1";
> + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> + };
> + hdd1-amber {
> + label = "synology:amber:hdd1";
> + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-green {
> + label = "synology:green:hdd2";
> + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-amber {
> + label = "synology:amber:hdd2";
> + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
> + };
> + hdd3-green {
> + label = "synology:green:hdd3";
> + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
> + };
> + hdd3-amber {
> + label = "synology:amber:hdd3";
> + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
> + };
> + hdd4-green {
> + label = "synology:green:hdd4";
> + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
> + };
> + hdd4-amber {
> + label = "synology:amber:hdd4";
> + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi b/arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi
> new file mode 100644
> index 000000000000..034323f9ffb0
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi
> @@ -0,0 +1,36 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_21: pmx-led-21 {
> + marvell,pins = "mpp21";
> + marvell,function = "gpio";
> + };
> + pmx_led_23: pmx-led-23 {
> + marvell,pins = "mpp23";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_21 &pmx_led_23>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:green:hdd1";
> + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
> + };
> + hdd1-amber {
> + label = "synology:amber:hdd1";
> + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi b/arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi
> new file mode 100644
> index 000000000000..446a28f2200b
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi
> @@ -0,0 +1,52 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_20: pmx-led-20 {
> + marvell,pins = "mpp20";
> + marvell,function = "gpio";
> + };
> + pmx_led_21: pmx-led-21 {
> + marvell,pins = "mpp21";
> + marvell,function = "gpio";
> + };
> + pmx_led_22: pmx-led-22 {
> + marvell,pins = "mpp22";
> + marvell,function = "gpio";
> + };
> + pmx_led_23: pmx-led-23 {
> + marvell,pins = "mpp23";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_21 &pmx_led_23 &pmx_led_20 &pmx_led_22>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:green:hdd1";
> + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
> + };
> + hdd1-amber {
> + label = "synology:amber:hdd1";
> + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-green {
> + label = "synology:green:hdd2";
> + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-amber {
> + label = "synology:amber:hdd2";
> + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-leds-36.dtsi b/arch/arm/boot/dts/synology/hdd-leds-36.dtsi
> new file mode 100644
> index 000000000000..9541c0c943e6
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-leds-36.dtsi
> @@ -0,0 +1,103 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_36: pmx-led-36 {
> + marvell,pins = "mpp36";
> + marvell,function = "gpio";
> + };
> + pmx_led_37: pmx-led-37 {
> + marvell,pins = "mpp37";
> + marvell,function = "gpio";
> + };
> + pmx_led_38: pmx-led-38 {
> + marvell,pins = "mpp38";
> + marvell,function = "gpio";
> + };
> + pmx_led_39: pmx-led-39 {
> + marvell,pins = "mpp39";
> + marvell,function = "gpio";
> + };
> + pmx_led_40: pmx-led-40 {
> + marvell,pins = "mpp40";
> + marvell,function = "gpio";
> + };
> + pmx_led_41: pmx-led-41 {
> + marvell,pins = "mpp41";
> + marvell,function = "gpio";
> + };
> + pmx_led_42: pmx-led-42 {
> + marvell,pins = "mpp42";
> + marvell,function = "gpio";
> + };
> + pmx_led_43: pmx-led-43 {
> + marvell,pins = "mpp43";
> + marvell,function = "gpio";
> + };
> + pmx_led_44: pmx-led-44 {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> + pmx_led_45: pmx-led-45 {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_36 &pmx_led_37 &pmx_led_38
> + &pmx_led_39 &pmx_led_40 &pmx_led_41
> + &pmx_led_42 &pmx_led_43 &pmx_led_44
> + &pmx_led_45>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:green:hdd1";
> + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + };
> + hdd1-amber {
> + label = "synology:amber:hdd1";
> + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-green {
> + label = "synology:green:hdd2";
> + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-amber {
> + label = "synology:amber:hdd2";
> + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> + };
> + hdd3-green {
> + label = "synology:green:hdd3";
> + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> + };
> + hdd3-amber {
> + label = "synology:amber:hdd3";
> + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> + };
> + hdd4-green {
> + label = "synology:green:hdd4";
> + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + };
> + hdd4-amber {
> + label = "synology:amber:hdd4";
> + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> + };
> + hdd5-green {
> + label = "synology:green:hdd5";
> + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
> + };
> + hdd5-amber {
> + label = "synology:amber:hdd5";
> + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-leds-38.dtsi b/arch/arm/boot/dts/synology/hdd-leds-38.dtsi
> new file mode 100644
> index 000000000000..d2fe351a0808
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-leds-38.dtsi
> @@ -0,0 +1,52 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_led_38: pmx-led-38 {
> + marvell,pins = "mpp38";
> + marvell,function = "gpio";
> + };
> + pmx_led_39: pmx-led-39 {
> + marvell,pins = "mpp39";
> + marvell,function = "gpio";
> + };
> + pmx_led_36: pmx-led-36 {
> + marvell,pins = "mpp36";
> + marvell,function = "gpio";
> + };
> + pmx_led_37: pmx-led-37 {
> + marvell,pins = "mpp37";
> + marvell,function = "gpio";
> + };
> + };
> + };
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pmx_led_38 &pmx_led_39 &pmx_led_36 &pmx_led_37>;
> + pinctrl-names = "default";
> + hdd1-green {
> + label = "synology:green:hdd1";
> + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
> + };
> + hdd1-amber {
> + label = "synology:amber:hdd1";
> + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-green {
> + label = "synology:green:hdd2";
> + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + };
> + hdd2-amber {
> + label = "synology:amber:hdd2";
> + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-29.dtsi b/arch/arm/boot/dts/synology/hdd-power-29.dtsi
> new file mode 100644
> index 000000000000..8b08c86ab942
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-29.dtsi
> @@ -0,0 +1,56 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
> + marvell,pins = "mpp29";
> + marvell,function = "gpio";
> + };
> + pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
> + marvell,pins = "mpp31";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
> + pinctrl-names = "default";
> +
> + hdd1_power: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "hdd1power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
> + };
> + hdd2_power: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "hdd2power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-30-1.dtsi b/arch/arm/boot/dts/synology/hdd-power-30-1.dtsi
> new file mode 100644
> index 000000000000..b0998d4e231f
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-30-1.dtsi
> @@ -0,0 +1,40 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
> + marvell,pins = "mpp30";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd1_pwr_30>;
> + pinctrl-names = "default";
> +
> + hdd1_power: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "hdd1power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-30-2.dtsi b/arch/arm/boot/dts/synology/hdd-power-30-2.dtsi
> new file mode 100644
> index 000000000000..766e6352d5af
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-30-2.dtsi
> @@ -0,0 +1,56 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
> + marvell,pins = "mpp30";
> + marvell,function = "gpio";
> + };
> + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
> + marvell,pins = "mpp34";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
> + pinctrl-names = "default";
> +
> + hdd1_power: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "hdd1power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
> + };
> + hdd2_power: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "hdd2power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-30-4.dtsi b/arch/arm/boot/dts/synology/hdd-power-30-4.dtsi
> new file mode 100644
> index 000000000000..5bbced207965
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-30-4.dtsi
> @@ -0,0 +1,89 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
> + marvell,pins = "mpp30";
> + marvell,function = "gpio";
> + };
> + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
> + marvell,pins = "mpp34";
> + marvell,function = "gpio";
> + };
> + pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> + pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
> + &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
> + pinctrl-names = "default";
> +
> + hdd1_power: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "hdd1power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
> + };
> + hdd2_power: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "hdd2power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
> + };
> + hdd3_power: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "hdd3power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> + };
> + hdd4_power: regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "hdd3power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 32 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-31.dtsi b/arch/arm/boot/dts/synology/hdd-power-31.dtsi
> new file mode 100644
> index 000000000000..0774ecdcaf64
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-31.dtsi
> @@ -0,0 +1,40 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
> + marvell,pins = "mpp31";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd2_pwr_31>;
> + pinctrl-names = "default";
> +
> + hdd2_power: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "hdd2power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/hdd-power-34.dtsi b/arch/arm/boot/dts/synology/hdd-power-34.dtsi
> new file mode 100644
> index 000000000000..d90becf582f1
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/hdd-power-34.dtsi
> @@ -0,0 +1,73 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + pinctrl: pinctrl@10000 {
> +
> + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
> + marvell,pins = "mpp34";
> + marvell,function = "gpio";
> + };
> + pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> + pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
> + &pmx_hdd4_pwr_45>;
> + pinctrl-names = "default";
> +
> + hdd2_power: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "hdd2power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
> + };
> + hdd3_power: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "hdd3power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> + };
> + hdd4_power: regulator@4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "hdd3power";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + startup-delay-us = <5000000>;
> + gpio = <&gpio1 32 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi b/arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi
> new file mode 100644
> index 000000000000..920ad215462d
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi
> @@ -0,0 +1,18 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + i2c@11000 {
> + rs5c372: rs5c372@32 {
> + compatible = "ricoh,rs5c372a";
> + reg = <0x32>;
> + };
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi b/arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi
> new file mode 100644
> index 000000000000..4b5054bb4a87
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi
> @@ -0,0 +1,18 @@
> +/*
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + ocp@f1000000 {
> + i2c@11000 {
> + s35390a: s35390a@30 {
> + compatible = "sii,s35390a";
> + reg = <0x30>;
> + };
> + };
> + };
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/synology/pcie-2.dtsi b/arch/arm/boot/dts/synology/pcie-2.dtsi
> new file mode 100644
> index 000000000000..e34ebb5515c2
> --- /dev/null
> +++ b/arch/arm/boot/dts/synology/pcie-2.dtsi
> @@ -0,0 +1,19 @@
> +/*
> + * Nodes which are common to all Synology devices
> + *
> + * Andrew Lunn <andrew@lunn.ch>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/ {
> + mbus {
> + pcie-controller {
> + pcie@2,0 {
> + status = "okay";
> + };
> + };
> + };
> +};
> \ No newline at end of file
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: MSM8974: Add pinctrl node
From: Ivan T. Ivanov @ 2014-02-06 15:28 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King
Cc: Ivan T. Ivanov, devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <1391700529-11816-1-git-send-email-iivanov@mm-sol.com>
From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Add the pin control node and pin definitions of SPI8.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9e5dadb..395603f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -117,5 +117,34 @@
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
+
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8974-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 208 0>;
+
+ spi8_default: spi8_default {
+ mosi {
+ pins = "gpio45";
+ function = "blsp_spi8";
+ };
+ miso {
+ pins = "gpio46";
+ function = "blsp_spi8";
+ };
+ cs {
+ pins = "gpio47";
+ function = "blsp_spi8";
+ };
+ clk {
+ pins = "gpio48";
+ function = "blsp_spi8";
+ };
+ };
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH 3/4] DT: i2c: Trivial: Add sii,s35390a
From: Jason Cooper @ 2014-02-06 15:21 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
pawel.moll-5wv7dgnIgG8, Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <1391634309-3123-4-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org>
+ devicetree ML, DT maintainers
On Wed, Feb 05, 2014 at 10:05:08PM +0100, Andrew Lunn wrote:
> Add the Seiko Instruments Inc S35390a to the list of trivial i2c
> devices.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> ---
> Documentation/devicetree/bindings/i2c/trivial-devices.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
thx,
Jason.
> diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
> index 1a1ac2e560e9..e11ed0fe770c 100644
> --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
> +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
> @@ -58,6 +58,7 @@ plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
> ramtron,24c64 i2c serial eeprom (24cxx)
> ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
> samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
> +sii,s35390a 2-wire CMOS real-time clock
> st-micro,24c256 i2c serial eeprom (24cxx)
> stm,m41t00 Serial Access TIMEKEEPER
> stm,m41t62 Serial real-time clock (RTC) with alarm
> --
> 1.7.10.4
>
--
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^ permalink raw reply
* Re: [PATCH 2/4] DT: Vendor prefixes: Add ricoh, ssi and synology
From: Jason Cooper @ 2014-02-06 15:19 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
pawel.moll-5wv7dgnIgG8, Mark Rutland, Ian Campbell, Kumar Gala
In-Reply-To: <1391634309-3123-3-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org>
+ devicetree ML, DT maintainers.
On Wed, Feb 05, 2014 at 10:05:07PM +0100, Andrew Lunn wrote:
> The following patches make use of vendor names ricoh, ssi and
> synology. Add them to the vendor prefix list.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 3f900cd51bf0..1629e8f33578 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -69,6 +69,7 @@ ralink Mediatek/Ralink Technology Corp.
> ramtron Ramtron International
> realtek Realtek Semiconductor Corp.
> renesas Renesas Electronics Corporation
> +ricoh Richoh Co. Ltd.
s/Richoh/Ricoh/
other than that,
Acked-by: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
thx,
Jason.
> rockchip Fuzhou Rockchip Electronics Co., Ltd
> samsung Samsung Semiconductor
> sbs Smart Battery System
> @@ -76,11 +77,13 @@ schindler Schindler
> sil Silicon Image
> silabs Silicon Laboratories
> simtek
> +sii Seiko Instruments, Inc.
> sirf SiRF Technology, Inc.
> snps Synopsys, Inc.
> st STMicroelectronics
> ste ST-Ericsson
> stericsson ST-Ericsson
> +synology Synology, Inc.
> ti Texas Instruments
> tlm Trusted Logic Mobility
> toshiba Toshiba Corporation
> --
> 1.7.10.4
>
--
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^ permalink raw reply
* [PATCH] Documentation: leds: common.txt: Fix reference to where "default-state" is explained
From: Fabio Estevam @ 2014-02-06 15:18 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
festevam-Re5JQEeQqe8AvxtiuMwx3w, Fabio Estevam
Documentation/devicetree/bindings/gpio/led.txt no longer exists, so update the
reference to the correct file where the "default-state" properly is explained.
Signed-off-by: Fabio Estevam <fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
Documentation/devicetree/bindings/leds/common.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
index 2d88816..fa08a65 100644
--- a/Documentation/devicetree/bindings/leds/common.txt
+++ b/Documentation/devicetree/bindings/leds/common.txt
@@ -9,7 +9,8 @@ Optional properties for child nodes:
"backlight" - LED will act as a back-light, controlled by the framebuffer
system
"default-on" - LED will turn on (but for leds-gpio see "default-state"
- property in Documentation/devicetree/bindings/gpio/led.txt)
+ property in:
+ Documentation/devicetree/bindings/leds/leds-gpio.txt)
"heartbeat" - LED "double" flashes at a load average based rate
"ide-disk" - LED indicates disk activity
"timer" - LED flashes at a fixed, configurable rate
--
1.8.1.2
--
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^ permalink raw reply related
* Re: Disabling autoneg and enforcing speed/duplex
From: Gerlando Falauto @ 2014-02-06 15:00 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org, Grant Likely,
Sebastian Hesselbarth, Brunck, Holger
In-Reply-To: <CAL_JsqJ=Me+MKF8DGMsh=0y4VLmekUHD7KgmQDkCpDEuKVOT+w@mail.gmail.com>
Hi Rob,
thanks for your reply.
On 02/06/2014 03:50 PM, Rob Herring wrote:
> On Thu, Feb 6, 2014 at 6:00 AM, Gerlando Falauto
> <gerlando.falauto@keymile.com> wrote:
>> Hi,
>>
>> I'm using the Kirkwood Ethernet controller (mv643xx_eth.c) with a Marvell
>> 88E3018 PHY which needs to be set in forced 100Base-TX mode.
>>
>> Thanks to Sebastian's addition of DT support to the ethernet driver, I can
>> easily set speed and duplex within the ethernet's port node, therefore
>> leaving the phy unmanaged -- this works fine (I guess this mode is set on
>> the phy by the bootloader or by strap settings).
>>
>> However, this PHY has an erratum whose workaround requires some registers be
>> written -- I believe the natural solution would be to start managing the PHY
>> (i.e. set "phy-handle") and implement the proper workaround within
>> drivers/net/phy/marvell.c. Making the PHY managed does however enable
>> autoneg and therefore break everything.
>>
>> Which brings me to my question: shouldn't there be a way to specify some
>> forced settings within the PHY's node for such cases?
>>
>> Only thing I found vaguely resembling what I'm looking for is Florian's
>> patch introducing "max-speed" in the PHY -- not quite the same thing though.
>> Which, if I understand it correctly, implements it as a property of the PHY,
>> whereas ePAPR specifies it as a property of the ethernet device (which makes
>> sense, since you might want to connect a 10/100 MII to a 10/100/1000 PHY and
>> therefore have the MII restrict the capabilities of the PHY).
>
> You shouldn't need a property in this case. The driver knows what the
> h/w is limited to and can configure the phy based on that.
I see, you're right.
> It is when
> both sides should support a higher speed and you need to limit it for
> some other reason like errata or board level configuration.
Which is exactly my case. The phy should be configured to work in
100Base-TX mode, full duplex.
>> Or perhaps I'm missing some important bits here?
>
> Does this patch help you:
>
> https://lkml.org/lkml/2014/1/15/533
I think so... So I guess I should jest set all
phy-mii-advertise-10full = <0>;
...
phy-mii-advertise-100full = <1>;
...
is that right?
I'll test it and let you know.
Thanks!
Gerlando
>
> Rob
>
>>
>> Thanks!
>> Gerlando
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: Disabling autoneg and enforcing speed/duplex
From: Rob Herring @ 2014-02-06 14:50 UTC (permalink / raw)
To: Gerlando Falauto
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Grant Likely,
Sebastian Hesselbarth, Brunck, Holger
In-Reply-To: <52F3796B.8050809-SkAbAL50j+5BDgjK7y7TUQ@public.gmane.org>
On Thu, Feb 6, 2014 at 6:00 AM, Gerlando Falauto
<gerlando.falauto-SkAbAL50j+5BDgjK7y7TUQ@public.gmane.org> wrote:
> Hi,
>
> I'm using the Kirkwood Ethernet controller (mv643xx_eth.c) with a Marvell
> 88E3018 PHY which needs to be set in forced 100Base-TX mode.
>
> Thanks to Sebastian's addition of DT support to the ethernet driver, I can
> easily set speed and duplex within the ethernet's port node, therefore
> leaving the phy unmanaged -- this works fine (I guess this mode is set on
> the phy by the bootloader or by strap settings).
>
> However, this PHY has an erratum whose workaround requires some registers be
> written -- I believe the natural solution would be to start managing the PHY
> (i.e. set "phy-handle") and implement the proper workaround within
> drivers/net/phy/marvell.c. Making the PHY managed does however enable
> autoneg and therefore break everything.
>
> Which brings me to my question: shouldn't there be a way to specify some
> forced settings within the PHY's node for such cases?
>
> Only thing I found vaguely resembling what I'm looking for is Florian's
> patch introducing "max-speed" in the PHY -- not quite the same thing though.
> Which, if I understand it correctly, implements it as a property of the PHY,
> whereas ePAPR specifies it as a property of the ethernet device (which makes
> sense, since you might want to connect a 10/100 MII to a 10/100/1000 PHY and
> therefore have the MII restrict the capabilities of the PHY).
You shouldn't need a property in this case. The driver knows what the
h/w is limited to and can configure the phy based on that. It is when
both sides should support a higher speed and you need to limit it for
some other reason like errata or board level configuration.
> Or perhaps I'm missing some important bits here?
Does this patch help you:
https://lkml.org/lkml/2014/1/15/533
Rob
>
> Thanks!
> Gerlando
> --
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^ permalink raw reply
* Re: [PATCH 5/9 v5] clk: samsung exynos5250/5420: Add gate clock for SSS module
From: Tomasz Figa @ 2014-02-06 14:43 UTC (permalink / raw)
To: Naveen Krishna Chatradhi, linux-crypto, linux-samsung-soc
Cc: linux-kernel, vzapolskiy, herbert, naveenkrishna.ch, cpgs,
devicetree, Kukjin Kim
In-Reply-To: <1390987446-18784-1-git-send-email-ch.naveen@samsung.com>
Hi Naveen,
On 29.01.2014 10:24, Naveen Krishna Chatradhi wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250/5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> TO: <linux-samsung-soc@vger.kernel.org>
> TO: Tomasz Figa <t.figa@samsung.com>
> CC: Kukjin Kim <kgene.kim@samsung.com>
> CC: <linux-crypto@vger.kernel.org>
> ---
> Changes since v4:
> Use register GATE_IP_G2D instead of GATE_BUS_G2D for Exynos5420
> Changes since v3:
> 1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> 2. Added new ID for SSS clock on Exynos5250, with Documentation and
> 3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
> .../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
> drivers/clk/samsung/clk-exynos5250.c | 1 +
> drivers/clk/samsung/clk-exynos5420.c | 4 ++++
> include/dt-bindings/clock/exynos5250.h | 1 +
> 4 files changed, 7 insertions(+)
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH 4/9 v5] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
From: Tomasz Figa @ 2014-02-06 14:41 UTC (permalink / raw)
To: Naveen Krishna Chatradhi, linux-crypto, linux-samsung-soc
Cc: linux-kernel, vzapolskiy, herbert, naveenkrishna.ch, cpgs,
devicetree, David S. Miller
In-Reply-To: <1390987354-18665-1-git-send-email-ch.naveen@samsung.com>
Hi Naveen,
On 29.01.2014 10:22, Naveen Krishna Chatradhi wrote:
> From: Naveen Krishna Ch <ch.naveen@samsung.com>
>
> This patch modifies Kconfig such that ARCH_EXYNOS SoCs
> which includes (Exynos4210, Exynos5250 and Exynos5420)
> can also select Samsung SSS(Security SubSystem) driver.
>
> Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
> CC: Herbert Xu <herbert@gondor.apana.org.au>
> CC: David S. Miller <davem@davemloft.net>
> CC: Vladimir Zapolskiy <vzapolskiy@gmail.com>
> TO: <linux-crypto@vger.kernel.org>
> CC: <linux-samsung-soc@vger.kernel.org>
> ---
> Changes since v4:
> none
> Changes since v3:
> Modified description to use "Exynos" instead of individual SoC name
> drivers/crypto/Kconfig | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH v2 06/15] dt: binding: add binding for ImgTec IR block
From: James Hogan @ 2014-02-06 14:41 UTC (permalink / raw)
To: Rob Herring
Cc: Mauro Carvalho Chehab, linux-media, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org, Rob Landley,
linux-doc@vger.kernel.org, Tomasz Figa
In-Reply-To: <CAL_Jsq+wk6_9Da5Xj3Ys-MZYPTpu6V3pAEpGFv44148BodmmrQ@mail.gmail.com>
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Hi Rob,
On 06/02/14 14:33, Rob Herring wrote:
> On Fri, Jan 17, 2014 at 7:58 AM, James Hogan <james.hogan@imgtec.com> wrote:
>> +Required properties:
>> +- compatible: Should be "img,ir1"
>
> Kind of short for a name. I don't have anything much better, but how
> about img,ir-rev1.
Okay, that sounds reasonable.
>> +Optional properties:
>> +- clocks: List of clock specifiers as described in standard
>> + clock bindings.
>> +- clock-names: List of clock names corresponding to the clocks
>> + specified in the clocks property.
>> + Accepted clock names are:
>> + "core": Core clock (defaults to 32.768KHz if omitted).
>> + "sys": System side (fast) clock.
>> + "mod": Power modulation clock.
>
> You need to define the order of clocks including how they are
> interpreted with different number of clocks (not relying on the name).
Would it be sufficient to specify that "clock-names" is required if
"clocks" is provided (i.e. unnamed clocks aren't used), or is there some
other reason that clock-names shouldn't be relied upon?
Thanks for reviewing,
Cheers
James
> Although, if the h/w block really has different number of clock
> inputs, then it is a different h/w block and should have a different
> compatible string.
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^ permalink raw reply
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