* [PATCH 1/7] Documentation: devicetree: fix up pl011 clocks
From: Mark Rutland @ 2014-02-11 11:37 UTC (permalink / raw)
To: devicetree
Cc: Mark Rutland, Russell King, pawel.moll, Arnd Bergmann, robh+dt,
linux-arm-kernel
In-Reply-To: <1392118632-11312-1-git-send-email-mark.rutland@arm.com>
The "arm,pl011" device tree binding only describes the apb_pclk clock
input, which is not sufficient to use the device. Knowledge of the
uartclk clock input is required to be able to change the baud rate, as
the baud rate is derived from the reference uartclk input. On systems
where the uartclk input is not initially enabled, it is also required to
use the device in any fashion.
This patch adds the uartclk input to the pl011 device tree binding. The
clock-names property is also described, as it is an implied requirement
of the primecell binding the pl011 binding is derived from.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
---
Documentation/devicetree/bindings/serial/pl011.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt
index 5d2e840..f0a9e77 100644
--- a/Documentation/devicetree/bindings/serial/pl011.txt
+++ b/Documentation/devicetree/bindings/serial/pl011.txt
@@ -8,8 +8,10 @@ Required properties:
Optional properties:
- pinctrl: When present, must have one state named "sleep"
and one state named "default"
-- clocks: When present, must refer to exactly one clock named
- "apb_pclk"
+- clocks: When present, must refer to a clock named
+ "apb_pclk", and optionally "uartclk".
+- clock-names: When present, should include "apb_pclk" and
+ "uartclk", matching the clocks property.
- dmas: When present, may have one or two dma channels.
The first one must be named "rx", the second one
must be named "tx".
--
1.8.1.1
^ permalink raw reply related
* [PATCH 0/7] primecell: make correct clock parsing possible
From: Mark Rutland @ 2014-02-11 11:37 UTC (permalink / raw)
To: devicetree; +Cc: Mark Rutland, robh+dt, pawel.moll, linux-arm-kernel
Currently either the drivers for primecell peripherals and their bindings
disagree, or those bindings disagree with the primecell binding which they
derive from. It is impossible in some cases to meet the requirements of both
bindings and drivers.
These patches attempt to harmonize the bindings and the drivers with what's in
use today, in a backwards compatible fashion, relieving us of our present
Kafkaesque nightmare. Each peripheral's clock(s) are given explicit names which
can be used, though code will fall back to the existing behaviour if said names
are not provided. Additionally the currently unmet ordering requirement of
apb_pclk is dropped, given all existing that code requires this to be named
anyway.
I've used IS_ERR to test is a clock wasn't provided by name, but this isn't
always right. In the case of a dodgy clock specifier we might get an error,
even if the expected name was provided explicitly in clock-names. For that case
it would be nice to fail rather than grabbing an almost certainly incorrect
clock. I'm not entirely sure how to check for that with the current
infrastructure though, and while it's possible to use of_property_match_string
to achieve the desired effect, it feels like working around the abstraction we
have in place today.
There are some other issues in the area which remain:
* The pl041 exists in DTs, but has no binding.
* Both pl110 and pl111 have no binding, but appear to be in use on OF
platforms, with the nspire code proving some sideband data via
OF_DEV_AUXDATA. The driver grabs a clock (CLCDCLK) without using a name.
* I'm not sure what to do with sp804. The bindings imply a given set of names
with a specific ordering, but all the dts do something different and the
driver doesn't bother with names. The given binding is incompatible with the
primecell binding's ordering requirement for apb_plck.
* There's no binding for the sp805, which grabs a clock with no name.
* There's no binding for the pl341 or pl354. Both seem to be unused yet exist
in DTs.
* The PL330 docs don't mention clocks at all, though the apb_pclk is required.
Use of PCLKEN isn't supported, but this doesn't seem to be a problem so far.
Thanks,
Mark.
Mark Rutland (7):
Documentation: devicetree: fix up pl011 clocks
serial: amba-pl011: attempt to get uartclk by name
Documentation: devicetree: fix up pl022 clocks
spi: pl022: attempt to get sspclk by name
Documentation: devicetree: fix up pl18x clocks
mmc: arm-mmci: attempt to get mclk by name
Documentation: devicetree: loosen primecell clock requirements
Documentation/devicetree/bindings/arm/primecell.txt | 11 ++++++-----
Documentation/devicetree/bindings/mmc/mmci.txt | 4 ++++
Documentation/devicetree/bindings/serial/pl011.txt | 6 ++++--
Documentation/devicetree/bindings/spi/spi_pl022.txt | 2 ++
drivers/mmc/host/mmci.c | 9 ++++++++-
drivers/spi/spi-pl022.c | 9 ++++++++-
drivers/tty/serial/amba-pl011.c | 9 ++++++++-
7 files changed, 40 insertions(+), 10 deletions(-)
--
1.8.1.1
^ permalink raw reply
* Re: [PATCH v2 4/5] ARM: init: add support for reserved memory defined by device tree
From: Marek Szyprowski @ 2014-02-11 10:52 UTC (permalink / raw)
To: Grant Likely, linux-kernel, linux-arm-kernel, linaro-mm-sig,
devicetree, linux-doc
Cc: Kyungmin Park, Benjamin Herrenschmidt, Arnd Bergmann,
Michal Nazarewicz, Tomasz Figa, Sascha Hauer, Laura Abbott,
Rob Herring, Olof Johansson, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Tomasz Figa, Kumar Gala,
Nishanth Peethambaran, Marc, Josh Cartwright
In-Reply-To: <20140210215929.4473BC408F7@trevor.secretlab.ca>
On 2014-02-10 22:59, Grant Likely wrote:
> On Thu, 06 Feb 2014 14:26:13 +0100, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On 2014-02-05 11:15, Grant Likely wrote:
> > > On Tue, 04 Feb 2014 13:09:32 +0100, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> > > > Enable reserved memory initialization from device tree.
> > > >
> > > > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > > > Cc: Laura Abbott <lauraa@codeaurora.org>
> > > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > > > ---
> > > > arch/arm/mm/init.c | 3 +++
> > > > 1 file changed, 3 insertions(+)
> > > >
> > > > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> > > > index 804d61566a53..ebafdb479410 100644
> > > > --- a/arch/arm/mm/init.c
> > > > +++ b/arch/arm/mm/init.c
> > > > @@ -17,6 +17,7 @@
> > > > #include <linux/nodemask.h>
> > > > #include <linux/initrd.h>
> > > > #include <linux/of_fdt.h>
> > > > +#include <linux/of_reserved_mem.h>
> > > > #include <linux/highmem.h>
> > > > #include <linux/gfp.h>
> > > > #include <linux/memblock.h>
> > > > @@ -323,6 +324,8 @@ void __init arm_memblock_init(struct meminfo *mi,
> > > > if (mdesc->reserve)
> > > > mdesc->reserve();
> > > >
> > > > + early_init_dt_scan_reserved_mem();
> > > > +
> > >
> > > The new binding is being made fundamental. If the reserved-memory node
> > > is present, then it needs to be honored, even if the kernel doesn't know
> > > how to use the regions. Therefore, This needs to be unconditional for
> > > all architectures. The hook should be called in early_init_dt_scan()
> > > (drivers/of/fdt.c) immediately after the early_init_dt_scan_memory()
> > > hook.
> >
> > In theory this will be the best solution, but it practice there is a
> > problem. early_init_dt_scan() is called as the first function from kernel
> > booting code. That time there is no memory yet added to the system, so it
> > would be really hard to reserve anything. Memory nodes are being added
> > later either with memblock_add() or by some other arch specific way.
>
> Hmmm, depends on the architecture. On ARM the memory is loaded into the
> meminfo structure first, and it isn't until arm_memblock_init() that
> memblock_add() gets called on all the regions. Some architectures do the
> memblock_add() directly from early_init_dt_add_memory_arch() function.
>
> The default early_init_dt_add_memory_arch() in drivers/of/fdt.c is
> overridden by ARM and a number of other architectures. However...
>
> > Finally, once all memory has been added to the system we can parse and
> > reserve all regions defined in the device tree. This really requires
> > creating another function which will be called by arch specific code.
>
> ...Or it means getting rid of meminfo entirely so that memblock is
> available earlier. Laura Abbott has just posted v2 of her series to do
> exactly that. If you base on that then you should be able to do exactly
> what I suggested.
I've checked Laura's patches and in fact it is possible to do memory
reservation as a last step in early_init_dt_scan_memory(). However still
see some problem which I have no idea how to resolve. Right now I focus
only on ARM, so I have no idea how it is solved by other architectures.
On of the key features of the new binding is the ability to automatically
allocate reserved regions of the given size. However kernel, initrd, dt
and other sub-arch specific critical regions are marked/allocated in
arm_memblock_init(), which is called after setup_machine_fdt(). This
might lead to some serious failures when automatically reserved region
overlaps with some critical resources. Do you have any idea how to solve
this without a new callback?
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* Re: [PATCH v9 2/4] ehci-platform: Add support for clks and phy passed through devicetree
From: Hans de Goede @ 2014-02-11 10:13 UTC (permalink / raw)
To: Roger Quadros, Greg Kroah-Hartman
Cc: Alan Stern, Tony Prisk, linux-usb, Maxime Ripard,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
Menon, Nishanth, Kevin Hilman
In-Reply-To: <52F9F4C6.6080201-l0cyMroinI0@public.gmane.org>
Hi,
On 02/11/2014 11:00 AM, Roger Quadros wrote:
> On 02/11/2014 11:31 AM, Hans de Goede wrote:
>> Hi,
>>
>> On 02/11/2014 10:12 AM, Roger Quadros wrote:
>>> Hi Hans,
>>>
>>> On 02/07/2014 05:36 PM, Hans de Goede wrote:
>>>> Currently ehci-platform is only used in combination with devicetree when used
>>>> with some Via socs. By extending it to (optionally) get clks and a phy from
>>>> devicetree, and enabling / disabling those on power_on / off, it can be used
>>>> more generically. Specifically after this commit it can be used for the
>>>> ehci controller on Allwinner sunxi SoCs.
>>>>
>>>> Since ehci-platform is intended to handle any generic enough non pci ehci
>>>> device, add a "usb-ehci" compatibility string.
>>>>
>>>> There already is a usb-ehci device-tree bindings document, update this
>>>> with clks and phy bindings info.
>>>>
>>>> Although actually quite generic so far the via,vt8500 compatibilty string
>>>> had its own bindings document. Somehow we even ended up with 2 of them. Since
>>>> these provide no extra information over the generic usb-ehci documentation,
>>>> this patch removes them.
>>>>
>>>> The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
>>>> even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
>>>> not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
>>>> 2 drivers claiming the same compatibility string getting build on ppc.
>>>>
>>>
>>> This breaks all OMAP platforms on linux-next for the exact same reason. see [1].
>>>
>>> ./arch/arm/boot/dts/omap4.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>>> ./arch/arm/boot/dts/omap3.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>>> ./arch/arm/boot/dts/omap5.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>>
>> That should not be the case, the driver core should try to find a driver matching
>> the compatibility string from left to right, or in other words from most specific
>> to least specific. This is part of the whole devicetree design.
>>
>> So as long as the driver claiming "ti,ehci-omap" is available at probe time that
>> one should get used and things should work fine. Now if ehci-platform is built-in
>> and ehci-omap is a module, then I guess one could see the described breakage.
>>
>> If the driver is built-in and things are not working, then we will need to do some
>> debugging as to why the left to right matching is not working as expected.
>
> Both ehci_platform and ehci_omap were built-in and still the ehci_platform driver got
> probe preference. So it looks like the left to right compatible list priority probing
> feature doesn't work.
Oops, I guess nothing relies on it sofar. Well we could go and debug and fix this but...
>
>>
>> I must admit I'm not sure what happens if both are a module, the kernel direct
>> module load will likely fail due to lack of a rootfs at that point, and then
>> the module will later get loaded by udev I assume, at which point there are no
>> loading ordering guarantees.
>>
>> The easiest solution to ensure that "ti,ehci-omap" is available at probe time
>> (if enabled) seems to be to change USB_EHCI_HCD_OMAP to a boolean.
>
> That is a limitation I don't like to have for USB_EHCI_HCD_OMAP.
I completely understand, thinking more about this I'm simply going to change the
compatibility string for ohci- and ehci-platform to be "ohci-platform" resp.
"ehci-platform". I know there are some people who don't like the -platform
suffix, but though luck, as the above clearly shows using the generic "usb-ohci" /
"usb-ehci" they were advocating for leads to a ton of issues, and we already
have a precedent for ?hci-platform in the form of "xhci-platform".
Regards,
Hans
^ permalink raw reply
* Re: [PATCH V2 2/3] ARM: dts: add dts files for exynos5260 SoC
From: Tomasz Figa @ 2014-02-11 10:04 UTC (permalink / raw)
To: Rahul Sharma, Tomasz Figa
Cc: Rahul Sharma, linux-samsung-soc, Kukjin Kim, sunil joshi,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Rob Herring, Mark Rutland, Grant Likely, Ian Campbell, Pawel Moll,
Kumar Gala
In-Reply-To: <CAPdUM4NBwXcnL2KK9Rsi46GWQz_KQsXF0EEeSmCb=wB8WfgUKQ@mail.gmail.com>
Hi Rahul,
On 11.02.2014 06:22, Rahul Sharma wrote:
> Hi Tomasz,
>
> On 6 February 2014 18:51, Tomasz Figa <t.figa@samsung.com> wrote:
>> Hi Rahul, Pankaj, Arun,
>>
>> [adding linux-arm-kernel, devicetree MLs and DT people on Cc]
>>
>> I think it's good time to stop accepting DTS files like this and force new
>> ones to use the proper structure with soc node, labels for every node and
>> node references.
>
> I am unable to find information on SoC node and grouping inside SoC node. Please
> share some pointers.
Well, there is not much information needed about this. Basically all the
devices built into the SoC should be listed under respective bus nodes
or a single soc node, instead of root level. Such node should be a
"simple-bus" and just group the components together to separate
board-specific devices (which are still at root level) from SoC devices.
Even though it might seem useless, it improves DT readability a bit and
still most of the platforms use this approach, so for consistency,
Exynos should use too.
Just for reference, back in April 2013, in his review of S3C64xx DT
series [1], Rob Herring requested that we don't submit any new device
trees using flat approach and start using bus hierarchy.
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/163659.html
>>
>>> + spi0_bus: spi0-bus {
>>> + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2",
>>> "gpa2-3";
>>
>>
>> What is the reason for SPI0 to have 4 pins, while SPI1 has just 3?
>>
>
> I should align SPI1 with SPI0.
>
Are you sure that SPI0 is the correct one? SPI usually uses four pins -
SDI, SDO, SCK and nCS, but we always used to treat nCS as a simple GPIO,
due to the fact that the controller can only support one dedicated chip
select and with direct GPIO control you can have more.
What is the fourth pin here?
>>
>>> + cpu@1 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a15";
>>> + reg = <1>;
>>> + cci-control-port = <&cci_control1>;
>>> + };
>>> + cpu@100 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a7";
>>> + reg = <0x100>;
>>> + cci-control-port = <&cci_control0>;
>>> + };
>>> + cpu@101 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a7";
>>> + reg = <0x101>;
>>> + cci-control-port = <&cci_control0>;
>>> + };
>>> + cpu@102 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a7";
>>> + reg = <0x102>;
>>> + cci-control-port = <&cci_control0>;
>>> + };
>>> + cpu@103 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a7";
>>> + reg = <0x103>;
>>> + cci-control-port = <&cci_control0>;
>>> + };
>>> + };
>>> +
>>> + cmus {
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> +
>>
>>
>> I don't think there is a need to group these nodes under a parent node that
>> doesn't give any additional information, especially when the CMUs are
>> scattered trough the whole address space, while we'd like to keep the nodes
>> ordered by their addresses, as most platforms do.
>>
>
> This is exactly the same case as "cpus". I mean, "cpus" also doesn't provide
> any common information about child cpu nodes. This looks to me as a logical
> grouping and I have implemented same thing for cmu nodes.
> I am ok with removing this grouping Just want to understand the rational behind
> grouping cpus which seems similar to cmus.
The "cpus" node is a defined standard node that should be present at
root of device tree and include subnodes for all CPUs. This is a
standard binding defined for low level code to be able to simply find
nodes of all CPUs in the system - so they can expect that at /cpus node
all the subnodes are subsequent CPUs.
> Similarly "soc" is just a logical entity used to group SoC elements which looks
> optional to me. What are we achieving with this? Please help me in understanding
> this better.
Also "soc" has a slightly wider meaning. It is a node grouping all nodes
from a single address space - the node specifies #address-cells and
#size-cells of this address space and all the devices under this
"simple-bus" can be accessed using addresses in this format. In
addition, it separates board-level devices from generic SoC devices.
Now, in case of "cmus", the only purpose is to group all CMU nodes
together and, while this improves readability a bit, it doesn't make the
DT better express the hardware topology, because the CMUs in the
hardware are in fact scattered through the whole address space, not
under a contiguous block of it, as the grouping would suggest.
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH v9 2/4] ehci-platform: Add support for clks and phy passed through devicetree
From: Roger Quadros @ 2014-02-11 10:00 UTC (permalink / raw)
To: Hans de Goede, Greg Kroah-Hartman
Cc: Alan Stern, Tony Prisk, linux-usb, Maxime Ripard,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
Menon, Nishanth, Kevin Hilman
In-Reply-To: <52F9EE06.3070003-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
On 02/11/2014 11:31 AM, Hans de Goede wrote:
> Hi,
>
> On 02/11/2014 10:12 AM, Roger Quadros wrote:
>> Hi Hans,
>>
>> On 02/07/2014 05:36 PM, Hans de Goede wrote:
>>> Currently ehci-platform is only used in combination with devicetree when used
>>> with some Via socs. By extending it to (optionally) get clks and a phy from
>>> devicetree, and enabling / disabling those on power_on / off, it can be used
>>> more generically. Specifically after this commit it can be used for the
>>> ehci controller on Allwinner sunxi SoCs.
>>>
>>> Since ehci-platform is intended to handle any generic enough non pci ehci
>>> device, add a "usb-ehci" compatibility string.
>>>
>>> There already is a usb-ehci device-tree bindings document, update this
>>> with clks and phy bindings info.
>>>
>>> Although actually quite generic so far the via,vt8500 compatibilty string
>>> had its own bindings document. Somehow we even ended up with 2 of them. Since
>>> these provide no extra information over the generic usb-ehci documentation,
>>> this patch removes them.
>>>
>>> The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
>>> even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
>>> not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
>>> 2 drivers claiming the same compatibility string getting build on ppc.
>>>
>>
>> This breaks all OMAP platforms on linux-next for the exact same reason. see [1].
>>
>> ./arch/arm/boot/dts/omap4.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>> ./arch/arm/boot/dts/omap3.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>> ./arch/arm/boot/dts/omap5.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
>
> That should not be the case, the driver core should try to find a driver matching
> the compatibility string from left to right, or in other words from most specific
> to least specific. This is part of the whole devicetree design.
>
> So as long as the driver claiming "ti,ehci-omap" is available at probe time that
> one should get used and things should work fine. Now if ehci-platform is built-in
> and ehci-omap is a module, then I guess one could see the described breakage.
>
> If the driver is built-in and things are not working, then we will need to do some
> debugging as to why the left to right matching is not working as expected.
Both ehci_platform and ehci_omap were built-in and still the ehci_platform driver got
probe preference. So it looks like the left to right compatible list priority probing
feature doesn't work.
>
> I must admit I'm not sure what happens if both are a module, the kernel direct
> module load will likely fail due to lack of a rootfs at that point, and then
> the module will later get loaded by udev I assume, at which point there are no
> loading ordering guarantees.
>
> The easiest solution to ensure that "ti,ehci-omap" is available at probe time
> (if enabled) seems to be to change USB_EHCI_HCD_OMAP to a boolean.
That is a limitation I don't like to have for USB_EHCI_HCD_OMAP.
cheers,
-roger
>
>
>>
>>
>> The other platforms that claim compatibility with "usb-ehci" are
>>
>> ARM
>> ./arch/arm/boot/dts/tegra30.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/tegra20.dtsi: compatible = "nvidia,tegra20-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/spear600.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
>>
>> ./arch/arm/boot/dts/spear3xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/sama5d3.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/at91sam9g45.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/spear13xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/at91sam9x5.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
>> ./arch/arm/boot/dts/tegra114.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
>>
>>
>> MIPS
>> ./arch/mips/cavium-octeon/octeon_68xx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
>> ./arch/mips/cavium-octeon/octeon_3xxx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
>>
>> Do we know that we don't break these platforms as well?
>>
>> cheers,
>> -roger
>>
>> [1] - http://marc.info/?l=linux-usb&m=139204800102167&w=2
>>
>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>> Acked-by: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
>>> ---
>>> Documentation/devicetree/bindings/usb/usb-ehci.txt | 25 +++-
>>> .../devicetree/bindings/usb/via,vt8500-ehci.txt | 15 ---
>>> .../devicetree/bindings/usb/vt8500-ehci.txt | 12 --
>>> drivers/usb/host/Kconfig | 1 +
>>> drivers/usb/host/ehci-platform.c | 147 +++++++++++++++++----
>>> 5 files changed, 142 insertions(+), 58 deletions(-)
>>> delete mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>>> delete mode 100644 Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
>>> index fa18612..2c1aeeb 100644
>>> --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
>>> +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
>>> @@ -7,13 +7,14 @@ Required properties:
>>> (debug-port or other) can be also specified here, but only after
>>> definition of standard EHCI registers.
>>> - interrupts : one EHCI interrupt should be described here.
>>> -If device registers are implemented in big endian mode, the device
>>> -node should have "big-endian-regs" property.
>>> -If controller implementation operates with big endian descriptors,
>>> -"big-endian-desc" property should be specified.
>>> -If both big endian registers and descriptors are used by the controller
>>> -implementation, "big-endian" property can be specified instead of having
>>> -both "big-endian-regs" and "big-endian-desc".
>>> +
>>> +Optional properties:
>>> + - big-endian-regs : boolean, set this for hcds with big-endian registers
>>> + - big-endian-desc : boolean, set this for hcds with big-endian descriptors
>>> + - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
>>> + - clocks : a list of phandle + clock specifier pairs
>>> + - phys : phandle + phy specifier pair
>>> + - phy-names : "usb"
>>>
>>> Example (Sequoia 440EPx):
>>> ehci@e0000300 {
>>> @@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
>>> reg = <0 e0000300 90 0 e0000390 70>;
>>> big-endian;
>>> };
>>> +
>>> +Example (Allwinner sun4i A10 SoC):
>>> + ehci0: usb@01c14000 {
>>> + compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
>>> + reg = <0x01c14000 0x100>;
>>> + interrupts = <39>;
>>> + clocks = <&ahb_gates 1>;
>>> + phys = <&usbphy 1>;
>>> + phy-names = "usb";
>>> + };
>>> diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>>> deleted file mode 100644
>>> index 17b3ad1..0000000
>>> --- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>>> +++ /dev/null
>>> @@ -1,15 +0,0 @@
>>> -VIA/Wondermedia VT8500 EHCI Controller
>>> ------------------------------------------------------
>>> -
>>> -Required properties:
>>> -- compatible : "via,vt8500-ehci"
>>> -- reg : Should contain 1 register ranges(address and length)
>>> -- interrupts : ehci controller interrupt
>>> -
>>> -Example:
>>> -
>>> - ehci@d8007900 {
>>> - compatible = "via,vt8500-ehci";
>>> - reg = <0xd8007900 0x200>;
>>> - interrupts = <43>;
>>> - };
>>> diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>>> deleted file mode 100644
>>> index 5fb8fd6..0000000
>>> --- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>>> +++ /dev/null
>>> @@ -1,12 +0,0 @@
>>> -VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
>>> -
>>> -Required properties:
>>> - - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
>>> - - reg: Address range of the ehci registers. size should be 0x200
>>> - - interrupts: Should contain the ehci interrupt.
>>> -
>>> -usb: ehci@D8007100 {
>>> - compatible = "wm,prizm-ehci", "usb-ehci";
>>> - reg = <0xD8007100 0x200>;
>>> - interrupts = <1>;
>>> -};
>>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>>> index a9707da..e28cbe0 100644
>>> --- a/drivers/usb/host/Kconfig
>>> +++ b/drivers/usb/host/Kconfig
>>> @@ -255,6 +255,7 @@ config USB_EHCI_ATH79
>>>
>>> config USB_EHCI_HCD_PLATFORM
>>> tristate "Generic EHCI driver for a platform device"
>>> + depends on !PPC_OF
>>> default n
>>> ---help---
>>> Adds an EHCI host driver for a generic platform device, which
>>> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
>>> index 01536cf..5ebd0b7 100644
>>> --- a/drivers/usb/host/ehci-platform.c
>>> +++ b/drivers/usb/host/ehci-platform.c
>>> @@ -3,6 +3,7 @@
>>> *
>>> * Copyright 2007 Steven Brown <sbrown-aLUkz7fEuXBWk0Htik3J/w@public.gmane.org>
>>> * Copyright 2010-2012 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>> *
>>> * Derived from the ohci-ssb driver
>>> * Copyright 2007 Michael Buesch <m@bues.ch>
>>> @@ -18,6 +19,7 @@
>>> *
>>> * Licensed under the GNU/GPL. See COPYING for details.
>>> */
>>> +#include <linux/clk.h>
>>> #include <linux/dma-mapping.h>
>>> #include <linux/err.h>
>>> #include <linux/kernel.h>
>>> @@ -25,6 +27,7 @@
>>> #include <linux/io.h>
>>> #include <linux/module.h>
>>> #include <linux/of.h>
>>> +#include <linux/phy/phy.h>
>>> #include <linux/platform_device.h>
>>> #include <linux/usb.h>
>>> #include <linux/usb/hcd.h>
>>> @@ -33,6 +36,13 @@
>>> #include "ehci.h"
>>>
>>> #define DRIVER_DESC "EHCI generic platform driver"
>>> +#define EHCI_MAX_CLKS 3
>>> +#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
>>> +
>>> +struct ehci_platform_priv {
>>> + struct clk *clks[EHCI_MAX_CLKS];
>>> + struct phy *phy;
>>> +};
>>>
>>> static const char hcd_name[] = "ehci-platform";
>>>
>>> @@ -64,38 +74,90 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
>>> return 0;
>>> }
>>>
>>> +static int ehci_platform_power_on(struct platform_device *dev)
>>> +{
>>> + struct usb_hcd *hcd = platform_get_drvdata(dev);
>>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>>> + int clk, ret;
>>> +
>>> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
>>> + ret = clk_prepare_enable(priv->clks[clk]);
>>> + if (ret)
>>> + goto err_disable_clks;
>>> + }
>>> +
>>> + if (priv->phy) {
>>> + ret = phy_init(priv->phy);
>>> + if (ret)
>>> + goto err_disable_clks;
>>> +
>>> + ret = phy_power_on(priv->phy);
>>> + if (ret)
>>> + goto err_exit_phy;
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +err_exit_phy:
>>> + phy_exit(priv->phy);
>>> +err_disable_clks:
>>> + while (--clk >= 0)
>>> + clk_disable_unprepare(priv->clks[clk]);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static void ehci_platform_power_off(struct platform_device *dev)
>>> +{
>>> + struct usb_hcd *hcd = platform_get_drvdata(dev);
>>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>>> + int clk;
>>> +
>>> + if (priv->phy) {
>>> + phy_power_off(priv->phy);
>>> + phy_exit(priv->phy);
>>> + }
>>> +
>>> + for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
>>> + if (priv->clks[clk])
>>> + clk_disable_unprepare(priv->clks[clk]);
>>> +}
>>> +
>>> static struct hc_driver __read_mostly ehci_platform_hc_driver;
>>>
>>> static const struct ehci_driver_overrides platform_overrides __initconst = {
>>> - .reset = ehci_platform_reset,
>>> + .reset = ehci_platform_reset,
>>> + .extra_priv_size = sizeof(struct ehci_platform_priv),
>>> };
>>>
>>> -static struct usb_ehci_pdata ehci_platform_defaults;
>>> +static struct usb_ehci_pdata ehci_platform_defaults = {
>>> + .power_on = ehci_platform_power_on,
>>> + .power_suspend = ehci_platform_power_off,
>>> + .power_off = ehci_platform_power_off,
>>> +};
>>>
>>> static int ehci_platform_probe(struct platform_device *dev)
>>> {
>>> struct usb_hcd *hcd;
>>> struct resource *res_mem;
>>> - struct usb_ehci_pdata *pdata;
>>> - int irq;
>>> - int err;
>>> + struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
>>> + struct ehci_platform_priv *priv;
>>> + int err, irq, clk = 0;
>>>
>>> if (usb_disabled())
>>> return -ENODEV;
>>>
>>> /*
>>> - * use reasonable defaults so platforms don't have to provide these.
>>> - * with DT probing on ARM, none of these are set.
>>> + * Use reasonable defaults so platforms don't have to provide these
>>> + * with DT probing on ARM.
>>> */
>>> - if (!dev_get_platdata(&dev->dev))
>>> - dev->dev.platform_data = &ehci_platform_defaults;
>>> + if (!pdata)
>>> + pdata = &ehci_platform_defaults;
>>>
>>> err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
>>> if (err)
>>> return err;
>>>
>>> - pdata = dev_get_platdata(&dev->dev);
>>> -
>>> irq = platform_get_irq(dev, 0);
>>> if (irq < 0) {
>>> dev_err(&dev->dev, "no irq provided");
>>> @@ -107,17 +169,40 @@ static int ehci_platform_probe(struct platform_device *dev)
>>> return -ENXIO;
>>> }
>>>
>>> + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>>> + dev_name(&dev->dev));
>>> + if (!hcd)
>>> + return -ENOMEM;
>>> +
>>> + platform_set_drvdata(dev, hcd);
>>> + dev->dev.platform_data = pdata;
>>> + priv = hcd_to_ehci_priv(hcd);
>>> +
>>> + if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
>>> + priv->phy = devm_phy_get(&dev->dev, "usb");
>>> + if (IS_ERR(priv->phy)) {
>>> + err = PTR_ERR(priv->phy);
>>> + if (err == -EPROBE_DEFER)
>>> + goto err_put_hcd;
>>> + priv->phy = NULL;
>>> + }
>>> +
>>> + for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
>>> + priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
>>> + if (IS_ERR(priv->clks[clk])) {
>>> + err = PTR_ERR(priv->clks[clk]);
>>> + if (err == -EPROBE_DEFER)
>>> + goto err_put_clks;
>>> + priv->clks[clk] = NULL;
>>> + break;
>>> + }
>>> + }
>>> + }
>>> +
>>> if (pdata->power_on) {
>>> err = pdata->power_on(dev);
>>> if (err < 0)
>>> - return err;
>>> - }
>>> -
>>> - hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>>> - dev_name(&dev->dev));
>>> - if (!hcd) {
>>> - err = -ENOMEM;
>>> - goto err_power;
>>> + goto err_put_clks;
>>> }
>>>
>>> hcd->rsrc_start = res_mem->start;
>>> @@ -126,22 +211,28 @@ static int ehci_platform_probe(struct platform_device *dev)
>>> hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
>>> if (IS_ERR(hcd->regs)) {
>>> err = PTR_ERR(hcd->regs);
>>> - goto err_put_hcd;
>>> + goto err_power;
>>> }
>>> err = usb_add_hcd(hcd, irq, IRQF_SHARED);
>>> if (err)
>>> - goto err_put_hcd;
>>> + goto err_power;
>>>
>>> device_wakeup_enable(hcd->self.controller);
>>> platform_set_drvdata(dev, hcd);
>>>
>>> return err;
>>>
>>> -err_put_hcd:
>>> - usb_put_hcd(hcd);
>>> err_power:
>>> if (pdata->power_off)
>>> pdata->power_off(dev);
>>> +err_put_clks:
>>> + while (--clk >= 0)
>>> + clk_put(priv->clks[clk]);
>>> +err_put_hcd:
>>> + if (pdata == &ehci_platform_defaults)
>>> + dev->dev.platform_data = NULL;
>>> +
>>> + usb_put_hcd(hcd);
>>>
>>> return err;
>>> }
>>> @@ -150,13 +241,19 @@ static int ehci_platform_remove(struct platform_device *dev)
>>> {
>>> struct usb_hcd *hcd = platform_get_drvdata(dev);
>>> struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
>>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>>> + int clk;
>>>
>>> usb_remove_hcd(hcd);
>>> - usb_put_hcd(hcd);
>>>
>>> if (pdata->power_off)
>>> pdata->power_off(dev);
>>>
>>> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
>>> + clk_put(priv->clks[clk]);
>>> +
>>> + usb_put_hcd(hcd);
>>> +
>>> if (pdata == &ehci_platform_defaults)
>>> dev->dev.platform_data = NULL;
>>>
>>> @@ -207,8 +304,10 @@ static int ehci_platform_resume(struct device *dev)
>>> static const struct of_device_id vt8500_ehci_ids[] = {
>>> { .compatible = "via,vt8500-ehci", },
>>> { .compatible = "wm,prizm-ehci", },
>>> + { .compatible = "usb-ehci", },
>>> {}
>>> };
>>> +MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
>>>
>>> static const struct platform_device_id ehci_platform_table[] = {
>>> { "ehci-platform", 0 },
>>>
>>
^ permalink raw reply
* [PATCH v3 3/3] ARM: STi: Add STiH416 ethernet support.
From: srinivas.kandagatla @ 2014-02-11 10:00 UTC (permalink / raw)
To: netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Rob Landley, Russell King, Srinivas Kandagatla, Stuart Menefy,
Giuseppe Cavallaro, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, davem
In-Reply-To: <1392112716-30803-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 44 +++++++++++++
3 files changed, 167 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 8863c38..c4beef2 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -132,6 +132,58 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -322,6 +374,63 @@
};
};
};
+
+ gmac0 {
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+ };
+ };
+
+ pinctrl_gmii0: gmii0 {
+ st,pins {
+ };
+ };
+ pinctrl_rgmii0: rgmii0 {
+ st,pins {
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+ rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
+ rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
+ rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
+ rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+ rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+ clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 788ba5b..a96055b 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -156,5 +156,49 @@
status = "disabled";
};
+
+ ethernet0: dwmac@fe810000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ };
+
+ ethernet1: dwmac@fef08000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ st,syscon = <&syscfg_sbc>;
+
+ resets = <&softreset STIH416_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_ETH1_PHY>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 2/3] ARM: STi: Add STiH415 ethernet support.
From: srinivas.kandagatla @ 2014-02-11 10:00 UTC (permalink / raw)
To: netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Rob Landley, Russell King, Srinivas Kandagatla, Stuart Menefy,
Giuseppe Cavallaro, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, davem
In-Reply-To: <1392112716-30803-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih415-pinctrl.dtsi | 121 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 48 +++++++++++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 22 ++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 26 +++++++
5 files changed, 231 insertions(+)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799..d047dbc 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
+
+ CLKS_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_GMAC0_PHY";
+ };
+
+ CLKS_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 887c5e5..9ca20aa 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -119,6 +119,56 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
+ };
+ };
+
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -284,6 +334,77 @@
};
};
};
+
+ gmac0{
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
+
+ };
+ };
+
+ pinctrl_gmii0: gmii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+
+
+ };
+ };
+ };
};
pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d52207c..cc9b22b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -147,5 +147,53 @@
status = "disabled";
};
+
+ ethernet0: dwmac@fe810000 {
+ device_type = "network";
+ compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+
+ reg = <0xfe810000 0x8000>, <0x148 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
+
+ st,syscon = <&syscfg_rear>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_GMAC0_PHY>;
+ };
+
+ ethernet1: dwmac@fef08000 {
+ device_type = "network";
+ compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>, <0x74 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
+
+ st,syscon = <&syscfg_sbc>;
+
+ resets = <&softreset STIH415_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_ETH1_PHY>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92..bf65c49 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
aliases {
ttyAS0 = &serial2;
+ ethernet0 = ðernet0;
+ ethernet1 = ðernet1;
};
soc {
@@ -46,5 +48,25 @@
status = "okay";
};
+
+ ethernet0: dwmac@fe810000 {
+ status = "okay";
+ phy-mode = "mii";
+ pinctrl-0 = <&pinctrl_mii0>;
+
+ snps,reset-gpio = <&PIO106 2>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+
+ ethernet1: dwmac@fef08000 {
+ status = "disabled";
+ phy-mode = "mii";
+ st,tx-retime-src = "txclk";
+
+ snps,reset-gpio = <&PIO4 7>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69..6c9a2ab 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
aliases {
ttyAS0 = &sbc_serial1;
+ ethernet1 = ðernet1;
};
soc {
sbc_serial1: serial@fe531000 {
@@ -60,5 +61,30 @@
i2c@fe541000 {
status = "okay";
};
+
+ /**
+ * ethernet clk routing:
+ * for
+ * max-speed = <1000>;
+ * set
+ * st,tx-retime-src = "clk_125";
+ *
+ * for
+ * max-speed = <100>;
+ * set
+ * st,tx-retime-src = "clkgen";
+ */
+
+ ethernet1: dwmac@fef08000 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ st,tx-retime-src = "clk_125";
+ snps,reset-gpio = <&PIO3 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 1/3] net: stmmac:sti: Add STi SOC glue driver.
From: srinivas.kandagatla @ 2014-02-11 9:59 UTC (permalink / raw)
To: netdev
Cc: Mark Rutland, devicetree, Russell King, kernel, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, linux-doc, linux-kernel,
Stuart Menefy, Rob Herring, Rob Landley, Kumar Gala,
Giuseppe Cavallaro, davem, linux-arm-kernel
In-Reply-To: <1392112716-30803-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
STi series SOCs have a glue layer on top of the synopsis gmac IP, this
glue layer needs to be configured before the gmac driver starts using
the IP.
This patch adds a support to this glue layer which is configured via
stmmac setup, init, exit callbacks.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/net/sti-dwmac.txt | 58 ++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 330 ++++++++++++++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 +
6 files changed, 408 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 0000000..3dd3d0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,58 @@
+STMicroelectronics SoC DWMAC glue layer controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+ "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
+ configuration regmap pointed by st,syscon property and size.
+
+ - reg-names : Should be "sti-ethconf".
+
+ - st,syscon : Should be phandle to system configuration node which
+ encompases this glue registers.
+
+ - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
+ wired up in from different sources. One via TXCLK pin and other via CLK_125
+ pin. This wiring is totally board dependent. However the retiming glue
+ logic should be configured accordingly. Possible values for this property
+
+ "txclk" - if 125Mhz clock is wired up via txclk line.
+ "clk_125" - if 125Mhz clock is wired up via clk_125 line.
+
+ This property is only valid for Giga bit setup( GMII, RGMII), and it is
+ un-used for non-giga bit (MII and RMII) setups. Also note that internal
+ clockgen can not generate stable 125Mhz clock.
+
+ - st,ext-phyclk: This boolean property indicates who is generating the clock
+ for tx and rx. This property is only valid for RMII case where the clock can
+ be generated from the MAC or PHY.
+
+ - clock-names: should be "sti-ethclk".
+ - clocks: Should point to ethernet clockgen which can generate phyclk.
+
+
+Example:
+
+ethernet0: dwmac@fe810000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ phy-mode = "mii";
+
+ st,syscon = <&syscfg_rear>;
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-0 = <&pinctrl_mii0>;
+ pinctrl-names = "default";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ clock-names = "stmmaceth";
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index e2f202e..f2d7c70 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -37,6 +37,17 @@ config DWMAC_SUNXI
stmmac device driver. This driver is used for A20/A31
GMAC ethernet controller.
+config DWMAC_STI
+ bool "STi GMAC support"
+ depends on STMMAC_PLATFORM && ARCH_STI
+ default y
+ ---help---
+ Support for ethernet controller on STi SOCs.
+
+ This selects STi SoC glue layer support for the stmmac
+ device driver. This driver is used on for the STi series
+ SOCs GMAC ethernet controller.
+
config STMMAC_PCI
bool "STMMAC PCI bus support"
depends on STMMAC_ETH && PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index ecadece..dcef287 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
+stmmac-$(CONFIG_DWMAC_STI) += dwmac-sti.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 0000000..552bbc1
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,330 @@
+/**
+ * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
+ *
+ * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/stmmac.h>
+#include <linux/phy.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+
+/**
+ * STi GMAC glue logic.
+ * --------------------
+ *
+ * _
+ * | \
+ * --------|0 \ ETH_SEL_INTERNAL_NOTEXT_PHYCLK
+ * phyclk | |___________________________________________
+ * | | | (phyclk-in)
+ * --------|1 / |
+ * int-clk |_ / |
+ * | _
+ * | | \
+ * |_______|1 \ ETH_SEL_TX_RETIME_CLK
+ * | |___________________________
+ * | | (tx-retime-clk)
+ * _______|0 /
+ * | |_ /
+ * _ |
+ * | \ |
+ * --------|0 \ |
+ * clk_125 | |__|
+ * | | ETH_SEL_TXCLK_NOT_CLK125
+ * --------|1 /
+ * txclk |_ /
+ *
+ *
+ * ETH_SEL_INTERNAL_NOTEXT_PHYCLK is valid only for RMII where PHY can
+ * generate 50MHz clock or MAC can generate it.
+ * This bit is configured by "st,ext-phyclk" property.
+ *
+ * ETH_SEL_TXCLK_NOT_CLK125 is only valid for gigabit modes, where the 125Mhz
+ * clock either comes from clk-125 pin or txclk pin. This configuration is
+ * totally driven by the board wiring. This bit is configured by
+ * "st,tx-retime-src" property.
+ *
+ * TXCLK configuration is different for different phy interface modes
+ * and changes according to link speed in modes like RGMII.
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes with link speeds.
+ * ________________________________________________
+ *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
+ * ------------------------------------------------
+ *| MII | n/a | 25Mhz |
+ *| | | txclk |
+ * ------------------------------------------------
+ *| GMII | 125Mhz | 25Mhz |
+ *| | clk-125/txclk | txclk |
+ * ------------------------------------------------
+ *| RGMII | 125Mhz | 25Mhz |
+ *| | clk-125/txclk | clkgen |
+ * ------------------------------------------------
+ *| RMII | n/a | 25Mhz |
+ *| | |clkgen/phyclk-in |
+ * ------------------------------------------------
+ *
+ * TX lines are always retimed with a clk, which can vary depending
+ * on the board configuration. Below is the table of these bits
+ * in eth configuration register depending on source of retime clk.
+ *
+ *---------------------------------------------------------------
+ * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
+ *---------------------------------------------------------------
+ * txclk | 0 | n/a | 1 |
+ *---------------------------------------------------------------
+ * ck_125| 0 | n/a | 0 |
+ *---------------------------------------------------------------
+ * phyclk| 1 | 0 | n/a |
+ *---------------------------------------------------------------
+ * clkgen| 1 | 1 | n/a |
+ *---------------------------------------------------------------
+ */
+
+ /* Register definition */
+
+ /* 3 bits [8:6]
+ * [6:6] ETH_SEL_TXCLK_NOT_CLK125
+ * [7:7] ETH_SEL_INTERNAL_NOTEXT_PHYCLK
+ * [8:8] ETH_SEL_TX_RETIME_CLK
+ *
+ */
+
+#define TX_RETIME_SRC_MASK GENMASK(8, 6)
+#define ETH_SEL_TX_RETIME_CLK BIT(8)
+#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
+#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
+
+#define ENMII_MASK GENMASK(5, 5)
+#define ENMII BIT(5)
+
+/**
+ * 3 bits [4:2]
+ * 000-GMII/MII
+ * 001-RGMII
+ * 010-SGMII
+ * 100-RMII
+*/
+#define MII_PHY_SEL_MASK GENMASK(4, 2)
+#define ETH_PHY_SEL_RMII BIT(4)
+#define ETH_PHY_SEL_SGMII BIT(3)
+#define ETH_PHY_SEL_RGMII BIT(2)
+#define ETH_PHY_SEL_GMII 0x0
+#define ETH_PHY_SEL_MII 0x0
+
+#define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
+ iface == PHY_INTERFACE_MODE_RGMII_ID || \
+ iface == PHY_INTERFACE_MODE_RGMII_RXID || \
+ iface == PHY_INTERFACE_MODE_RGMII_TXID)
+
+#define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
+ iface == PHY_INTERFACE_MODE_GMII)
+
+struct sti_dwmac {
+ int interface;
+ bool ext_phyclk;
+ bool is_tx_retime_src_clk_125;
+ struct clk *clk;
+ int reg;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static u32 phy_intf_sels[] = {
+ [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
+ [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
+ [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
+ [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
+};
+
+enum {
+ TX_RETIME_SRC_NA = 0,
+ TX_RETIME_SRC_TXCLK = 1,
+ TX_RETIME_SRC_CLK_125,
+ TX_RETIME_SRC_PHYCLK,
+ TX_RETIME_SRC_CLKGEN,
+};
+
+static const char *const tx_retime_srcs[] = {
+ [TX_RETIME_SRC_NA] = "",
+ [TX_RETIME_SRC_TXCLK] = "txclk",
+ [TX_RETIME_SRC_CLK_125] = "clk_125",
+ [TX_RETIME_SRC_PHYCLK] = "phyclk",
+ [TX_RETIME_SRC_CLKGEN] = "clkgen",
+};
+
+static u32 tx_retime_val[] = {
+ [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
+ [TX_RETIME_SRC_CLK_125] = 0x0,
+ [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
+ [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
+ ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
+};
+
+static void setup_retime_src(struct sti_dwmac *dwmac, u32 spd)
+{
+ u32 src = 0, freq = 0;
+
+ if (spd == SPEED_100) {
+ if (dwmac->interface == PHY_INTERFACE_MODE_MII ||
+ dwmac->interface == PHY_INTERFACE_MODE_GMII) {
+ src = TX_RETIME_SRC_TXCLK;
+ } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
+ if (dwmac->ext_phyclk) {
+ src = TX_RETIME_SRC_PHYCLK;
+ } else {
+ src = TX_RETIME_SRC_CLKGEN;
+ freq = 50000000;
+ }
+
+ } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
+ src = TX_RETIME_SRC_CLKGEN;
+ freq = 25000000;
+ }
+
+ if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk)
+ clk_set_rate(dwmac->clk, freq);
+
+ } else if (spd == SPEED_1000) {
+ if (dwmac->is_tx_retime_src_clk_125)
+ src = TX_RETIME_SRC_CLK_125;
+ else
+ src = TX_RETIME_SRC_TXCLK;
+ }
+
+ regmap_update_bits(dwmac->regmap, dwmac->reg,
+ TX_RETIME_SRC_MASK, tx_retime_val[src]);
+}
+
+static void sti_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+ struct sti_dwmac *dwmac = priv;
+
+ if (dwmac->clk)
+ clk_disable_unprepare(dwmac->clk);
+}
+
+static void sti_fix_mac_speed(void *priv, unsigned int spd)
+{
+ struct sti_dwmac *dwmac = priv;
+
+ setup_retime_src(dwmac, spd);
+
+ return;
+}
+
+static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
+ struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct regmap *regmap;
+ int err;
+
+ if (!np)
+ return -EINVAL;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
+ if (!res)
+ return -ENODATA;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ dwmac->dev = dev;
+ dwmac->interface = of_get_phy_mode(np);
+ dwmac->regmap = regmap;
+ dwmac->reg = res->start;
+ dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
+ dwmac->is_tx_retime_src_clk_125 = false;
+
+ if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
+ const char *rs;
+
+ err = of_property_read_string(np, "st,tx-retime-src", &rs);
+ if (err < 0) {
+ dev_err(dev, "st,tx-retime-src not specified\n");
+ return err;
+ }
+
+ if (!strcasecmp(rs, "clk_125"))
+ dwmac->is_tx_retime_src_clk_125 = true;
+ }
+
+ dwmac->clk = devm_clk_get(dev, "sti-ethclk");
+
+ if (IS_ERR(dwmac->clk))
+ dwmac->clk = NULL;
+
+ return 0;
+}
+
+static int sti_dwmac_init(struct platform_device *pdev, void *priv)
+{
+ struct sti_dwmac *dwmac = priv;
+ struct regmap *regmap = dwmac->regmap;
+ int iface = dwmac->interface;
+ u32 reg = dwmac->reg;
+ u32 val, spd;
+
+ if (dwmac->clk)
+ clk_prepare_enable(dwmac->clk);
+
+ regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
+
+ val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
+ regmap_update_bits(regmap, reg, ENMII_MASK, val);
+
+ if (IS_PHY_IF_MODE_GBIT(iface))
+ spd = SPEED_1000;
+ else
+ spd = SPEED_100;
+
+ setup_retime_src(dwmac, spd);
+
+ return 0;
+}
+
+static void *sti_dwmac_setup(struct platform_device *pdev)
+{
+ struct sti_dwmac *dwmac;
+ int ret;
+
+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
+ if (!dwmac)
+ return ERR_PTR(-ENOMEM);
+
+ ret = sti_dwmac_parse_data(dwmac, pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to parse OF data\n");
+ return ERR_PTR(ret);
+ }
+
+ return dwmac;
+}
+
+const struct stmmac_of_data sti_gmac_data = {
+ .fix_mac_speed = sti_fix_mac_speed,
+ .setup = sti_dwmac_setup,
+ .init = sti_dwmac_init,
+ .exit = sti_dwmac_exit,
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index d9af26e..f9e60d7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -133,6 +133,9 @@ bool stmmac_eee_init(struct stmmac_priv *priv);
#ifdef CONFIG_DWMAC_SUNXI
extern const struct stmmac_of_data sun7i_gmac_data;
#endif
+#ifdef CONFIG_DWMAC_STI
+extern const struct stmmac_of_data sti_gmac_data;
+#endif
extern struct platform_driver stmmac_pltfr_driver;
static inline int stmmac_register_platform(void)
{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5884a7d..c61bc72b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -33,6 +33,11 @@ static const struct of_device_id stmmac_dt_ids[] = {
#ifdef CONFIG_DWMAC_SUNXI
{ .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
#endif
+#ifdef CONFIG_DWMAC_STI
+ { .compatible = "st,stih415-dwmac", .data = &sti_gmac_data},
+ { .compatible = "st,stih416-dwmac", .data = &sti_gmac_data},
+ { .compatible = "st,stih127-dwmac", .data = &sti_gmac_data},
+#endif
/* SoC specific glue layers should come before generic bindings */
{ .compatible = "st,spear600-gmac"},
{ .compatible = "snps,dwmac-3.610"},
--
1.7.9.5
^ permalink raw reply related
* IRC logging
From: Grant Likely @ 2014-02-11 9:58 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Anybody object to the #devicetree channel on freenode getting logged
on irclogs.linaro.org? I'd like to use the linaro meeting bot to track
the weekly meeting.
g.
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v3 0/3] net: stmmac: Add STi GMAC ethernet
From: srinivas.kandagatla @ 2014-02-11 9:58 UTC (permalink / raw)
To: netdev
Cc: Mark Rutland, devicetree, Russell King, kernel, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, linux-doc, linux-kernel,
Stuart Menefy, Rob Herring, Rob Landley, Kumar Gala,
Giuseppe Cavallaro, davem, linux-arm-kernel
In-Reply-To: <1391770455-24291-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
STi SOC series integrates dwmac IP from synopsis, however there is a hardware
glue on top of this standard IP, this glue needs to configured before the
actual dwmac can be used. Also the glue logic needs re-configuring when the
link speed changes, This is because the clk source can change as the link
speed changes.
This patch just adds STi specific callbacks into of_data for configuring the
glue layer.
I have rebased my original patches (http://lkml.org/lkml/2013/11/12/243)
to latest stmmac which updates callbacks to suit glue drivers like this.
These patches are tested on b2000 and B2020 with STiH415 and STiH416.
Changes since v1:
- fixed multi-line function call format as suggested by David Miller.
Changes since v2:
- fix indenting issues & superfluous empty lines as suggested by David Miller.
- Run the code through scripts/Lindent.
Dave, Can I request you to take the first patch via net tree for v3.15, I can
request Arnd or Olof to take the DT patches via the arm-soc tree for v3.15.
Thanks,
srini
Srinivas Kandagatla (3):
net: stmmac:sti: Add STi SOC glue driver.
ARM: STi: Add STiH415 ethernet support.
ARM: STi: Add STiH416 ethernet support.
.../devicetree/bindings/net/sti-dwmac.txt | 58 ++++
arch/arm/boot/dts/stih415-clock.dtsi | 14 +
arch/arm/boot/dts/stih415-pinctrl.dtsi | 121 +++++++
arch/arm/boot/dts/stih415.dtsi | 48 +++
arch/arm/boot/dts/stih416-clock.dtsi | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109 +++++++
arch/arm/boot/dts/stih416.dtsi | 44 +++
arch/arm/boot/dts/stih41x-b2000.dtsi | 22 ++
arch/arm/boot/dts/stih41x-b2020.dtsi | 26 ++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 330 ++++++++++++++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 +
14 files changed, 806 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
--
1.7.9.5
^ permalink raw reply
* Re: [PATCH v6 01/19] clocksource: orion: Use atomic access for shared registers
From: Ezequiel Garcia @ 2014-02-11 9:47 UTC (permalink / raw)
To: Daniel Lezcano
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, Wim Van Sebroeck,
Jason Cooper, Thomas Petazzoni, Gregory Clement, Lior Amsalem,
Sebastian Hesselbarth, Andrew Lunn
In-Reply-To: <52F9E947.5020004-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tue, Feb 11, 2014 at 10:11:35AM +0100, Daniel Lezcano wrote:
> On 02/11/2014 09:30 AM, Ezequiel Garcia wrote:
> > On Tue, Feb 11, 2014 at 01:06:43AM +0100, Daniel Lezcano wrote:
> >> On 02/06/2014 06:20 PM, Ezequiel Garcia wrote:
> >>> Replace the driver-specific thread-safe shared register API
> >>> by the recently introduced atomic_io_clear_set().
> >>>
> >>> Cc: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >>> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >>> Tested-by: Willy Tarreau <w@1wt.eu>
> >>> Acked-by: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
> >>> Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTGGXanvQGlWp@public.gmane.orgm>
> >>
> >> The patch looks good for me.
> >>
> >> Acked-by: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >>
> >
> > Daniel,
> >
> > Jason acked this patch for you to take it. Or do you prefer that we
> > merge it with the rest of the watchdog series?
>
> I can pick it, but doesn't the watchdog series depend on it ?
>
Nope. It's indepedent of it.
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v9 2/4] ehci-platform: Add support for clks and phy passed through devicetree
From: Hans de Goede @ 2014-02-11 9:31 UTC (permalink / raw)
To: Roger Quadros, Greg Kroah-Hartman
Cc: Alan Stern, Tony Prisk, linux-usb, Maxime Ripard,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
Menon, Nishanth, Kevin Hilman
In-Reply-To: <52F9E98B.90407-l0cyMroinI0@public.gmane.org>
Hi,
On 02/11/2014 10:12 AM, Roger Quadros wrote:
> Hi Hans,
>
> On 02/07/2014 05:36 PM, Hans de Goede wrote:
>> Currently ehci-platform is only used in combination with devicetree when used
>> with some Via socs. By extending it to (optionally) get clks and a phy from
>> devicetree, and enabling / disabling those on power_on / off, it can be used
>> more generically. Specifically after this commit it can be used for the
>> ehci controller on Allwinner sunxi SoCs.
>>
>> Since ehci-platform is intended to handle any generic enough non pci ehci
>> device, add a "usb-ehci" compatibility string.
>>
>> There already is a usb-ehci device-tree bindings document, update this
>> with clks and phy bindings info.
>>
>> Although actually quite generic so far the via,vt8500 compatibilty string
>> had its own bindings document. Somehow we even ended up with 2 of them. Since
>> these provide no extra information over the generic usb-ehci documentation,
>> this patch removes them.
>>
>> The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
>> even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
>> not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
>> 2 drivers claiming the same compatibility string getting build on ppc.
>>
>
> This breaks all OMAP platforms on linux-next for the exact same reason. see [1].
>
> ./arch/arm/boot/dts/omap4.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
> ./arch/arm/boot/dts/omap3.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
> ./arch/arm/boot/dts/omap5.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
That should not be the case, the driver core should try to find a driver matching
the compatibility string from left to right, or in other words from most specific
to least specific. This is part of the whole devicetree design.
So as long as the driver claiming "ti,ehci-omap" is available at probe time that
one should get used and things should work fine. Now if ehci-platform is built-in
and ehci-omap is a module, then I guess one could see the described breakage.
If the driver is built-in and things are not working, then we will need to do some
debugging as to why the left to right matching is not working as expected.
I must admit I'm not sure what happens if both are a module, the kernel direct
module load will likely fail due to lack of a rootfs at that point, and then
the module will later get loaded by udev I assume, at which point there are no
loading ordering guarantees.
The easiest solution to ensure that "ti,ehci-omap" is available at probe time
(if enabled) seems to be to change USB_EHCI_HCD_OMAP to a boolean.
Regards,
Hans
>
>
> The other platforms that claim compatibility with "usb-ehci" are
>
> ARM
> ./arch/arm/boot/dts/tegra30.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
> ./arch/arm/boot/dts/tegra20.dtsi: compatible = "nvidia,tegra20-ehci", "usb-ehci";
> ./arch/arm/boot/dts/spear600.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
>
> ./arch/arm/boot/dts/spear3xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
> ./arch/arm/boot/dts/sama5d3.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> ./arch/arm/boot/dts/at91sam9g45.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> ./arch/arm/boot/dts/spear13xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
> ./arch/arm/boot/dts/at91sam9x5.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> ./arch/arm/boot/dts/tegra114.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
>
>
> MIPS
> ./arch/mips/cavium-octeon/octeon_68xx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
> ./arch/mips/cavium-octeon/octeon_3xxx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
>
> Do we know that we don't break these platforms as well?
>
> cheers,
> -roger
>
> [1] - http://marc.info/?l=linux-usb&m=139204800102167&w=2
>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> Acked-by: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/usb/usb-ehci.txt | 25 +++-
>> .../devicetree/bindings/usb/via,vt8500-ehci.txt | 15 ---
>> .../devicetree/bindings/usb/vt8500-ehci.txt | 12 --
>> drivers/usb/host/Kconfig | 1 +
>> drivers/usb/host/ehci-platform.c | 147 +++++++++++++++++----
>> 5 files changed, 142 insertions(+), 58 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>> delete mode 100644 Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
>> index fa18612..2c1aeeb 100644
>> --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
>> +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
>> @@ -7,13 +7,14 @@ Required properties:
>> (debug-port or other) can be also specified here, but only after
>> definition of standard EHCI registers.
>> - interrupts : one EHCI interrupt should be described here.
>> -If device registers are implemented in big endian mode, the device
>> -node should have "big-endian-regs" property.
>> -If controller implementation operates with big endian descriptors,
>> -"big-endian-desc" property should be specified.
>> -If both big endian registers and descriptors are used by the controller
>> -implementation, "big-endian" property can be specified instead of having
>> -both "big-endian-regs" and "big-endian-desc".
>> +
>> +Optional properties:
>> + - big-endian-regs : boolean, set this for hcds with big-endian registers
>> + - big-endian-desc : boolean, set this for hcds with big-endian descriptors
>> + - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
>> + - clocks : a list of phandle + clock specifier pairs
>> + - phys : phandle + phy specifier pair
>> + - phy-names : "usb"
>>
>> Example (Sequoia 440EPx):
>> ehci@e0000300 {
>> @@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
>> reg = <0 e0000300 90 0 e0000390 70>;
>> big-endian;
>> };
>> +
>> +Example (Allwinner sun4i A10 SoC):
>> + ehci0: usb@01c14000 {
>> + compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
>> + reg = <0x01c14000 0x100>;
>> + interrupts = <39>;
>> + clocks = <&ahb_gates 1>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + };
>> diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>> deleted file mode 100644
>> index 17b3ad1..0000000
>> --- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
>> +++ /dev/null
>> @@ -1,15 +0,0 @@
>> -VIA/Wondermedia VT8500 EHCI Controller
>> ------------------------------------------------------
>> -
>> -Required properties:
>> -- compatible : "via,vt8500-ehci"
>> -- reg : Should contain 1 register ranges(address and length)
>> -- interrupts : ehci controller interrupt
>> -
>> -Example:
>> -
>> - ehci@d8007900 {
>> - compatible = "via,vt8500-ehci";
>> - reg = <0xd8007900 0x200>;
>> - interrupts = <43>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>> deleted file mode 100644
>> index 5fb8fd6..0000000
>> --- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>> +++ /dev/null
>> @@ -1,12 +0,0 @@
>> -VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
>> -
>> -Required properties:
>> - - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
>> - - reg: Address range of the ehci registers. size should be 0x200
>> - - interrupts: Should contain the ehci interrupt.
>> -
>> -usb: ehci@D8007100 {
>> - compatible = "wm,prizm-ehci", "usb-ehci";
>> - reg = <0xD8007100 0x200>;
>> - interrupts = <1>;
>> -};
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index a9707da..e28cbe0 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -255,6 +255,7 @@ config USB_EHCI_ATH79
>>
>> config USB_EHCI_HCD_PLATFORM
>> tristate "Generic EHCI driver for a platform device"
>> + depends on !PPC_OF
>> default n
>> ---help---
>> Adds an EHCI host driver for a generic platform device, which
>> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
>> index 01536cf..5ebd0b7 100644
>> --- a/drivers/usb/host/ehci-platform.c
>> +++ b/drivers/usb/host/ehci-platform.c
>> @@ -3,6 +3,7 @@
>> *
>> * Copyright 2007 Steven Brown <sbrown-aLUkz7fEuXBWk0Htik3J/w@public.gmane.org>
>> * Copyright 2010-2012 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> *
>> * Derived from the ohci-ssb driver
>> * Copyright 2007 Michael Buesch <m@bues.ch>
>> @@ -18,6 +19,7 @@
>> *
>> * Licensed under the GNU/GPL. See COPYING for details.
>> */
>> +#include <linux/clk.h>
>> #include <linux/dma-mapping.h>
>> #include <linux/err.h>
>> #include <linux/kernel.h>
>> @@ -25,6 +27,7 @@
>> #include <linux/io.h>
>> #include <linux/module.h>
>> #include <linux/of.h>
>> +#include <linux/phy/phy.h>
>> #include <linux/platform_device.h>
>> #include <linux/usb.h>
>> #include <linux/usb/hcd.h>
>> @@ -33,6 +36,13 @@
>> #include "ehci.h"
>>
>> #define DRIVER_DESC "EHCI generic platform driver"
>> +#define EHCI_MAX_CLKS 3
>> +#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
>> +
>> +struct ehci_platform_priv {
>> + struct clk *clks[EHCI_MAX_CLKS];
>> + struct phy *phy;
>> +};
>>
>> static const char hcd_name[] = "ehci-platform";
>>
>> @@ -64,38 +74,90 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
>> return 0;
>> }
>>
>> +static int ehci_platform_power_on(struct platform_device *dev)
>> +{
>> + struct usb_hcd *hcd = platform_get_drvdata(dev);
>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>> + int clk, ret;
>> +
>> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
>> + ret = clk_prepare_enable(priv->clks[clk]);
>> + if (ret)
>> + goto err_disable_clks;
>> + }
>> +
>> + if (priv->phy) {
>> + ret = phy_init(priv->phy);
>> + if (ret)
>> + goto err_disable_clks;
>> +
>> + ret = phy_power_on(priv->phy);
>> + if (ret)
>> + goto err_exit_phy;
>> + }
>> +
>> + return 0;
>> +
>> +err_exit_phy:
>> + phy_exit(priv->phy);
>> +err_disable_clks:
>> + while (--clk >= 0)
>> + clk_disable_unprepare(priv->clks[clk]);
>> +
>> + return ret;
>> +}
>> +
>> +static void ehci_platform_power_off(struct platform_device *dev)
>> +{
>> + struct usb_hcd *hcd = platform_get_drvdata(dev);
>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>> + int clk;
>> +
>> + if (priv->phy) {
>> + phy_power_off(priv->phy);
>> + phy_exit(priv->phy);
>> + }
>> +
>> + for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
>> + if (priv->clks[clk])
>> + clk_disable_unprepare(priv->clks[clk]);
>> +}
>> +
>> static struct hc_driver __read_mostly ehci_platform_hc_driver;
>>
>> static const struct ehci_driver_overrides platform_overrides __initconst = {
>> - .reset = ehci_platform_reset,
>> + .reset = ehci_platform_reset,
>> + .extra_priv_size = sizeof(struct ehci_platform_priv),
>> };
>>
>> -static struct usb_ehci_pdata ehci_platform_defaults;
>> +static struct usb_ehci_pdata ehci_platform_defaults = {
>> + .power_on = ehci_platform_power_on,
>> + .power_suspend = ehci_platform_power_off,
>> + .power_off = ehci_platform_power_off,
>> +};
>>
>> static int ehci_platform_probe(struct platform_device *dev)
>> {
>> struct usb_hcd *hcd;
>> struct resource *res_mem;
>> - struct usb_ehci_pdata *pdata;
>> - int irq;
>> - int err;
>> + struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
>> + struct ehci_platform_priv *priv;
>> + int err, irq, clk = 0;
>>
>> if (usb_disabled())
>> return -ENODEV;
>>
>> /*
>> - * use reasonable defaults so platforms don't have to provide these.
>> - * with DT probing on ARM, none of these are set.
>> + * Use reasonable defaults so platforms don't have to provide these
>> + * with DT probing on ARM.
>> */
>> - if (!dev_get_platdata(&dev->dev))
>> - dev->dev.platform_data = &ehci_platform_defaults;
>> + if (!pdata)
>> + pdata = &ehci_platform_defaults;
>>
>> err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
>> if (err)
>> return err;
>>
>> - pdata = dev_get_platdata(&dev->dev);
>> -
>> irq = platform_get_irq(dev, 0);
>> if (irq < 0) {
>> dev_err(&dev->dev, "no irq provided");
>> @@ -107,17 +169,40 @@ static int ehci_platform_probe(struct platform_device *dev)
>> return -ENXIO;
>> }
>>
>> + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>> + dev_name(&dev->dev));
>> + if (!hcd)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(dev, hcd);
>> + dev->dev.platform_data = pdata;
>> + priv = hcd_to_ehci_priv(hcd);
>> +
>> + if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
>> + priv->phy = devm_phy_get(&dev->dev, "usb");
>> + if (IS_ERR(priv->phy)) {
>> + err = PTR_ERR(priv->phy);
>> + if (err == -EPROBE_DEFER)
>> + goto err_put_hcd;
>> + priv->phy = NULL;
>> + }
>> +
>> + for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
>> + priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
>> + if (IS_ERR(priv->clks[clk])) {
>> + err = PTR_ERR(priv->clks[clk]);
>> + if (err == -EPROBE_DEFER)
>> + goto err_put_clks;
>> + priv->clks[clk] = NULL;
>> + break;
>> + }
>> + }
>> + }
>> +
>> if (pdata->power_on) {
>> err = pdata->power_on(dev);
>> if (err < 0)
>> - return err;
>> - }
>> -
>> - hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>> - dev_name(&dev->dev));
>> - if (!hcd) {
>> - err = -ENOMEM;
>> - goto err_power;
>> + goto err_put_clks;
>> }
>>
>> hcd->rsrc_start = res_mem->start;
>> @@ -126,22 +211,28 @@ static int ehci_platform_probe(struct platform_device *dev)
>> hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
>> if (IS_ERR(hcd->regs)) {
>> err = PTR_ERR(hcd->regs);
>> - goto err_put_hcd;
>> + goto err_power;
>> }
>> err = usb_add_hcd(hcd, irq, IRQF_SHARED);
>> if (err)
>> - goto err_put_hcd;
>> + goto err_power;
>>
>> device_wakeup_enable(hcd->self.controller);
>> platform_set_drvdata(dev, hcd);
>>
>> return err;
>>
>> -err_put_hcd:
>> - usb_put_hcd(hcd);
>> err_power:
>> if (pdata->power_off)
>> pdata->power_off(dev);
>> +err_put_clks:
>> + while (--clk >= 0)
>> + clk_put(priv->clks[clk]);
>> +err_put_hcd:
>> + if (pdata == &ehci_platform_defaults)
>> + dev->dev.platform_data = NULL;
>> +
>> + usb_put_hcd(hcd);
>>
>> return err;
>> }
>> @@ -150,13 +241,19 @@ static int ehci_platform_remove(struct platform_device *dev)
>> {
>> struct usb_hcd *hcd = platform_get_drvdata(dev);
>> struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
>> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
>> + int clk;
>>
>> usb_remove_hcd(hcd);
>> - usb_put_hcd(hcd);
>>
>> if (pdata->power_off)
>> pdata->power_off(dev);
>>
>> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
>> + clk_put(priv->clks[clk]);
>> +
>> + usb_put_hcd(hcd);
>> +
>> if (pdata == &ehci_platform_defaults)
>> dev->dev.platform_data = NULL;
>>
>> @@ -207,8 +304,10 @@ static int ehci_platform_resume(struct device *dev)
>> static const struct of_device_id vt8500_ehci_ids[] = {
>> { .compatible = "via,vt8500-ehci", },
>> { .compatible = "wm,prizm-ehci", },
>> + { .compatible = "usb-ehci", },
>> {}
>> };
>> +MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
>>
>> static const struct platform_device_id ehci_platform_table[] = {
>> { "ehci-platform", 0 },
>>
>
^ permalink raw reply
* [PATCH V6 08/12] SPEAr13xx: Add binding information for PCIe controller
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <cover.1392109054.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
SPEAr13XX uses designware PCIe controller. This patch adds information
for the binding properties which are specific to SPEAr13XX SoC series.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/pci/spear13xx-pcie.txt | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..700e43e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,14 @@
+SPEAr13xx PCIe DT detail:
+================================
+
+SPEAr13xx uses synopsis designware PCIe controller and ST MiPHY40lp as phy
+controller.
+
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to phy node associated with pcie controller
+- phy-names : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
+
+ Optional properties:
+- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
--
1.7.0.1
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related
* [PATCH V6 05/12] SPEAr: misc: Add binding information
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <cover.1392109054.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
SPEAr SOCs have some miscellaneous registers which are used to configure
few properties of different peripheral controllers.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/arm/spear-misc.txt | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..ab324e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,9 @@
+SPEAr Misc configuration
+===========================
+SPEAr SOCs have some miscellaneous registers which are used to configure
+few properties of different peripheral controllers.
+
+misc node required properties:
+
+- compatible Should be "st,spear1340-misc", "syscon".
+- reg: Address range of misc space
--
1.7.0.1
--
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^ permalink raw reply related
* [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
From: Mohit Kumar @ 2014-02-11 9:29 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Pratyush Anand, Mohit Kumar, Viresh Kumar, Kishon Vijay Abraham I,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <cover.1392109054.git.mohit.kumar-qxv4g6HH51o@public.gmane.org>
From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
ST miphy40lp can be used with PCIe, SATA and Super Speed USB
controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/phy/st-miphy40lp.txt | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..1c8d04c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,18 @@
+ST miphy40lp DT detail
+===================================
+
+miphy40lp is a phy controller from ST Microelectronics which supports PCIe,
+SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs.
+
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+ Other supported soc specific compatible:
+ "st,spear1310-miphy"
+ "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - 1st cell: phandle to the phy node.
+ - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+ and 2 for Super Speed USB.
--
1.7.0.1
--
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^ permalink raw reply related
* [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support
From: Mohit Kumar @ 2014-02-11 9:29 UTC (permalink / raw)
To: arnd-r2nGTMty4D4
Cc: Mohit Kumar, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
linux-pci-u79uwXL29TY76Z2rM5mHXA,
spear-devel-nkJGhpqTU55BDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
Patch# 1 and 2: Improvement and fixes for SPEAr13xx support.
Patch# 3,5 and 8: Add DT bindings for miphy40lp, misc and pcie node
Patch# 4,6 and 7: Add miphy40lp skelten driver and support for spear1310/40
miphy wrapper.
Patch# 9-11: Add SPEAr13xx PCIe driver and dt support.
These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk-l0cyMroinI0@public.gmane.org>
Date: Mon Jan 20 16:41:27 2014 +0200
ata: ahci_platform: Manage SATA PHY
Tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config options PCIE_SPEAR13XX and PCI_MSI into defconfig patch
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to
the of_device_id instead of of_device_is_compatible.
- Incorporated other minor comments from v4
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (10):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: st-miphy40lp: Add binding information
phy: st-miphy40lp: Add skeleton driver
SPEAr: misc: Add binding information
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
SPEAr13xx: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support
.../devicetree/bindings/arm/spear-misc.txt | 9 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 14 +
.../devicetree/bindings/phy/st-miphy40lp.txt | 18 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 93 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 31 ++-
arch/arm/boot/dts/spear13xx.dtsi | 9 +-
arch/arm/configs/spear13xx_defconfig | 16 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +-----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 543 ++++++++++++++++++++
22 files changed, 1183 insertions(+), 139 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-miphy40lp.c
--
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^ permalink raw reply
* Re: [PATCH v3 7/7] devicetree: bindings: Document PM8921/8058 PMICs
From: Lee Jones @ 2014-02-11 9:29 UTC (permalink / raw)
To: Stephen Boyd
Cc: Samuel Ortiz, linux-kernel, linux-arm-msm, linux-arm-kernel,
devicetree
In-Reply-To: <1389206270-3728-8-git-send-email-sboyd@codeaurora.org>
> PM8921 and PM8058 are PMICs found paired with MSM8960 and MSM8660
> devices respectively. They contain subdevices such as keypads,
> RTCs, regulators, clocks, etc.
>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
> .../devicetree/bindings/mfd/qcom,pm8xxx.txt | 63 ++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
> new file mode 100644
> index 000000000000..e3fe625ffd58
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
> @@ -0,0 +1,63 @@
<snip>
> +- interrupts:
> + Usage: required
> + Value type: <prop-encoded-array>
Either provide an example or a comment to see the description of
#interrupt-cells
> + Definition: specifies the interrupt that indicates a subdevice
> + has generated an interrupt (summary interrupt). The
> + format of the specifier is defined by the binding document
> + describing the node's interrupt parent.
> +
> +- #interrupt-cells:
> + Usage: required
> + Value type : <u32>
> + Definition: must be 2. Specifies the number of cells needed to encode
> + an interrupt source. The 1st cell contains the interrupt
> + number. The 2nd cell is the trigger type and level flags
> + encoded as follows:
> +
> + 1 = low-to-high edge triggered
> + 2 = high-to-low edge triggered
> + 4 = active high level-sensitive
> + 8 = active low level-sensitive
Actually I'd prefer if you used the definitions in:
dt-bindings/interrupt-controller/irq.h
> +- interrupt-controller:
> + Usage: required
> + Value type: <empty>
> + Definition: identifies this node as an interrupt controller
> +
> +EXAMPLE
> +
> + pmicintc: pmic@0 {
> + compatible = "qcom,pm8921";
> + interrupts = <104 8>;
As above.
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pwrkey {
> + compatible = "qcom,pm8921-pwrkey";
> + interrupt-parent = <&pmicintc>;
> + interrupts = <50 1>, <51 1>;
As above.
> + };
> + };
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH 45/47] adv7604: Add DT support
From: Hans Verkuil @ 2014-02-11 9:23 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Hans Verkuil, Lars-Peter Clausen, devicetree
In-Reply-To: <1391618558-5580-46-git-send-email-laurent.pinchart@ideasonboard.com>
On 02/05/14 17:42, Laurent Pinchart wrote:
> Parse the device tree node to populate platform data.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> .../devicetree/bindings/media/i2c/adv7604.txt | 56 ++++++++++++
> drivers/media/i2c/adv7604.c | 101 ++++++++++++++++++---
> 2 files changed, 143 insertions(+), 14 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/i2c/adv7604.txt
>
> diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.txt b/Documentation/devicetree/bindings/media/i2c/adv7604.txt
> new file mode 100644
> index 0000000..0845c50
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/i2c/adv7604.txt
> @@ -0,0 +1,56 @@
> +* Analog Devices ADV7604/11 video decoder with HDMI receiver
> +
> +The ADV7604 and ADV7611 are multiformat video decoders with an integrated HDMI
> +receiver. The ADV7604 has four multiplexed HDMI inputs and one analog input,
> +and the ADV7611 has one HDMI input and no analog input.
> +
> +Required Properties:
> +
> + - compatible: Must contain one of the following
> + - "adi,adv7604" for the ADV7604
> + - "adi,adv7611" for the ADV7611
> +
> + - reg: I2C slave address
> +
> + - hpd-gpios: References to the GPIOs that control the HDMI hot-plug
> + detection pins, one per HDMI input. The active flag indicates the GPIO
> + level that enables hot-plug detection.
> +
> +Optional Properties:
> +
> + - reset-gpios: Reference to the GPIO connected to the device's reset pin.
> +
> + - adi,default-input: Index of the input to be configured as default. Valid
> + values are 0..5 for the ADV7604 and 0 for the ADV7611.
> +
> + - adi,disable-power-down: Boolean property. When set forces the device to
> + ignore the power-down pin. The property is valid for the ADV7604 only as
> + the ADV7611 has no power-down pin.
> +
> + - adi,disable-cable-reset: Boolean property. When set disables the HDMI
> + receiver automatic reset when the HDMI cable is unplugged.
> +
> +Example:
> +
> + hdmi_receiver@4c {
> + compatible = "adi,adv7611";
> + reg = <0x4c>;
> +
> + reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
> + hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
> +
> + adi,default-input = <0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> + port@1 {
> + reg = <1>;
> + hdmi_in: endpoint {
> + remote-endpoint = <&ccdc_in>;
> + };
> + };
> + };
> diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c
> index e586c1c..cd8a2dc 100644
> --- a/drivers/media/i2c/adv7604.c
> +++ b/drivers/media/i2c/adv7604.c
> @@ -32,6 +32,7 @@
> #include <linux/i2c.h>
> #include <linux/kernel.h>
> #include <linux/module.h>
> +#include <linux/of_gpio.h>
> #include <linux/slab.h>
> #include <linux/v4l2-dv-timings.h>
> #include <linux/videodev2.h>
> @@ -2641,13 +2642,83 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
> },
> };
>
> +static struct i2c_device_id adv7604_i2c_id[] = {
> + { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
> + { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
> + { }
> +};
> +MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
> +
> +static struct of_device_id adv7604_of_id[] = {
> + { .compatible = "adi,adv7604", .data = &adv7604_chip_info[ADV7604] },
> + { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, adv7604_of_id);
> +
> +static int adv7604_parse_dt(struct adv7604_state *state)
Put this under #ifdef CONFIG_OF. It fails to compile if CONFIG_OF is not set
(as it is in my case since this driver is used with a PCIe card).
Regards,
Hans
> +{
> + struct device_node *np;
> + unsigned int i;
> + int ret;
> +
> + np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
> + state->info = of_match_node(adv7604_of_id, np)->data;
> +
> + state->pdata.disable_pwrdnb =
> + of_property_read_bool(np, "adi,disable-power-down");
> + state->pdata.disable_cable_det_rst =
> + of_property_read_bool(np, "adi,disable-cable-reset");
> +
> + ret = of_property_read_u32(np, "adi,default-input",
> + &state->pdata.default_input);
> + if (ret < 0)
> + state->pdata.default_input = -1;
> +
> + for (i = 0; i < state->info->num_dv_ports; ++i) {
> + enum of_gpio_flags flags;
> +
> + state->pdata.hpd_gpio[i] =
> + of_get_named_gpio_flags(np, "hpd-gpios", i, &flags);
> + if (IS_ERR_VALUE(state->pdata.hpd_gpio[i]))
> + continue;
> +
> + state->pdata.hpd_gpio_low[i] = flags == OF_GPIO_ACTIVE_LOW;
> + }
> +
> + /* Disable the interrupt for now as no DT-based board uses it. */
> + state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
> +
> + /* Use the default I2C addresses. */
> + state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
> + state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
> + state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
> + state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
> + state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
> + state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
> + state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
> + state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
> + state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
> + state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
> + state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
> + state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
> +
> + /* HACK: Hardcode the remaining platform data fields. */
> + state->pdata.blank_data = 1;
> + state->pdata.op_656_range = 1;
> + state->pdata.alt_data_sat = 1;
> + state->pdata.insert_av_codes = 1;
> + state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
> +
> + return 0;
> +}
> +
> static int adv7604_probe(struct i2c_client *client,
> const struct i2c_device_id *id)
> {
> static const struct v4l2_dv_timings cea640x480 =
> V4L2_DV_BT_CEA_640X480P59_94;
> struct adv7604_state *state;
> - struct adv7604_platform_data *pdata = client->dev.platform_data;
> struct v4l2_ctrl_handler *hdl;
> struct v4l2_subdev *sd;
> unsigned int i;
> @@ -2666,19 +2737,27 @@ static int adv7604_probe(struct i2c_client *client,
> return -ENOMEM;
> }
>
> - state->info = &adv7604_chip_info[id->driver_data];
> state->i2c_clients[ADV7604_PAGE_IO] = client;
>
> /* initialize variables */
> state->restart_stdi_once = true;
> state->selected_input = ~0;
>
> - /* platform data */
> - if (!pdata) {
> + if (client->dev.of_node) {
> + err = adv7604_parse_dt(state);
> + if (err < 0) {
> + v4l_err(client, "DT parsing error\n");
> + return err;
> + }
> + } else if (client->dev.platform_data) {
> + struct adv7604_platform_data *pdata = client->dev.platform_data;
> +
> + state->info = (const struct adv7604_chip_info *)id->driver_data;
> + state->pdata = *pdata;
> + } else {
> v4l_err(client, "No platform data!\n");
> return -ENODEV;
> }
> - state->pdata = *pdata;
>
> /* Request GPIOs. */
> for (i = 0; i < state->info->num_dv_ports; ++i) {
> @@ -2786,7 +2865,7 @@ static int adv7604_probe(struct i2c_client *client,
> continue;
>
> state->i2c_clients[i] =
> - adv7604_dummy_client(sd, pdata->i2c_addresses[i],
> + adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
> 0xf2 + i);
> if (state->i2c_clients[i] == NULL) {
> err = -ENOMEM;
> @@ -2860,21 +2939,15 @@ static int adv7604_remove(struct i2c_client *client)
>
> /* ----------------------------------------------------------------------- */
>
> -static struct i2c_device_id adv7604_id[] = {
> - { "adv7604", ADV7604 },
> - { "adv7611", ADV7611 },
> - { }
> -};
> -MODULE_DEVICE_TABLE(i2c, adv7604_id);
> -
> static struct i2c_driver adv7604_driver = {
> .driver = {
> .owner = THIS_MODULE,
> .name = "adv7604",
> + .of_match_table = of_match_ptr(adv7604_of_id),
> },
> .probe = adv7604_probe,
> .remove = adv7604_remove,
> - .id_table = adv7604_id,
> + .id_table = adv7604_i2c_id,
> };
>
> module_i2c_driver(adv7604_driver);
>
^ permalink raw reply
* Re: [PATCH v9 2/4] ehci-platform: Add support for clks and phy passed through devicetree
From: Roger Quadros @ 2014-02-11 9:12 UTC (permalink / raw)
To: Hans de Goede, Greg Kroah-Hartman
Cc: Alan Stern, Tony Prisk, linux-usb, Maxime Ripard,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
Menon, Nishanth, Kevin Hilman
In-Reply-To: <1391787403-20961-3-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Hi Hans,
On 02/07/2014 05:36 PM, Hans de Goede wrote:
> Currently ehci-platform is only used in combination with devicetree when used
> with some Via socs. By extending it to (optionally) get clks and a phy from
> devicetree, and enabling / disabling those on power_on / off, it can be used
> more generically. Specifically after this commit it can be used for the
> ehci controller on Allwinner sunxi SoCs.
>
> Since ehci-platform is intended to handle any generic enough non pci ehci
> device, add a "usb-ehci" compatibility string.
>
> There already is a usb-ehci device-tree bindings document, update this
> with clks and phy bindings info.
>
> Although actually quite generic so far the via,vt8500 compatibilty string
> had its own bindings document. Somehow we even ended up with 2 of them. Since
> these provide no extra information over the generic usb-ehci documentation,
> this patch removes them.
>
> The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
> even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
> not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
> 2 drivers claiming the same compatibility string getting build on ppc.
>
This breaks all OMAP platforms on linux-next for the exact same reason. see [1].
./arch/arm/boot/dts/omap4.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
./arch/arm/boot/dts/omap3.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
./arch/arm/boot/dts/omap5.dtsi: compatible = "ti,ehci-omap", "usb-ehci";
The other platforms that claim compatibility with "usb-ehci" are
ARM
./arch/arm/boot/dts/tegra30.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
./arch/arm/boot/dts/tegra20.dtsi: compatible = "nvidia,tegra20-ehci", "usb-ehci";
./arch/arm/boot/dts/spear600.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
./arch/arm/boot/dts/spear3xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
./arch/arm/boot/dts/sama5d3.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
./arch/arm/boot/dts/at91sam9g45.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
./arch/arm/boot/dts/spear13xx.dtsi: compatible = "st,spear600-ehci", "usb-ehci";
./arch/arm/boot/dts/at91sam9x5.dtsi: compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
./arch/arm/boot/dts/tegra114.dtsi: compatible = "nvidia,tegra30-ehci", "usb-ehci";
MIPS
./arch/mips/cavium-octeon/octeon_68xx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
./arch/mips/cavium-octeon/octeon_3xxx.dts: compatible = "cavium,octeon-6335-ehci","usb-ehci";
Do we know that we don't break these platforms as well?
cheers,
-roger
[1] - http://marc.info/?l=linux-usb&m=139204800102167&w=2
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> Acked-by: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
> ---
> Documentation/devicetree/bindings/usb/usb-ehci.txt | 25 +++-
> .../devicetree/bindings/usb/via,vt8500-ehci.txt | 15 ---
> .../devicetree/bindings/usb/vt8500-ehci.txt | 12 --
> drivers/usb/host/Kconfig | 1 +
> drivers/usb/host/ehci-platform.c | 147 +++++++++++++++++----
> 5 files changed, 142 insertions(+), 58 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
> delete mode 100644 Documentation/devicetree/bindings/usb/vt8500-ehci.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> index fa18612..2c1aeeb 100644
> --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
> +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> @@ -7,13 +7,14 @@ Required properties:
> (debug-port or other) can be also specified here, but only after
> definition of standard EHCI registers.
> - interrupts : one EHCI interrupt should be described here.
> -If device registers are implemented in big endian mode, the device
> -node should have "big-endian-regs" property.
> -If controller implementation operates with big endian descriptors,
> -"big-endian-desc" property should be specified.
> -If both big endian registers and descriptors are used by the controller
> -implementation, "big-endian" property can be specified instead of having
> -both "big-endian-regs" and "big-endian-desc".
> +
> +Optional properties:
> + - big-endian-regs : boolean, set this for hcds with big-endian registers
> + - big-endian-desc : boolean, set this for hcds with big-endian descriptors
> + - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
> + - clocks : a list of phandle + clock specifier pairs
> + - phys : phandle + phy specifier pair
> + - phy-names : "usb"
>
> Example (Sequoia 440EPx):
> ehci@e0000300 {
> @@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
> reg = <0 e0000300 90 0 e0000390 70>;
> big-endian;
> };
> +
> +Example (Allwinner sun4i A10 SoC):
> + ehci0: usb@01c14000 {
> + compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
> + reg = <0x01c14000 0x100>;
> + interrupts = <39>;
> + clocks = <&ahb_gates 1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + };
> diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
> deleted file mode 100644
> index 17b3ad1..0000000
> --- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -VIA/Wondermedia VT8500 EHCI Controller
> ------------------------------------------------------
> -
> -Required properties:
> -- compatible : "via,vt8500-ehci"
> -- reg : Should contain 1 register ranges(address and length)
> -- interrupts : ehci controller interrupt
> -
> -Example:
> -
> - ehci@d8007900 {
> - compatible = "via,vt8500-ehci";
> - reg = <0xd8007900 0x200>;
> - interrupts = <43>;
> - };
> diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
> deleted file mode 100644
> index 5fb8fd6..0000000
> --- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
> -
> -Required properties:
> - - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
> - - reg: Address range of the ehci registers. size should be 0x200
> - - interrupts: Should contain the ehci interrupt.
> -
> -usb: ehci@D8007100 {
> - compatible = "wm,prizm-ehci", "usb-ehci";
> - reg = <0xD8007100 0x200>;
> - interrupts = <1>;
> -};
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index a9707da..e28cbe0 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -255,6 +255,7 @@ config USB_EHCI_ATH79
>
> config USB_EHCI_HCD_PLATFORM
> tristate "Generic EHCI driver for a platform device"
> + depends on !PPC_OF
> default n
> ---help---
> Adds an EHCI host driver for a generic platform device, which
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index 01536cf..5ebd0b7 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -3,6 +3,7 @@
> *
> * Copyright 2007 Steven Brown <sbrown-aLUkz7fEuXBWk0Htik3J/w@public.gmane.org>
> * Copyright 2010-2012 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> + * Copyright 2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> *
> * Derived from the ohci-ssb driver
> * Copyright 2007 Michael Buesch <m@bues.ch>
> @@ -18,6 +19,7 @@
> *
> * Licensed under the GNU/GPL. See COPYING for details.
> */
> +#include <linux/clk.h>
> #include <linux/dma-mapping.h>
> #include <linux/err.h>
> #include <linux/kernel.h>
> @@ -25,6 +27,7 @@
> #include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/usb.h>
> #include <linux/usb/hcd.h>
> @@ -33,6 +36,13 @@
> #include "ehci.h"
>
> #define DRIVER_DESC "EHCI generic platform driver"
> +#define EHCI_MAX_CLKS 3
> +#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
> +
> +struct ehci_platform_priv {
> + struct clk *clks[EHCI_MAX_CLKS];
> + struct phy *phy;
> +};
>
> static const char hcd_name[] = "ehci-platform";
>
> @@ -64,38 +74,90 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
> return 0;
> }
>
> +static int ehci_platform_power_on(struct platform_device *dev)
> +{
> + struct usb_hcd *hcd = platform_get_drvdata(dev);
> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
> + int clk, ret;
> +
> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
> + ret = clk_prepare_enable(priv->clks[clk]);
> + if (ret)
> + goto err_disable_clks;
> + }
> +
> + if (priv->phy) {
> + ret = phy_init(priv->phy);
> + if (ret)
> + goto err_disable_clks;
> +
> + ret = phy_power_on(priv->phy);
> + if (ret)
> + goto err_exit_phy;
> + }
> +
> + return 0;
> +
> +err_exit_phy:
> + phy_exit(priv->phy);
> +err_disable_clks:
> + while (--clk >= 0)
> + clk_disable_unprepare(priv->clks[clk]);
> +
> + return ret;
> +}
> +
> +static void ehci_platform_power_off(struct platform_device *dev)
> +{
> + struct usb_hcd *hcd = platform_get_drvdata(dev);
> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
> + int clk;
> +
> + if (priv->phy) {
> + phy_power_off(priv->phy);
> + phy_exit(priv->phy);
> + }
> +
> + for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
> + if (priv->clks[clk])
> + clk_disable_unprepare(priv->clks[clk]);
> +}
> +
> static struct hc_driver __read_mostly ehci_platform_hc_driver;
>
> static const struct ehci_driver_overrides platform_overrides __initconst = {
> - .reset = ehci_platform_reset,
> + .reset = ehci_platform_reset,
> + .extra_priv_size = sizeof(struct ehci_platform_priv),
> };
>
> -static struct usb_ehci_pdata ehci_platform_defaults;
> +static struct usb_ehci_pdata ehci_platform_defaults = {
> + .power_on = ehci_platform_power_on,
> + .power_suspend = ehci_platform_power_off,
> + .power_off = ehci_platform_power_off,
> +};
>
> static int ehci_platform_probe(struct platform_device *dev)
> {
> struct usb_hcd *hcd;
> struct resource *res_mem;
> - struct usb_ehci_pdata *pdata;
> - int irq;
> - int err;
> + struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
> + struct ehci_platform_priv *priv;
> + int err, irq, clk = 0;
>
> if (usb_disabled())
> return -ENODEV;
>
> /*
> - * use reasonable defaults so platforms don't have to provide these.
> - * with DT probing on ARM, none of these are set.
> + * Use reasonable defaults so platforms don't have to provide these
> + * with DT probing on ARM.
> */
> - if (!dev_get_platdata(&dev->dev))
> - dev->dev.platform_data = &ehci_platform_defaults;
> + if (!pdata)
> + pdata = &ehci_platform_defaults;
>
> err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
> if (err)
> return err;
>
> - pdata = dev_get_platdata(&dev->dev);
> -
> irq = platform_get_irq(dev, 0);
> if (irq < 0) {
> dev_err(&dev->dev, "no irq provided");
> @@ -107,17 +169,40 @@ static int ehci_platform_probe(struct platform_device *dev)
> return -ENXIO;
> }
>
> + hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
> + dev_name(&dev->dev));
> + if (!hcd)
> + return -ENOMEM;
> +
> + platform_set_drvdata(dev, hcd);
> + dev->dev.platform_data = pdata;
> + priv = hcd_to_ehci_priv(hcd);
> +
> + if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
> + priv->phy = devm_phy_get(&dev->dev, "usb");
> + if (IS_ERR(priv->phy)) {
> + err = PTR_ERR(priv->phy);
> + if (err == -EPROBE_DEFER)
> + goto err_put_hcd;
> + priv->phy = NULL;
> + }
> +
> + for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
> + priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
> + if (IS_ERR(priv->clks[clk])) {
> + err = PTR_ERR(priv->clks[clk]);
> + if (err == -EPROBE_DEFER)
> + goto err_put_clks;
> + priv->clks[clk] = NULL;
> + break;
> + }
> + }
> + }
> +
> if (pdata->power_on) {
> err = pdata->power_on(dev);
> if (err < 0)
> - return err;
> - }
> -
> - hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
> - dev_name(&dev->dev));
> - if (!hcd) {
> - err = -ENOMEM;
> - goto err_power;
> + goto err_put_clks;
> }
>
> hcd->rsrc_start = res_mem->start;
> @@ -126,22 +211,28 @@ static int ehci_platform_probe(struct platform_device *dev)
> hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
> if (IS_ERR(hcd->regs)) {
> err = PTR_ERR(hcd->regs);
> - goto err_put_hcd;
> + goto err_power;
> }
> err = usb_add_hcd(hcd, irq, IRQF_SHARED);
> if (err)
> - goto err_put_hcd;
> + goto err_power;
>
> device_wakeup_enable(hcd->self.controller);
> platform_set_drvdata(dev, hcd);
>
> return err;
>
> -err_put_hcd:
> - usb_put_hcd(hcd);
> err_power:
> if (pdata->power_off)
> pdata->power_off(dev);
> +err_put_clks:
> + while (--clk >= 0)
> + clk_put(priv->clks[clk]);
> +err_put_hcd:
> + if (pdata == &ehci_platform_defaults)
> + dev->dev.platform_data = NULL;
> +
> + usb_put_hcd(hcd);
>
> return err;
> }
> @@ -150,13 +241,19 @@ static int ehci_platform_remove(struct platform_device *dev)
> {
> struct usb_hcd *hcd = platform_get_drvdata(dev);
> struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
> + struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
> + int clk;
>
> usb_remove_hcd(hcd);
> - usb_put_hcd(hcd);
>
> if (pdata->power_off)
> pdata->power_off(dev);
>
> + for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
> + clk_put(priv->clks[clk]);
> +
> + usb_put_hcd(hcd);
> +
> if (pdata == &ehci_platform_defaults)
> dev->dev.platform_data = NULL;
>
> @@ -207,8 +304,10 @@ static int ehci_platform_resume(struct device *dev)
> static const struct of_device_id vt8500_ehci_ids[] = {
> { .compatible = "via,vt8500-ehci", },
> { .compatible = "wm,prizm-ehci", },
> + { .compatible = "usb-ehci", },
> {}
> };
> +MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
>
> static const struct platform_device_id ehci_platform_table[] = {
> { "ehci-platform", 0 },
>
^ permalink raw reply
* Re: [PATCH v6 01/19] clocksource: orion: Use atomic access for shared registers
From: Daniel Lezcano @ 2014-02-11 9:11 UTC (permalink / raw)
To: Ezequiel Garcia
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA, Wim Van Sebroeck,
Jason Cooper, Thomas Petazzoni, Gregory Clement, Lior Amsalem,
Sebastian Hesselbarth, Andrew Lunn
In-Reply-To: <20140211083024.GA3687@localhost>
On 02/11/2014 09:30 AM, Ezequiel Garcia wrote:
> On Tue, Feb 11, 2014 at 01:06:43AM +0100, Daniel Lezcano wrote:
>> On 02/06/2014 06:20 PM, Ezequiel Garcia wrote:
>>> Replace the driver-specific thread-safe shared register API
>>> by the recently introduced atomic_io_clear_set().
>>>
>>> Cc: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>> Tested-by: Willy Tarreau <w@1wt.eu>
>>> Acked-by: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
>>> Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>
>> The patch looks good for me.
>>
>> Acked-by: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>
>
> Daniel,
>
> Jason acked this patch for you to take it. Or do you prefer that we
> merge it with the rest of the watchdog series?
I can pick it, but doesn't the watchdog series depend on it ?
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^ permalink raw reply
* Re: [PATCH V3] net/dt: Add support for overriding phy configuration from device tree
From: Gerlando Falauto @ 2014-02-11 9:09 UTC (permalink / raw)
To: Florian Fainelli
Cc: Matthew Garrett, netdev, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Kishon Vijay Abraham I
In-Reply-To: <29007785.iYrLORbRAN@lenovo>
Hi Florian,
first of all, thank you for your answer.
On 02/10/2014 06:09 PM, Florian Fainelli wrote:
> Hi Gerlando,
>
> Le lundi 10 février 2014, 17:14:59 Gerlando Falauto a écrit :
>> Hi,
>>
>> I'm currently trying to fix an issue for which this patch provides a
>> partial solution, so apologies in advance for jumping into the
>> discussion for my own purposes...
>>
>> On 02/04/2014 09:39 PM, Florian Fainelli wrote:> 2014-01-17 Matthew
>>
>> Garrett <matthew.garrett@nebula.com>:
>> >> Some hardware may be broken in interesting and board-specific ways, such
>> >> that various bits of functionality don't work. This patch provides a
>> >> mechanism for overriding mii registers during init based on the
>>
>> contents of
>>
>> >> the device tree data, allowing board-specific fixups without having to
>> >> pollute generic code.
>> >
>> > It would be good to explain exactly how your hardware is broken
>> > exactly. I really do not think that such a fine-grained setting where
>> > you could disable, e.g: 100BaseT_Full, but allow 100BaseT_Half to
>> > remain usable makes that much sense. In general, Gigabit might be
>> > badly broken, but 100 and 10Mbits/sec should work fine. How about the
>> > MASTER-SLAVE bit, is overriding it really required?
>> >
>> > Is not a PHY fixup registered for a specific OUI the solution you are
>> > looking for? I am also concerned that this creates PHY troubleshooting
>> > issues much harder to debug than before as we may have no idea about
>> > how much information has been put in Device Tree to override that.
>> >
>> > Finally, how about making this more general just like the BCM87xx PHY
>> > driver, which is supplied value/reg pairs directly? There are 16
>> > common MII registers, and 16 others for vendor specific registers,
>> > this is just covering for about 2% of the possible changes.
>>
>> Good point. That would easily help me with my current issue, which
>> requires autoneg to be disabled to begin with (by clearing BMCR_ANENABLE
>> from register 0).
>
> Is there a point in time (e.g: after some specific initial configuration has
> been made) where BMCR_ANENABLE can be used?
What do you mean? In my case, for some HW-related reason (due to the PHY
counterpart I guess) autoneg needs to be disabled.
This is currently done by the bootloader code (which clears the bit).
What I'm looking for is some way for the kernel to either reinforce this
setting, or just take that into account and skip autoneg.
On top of that, there's a HW errata about that particular PHY, which
requires certain operations to be performed on the PHY as a workaround
*WHEN AUTONEG IS DISABLED*. That I'd implement on a PHY-specif driver.
>> This would not however fix it entirely (I tried a quick hardwired
>> implementation), as the whole PHY machinery would not take that into
>> account and would re-enable autoneg anyway.
>> I also tried changing the patch so that phydev->support gets updated
>
> There are multiple things that you could try doing here:
>
> - override the PHY state machine in your read_status callback to make sure
> that you always set phydev->autoneg set to AUTONEG_ENABLE
[you mean AUTONEG_DISABLE, right?]
Uhm, but I don't want to implement a driver for that PHY that always
disables autoneg. I only want to disable autoneg for that particular
board. I figure I might register a fixup for that board, but that kindof
makes everything more complicated and less clear. Plus, what should be
the criterion to determine whether we're running on that particular
hardware?
> - clear the SUPPORTED_Autoneg bits from phydev->supported right after PHY
> registration and before the call to phy_start()
I actually tried clearing it by tweaking the patch on this thread, but
the end result is that it does not produce any effect (see further
comments below). Only thing that seems to play a role here is explictly
setting phydev->autoneg = AUTONEG_DISABLE.
> - set the PHY_HAS_MAGICANEG bit in your PHY driver flag
Again, this seems to play no role whatsoever here:
} else if (0 == phydev->link_timeout--) {
needs_aneg = 1;
/* If we have the magic_aneg bit,
* we try again */
if (phydev->drv->flags & PHY_HAS_MAGICANEG)
break;
}
break;
case PHY_NOLINK:
This code might have made sense when it was written in 2006 -- back
then, the break statement was skipping some fallback code. But now it
seems to do nothing.
>
>>
>> (instead of phydev->advertising):
>> >> + if (!of_property_read_u32(np, override->prop, &tmp)) {
>> >> + if (tmp) {
>> >> + *val |= override->value;
>> >> + phydev->advertising |=
>>
>> override->supported;
>>
>> >> + } else {
>> >> + phydev->advertising &=
>>
>> ~(override->supported);
>>
>> >> + }
>> >> +
>> >> + *mask |= override->value;
>>
>> What I find weird is that the only way phydev->autoneg could ever be set
>> to disabled is from here (phy.c):
>>
>> static void phy_sanitize_settings(struct phy_device *phydev)
>> {
>> u32 features = phydev->supported;
>> int idx;
>>
>> /* Sanitize settings based on PHY capabilities */
>> if ((features & SUPPORTED_Autoneg) == 0)
>> phydev->autoneg = AUTONEG_DISABLE;
>>
>> which is in turn only called when phydev->autoneg is set to
>> AUTONEG_DISABLE to begin with:
>>
>> int phy_start_aneg(struct phy_device *phydev)
>> {
>> int err;
>>
>> mutex_lock(&phydev->lock);
>>
>> if (AUTONEG_DISABLE == phydev->autoneg)
>> phy_sanitize_settings(phydev);
>>
>> So could someone please help me figure out what I'm missing here?
>
> At first glance it looks like the PHY driver should be reading the phydev-
>> autoneg value when the PHY driver config_aneg() callback is called to be
> allowed to set the forced speed and settings.
>
> The way phy_sanitize_settings() is coded does not make it return a mask of
> features, but only the forced supported speed and duplex. Then when the link
> is forced but we are having some issues getting a link status, libphy tries
> lower speeds and this function is used again to provide the next speed/duplex
> pair to try.
>
What I was trying to say is that phy_sanitize_settings() is only called
when phydev->autoneg == AUTONEG_DISABLE, and in turn it's the only
generic function setting phydev->autoneg = AUTONEG_DISABLE.
So perhaps the condition should read:
- if (AUTONEG_DISABLE == phydev->autoneg)
+ if ((features & SUPPORTED_Autoneg) == 0)
phy_sanitize_settings(phydev);
Or else, some other parts of the generic code should take care of
setting it to AUTONEG_DISABLE, depending on whether the feature is
supported or not.
What I found weird is explicitly setting a value (phydev->autoneg =
AUTONEG_DISABLE), from a static function which is only called when that
condition is already true.
BTW, I feel like disabling autoneg from the start has never been a use
case before, am I right?
Thanks!
Gerlando
^ permalink raw reply
* Re: [PATCH v2 1/3] net: stmmac:sti: Add STi SOC glue driver.
From: srinivas kandagatla @ 2014-02-11 9:01 UTC (permalink / raw)
To: David Miller
Cc: netdev, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
rob, linux, stuart.menefy, peppe.cavallaro, devicetree, linux-doc,
linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20140210.144054.2066120014050984537.davem@davemloft.net>
Thankyou Dave,
I will fix these in next version.
On 10/02/14 22:40, David Miller wrote:
> From: <srinivas.kandagatla@st.com>
> Date: Fri, 7 Feb 2014 10:55:25 +0000
>
>> + if (dwmac->interface == PHY_INTERFACE_MODE_MII ||
>> + dwmac->interface == PHY_INTERFACE_MODE_GMII) {
>
> This is not indented correctly, the first character on the second line should
> line up exactly at the column after the openning parenthesis on the first
> line.
>
> The objective is not to indent using only TAB characters, which you
> are doing here.
>
> Rather, the objective is to use the appropriate number of TAB _and_
> space characters necessary to reach the proper column.
>
>> + const char *rs;
>> + err = of_property_read_string(np, "st,tx-retime-src", &rs);
>
> Please add an empty line after the local variable declaration.
>
>> + if (!strcasecmp(rs, "clk_125"))
>> + dwmac->is_tx_retime_src_clk_125 = true;
>> +
>> + }
>
> That empty line is superfluous, please delete it.
>
>
Thanks,
srini
^ permalink raw reply
* [PATCH 2/2] ARM: shmobile: bockw reference dts: Add SPI FLASH
From: Geert Uytterhoeven @ 2014-02-11 8:56 UTC (permalink / raw)
To: Simon Horman, Kuninori Morimoto
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-sh-u79uwXL29TY76Z2rM5mHXA,
Geert Uytterhoeven
In-Reply-To: <1392109008-29941-1-git-send-email-geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Add Spansion s25fl008k SPI FLASH and MTD partition, based on bockw legacy
board code.
Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
---
Untested due to lack of hardware
arch/arm/boot/dts/r8a7778-bockw-reference.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 06cda19dac6a..f76f6ec01e19 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -109,4 +109,18 @@
pinctrl-0 = <&hspi0_pins>;
pinctrl-names = "default";
status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl008k";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ m25p,fast-read;
+
+ partition@0 {
+ label = "data(spi)";
+ reg = <0x00000000 0x00100000>;
+ };
+ };
};
--
1.7.9.5
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* [PATCH 1/2] ARM: shmobile: r8a7778/r8a7779 dtsi: Improve and correct HSPI bindings
From: Geert Uytterhoeven @ 2014-02-11 8:56 UTC (permalink / raw)
To: Simon Horman, Kuninori Morimoto
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-sh-u79uwXL29TY76Z2rM5mHXA,
Geert Uytterhoeven, Mark Brown
From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Binding documentation:
- Add future-proof "renesas,hspi-<soctype>" compatible values,
- Add "interrupt-parent", "#address-cells" and "#size-cells" properties,
- Add reference to pinctrl documentation,
- Add example bindings.
r8a7778 and r8a7779 dtsi:
- Add "renesas,hspi-r8a7778" resp. "renesas,hspi-r8a7779" compatible
values,
- Correct reference to parent interrupt controller
(use "interrupt-parent" instead of "interrupt-controller"),
- Add missing "#address-cells" and "#size-cells" properties, which are
needed when populating the SPI buses.
Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Untested due to lack of hardware
Documentation/devicetree/bindings/spi/sh-hspi.txt | 27 ++++++++++++++++++---
arch/arm/boot/dts/r8a7778.dtsi | 18 +++++++++-----
arch/arm/boot/dts/r8a7779.dtsi | 18 +++++++++-----
3 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/sh-hspi.txt b/Documentation/devicetree/bindings/spi/sh-hspi.txt
index 30b57b1c8a13..d43080eb6b3a 100644
--- a/Documentation/devicetree/bindings/spi/sh-hspi.txt
+++ b/Documentation/devicetree/bindings/spi/sh-hspi.txt
@@ -1,7 +1,28 @@
Renesas HSPI.
Required properties:
-- compatible : "renesas,hspi"
-- reg : Offset and length of the register set for the device
-- interrupts : interrupt line used by HSPI
+- compatible : "renesas,hspi-<soctype>", "renesas,hspi" as fallback.
+ Examples of valid soctypes are "r8a7778" (R-Car M1),
+ and "r8a7779" (R-Car H1)
+- reg : Offset and length of the register set for the device
+- interrupt-parent : The phandle for the interrupt controller that
+ services interrupts for this device
+- interrupts : Interrupt specifier
+- #address-cells : Must be <1>
+- #size-cells : Must be <0>
+
+Pinctrl properties might be needed, too. See
+Documentation/devicetree/bindings/pinctrl/renesas,*.
+
+Example:
+
+ hspi0: spi@fffc7000 {
+ compatible = "renesas,hspi-r8a7778", "renesas,hspi";
+ reg = <0xfffc7000 0x18>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 85c5b3b99f5e..3c6fab5c9702 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -204,26 +204,32 @@
};
hspi0: spi@fffc7000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc7000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
hspi1: spi@fffc8000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc8000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
hspi2: spi@fffc6000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc6000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4c7c46..8b1a336ee401 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -256,26 +256,32 @@
};
hspi0: spi@fffc7000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc7000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
hspi1: spi@fffc8000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc8000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
hspi2: spi@fffc6000 {
- compatible = "renesas,hspi";
+ compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc6000 0x18>;
- interrupt-controller = <&gic>;
+ interrupt-parent = <&gic>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
};
--
1.7.9.5
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