* Re: [PATCH] net: stmmac: Add OXNAS Glue Driver
From: Neil Armstrong @ 2016-10-21 14:43 UTC (permalink / raw)
To: Joachim Eastwood
Cc: peppe.cavallaro, alexandre.torgue, netdev, linux-oxnas,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree
In-Reply-To: <CAGhQ9Vxe8fe8kfF_WY40xdh6YX9TuxQ3-Dd6pBG=AHpLtrHnMA@mail.gmail.com>
On 10/21/2016 12:20 PM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 21 October 2016 at 10:44, Neil Armstrong <narmstrong@baylibre.com> wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../devicetree/bindings/net/oxnas-dwmac.txt | 44 +++++
>> drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
>> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
>> drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 219 +++++++++++++++++++++
>> 4 files changed, 275 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
>> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
>>
>> Changes since RFC at https://patchwork.kernel.org/patch/9387257 :
>> - Drop init/exit callbacks
>> - Implement proper remove and PM callback
>> - Call init from probe
>> - Disable/Unprepare clock if stmmac probe fails
>
> <snip>
>
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
>> @@ -0,0 +1,219 @@
>> +/*
>> + * Oxford Semiconductor OXNAS DWMAC glue layer
>> + *
>> + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
>> + * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
>> + * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
>> + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/stmmac.h>
>> +
>> +#include "stmmac_platform.h"
>> +
>> +/* System Control regmap offsets */
>> +#define OXNAS_DWMAC_CTRL_REGOFFSET 0x78
>> +#define OXNAS_DWMAC_DELAY_REGOFFSET 0x100
>> +
>> +/* Control Register */
>> +#define DWMAC_CKEN_RX_IN 14
>> +#define DWMAC_CKEN_RXN_OUT 13
>> +#define DWMAC_CKEN_RX_OUT 12
>> +#define DWMAC_CKEN_TX_IN 10
>> +#define DWMAC_CKEN_TXN_OUT 9
>> +#define DWMAC_CKEN_TX_OUT 8
>> +#define DWMAC_RX_SOURCE 7
>> +#define DWMAC_TX_SOURCE 6
>> +#define DWMAC_LOW_TX_SOURCE 4
>> +#define DWMAC_AUTO_TX_SOURCE 3
>> +#define DWMAC_RGMII 2
>> +#define DWMAC_SIMPLE_MUX 1
>> +#define DWMAC_CKEN_GTX 0
>> +
>> +/* Delay register */
>> +#define DWMAC_TX_VARDELAY_SHIFT 0
>> +#define DWMAC_TXN_VARDELAY_SHIFT 8
>> +#define DWMAC_RX_VARDELAY_SHIFT 16
>> +#define DWMAC_RXN_VARDELAY_SHIFT 24
>> +#define DWMAC_TX_VARDELAY(d) ((d) << DWMAC_TX_VARDELAY_SHIFT)
>> +#define DWMAC_TXN_VARDELAY(d) ((d) << DWMAC_TXN_VARDELAY_SHIFT)
>> +#define DWMAC_RX_VARDELAY(d) ((d) << DWMAC_RX_VARDELAY_SHIFT)
>> +#define DWMAC_RXN_VARDELAY(d) ((d) << DWMAC_RXN_VARDELAY_SHIFT)
>> +
>> +struct oxnas_dwmac {
>> + struct device *dev;
>> + struct clk *clk;
>> + struct regmap *regmap;
>> +};
>> +
>> +static int oxnas_dwmac_init(struct oxnas_dwmac *dwmac)
>> +{
>> + unsigned int value;
>> + int ret;
>> +
>> + /* Reset HW here before changing the glue configuration */
>> + ret = device_reset(dwmac->dev);
>> + if (ret)
>> + return ret;
>> +
>> + clk_prepare_enable(dwmac->clk);
>
> You might want to check the return value from clk_prepare_enable() as well.
>
>> +
>> + ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value);
>> + if (ret < 0)
>> + return ret;
>> +
>> + /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
>> + value |= BIT(DWMAC_CKEN_GTX);
>> + /* Use simple mux for 25/125 Mhz clock switching */
>> + value |= BIT(DWMAC_SIMPLE_MUX);
>> + /* set auto switch tx clock source */
>> + value |= BIT(DWMAC_AUTO_TX_SOURCE);
>> + /* enable tx & rx vardelay */
>> + value |= BIT(DWMAC_CKEN_TX_OUT);
>> + value |= BIT(DWMAC_CKEN_TXN_OUT);
>> + value |= BIT(DWMAC_CKEN_TX_IN);
>> + value |= BIT(DWMAC_CKEN_RX_OUT);
>> + value |= BIT(DWMAC_CKEN_RXN_OUT);
>> + value |= BIT(DWMAC_CKEN_RX_IN);
>> + regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value);
>> +
>> + /* set tx & rx vardelay */
>> + value = DWMAC_TX_VARDELAY(4);
>> + value |= DWMAC_TXN_VARDELAY(2);
>> + value |= DWMAC_RX_VARDELAY(10);
>> + value |= DWMAC_RXN_VARDELAY(8);
>> + regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value);
>> +
>> + return 0;
>> +}
>> +
>> +static int oxnas_dwmac_probe(struct platform_device *pdev)
>> +{
>> + struct plat_stmmacenet_data *plat_dat;
>> + struct stmmac_resources stmmac_res;
>> + struct device_node *sysctrl;
>> + struct oxnas_dwmac *dwmac;
>> + int ret;
>> +
>> + sysctrl = of_parse_phandle(pdev->dev.of_node, "oxsemi,sys-ctrl", 0);
>> + if (!sysctrl) {
>> + dev_err(&pdev->dev, "failed to get sys-ctrl node\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = stmmac_get_platform_resources(pdev, &stmmac_res);
>> + if (ret)
>> + return ret;
>> +
>> + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
>> + if (IS_ERR(plat_dat))
>> + return PTR_ERR(plat_dat);
>> +
>> + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
>> + if (!dwmac)
>> + return -ENOMEM;
>> +
>> + dwmac->dev = &pdev->dev;
>> + plat_dat->bsp_priv = dwmac;
>> +
>> + dwmac->regmap = syscon_node_to_regmap(sysctrl);
>> + if (IS_ERR(dwmac->regmap)) {
>> + dev_err(&pdev->dev, "failed to have sysctrl regmap\n");
>> + return PTR_ERR(dwmac->regmap);
>> + }
>> +
>> + dwmac->clk = devm_clk_get(&pdev->dev, "gmac");
>> + if (IS_ERR(dwmac->clk))
>> + return PTR_ERR(dwmac->clk);
>> +
>> + ret = oxnas_dwmac_init(dwmac);
>> + if (ret)
>> + return ret;
>> +
>> + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
>> + if (ret)
>> + clk_disable_unprepare(dwmac->clk);
>> +
>> + return ret;
>> +}
>> +
>> +static int oxnas_dwmac_remove(struct platform_device *pdev)
>> +{
>> + struct net_device *ndev = platform_get_drvdata(pdev);
>> + struct stmmac_priv *priv = netdev_priv(ndev);
>> + struct oxnas_dwmac *dwmac = priv->plat->bsp_priv;
>
> Instead of this long dance of variables use the get_stmmac_bsp_priv()-helper.
>
> You can take a look at dwmac-meson8b.c for reference.
>
>
>> + int ret = stmmac_dvr_remove(&pdev->dev);
>> +
>> + clk_disable_unprepare(dwmac->clk);
>> +
>> + return ret;
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int oxnas_dwmac_suspend(struct device *dev)
>> +{
>> + struct net_device *ndev = dev_get_drvdata(dev);
>> + struct stmmac_priv *priv = netdev_priv(ndev);
>> + struct oxnas_dwmac *dwmac = priv->plat->bsp_priv;
>
> get_stmmac_bsp_priv()
>
>
>> + int ret;
>> +
>> + ret = stmmac_suspend(dev);
>> + clk_disable_unprepare(dwmac->clk);
>> +
>> + return ret;
>> +}
>> +
>> +static int oxnas_dwmac_resume(struct device *dev)
>> +{
>> + struct net_device *ndev = dev_get_drvdata(dev);
>> + struct stmmac_priv *priv = netdev_priv(ndev);
>> + struct oxnas_dwmac *dwmac = priv->plat->bsp_priv;
>
> get_stmmac_bsp_priv()
>
>
>> + int ret;
>> +
>> + ret = oxnas_dwmac_init(dwmac);
>> + if (ret)
>> + return ret;
>> +
>> + ret = stmmac_resume(dev);
>> +
>> + return ret;
>> +}
>> +#endif /* CONFIG_PM_SLEEP */
>
> With these changes:
> Acked-by: Joachim Eastwood <manabian@gmail.com>
>
>
> best regards,
> Joachim Eastwood
>
Thanks,
Will do this for v2
Neil
^ permalink raw reply
* Re: [PATCH] net: stmmac: Add OXNAS Glue Driver
From: Neil Armstrong @ 2016-10-21 14:43 UTC (permalink / raw)
To: Giuseppe CAVALLARO, Joachim Eastwood
Cc: alexandre.torgue, netdev, linux-oxnas,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree
In-Reply-To: <474261f0-1cb7-5932-4c9f-0cbcc705fa61@st.com>
On 10/21/2016 01:53 PM, Giuseppe CAVALLARO wrote:
> Hello
>
> some my minor cents below
>
> On 10/21/2016 12:20 PM, Joachim Eastwood wrote:
>> Hi Neil,
>>
>> On 21 October 2016 at 10:44, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>> ---
>>> .../devicetree/bindings/net/oxnas-dwmac.txt | 44 +++++
>>> drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
>>> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
>>> drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 219 +++++++++++++++++++++
>>> 4 files changed, 275 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
>>> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
>>>
>>> Changes since RFC at https://patchwork.kernel.org/patch/9387257 :
>>> - Drop init/exit callbacks
>>> - Implement proper remove and PM callback
>>> - Call init from probe
>>> - Disable/Unprepare clock if stmmac probe fails
>>
>> <snip>
>>
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c
>>> @@ -0,0 +1,219 @@
>>> +/*
>>> + * Oxford Semiconductor OXNAS DWMAC glue layer
>>> + *
>>> + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
>>> + * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
>>> + * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
>>> + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include <linux/device.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/stmmac.h>
>>> +
>>> +#include "stmmac_platform.h"
>>> +
>>> +/* System Control regmap offsets */
>>> +#define OXNAS_DWMAC_CTRL_REGOFFSET 0x78
>>> +#define OXNAS_DWMAC_DELAY_REGOFFSET 0x100
>>> +
>>> +/* Control Register */
>>> +#define DWMAC_CKEN_RX_IN 14
>>> +#define DWMAC_CKEN_RXN_OUT 13
>>> +#define DWMAC_CKEN_RX_OUT 12
>>> +#define DWMAC_CKEN_TX_IN 10
>>> +#define DWMAC_CKEN_TXN_OUT 9
>>> +#define DWMAC_CKEN_TX_OUT 8
>>> +#define DWMAC_RX_SOURCE 7
>>> +#define DWMAC_TX_SOURCE 6
>>> +#define DWMAC_LOW_TX_SOURCE 4
>>> +#define DWMAC_AUTO_TX_SOURCE 3
>>> +#define DWMAC_RGMII 2
>>> +#define DWMAC_SIMPLE_MUX 1
>>> +#define DWMAC_CKEN_GTX 0
>>> +
>>> +/* Delay register */
>>> +#define DWMAC_TX_VARDELAY_SHIFT 0
>>> +#define DWMAC_TXN_VARDELAY_SHIFT 8
>>> +#define DWMAC_RX_VARDELAY_SHIFT 16
>>> +#define DWMAC_RXN_VARDELAY_SHIFT 24
>>> +#define DWMAC_TX_VARDELAY(d) ((d) << DWMAC_TX_VARDELAY_SHIFT)
>>> +#define DWMAC_TXN_VARDELAY(d) ((d) << DWMAC_TXN_VARDELAY_SHIFT)
>>> +#define DWMAC_RX_VARDELAY(d) ((d) << DWMAC_RX_VARDELAY_SHIFT)
>>> +#define DWMAC_RXN_VARDELAY(d) ((d) << DWMAC_RXN_VARDELAY_SHIFT)
>>> +
>>> +struct oxnas_dwmac {
>>> + struct device *dev;
>>> + struct clk *clk;
>>> + struct regmap *regmap;
>>> +};
>>> +
>>> +static int oxnas_dwmac_init(struct oxnas_dwmac *dwmac)
>>> +{
>>> + unsigned int value;
>>> + int ret;
>>> +
>>> + /* Reset HW here before changing the glue configuration */
>>> + ret = device_reset(dwmac->dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + clk_prepare_enable(dwmac->clk);
>>
>> You might want to check the return value from clk_prepare_enable() as well.
>>
>>> +
>>> + ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
>>> + value |= BIT(DWMAC_CKEN_GTX);
>>> + /* Use simple mux for 25/125 Mhz clock switching */
>>> + value |= BIT(DWMAC_SIMPLE_MUX);
>>> + /* set auto switch tx clock source */
>>> + value |= BIT(DWMAC_AUTO_TX_SOURCE);
>>> + /* enable tx & rx vardelay */
>>> + value |= BIT(DWMAC_CKEN_TX_OUT);
>>> + value |= BIT(DWMAC_CKEN_TXN_OUT);
>>> + value |= BIT(DWMAC_CKEN_TX_IN);
>>> + value |= BIT(DWMAC_CKEN_RX_OUT);
>>> + value |= BIT(DWMAC_CKEN_RXN_OUT);
>>> + value |= BIT(DWMAC_CKEN_RX_IN);
>>> + regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value);
>>> +
>>> + /* set tx & rx vardelay */
>>> + value = DWMAC_TX_VARDELAY(4);
>>> + value |= DWMAC_TXN_VARDELAY(2);
>>> + value |= DWMAC_RX_VARDELAY(10);
>>> + value |= DWMAC_RXN_VARDELAY(8);
>>> + regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value);
>
>
> there is no if condition so, I can suggest you, to hardwire
> value with macros instead of computing at runtime:
>
> e.g.
>
> var = DWMAC_VARDELAY where
> #define DWMAC_VARDELAY (DWMAC_TX_VARDELAY(4) | ...)
>
> ... same for OXNAS_DWMAC_CTRL_REGOFFSET where
> BIT(DWMAC_CKEN_ ... ) should be re-organized as macros,
> I mean:
> #define DWMAC_CKEN_.. BIT(xxx)
I will think about something similar for v2,
Thanks,
Neil
[...]
^ permalink raw reply
* RE: [RFC 1/5] media: i2c: max2175: Add MAX2175 support
From: Ramesh Shanmugasundaram @ 2016-10-21 14:49 UTC (permalink / raw)
To: Laurent Pinchart
Cc: robh+dt@kernel.org, mark.rutland@arm.com, mchehab@kernel.org,
hverkuil@xs4all.nl, sakari.ailus@linux.intel.com, crope@iki.fi,
Chris Paterson, geert@linux-m68k.org, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
In-Reply-To: <2034831.3otZHvJ6bZ@avalon>
Hi Laurent,
Thank you for the review comments.
> On Wednesday 12 Oct 2016 15:10:25 Ramesh Shanmugasundaram wrote:
> > This patch adds driver support for MAX2175 chip. This is Maxim
> > Integrated's RF to Bits tuner front end chip designed for
> > software-defined radio solutions. This driver exposes the tuner as a
> > sub-device instance with standard and custom controls to configure the
> device.
> >
> > Signed-off-by: Ramesh Shanmugasundaram
> > <ramesh.shanmugasundaram@bp.renesas.com> ---
> > .../devicetree/bindings/media/i2c/max2175.txt | 60 +
> > drivers/media/i2c/Kconfig | 4 +
> > drivers/media/i2c/Makefile | 2 +
> > drivers/media/i2c/max2175/Kconfig | 8 +
> > drivers/media/i2c/max2175/Makefile | 4 +
> > drivers/media/i2c/max2175/max2175.c | 1624
> +++++++++++++++++
> > drivers/media/i2c/max2175/max2175.h | 124 ++
> > 7 files changed, 1826 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/i2c/max2175.txt
> > create mode 100644 drivers/media/i2c/max2175/Kconfig create mode
> > 100644 drivers/media/i2c/max2175/Makefile
> > create mode 100644 drivers/media/i2c/max2175/max2175.c
> > create mode 100644 drivers/media/i2c/max2175/max2175.h
> >
> > diff --git a/Documentation/devicetree/bindings/media/i2c/max2175.txt
> > b/Documentation/devicetree/bindings/media/i2c/max2175.txt new file
> > mode
> > 100644
> > index 0000000..2250d5f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/i2c/max2175.txt
> > @@ -0,0 +1,60 @@
> > +Maxim Integrated MAX2175 RF to Bits tuner
> > +-----------------------------------------
> > +
> > +The MAX2175 IC is an advanced analog/digital hybrid-radio receiver
> > +with RF to Bits(r) front-end designed for software-defined radio
> solutions.
> > +
> > +Required properties:
> > +--------------------
> > +- compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
> > +- clocks: phandle to the fixed xtal clock.
> > +- clock-names: name of the fixed xtal clock.
> > +- port: video interface child port node of a tuner that defines the
> > +local
>
> As Rob pointed out in his review of patch 3/5, this isn't video.
Agreed & corrected.
>
> > + and remote endpoints. The remote endpoint is assumed to be an SDR
> > + device that is capable of receiving the digital samples from the
> tuner.
> > +
> > +Optional properties:
> > +--------------------
> > +- maxim,slave : empty property indicates this is a slave of
> another
> > + master tuner. This is used to define two tuners in
> > + diversity mode (1 master, 1 slave). By default each
> > + tuner is an individual master.
>
> Would it be useful to make that property a phandle to the master tuner, to
> give drivers a way to access the master ? I haven't checked whether there
> could be use cases for that.
As of now, I cannot find any use case for it from the datasheet. In future, we could add if such need arise.
>
> > +- maxim,refout-load: load capacitance value (in pF) on reference output
> > + drive level. The mapping of these load values to
> > + respective bit values are given below.
> > + 0 - Reference output disabled
> > + 1 - 10pF load
> > + 2 - 20pF load
> > + 3 - 30pF load
> > + 4 - 40pF load
> > + 5 - 60pF load
> > + 6 - 70pF load
>
> As Geert pointed out, you can simply specify the value in pF.
Agreed & corrected.
>
> > +
> > +Example:
> > +--------
> > +
> > +Board specific DTS file
> > +
> > +/* Fixed XTAL clock node */
> > +maxim_xtal: maximextal {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <36864000>;
> > +};
> > +
> > +/* A tuner device instance under i2c bus */
> > +max2175_0: tuner@60 {
> > + #clock-cells = <0>;
>
> Is the tuner a clock provider ? If it isn't you don't need this property.
Thanks. It's a copy/paste mistake :-(. Corrected.
>
> > + compatible = "maxim,max2175";
> > + reg = <0x60>;
> > + clocks = <&maxim_xtal>;
> > + clock-names = "xtal";
> > + maxim,refout-load = <10>;
> > +
> > + port {
> > + max2175_0_ep: endpoint {
> > + remote-endpoint = <&slave_rx_v4l2_sdr_device>;
> > + };
> > + };
> > +
> > +};
>
> [snip]
>
> > diff --git a/drivers/media/i2c/max2175/Makefile
> > b/drivers/media/i2c/max2175/Makefile new file mode 100644 index
> > 0000000..9bb46ac
> > --- /dev/null
> > +++ b/drivers/media/i2c/max2175/Makefile
> > @@ -0,0 +1,4 @@
> > +#
> > +# Makefile for Maxim RF to Bits tuner device #
> > +obj-$(CONFIG_SDR_MAX2175) += max2175.o
>
> If there's a single source file you might want to move it to
> drivers/media/i2c/.
MAX2175 is huge with lot more modes and functionality. When more modes are added (it's pre-set hex values), we may have to introduce the new file containing that the hex values alone. Hence, I thought of a folder. However, I cannot tell when the next set of modes will be added. So I'll remove the folder in the next patch.
>
> > diff --git a/drivers/media/i2c/max2175/max2175.c
> > b/drivers/media/i2c/max2175/max2175.c new file mode 100644 index
> > 0000000..71b60c2
> > --- /dev/null
> > +++ b/drivers/media/i2c/max2175/max2175.c
> > @@ -0,0 +1,1624 @@
> > +/*
> > + * Maxim Integrated MAX2175 RF to Bits tuner driver
> > + *
> > + * This driver & most of the hard coded values are based on the
> > +reference
> > + * application delivered by Maxim for this chip.
> > + *
> > + * Copyright (C) 2016 Maxim Integrated Products
> > + * Copyright (C) 2016 Renesas Electronics Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/errno.h>
> > +#include <linux/i2c.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/slab.h>
> > +#include <linux/delay.h>
>
> You can move delay.h right below clk.h and everything will be in
> alphabetical order :-)
Agreed.
>
> > +#include <media/v4l2-ctrls.h>
> > +#include <media/v4l2-device.h>
> > +#include <media/v4l2-of.h>
> > +
> > +#include "max2175.h"
> > +
> > +#define DRIVER_NAME "max2175"
> > +
> > +static unsigned int max2175_debug;
> > +module_param(max2175_debug, uint, 0644);
> > +MODULE_PARM_DESC(max2175_debug, "activate debug info");
>
> You can name the parameter "debug".
Agreed
>
> > +#define mxm_dbg(ctx, fmt, arg...) \
> > + v4l2_dbg(1, max2175_debug, &ctx->sd, fmt, ## arg)
>
> [snip]
>
> > +/* Preset values:
> > + * Based on Maxim MAX2175 Register Table revision: 130p10 */
>
> The preferred multi-line comment style is
>
> /*
> * foo
> * bar
> */
>
Agreed. I used it because checkpatch moaned but then I see Linus's comment :-).
> [snip]
>
> > +struct max2175_ctx {
>
> Nitpicking, such a structure would usually be named max2175 or
> max2175_device.
> Context seems to imply that you can have multiple of them per device.
Thanks for the explanation. I have changed it to max2175.
>
> > + struct v4l2_subdev sd;
> > + struct i2c_client *client;
> > + struct device *dev;
> > +
> > + /* Cached configuration */
> > + u8 regs[256];
>
> If you want to cache register values you should use regmap.
Thanks. I did not know about regmap. I'll try this.
>
> > + enum max2175_modetag mode; /* Receive mode tag */
> > + u32 freq; /* In Hz */
> > + struct max2175_rxmode *rx_modes;
> > +
> > + /* Device settings */
> > + bool master;
> > + u32 decim_ratio;
> > + u64 xtal_freq;
> > +
> > + /* ROM values */
> > + u8 rom_bbf_bw_am;
> > + u8 rom_bbf_bw_fm;
> > + u8 rom_bbf_bw_dab;
> > +
> > + /* Local copy of old settings */
> > + u8 i2s_test;
> > +
> > + u8 nbd_gain;
> > + u8 nbd_threshold;
> > + u8 wbd_gain;
> > + u8 wbd_threshold;
> > + u8 bbd_threshold;
> > + u8 bbdclip_threshold;
> > + u8 lt_wbd_threshold;
> > + u8 lt_wbd_gain;
> > +
> > + /* Controls */
> > + struct v4l2_ctrl_handler ctrl_hdl;
> > + struct v4l2_ctrl *lna_gain; /* LNA gain value */
> > + struct v4l2_ctrl *if_gain; /* I/F gain value */
> > + struct v4l2_ctrl *pll_lock; /* PLL lock */
> > + struct v4l2_ctrl *i2s_en; /* I2S output enable */
> > + struct v4l2_ctrl *i2s_mode; /* I2S mode value */
> > + struct v4l2_ctrl *am_hiz; /* AM High impledance input */
> > + struct v4l2_ctrl *hsls; /* High-side/Low-side polarity */
> > + struct v4l2_ctrl *rx_mode; /* Receive mode */
> > +
> > + /* Driver private variables */
> > + bool mode_resolved; /* Flag to sanity check settings */
> > +};
>
> [snip]
>
> > +/* Local store bitops helpers */
> > +static u8 max2175_get_bits(struct max2175_ctx *ctx, u8 idx, u8 msb,
> > +u8 lsb) {
> > + if (max2175_debug >= 2)
> > + mxm_dbg(ctx, "get_bits: idx:%u msb:%u lsb:%u\n",
> > + idx, msb, lsb);
>
> Do we really need such detailed debugging ?
Unfortunately yes. I'll try to remove this after some more testing or may be later as a separate patch.
I have converted a Windows GUI app code to this driver. Most of the register details & configuration sequence are not available in the datasheet. I used similar pattern of log message as in GUI logs because it helps in testing :-(
>
> > + return __max2175_get_bits(ctx->regs[idx], msb, lsb); }
> > +
> > +static bool max2175_get_bit(struct max2175_ctx *ctx, u8 idx, u8 bit)
> > +{
> > + return !!max2175_get_bits(ctx, idx, bit, bit); }
> > +
> > +static void max2175_set_bits(struct max2175_ctx *ctx, u8 idx,
> > + u8 msb, u8 lsb, u8 newval)
> > +{
> > + if (max2175_debug >= 2)
> > + mxm_dbg(ctx, "set_bits: idx:%u msb:%u lsb:%u newval:%u\n",
> > + idx, msb, lsb, newval);
> > + ctx->regs[idx] = __max2175_set_bits(ctx->regs[idx], msb, lsb,
> > + newval);
> > +}
> > +
> > +static void max2175_set_bit(struct max2175_ctx *ctx, u8 idx, u8 bit,
> > +u8
> > newval)
> > +{
> > + max2175_set_bits(ctx, idx, bit, bit, newval); }
> > +
> > +/* Device register bitops helpers */
> > +static u8 max2175_read_bits(struct max2175_ctx *ctx, u8 idx, u8 msb,
> > +u8
> > lsb)
> > +{
> > + return __max2175_get_bits(max2175_reg_read(ctx, idx), msb, lsb); }
> > +
> > +static void max2175_write_bits(struct max2175_ctx *ctx, u8 idx, u8 msb,
> > + u8 lsb, u8 newval)
> > +{
> > + /* Update local copy & write to device */
> > + max2175_set_bits(ctx, idx, msb, lsb, newval);
> > + max2175_reg_write(ctx, idx, ctx->regs[idx]); }
> > +
> > +static void max2175_write_bit(struct max2175_ctx *ctx, u8 idx, u8 bit,
> > + u8 newval)
> > +{
> > + if (max2175_debug >= 2)
> > + mxm_dbg(ctx, "idx %u, bit %u, newval %u\n", idx, bit, newval);
> > + max2175_write_bits(ctx, idx, bit, bit, newval); }
>
> Really, please use regmap :-)
Agreed.
>
> > +static int max2175_poll_timeout(struct max2175_ctx *ctx, u8 idx, u8
> > +msb, u8
> > lsb,
> > + u8 exp_val, u32 timeout)
> > +{
> > + unsigned long end = jiffies + msecs_to_jiffies(timeout);
> > + int ret;
> > +
> > + do {
> > + ret = max2175_read_bits(ctx, idx, msb, lsb);
> > + if (ret < 0)
> > + return ret;
> > + if (ret == exp_val)
> > + return 0;
> > +
> > + usleep_range(1000, 1500);
> > + } while (time_is_after_jiffies(end));
> > +
> > + return -EBUSY;
> > +}
> > +
> > +static int max2175_poll_csm_ready(struct max2175_ctx *ctx) {
> > + return max2175_poll_timeout(ctx, 69, 1, 1, 0, 50);
>
> Please define macros for register addresses and values, this is just
> unreadable.
The Tuner provider is unwilling to disclose all register details. I agree on the readability issue with this restriction but this is somewhat true for some sensitive IPs in the media subsystem.
>
> > +}
>
> [snip]
>
> > +
> > +#define MAX2175_IS_BAND_AM(ctx) \
> > + (max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_AM)
> > +
> > +#define MAX2175_IS_FM_MODE(ctx) \
> > + (max2175_get_bits(ctx, 12, 5, 4) == 0)
> > +
> > +#define MAX2175_IS_FMHD_MODE(ctx) \
> > + (max2175_get_bits(ctx, 12, 5, 4) == 1)
> > +
> > +#define MAX2175_IS_DAB_MODE(ctx) \
> > + (max2175_get_bits(ctx, 12, 5, 4) == 2)
> > +
> > +static int max2175_band_from_freq(u64 freq) {
> > + if (freq >= 144000 && freq <= 26100000)
> > + return MAX2175_BAND_AM;
> > + else if (freq >= 65000000 && freq <= 108000000)
> > + return MAX2175_BAND_FM;
> > + else if (freq >= 160000000 && freq <= 240000000)
> > + return MAX2175_BAND_VHF;
> > +
> > + /* Add other bands on need basis */
> > + return -ENOTSUPP;
> > +}
> > +
> > +static int max2175_update_i2s_mode(struct max2175_ctx *ctx, u32
> > +i2s_mode) {
> > + /* Only change if it's new */
> > + if (max2175_read_bits(ctx, 29, 2, 0) == i2s_mode)
> > + return 0;
> > +
> > + max2175_write_bits(ctx, 29, 2, 0, i2s_mode);
> > +
> > + /* Based on I2S mode value I2S_WORD_CNT values change */
> > + if (i2s_mode == MAX2175_I2S_MODE3) {
> > + max2175_write_bits(ctx, 30, 6, 0, 1);
> > + } else if (i2s_mode == MAX2175_I2S_MODE2 ||
> > + i2s_mode == MAX2175_I2S_MODE4) {
> > + max2175_write_bits(ctx, 30, 6, 0, 0);
> > + } else if (i2s_mode == MAX2175_I2S_MODE0) {
> > + max2175_write_bits(ctx, 30, 6, 0,
> > + ctx->rx_modes[ctx->mode].i2s_word_size);
> > + } else {
> > + v4l2_err(ctx->client,
> > + "failed: i2s_mode %u unsupported\n", i2s_mode);
>
> This should never happen as the control framework will validate control
> values.
Agreed.
>
> > + return 1;
>
> Error codes should be negative.
Agreed.
>
> > + }
> > + mxm_dbg(ctx, "updated i2s_mode %u\n", i2s_mode);
> > + return 0;
> > +}
>
> [snip]
>
> > +static void max2175_load_dab_1p2(struct max2175_ctx *ctx) {
> > + u32 i;
>
> unsigned int will do, no need for an explicitly sized type.
Agreed.
>
> > +
> > + /* Master is already set on init */
> > + for (i = 0; i < ARRAY_SIZE(dab12_map); i++)
> > + max2175_reg_write(ctx, dab12_map[i].idx, dab12_map[i].val);
> > +
> > + /* The default settings assume master */
> > + if (!ctx->master)
> > + max2175_write_bit(ctx, 30, 7, 1);
> > +
> > + /* Cache i2s_test value at this point */
> > + ctx->i2s_test = max2175_get_bits(ctx, 104, 3, 0);
> > + ctx->decim_ratio = 1;
> > +
> > + /* Load the Channel Filter Coefficients into channel filter bank #2
> */
> > + max2175_set_filter_coeffs(ctx, MAX2175_CH_MSEL, 2, ch_coeff_dab1); }
>
> [snip]
>
> > +static bool max2175_set_csm_mode(struct max2175_ctx *ctx,
> > + enum max2175_csm_mode new_mode)
> > +{
> > + int ret = max2175_poll_csm_ready(ctx);
> > +
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm not ready: new mode %d\n",
> new_mode);
> > + return ret;
> > + }
> > +
> > + mxm_dbg(ctx, "set csm mode: new mode %d\n", new_mode);
> > +
> > + max2175_write_bits(ctx, 0, 2, 0, new_mode);
> > +
> > + /* Wait for a fixed settle down time depending on new mode and band
> */
> > + switch (new_mode) {
> > + case MAX2175_CSM_MODE_JUMP_FAST_TUNE:
> > + if (MAX2175_IS_BAND_AM(ctx)) {
> > + usleep_range(1250, 1500); /* 1.25ms */
> > + } else {
> > + if (MAX2175_IS_DAB_MODE(ctx))
> > + usleep_range(3000, 3500); /* 3ms */
> > + else
> > + usleep_range(1250, 1500); /* 1.25ms */
> > + }
>
> You can write this as
>
> if (MAX2175_IS_BAND_AM(ctx))
> usleep_range(1250, 1500); /* 1.25ms */
> else if (MAX2175_IS_DAB_MODE(ctx))
> usleep_range(3000, 3500); /* 3ms */
> else
> usleep_range(1250, 1500); /* 1.25ms */
Agreed.
>
>
> > + break;
> > +
> > + /* Other mode switches can be added in the future if needed */
> > + default:
> > + break;
> > + }
> > +
> > + ret = max2175_poll_csm_ready(ctx);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm did not settle: new mode %d\n",
> > + new_mode);
> > + return ret;
> > + }
> > + return ret;
> > +}
>
> [snip]
>
> > +
> > +static int max2175_csm_action(struct max2175_ctx *ctx,
> > + enum max2175_csm_mode action) {
> > + int ret;
> > + int load_buffer = MAX2175_CSM_MODE_LOAD_TO_BUFFER;
> > +
> > + mxm_dbg(ctx, "csm action: %d\n", action);
> > +
> > + /* Perform one or two CSM mode commands. */
> > + switch (action) {
> > + case MAX2175_CSM_MODE_NO_ACTION:
> > + /* Take no FSM Action. */
> > + return 0;
> > + case MAX2175_CSM_MODE_LOAD_TO_BUFFER:
> > + case MAX2175_CSM_MODE_PRESET_TUNE:
> > + case MAX2175_CSM_MODE_SEARCH:
> > + case MAX2175_CSM_MODE_AF_UPDATE:
> > + case MAX2175_CSM_MODE_JUMP_FAST_TUNE:
> > + case MAX2175_CSM_MODE_CHECK:
> > + case MAX2175_CSM_MODE_LOAD_AND_SWAP:
> > + case MAX2175_CSM_MODE_END:
> > + ret = max2175_set_csm_mode(ctx, action);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_PRESET_TUNE:
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
> > + ret = max2175_set_csm_mode(ctx, MAX2175_CSM_MODE_PRESET_TUNE);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_SEARCH:
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
>
> Don't duplicate the error messages, move them after the switch statement.
Agreed. The error messages are not needed as the csm_mode function logs the mode argument in error log. Cleaned up.
>
> > + ret = max2175_set_csm_mode(ctx, MAX2175_CSM_MODE_SEARCH);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_AF_UPDATE:
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
> > + ret = max2175_set_csm_mode(ctx, MAX2175_CSM_MODE_AF_UPDATE);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_JUMP_FAST_TUNE:
>
> This function is only called with action set to
> MAX2175_CSM_MODE_BUFFER_PLUS_JUMP_FAST_TUNE. I'd remove the rest of the
> code for now, unless you have a plan to use it soon.
I'll remove. As mentioned earlier, I cannot tell how soon the other modes will be added. There are few other places with placeholders for other modes. I'll try to clean.
>
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
> > + ret = max2175_set_csm_mode(ctx,
> > + MAX2175_CSM_MODE_JUMP_FAST_TUNE);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_CHECK:
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
> > + ret = max2175_set_csm_mode(ctx, MAX2175_CSM_MODE_CHECK);
> > + break;
> > + case MAX2175_CSM_MODE_BUFFER_PLUS_LOAD_AND_SWAP:
> > + ret = max2175_set_csm_mode(ctx, load_buffer);
> > + if (ret) {
> > + v4l2_err(ctx->client, "csm action %d load buf
> failed\n",
> > + action);
> > + break;
> > + }
> > + ret = max2175_set_csm_mode(ctx,
> MAX2175_CSM_MODE_LOAD_AND_SWAP);
> > + break;
> > + default:
> > + ret = max2175_set_csm_mode(ctx, MAX2175_CSM_MODE_NO_ACTION);
> > + break;
> > + }
> > + return ret;
> > +}
> > +
> > +static int max2175_set_lo_freq(struct max2175_ctx *ctx, u64 lo_freq)
> > +{
> > + int ret;
> > + u32 lo_mult;
> > + u64 scaled_lo_freq;
> > + const u64 scale_factor = 1000000ULL;
> > + u64 scaled_npf, scaled_integer, scaled_fraction;
> > + u32 frac_desired, int_desired;
> > + u8 loband_bits, vcodiv_bits;
>
> Do you really support frequencies above 4GHz ?
Nope.
If not most of the 64-bit
> values could be stored in 32 bits.
The 64bit variables are needed to extract the fractional part (upto 6 digit precision) out of floating point divisions (original user space code).
>
> > +
> > + scaled_lo_freq = lo_freq;
> > + /* Scale to larger number for precision */
> > + scaled_lo_freq = scaled_lo_freq * scale_factor * 100;
> > +
> > + mxm_dbg(ctx, "scaled lo_freq %llu lo_freq %llu\n",
> > + scaled_lo_freq, lo_freq);
> > +
> > + if (MAX2175_IS_BAND_AM(ctx)) {
> > + if (max2175_get_bit(ctx, 5, 7) == 0)
> > + loband_bits = 0;
> > + vcodiv_bits = 0;
> > + lo_mult = 16;
> > + } else if (max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_FM) {
> > + if (lo_freq <= 74700000) {
> > + loband_bits = 0;
> > + vcodiv_bits = 0;
> > + lo_mult = 16;
> > + } else if ((lo_freq > 74700000) && (lo_freq <= 110000000)) {
>
> No need for the inner parentheses.
Agreed.
>
> > + loband_bits = 1;
> > + vcodiv_bits = 0;
> > + } else {
> > + loband_bits = 1;
> > + vcodiv_bits = 3;
> > + }
> > + lo_mult = 8;
> > + } else if (max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_VHF) {
> > + if (lo_freq <= 210000000) {
> > + loband_bits = 2;
> > + vcodiv_bits = 2;
> > + } else {
> > + loband_bits = 2;
> > + vcodiv_bits = 1;
> > + }
> > + lo_mult = 4;
> > + } else {
> > + loband_bits = 3;
> > + vcodiv_bits = 2;
> > + lo_mult = 2;
> > + }
> > +
> > + if (max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_L)
> > + scaled_npf = (scaled_lo_freq / ctx->xtal_freq / lo_mult) /
> 100;
> > + else
> > + scaled_npf = (scaled_lo_freq / ctx->xtal_freq * lo_mult) /
> 100;
> > +
> > + scaled_integer = scaled_npf / scale_factor * scale_factor;
> > + int_desired = (u32)(scaled_npf / scale_factor);
> > + scaled_fraction = scaled_npf - scaled_integer;
> > + frac_desired = (u32)(scaled_fraction * 1048576 / scale_factor);
> > +
> > + /* Check CSM is not busy */
> > + ret = max2175_poll_csm_ready(ctx);
> > + if (ret) {
> > + v4l2_err(ctx->client, "lo_freq: csm busy. freq %llu\n",
> > + lo_freq);
> > + return ret;
> > + }
> > +
> > + mxm_dbg(ctx, "loband %u vcodiv %u lo_mult %u scaled_npf %llu\n",
> > + loband_bits, vcodiv_bits, lo_mult, scaled_npf);
> > + mxm_dbg(ctx, "scaled int %llu frac %llu desired int %u frac %u\n",
> > + scaled_integer, scaled_fraction, int_desired, frac_desired);
> > +
> > + /* Write the calculated values to the appropriate registers */
> > + max2175_set_bits(ctx, 5, 3, 2, loband_bits);
> > + max2175_set_bits(ctx, 6, 7, 6, vcodiv_bits);
> > + max2175_set_bits(ctx, 1, 7, 0, (u8)(int_desired & 0xff));
> > + max2175_set_bits(ctx, 2, 3, 0, (u8)((frac_desired >> 16) & 0x1f));
> > + max2175_set_bits(ctx, 3, 7, 0, (u8)((frac_desired >> 8) & 0xff));
> > + max2175_set_bits(ctx, 4, 7, 0, (u8)(frac_desired & 0xff));
> > + /* Flush the above registers to device */
> > + max2175_flush_regstore(ctx, 1, 6);
> > + return ret;
> > +}
>
> [snip]
>
> > +static int max2175_set_rf_freq_non_am_bands(struct max2175_ctx *ctx,
> > +u64
> > freq,
> > + u32 lo_pos)
> > +{
> > + int ret;
> > + s64 adj_freq;
> > + u64 low_if_freq;
> > +
> > + mxm_dbg(ctx, "rf_freq: non AM bands\n");
> > +
> > + if (MAX2175_IS_FM_MODE(ctx))
> > + low_if_freq = 128000;
> > + else if (MAX2175_IS_FMHD_MODE(ctx))
> > + low_if_freq = 228000;
> > + else
> > + return max2175_set_lo_freq(ctx, freq);
> > +
> > + if (max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_VHF) {
>
> You perform this check in multiple places, you could create a helper
> function.
Agreed.
>
> > + if (lo_pos == MAX2175_LO_ABOVE_DESIRED)
> > + adj_freq = freq + low_if_freq;
> > + else
> > + adj_freq = freq - low_if_freq;
> > + } else {
> > + if (lo_pos == MAX2175_LO_ABOVE_DESIRED)
> > + adj_freq = freq - low_if_freq;
> > + else
> > + adj_freq = freq + low_if_freq;
> > + }
>
> This could be written
>
> if ((max2175_get_bits(ctx, 5, 1, 0) == MAX2175_BAND_VHF) ==
> (lo_pos == MAX2175_LO_ABOVE_DESIRED))
> adj_freq = freq + low_if_freq;
> else
> adj_freq = freq - low_if_freq;
>
> Same for the other similar constructs in the driver. Up to you.
Agreed. Nice :-)
>
> > +
> > + ret = max2175_set_lo_freq(ctx, adj_freq);
> > + if (ret)
> > + return ret;
> > +
> > + return max2175_set_nco_freq(ctx, low_if_freq); }
>
> [snip]
>
> > +#define max2175_ctx_from_sd(x) \
> > + container_of(x, struct max2175_ctx, sd)
> > +#define max2175_ctx_from_ctrl(x) \
> > + container_of(x, struct max2175_ctx, ctrl_hdl)
>
> I'd move it right after the structure definition, and turn them into
> static inline functions.
Agreed.
>
> > +static int max2175_s_ctrl(struct v4l2_ctrl *ctrl) {
> > + struct max2175_ctx *ctx = max2175_ctx_from_ctrl(ctrl->handler);
> > + int ret = 0;
> > +
> > + mxm_dbg(ctx, "s_ctrl: id 0x%x, val %u\n", ctrl->id, ctrl->val);
> > + switch (ctrl->id) {
> > + case V4L2_CID_MAX2175_I2S_EN:
> > + max2175_i2s_enable(ctx, ctrl->val == 1);
> > + break;
> > + case V4L2_CID_MAX2175_I2S_MODE:
> > + max2175_s_ctrl_i2s_mode(ctx, ctrl->val);
> > + break;
> > + case V4L2_CID_MAX2175_AM_HIZ:
> > + v4l2_ctrl_activate(ctx->am_hiz, false);
> > + break;
> > + case V4L2_CID_MAX2175_HSLS:
> > + v4l2_ctrl_activate(ctx->hsls, false);
> > + break;
> > + case V4L2_CID_MAX2175_RX_MODE:
> > + mxm_dbg(ctx, "rx mode %u\n", ctrl->val);
> > + max2175_s_ctrl_rx_mode(ctx, ctrl->val);
> > + break;
> > + default:
> > + v4l2_err(ctx->client, "s:invalid ctrl id 0x%x\n", ctrl->id);
> > + ret = -EINVAL;
>
> This should never happen. The driver has too many error and debug messages
> overall.
Agreed :-). Will clean up.
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int max2175_get_lna_gain(struct max2175_ctx *ctx) {
> > + int gain = 0;
> > + enum max2175_band band = max2175_get_bits(ctx, 5, 1, 0);
> > +
> > + switch (band) {
> > + case MAX2175_BAND_AM:
> > + gain = max2175_read_bits(ctx, 51, 3, 1);
> > + break;
> > + case MAX2175_BAND_FM:
> > + gain = max2175_read_bits(ctx, 50, 3, 1);
> > + break;
> > + case MAX2175_BAND_VHF:
> > + gain = max2175_read_bits(ctx, 52, 3, 0);
> > + break;
> > + default:
> > + v4l2_err(ctx->client, "invalid band %d to get rf gain\n",
> band);
>
> Can this happen ?
Yes, there is "L-band". It is a paranoia check as I am testing by comparing logs sometimes :-(
>
> > + break;
> > + }
> > + return gain;
> > +}
> > +
> > +static int max2175_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
> > +{
> > + struct max2175_ctx *ctx = max2175_ctx_from_ctrl(ctrl->handler);
> > +
> > + /* Only the dynamically changing values need to be in
> g_volatile_ctrl
> */
> > + mxm_dbg(ctx, "g_volatile_ctrl: id 0x%x\n", ctrl->id);
> > + switch (ctrl->id) {
> > + case V4L2_CID_RF_TUNER_LNA_GAIN:
> > + ctrl->val = max2175_get_lna_gain(ctx);
> > + break;
> > + case V4L2_CID_RF_TUNER_IF_GAIN:
> > + ctrl->val = max2175_read_bits(ctx, 49, 4, 0);
> > + break;
> > + case V4L2_CID_RF_TUNER_PLL_LOCK:
> > + ctrl->val = (max2175_read_bits(ctx, 60, 7, 6) == 3);
> > + break;
> > + default:
> > + v4l2_err(ctx->client, "g:invalid ctrl id 0x%x\n", ctrl->id);
>
> This should never happen either.
I agree.
>
> > + return -EINVAL;
> > + }
> > + mxm_dbg(ctx, "g_volatile_ctrl: id 0x%x val %d\n", ctrl->id, ctrl-
> >val);
> > + return 0;
> > +};
>
> [snip]
>
> > +static const struct v4l2_ctrl_config max2175_i2s_en = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_I2S_EN,
>
> V4L2_CID_MAX2175_I2S_ENABLE ?
Agreed.
>
> > + .name = "I2S Enable",
> > + .type = V4L2_CTRL_TYPE_BOOLEAN,
> > + .min = 0,
> > + .max = 1,
> > + .step = 1,
> > + .def = 1,
> > +};
> > +
> > +static const struct v4l2_ctrl_config max2175_i2s_mode = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_I2S_MODE,
> > + .name = "I2S_MODE value",
> > + .type = V4L2_CTRL_TYPE_INTEGER,
>
> Should this be a menu control ?
Hmm... the strings would be named "i2s mode x"? Will that be OK?
>
> > + .min = 0,
> > + .max = 4,
> > + .step = 1,
> > + .def = 0,
> > +};
> > +
> > +static const struct v4l2_ctrl_config max2175_am_hiz = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_AM_HIZ,
> > + .name = "AM High impedance input",
> > + .type = V4L2_CTRL_TYPE_BOOLEAN,
> > + .min = 0,
> > + .max = 1,
> > + .step = 1,
> > + .def = 0,
> > +};
> > +
> > +static const struct v4l2_ctrl_config max2175_hsls = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_HSLS,
> > + .name = "HSLS above/below desired",
> > + .type = V4L2_CTRL_TYPE_INTEGER,
> > + .min = 0,
> > + .max = 1,
> > + .step = 1,
> > + .def = 1,
> > +};
> > +
> > +
> > +/* NOTE: Any addition/deletion in the below list should be reflected in
> > + * max2175_modetag enum
> > + */
> > +static const char * const max2175_ctrl_eu_rx_mode_strings[] = {
> > + "DAB 1.2",
> > + "NULL",
>
> Do you really mean "NULL", not NULL ?
Sorry, That's cut/paste from vivid-ctrl. I have cleaned it up with designated initializers as Geert pointed out.
>
> > +};
> > +
> > +static const char * const max2175_ctrl_na_rx_mode_strings[] = {
> > + "NA FM 1.0",
> > + "NULL",
> > +};
> > +
> > +static const struct v4l2_ctrl_config max2175_eu_rx_mode = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_RX_MODE,
> > + .name = "RX MODE",
> > + .type = V4L2_CTRL_TYPE_MENU,
> > + .max = ARRAY_SIZE(max2175_ctrl_eu_rx_mode_strings) - 2,
>
> If there's a single mode supported I'd skip adding those controls for now.
I'll try to add one more mode support if time permits. The menu looks much readable with v4l2-ctl & comparing the same with datasheet.
>
> > + .def = 0,
> > + .qmenu = max2175_ctrl_eu_rx_mode_strings,
> > +};
> > +
> > +static const struct v4l2_ctrl_config max2175_na_rx_mode = {
> > + .ops = &max2175_ctrl_ops,
> > + .id = V4L2_CID_MAX2175_RX_MODE,
> > + .name = "RX MODE",
> > + .type = V4L2_CTRL_TYPE_MENU,
> > + .max = ARRAY_SIZE(max2175_ctrl_na_rx_mode_strings) - 2,
> > + .def = 0,
> > + .qmenu = max2175_ctrl_na_rx_mode_strings,
> > +};
> > +
> > +static u32 max2175_refout_load_to_bits(struct i2c_client *client, u32
> load)
> > +{
> > + u32 bits = 0; /* REFOUT disabled */
> > +
> > + if (load >= 0 && load <= 40)
> > + bits = load / 10;
> > + else if (load >= 60 && load <= 70)
> > + bits = load / 10 - 1;
> > + else
> > + dev_warn(&client->dev, "invalid refout_load %u\n", load);
>
> Your DT bindings specify 0 as a valid value.
Agreed. The DT values are changed to 10-70 range.
>
> An invalid value specified in DT should be a fatal error.
OK. Will correct this.
>
> > +
> > + return bits;
> > +}
> > +
> > +static int max2175_probe(struct i2c_client *client,
> > + const struct i2c_device_id *id)
> > +{
> > + struct max2175_ctx *ctx;
> > + struct device *dev = &client->dev;
> > + struct v4l2_subdev *sd;
> > + struct v4l2_ctrl_handler *hdl;
> > + struct clk *clk;
> > + bool master = true;
> > + u32 refout_load, refout_bits = 0; /* REFOUT disabled */
> > + int ret;
> > +
> > + /* Check if the adapter supports the needed features */
> > + if (!i2c_check_functionality(client->adapter,
> > + I2C_FUNC_SMBUS_BYTE_DATA)) {
> > + dev_err(&client->dev, "i2c check failed\n");
> > + return -EIO;
> > + }
> > +
> > + if (of_find_property(client->dev.of_node, "maxim,slave", NULL))
> > + master = false;
> > +
> > + if (!of_property_read_u32(client->dev.of_node, "maxim,refout-load",
> > + &refout_load))
> > + refout_bits = max2175_refout_load_to_bits(client,
> refout_load);
> > +
> > + clk = devm_clk_get(&client->dev, "xtal");
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
> > + dev_err(&client->dev, "cannot get xtal clock %d\n", ret);
> > + return -ENODEV;
> > + }
> > +
> > + ctx = kzalloc(sizeof(struct max2175_ctx),
>
> sizeof(*ctx)
>
> > + GFP_KERNEL);
>
> This fits on one line.
Yes, corrected in last cleanup.
>
> > + if (ctx == NULL)
> > + return -ENOMEM;
> > +
> > + sd = &ctx->sd;
> > + ctx->master = master;
> > + ctx->mode_resolved = false;
> > +
> > + /* Set the defaults */
> > + ctx->freq = bands_rf.rangelow;
> > +
> > + ctx->xtal_freq = clk_get_rate(clk);
> > + dev_info(&client->dev, "xtal freq %lluHz\n", ctx->xtal_freq);
> > +
> > + v4l2_i2c_subdev_init(sd, client, &max2175_ops);
> > + ctx->client = client;
> > +
> > + sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
> > + ctx->dev = dev;
> > +
> > + /* Controls */
> > + hdl = &ctx->ctrl_hdl;
> > + ret = v4l2_ctrl_handler_init(hdl, 8);
> > + if (ret) {
> > + dev_err(&client->dev, "ctrl handler init failed\n");
> > + goto err;
> > + }
> > +
> > + ctx->lna_gain = v4l2_ctrl_new_std(hdl, &max2175_ctrl_ops,
> > + V4L2_CID_RF_TUNER_LNA_GAIN,
> > + 0, 15, 1, 2);
> > + ctx->lna_gain->flags |= (V4L2_CTRL_FLAG_VOLATILE |
> > + V4L2_CTRL_FLAG_READ_ONLY);
> > + ctx->if_gain = v4l2_ctrl_new_std(hdl, &max2175_ctrl_ops,
> > + V4L2_CID_RF_TUNER_IF_GAIN,
> > + 0, 31, 1, 0);
> > + ctx->if_gain->flags |= (V4L2_CTRL_FLAG_VOLATILE |
> > + V4L2_CTRL_FLAG_READ_ONLY);
> > + ctx->pll_lock = v4l2_ctrl_new_std(hdl, &max2175_ctrl_ops,
> > + V4L2_CID_RF_TUNER_PLL_LOCK,
> > + 0, 1, 1, 0);
> > + ctx->pll_lock->flags |= (V4L2_CTRL_FLAG_VOLATILE |
> > + V4L2_CTRL_FLAG_READ_ONLY);
> > + ctx->i2s_en = v4l2_ctrl_new_custom(hdl, &max2175_i2s_en, NULL);
> > + ctx->i2s_mode = v4l2_ctrl_new_custom(hdl, &max2175_i2s_mode, NULL);
> > + ctx->am_hiz = v4l2_ctrl_new_custom(hdl, &max2175_am_hiz, NULL);
> > + ctx->hsls = v4l2_ctrl_new_custom(hdl, &max2175_hsls, NULL);
> > +
> > + if (ctx->xtal_freq == MAX2175_EU_XTAL_FREQ) {
> > + ctx->rx_mode = v4l2_ctrl_new_custom(hdl,
> > + &max2175_eu_rx_mode,
> NULL);
> > + ctx->rx_modes = (struct max2175_rxmode *)eu_rx_modes;
> > + } else {
> > + ctx->rx_mode = v4l2_ctrl_new_custom(hdl,
> > + &max2175_na_rx_mode,
> NULL);
> > + ctx->rx_modes = (struct max2175_rxmode *)na_rx_modes;
> > + }
> > + ctx->sd.ctrl_handler = &ctx->ctrl_hdl;
> > +
> > + ret = v4l2_async_register_subdev(sd);
> > + if (ret) {
> > + dev_err(&client->dev, "register subdev failed\n");
> > + goto err_reg;
> > + }
> > + dev_info(&client->dev, "subdev registered\n");
> > +
> > + /* Initialize device */
> > + ret = max2175_core_init(ctx, refout_bits);
> > + if (ret)
> > + goto err_init;
> > +
> > + mxm_dbg(ctx, "probed\n");
> > + return 0;
> > +
> > +err_init:
> > + v4l2_async_unregister_subdev(sd);
> > +err_reg:
> > + v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
> > +err:
> > + kfree(ctx);
> > + return ret;
> > +}
> > +
> > +static int max2175_remove(struct i2c_client *client)
> > +{
> > + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> > + struct max2175_ctx *ctx = max2175_ctx_from_sd(sd);
> > +
> > + v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
> > + v4l2_async_unregister_subdev(sd);
> > + mxm_dbg(ctx, "removed\n");
> > + kfree(ctx);
> > + return 0;
> > +}
> > +
> > +static const struct i2c_device_id max2175_id[] = {
> > + { DRIVER_NAME, 0},
> > + {},
> > +};
> > +
>
> No need for a blank line here.
Agreed.
>
> > +MODULE_DEVICE_TABLE(i2c, max2175_id);
> > +
> > +static const struct of_device_id max2175_of_ids[] = {
> > + { .compatible = "maxim, max2175", },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, max2175_of_ids);
> > +
> > +static struct i2c_driver max2175_driver = {
> > + .driver = {
> > + .name = DRIVER_NAME,
> > + .of_match_table = max2175_of_ids,
> > + },
> > + .probe = max2175_probe,
> > + .remove = max2175_remove,
> > + .id_table = max2175_id,
> > +};
> > +
> > +module_i2c_driver(max2175_driver);
> > +
> > +MODULE_DESCRIPTION("Maxim MAX2175 RF to Bits tuner driver");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_AUTHOR("Ramesh Shanmugasundaram
> > <ramesh.shanmugasundaram@bp.renesas.com>"); diff --git
> > a/drivers/media/i2c/max2175/max2175.h
> b/drivers/media/i2c/max2175/max2175.h
> > new file mode 100644
> > index 0000000..61a508b
> > --- /dev/null
> > +++ b/drivers/media/i2c/max2175/max2175.h
> > @@ -0,0 +1,124 @@
> > +/*
> > + * Maxim Integrated MAX2175 RF to Bits tuner driver
> > + *
> > + * This driver & most of the hard coded values are based on the
> reference
> > + * application delivered by Maxim for this chip.
> > + *
> > + * Copyright (C) 2016 Maxim Integrated Products
> > + * Copyright (C) 2016 Renesas Electronics Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MAX2175_H__
> > +#define __MAX2175_H__
> > +
> > +#include <linux/types.h>
> > +
> > +enum max2175_region {
> > + MAX2175_REGION_EU = 0, /* Europe */
> > + MAX2175_REGION_NA, /* North America */
> > +};
> > +
> > +#define MAX2175_EU_XTAL_FREQ (36864000) /* In Hz */
> > +#define MAX2175_NA_XTAL_FREQ (40186125) /* In Hz */
> > +
> > +enum max2175_band {
> > + MAX2175_BAND_AM = 0,
> > + MAX2175_BAND_FM,
> > + MAX2175_BAND_VHF,
> > + MAX2175_BAND_L,
> > +};
> > +
> > +/* NOTE: Any addition/deletion in the below enum should be reflected in
> > + * V4L2_CID_MAX2175_RX_MODE ctrl strings
> > + */
> > +enum max2175_modetag {
> > + /* EU modes */
> > + MAX2175_DAB_1_2 = 0,
> > +
> > + /* Other possible modes to add in future
> > + * MAX2175_DAB_1_0,
> > + * MAX2175_DAB_1_3,
> > + * MAX2175_EU_FM_2_2,
> > + * MAX2175_EU_FM_1_0,
> > + * MAX2175_EU_FMHD_4_0,
> > + * MAX2175_EU_AM_1_0,
> > + * MAX2175_EU_AM_2_2,
> > + */
> > +
> > + /* NA modes */
> > + MAX2175_NA_FM_1_0 = 0,
> > +
> > + /* Other possible modes to add in future
> > + * MAX2175_NA_FM_1_2,
> > + * MAX2175_NA_FMHD_1_0,
> > + * MAX2175_NA_FMHD_1_2,
> > + * MAX2175_NA_AM_1_0,
> > + * MAX2175_NA_AM_1_2,
> > + */
> > +};
> > +
> > +/* Supported I2S modes */
> > +enum {
> > + MAX2175_I2S_MODE0 = 0,
> > + MAX2175_I2S_MODE1,
> > + MAX2175_I2S_MODE2,
> > + MAX2175_I2S_MODE3,
> > + MAX2175_I2S_MODE4,
> > +};
> > +
> > +/* Coefficient table groups */
> > +enum {
> > + MAX2175_CH_MSEL = 0,
> > + MAX2175_EQ_MSEL,
> > + MAX2175_AA_MSEL,
> > +};
> > +
> > +/* HSLS LO injection polarity */
> > +enum {
> > + MAX2175_LO_BELOW_DESIRED = 0,
> > + MAX2175_LO_ABOVE_DESIRED,
> > +};
> > +
> > +/* Channel FSM modes */
> > +enum max2175_csm_mode {
> > + MAX2175_CSM_MODE_LOAD_TO_BUFFER = 0,
> > + MAX2175_CSM_MODE_PRESET_TUNE,
> > + MAX2175_CSM_MODE_SEARCH,
> > + MAX2175_CSM_MODE_AF_UPDATE,
> > + MAX2175_CSM_MODE_JUMP_FAST_TUNE,
> > + MAX2175_CSM_MODE_CHECK,
> > + MAX2175_CSM_MODE_LOAD_AND_SWAP,
> > + MAX2175_CSM_MODE_END,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_PRESET_TUNE,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_SEARCH,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_AF_UPDATE,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_JUMP_FAST_TUNE,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_CHECK,
> > + MAX2175_CSM_MODE_BUFFER_PLUS_LOAD_AND_SWAP,
> > + MAX2175_CSM_MODE_NO_ACTION
> > +};
> > +
> > +/* Rx mode */
> > +struct max2175_rxmode {
> > + enum max2175_band band; /* Associated band */
> > + u32 freq; /* Default freq in Hz */
> > + u8 i2s_word_size; /* Bit value */
> > + u8 i2s_modes[4]; /* Supported modes */
> > +};
> > +
> > +/* Register map */
> > +struct max2175_regmap {
> > + u8 idx; /* Register index */
> > + u8 val; /* Register value */
> > +};
>
> As no other file than max2175.c includes this, I would move at least the
> structure definitions to the .c file.
Agreed.
Thanks a lot for all the comments and suggestions. I'll post the next version soon.
Thanks,
Ramesh
^ permalink raw reply
* [PATCH] gpio: mcp23s08: Add option to configure pullups.
From: Enric Balletbo i Serra @ 2016-10-21 15:00 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-gpio; +Cc: Linus Walleij, Rob Herring
Default is without pullups, but if property is specified in DT and the bit
is set, set a pullup on GPIO-n.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt | 1 +
drivers/gpio/gpio-mcp23s08.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
index c934106..40306b1 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
@@ -57,6 +57,7 @@ Optional device specific properties:
On devices with only one interrupt output this property is useless.
- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
configures the IRQ output polarity as active high.
+- microchip,pullups : If n-th bit is set, set a pullup on GPIO-n.
Example I2C (with interrupt):
gpiom1: gpio@20 {
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index 99d37b5..0cedf82 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -766,7 +766,8 @@ static int mcp230xx_probe(struct i2c_client *client,
if (match) {
pdata = &local_pdata;
pdata->base = -1;
- pdata->chip[0].pullups = 0;
+ of_property_read_u32(client->dev.of_node, "microchip,pullups",
+ &pdata->chip[0].pullups);
pdata->irq_controller = of_property_read_bool(
client->dev.of_node,
"interrupt-controller");
--
2.1.0
^ permalink raw reply related
* Re: [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Shawn Guo @ 2016-10-21 15:03 UTC (permalink / raw)
To: Stefan Wahren
Cc: Mark Rutland, Marek Vasut, Arnd Bergmann,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jörg Krause, Rob Herring,
Sascha Hauer, Fabio Estevam,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lothar Waßmann
In-Reply-To: <9bf7c925-bdc2-d0b8-9886-70d46383d1e0-eS4NqCHxEME@public.gmane.org>
On Fri, Oct 21, 2016 at 04:05:59PM +0200, Stefan Wahren wrote:
> Am 21.10.2016 um 15:53 schrieb Shawn Guo:
> > On Tue, Sep 13, 2016 at 05:51:02PM +0000, Stefan Wahren wrote:
> >> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
> >> for suspend to RAM and standby mode. But before we need to remove the fake reg
> >> properties of all internal bus nodes as discussed in this thread [1].
> >>
> >> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
> >> Remove skeleton.dtsi inclusion" [2].
> >>
> >> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
> > The page cannot be reached. I would like to understand the
> > background for this change.
>
> Strange, because i don't have any problems while clicking on the URL.
>
> It's an older discussion on the devicetree / kernel newbie mailing list
> with subject "strange dtc errors after adding sram node". Arnd suggested
> in the discussion to remove the reg property from the ahb node.
>
> Please try this one: http://www.spinics.net/lists/newbies/msg57652.html
If you go through 'Table 4-1. Address Map for i.MX28' of MCIMX28RM, you
should be able to find there are 3 AHB buses: ahb@0, ahb@80080000 and
ahb@c0000000. The ocram goes to ahb@0. The following change should be
the right one for ocram addition.
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 0ad893bf5f43..8e5718df06b2 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -47,6 +47,19 @@
};
};
+ ahb@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x80000000>;
+ ranges;
+
+ ocram: sram@0 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x20000>;
+ };
+ };
+
apb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
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* [PATCH v4 1/2] ARM: dts: imx6ul: Add DTS for liteSOM module
From: Marcin Niestroj @ 2016-10-21 15:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Marcin Niestroj
This is a SOM (System on Module), so it will be part of another boards.
Hence, this is a "dtsi" file that will be included from another device
tree files.
Hardware specification:
* Freescale i.MX6UL SoC
* up to 512 MB RAM
* eMMC on uSDHC2
Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
---
Changes v3 -> v4: none
Changes v2 -> v3:
* Remove cpu0 supplies (arm-supply, soc-supply), as they were already
set in imx6ul.dtsi file (reported by Sébastien Szymanski)
Changes v1 -> v2:
* Use dual license
arch/arm/boot/dts/imx6ul-litesom.dtsi | 82 +++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-litesom.dtsi
diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi
new file mode 100644
index 0000000..461292d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2016 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul.dtsi"
+
+/ {
+ model = "Grinn i.MX6UL liteSOM";
+ compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
+ >;
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ bus-width = <8>;
+ status = "okay";
+};
--
2.10.0
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* [PATCH v4 2/2] ARM: dts: imx6ul: Add DTS for liteBoard
From: Marcin Niestroj @ 2016-10-21 15:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Marcin Niestroj
In-Reply-To: <20161021150717.27573-1-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
liteBoard is a development board which uses liteSOM as its base.
Hardware specification:
* liteSOM (i.MX6UL, DRAM, eMMC)
* Ethernet PHY (id 0)
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
---
Changes v3 -> v4:
* Put usb otg regulator directly under root, use hyphens in node name
(suggested by Shawn)
* Rename node name: usb_otg1_vbus -> usb-otg1-vbus
Changes v2 -> v3: none
Changes v1 -> v2:
* Use dual license
* Fix typo "defaullt" -> "default"
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-liteboard.dts | 147 +++++++++++++++++++++++++++++++++
2 files changed, 148 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-liteboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..c1ce5f4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
+ imx6ul-liteboard.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts
new file mode 100644
index 0000000..6e04cb9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-liteboard.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2016 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6ul-litesom.dtsi"
+
+/ {
+ model = "Grinn i.MX6UL liteBoard";
+ compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
+ "fsl,imx6ul";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg1_vbus: usb-otg1-vbus {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79
+ >;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
--
2.10.0
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* Re: [PATCH 3/3] clocksource: Add clockevent support to NPS400 driver
From: Daniel Lezcano @ 2016-10-21 15:08 UTC (permalink / raw)
To: Noam Camus
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, John Stultz
In-Reply-To: <1476370350-3853-4-git-send-email-noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
On Thu, Oct 13, 2016 at 05:52:30PM +0300, Noam Camus wrote:
> From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
>
> Till now we used clockevent from generic ARC driver.
> This was enough as long as we worked with simple multicore SoC.
> When we are working with multithread SoC each HW thread can be
> scheduled to receive timer interrupt using timer mask register
> (TSI1).
>
> This patch will provide a way to control clock events per
> HW thread.
The description is not very clear. Can you elaborate ?
> Driver can be used from device tree by:
> compatible = "ezchip,nps400-timer0" <-- for clocksource
> compatible = "ezchip,nps400-timer1" <-- for clockevent
>
> Cc: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
> Cc: John Stultz <john.stultz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
> ---
[ ... ]
> -static int __init nps_setup_clocksource(struct device_node *node,
> - struct clk *clk)
> +static void __init nps_setup_clocksource(struct device_node *node)
CLOCKSOURCE_OF_DECLARE is expecting an int __init (*func)(struct device_node *)
This function returns void at the beginning then it is not changed and returns
an error value.
linux/drivers/clocksource/timer-nps.c: In function ‘nps_setup_clocksource’:
linux/drivers/clocksource/timer-nps.c:77:10: warning: ‘return’ with a value, in function returning void
return ret;
^
linux/drivers/clocksource/timer-nps.c:89:9: warning: ‘return’ with a value, in function returning void
return ret;
^
linux/drivers/clocksource/timer-nps.c: At top level:
linux/drivers/clocksource/timer-nps.c:92:216: warning: comparison of distinct pointer types lacks a cast
Don't submit changes which are not correctly compiled / tested, except you want to live
dangerously and watch your karma collapse.
I will let you fix this before reviewing the patches in details.
BTW, have a look at the hotplug callbacks, they changed to a finite state machine [1] and their usage
changed [2].
-- Daniel
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=710d60cbf1b312a8075a2158cbfbbd9c66132dcc
[2] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=eb0a9d8c672dc01db41352afa646405d035ee7a4
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* [PATCH 0/3] ARM: dts: oxnas: Update support for OX820 and use dt-bindings
From: Neil Armstrong @ 2016-10-21 15:10 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, linux-oxnas, devicetree; +Cc: Neil Armstrong
This patchset updates the ARM DTS for the Oxnas platform by :
- Add support for the Oxford Semicondutor OX820 and the PogoPlug V3
- Update the OX810SE to use the dt-bindings includes files introduced in [1] and [2]
- Fix the MAINTAINERS entry and add the PogoPlug V3 file maintainance
This patchset depends on dt-bindings include headers posted at [1] and [2],
that were accepted/merged in the subsystem trees.
How could I manage this dependency for 4.10 ?
[1] https://listengine.tuxfamily.org/lists.tuxfamily.org/linux-oxnas/2016/10/msg00008.html
[2] https://listengine.tuxfamily.org/lists.tuxfamily.org/linux-oxnas/2016/10/msg00007.html
Neil Armstrong (3):
ARM: dts: Add support for OX820 and Pogoplug V3
ARM: dts: OX810: Update with dt-bindings includes
MAINTAINERS: oxnas: Add new files definitions
Documentation/devicetree/bindings/arm/oxnas.txt | 5 +
MAINTAINERS | 3 +-
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/cloudengines-pogoplug-series-3.dts | 94 +++++++
arch/arm/boot/dts/ox810se.dtsi | 10 +-
arch/arm/boot/dts/ox820.dtsi | 298 +++++++++++++++++++++
6 files changed, 407 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
create mode 100644 arch/arm/boot/dts/ox820.dtsi
--
2.7.0
^ permalink raw reply
* [PATCH 1/3] ARM: dts: Add support for OX820 and Pogoplug V3
From: Neil Armstrong @ 2016-10-21 15:10 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, linux-oxnas, devicetree; +Cc: Neil Armstrong
In-Reply-To: <20161021151037.20112-1-narmstrong@baylibre.com>
Add device tree for the Oxford Seminconductor OX820 SoC and the
Cloud Engines PogoPlug v3 board.
Add the SoC and board compatible strings to oxnas bindings.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/oxnas.txt | 5 +
arch/arm/boot/dts/Makefile | 3 +-
.../boot/dts/cloudengines-pogoplug-series-3.dts | 94 +++++++
arch/arm/boot/dts/ox820.dtsi | 298 +++++++++++++++++++++
4 files changed, 399 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
create mode 100644 arch/arm/boot/dts/ox820.dtsi
diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt
index b9e4971..ac64e60 100644
--- a/Documentation/devicetree/bindings/arm/oxnas.txt
+++ b/Documentation/devicetree/bindings/arm/oxnas.txt
@@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties:
Required root node property:
compatible: "oxsemi,ox810se"
+Boards with the OX820 SoC shall have the following properties:
+ Required root node property:
+ compatible: "oxsemi,ox820"
+
Board compatible values:
- "wd,mbwe" (OX810SE)
+ - "cloudengines,pogoplugv3" (OX820)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..3b0c74f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -604,7 +604,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
- wd-mbwe.dtb
+ wd-mbwe.dtb \
+ cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
new file mode 100644
index 0000000..bfde32e
--- /dev/null
+++ b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
@@ -0,0 +1,94 @@
+/*
+ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+ model = "Cloud Engines PogoPlug Series 3";
+
+ compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ /* 128Mbytes DDR */
+ reg = <0x60000000 0x8000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "pogoplug:blue";
+ gpios = <&gpio0 2 0>;
+ default-state = "keep";
+ };
+
+ orange {
+ label = "pogoplug:orange";
+ gpios = <&gpio1 16 1>;
+ default-state = "keep";
+ };
+
+ green {
+ label = "pogoplug:green";
+ gpios = <&gpio1 17 1>;
+ default-state = "keep";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&nandc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "hamming";
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00e00000>;
+ read-only;
+ };
+
+ partition@e00000 {
+ label = "ubi";
+ reg = <0x00e00000 0x07200000>;
+ };
+ };
+};
+
+ða {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_etha_mdio>;
+};
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
new file mode 100644
index 0000000..4592075
--- /dev/null
+++ b/arch/arm/boot/dts/ox820.dtsi
@@ -0,0 +1,298 @@
+/*
+ * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/oxsemi,ox820.h>
+#include <dt-bindings/reset/oxsemi,ox820.h>
+
+/ {
+ compatible = "oxsemi,ox820";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "oxsemi,ox820-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,arm11mpcore";
+ clocks = <&armclk>;
+ reg = <1>;
+ };
+ };
+
+ memory {
+ /* Max 512MB @ 0x60000000 */
+ reg = <0x60000000 0x20000000>;
+ };
+
+ clocks {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&osc>;
+ };
+
+ plla: plla {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <850000000>;
+ };
+
+ armclk: armclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&plla>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&gic>;
+
+ nandc: nand-controller@41000000 {
+ compatible = "oxsemi,ox820-nand";
+ reg = <0x41000000 0x100000>;
+ clocks = <&stdclk CLK_820_NAND>;
+ resets = <&reset RESET_NAND>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ etha: ethernet@40400000 {
+ compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
+ reg = <0x40400000 0x2000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+
+ clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
+ clock-names = "gmac", "stmmaceth";
+ resets = <&reset RESET_MAC>;
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ status = "disabled";
+ };
+
+ apb-bridge@44000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x44000000 0x1000000>;
+
+ pinctrl: pinctrl {
+ compatible = "oxsemi,ox820-pinctrl";
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ pinctrl_uart0: uart0 {
+ uart0 {
+ pins = "gpio30", "gpio31";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart0_modem: uart0_modem {
+ uart0_modem_a {
+ pins = "gpio24", "gpio24", "gpio26", "gpio27";
+ function = "fct4";
+ };
+ uart0_modem_b {
+ pins = "gpio28", "gpio29";
+ function = "fct5";
+ };
+ };
+
+ pinctrl_uart1: uart1 {
+ uart1 {
+ pins = "gpio7", "gpio8";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_uart1_modem: uart1_modem {
+ uart1_modem {
+ pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
+ function = "fct4";
+ };
+ };
+
+ pinctrl_etha_mdio: etha_mdio {
+ etha_mdio {
+ pins = "gpio3", "gpio4";
+ function = "fct1";
+ };
+ };
+
+ pinctrl_nand: nand {
+ nand {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15",
+ "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24";
+ function = "fct1";
+ };
+ };
+ };
+
+ gpio0: gpio@000000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x000000 0x100000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <32>;
+ oxsemi,gpio-bank = <0>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+
+ gpio1: gpio@100000 {
+ compatible = "oxsemi,ox820-gpio";
+ reg = <0x100000 0x100000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <18>;
+ oxsemi,gpio-bank = <1>;
+ gpio-ranges = <&pinctrl 0 32 18>;
+ };
+
+ uart0: serial@200000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset RESET_UART1>;
+ };
+
+ uart1: serial@300000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ clocks = <&sysclk>;
+ resets = <&reset RESET_UART2>;
+ };
+
+ rps@400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+
+ intc: interrupt-controller@0 {
+ compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
+ interrupt-controller;
+ reg = <0 0x200>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ valid-mask = <0xFFFFFFFF>;
+ clear-mask = <0>;
+ };
+
+ timer0: timer@200 {
+ compatible = "oxsemi,ox820-rps-timer";
+ reg = <0x200 0x40>;
+ clocks = <&sysclk>;
+ interrupt-parent = <&intc>;
+ interrupts = <4>;
+ };
+ };
+
+ sys: sys-ctrl@e00000 {
+ compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
+ reg = <0xe00000 0x200000>;
+
+ reset: reset-controller {
+ compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
+ #reset-cells = <1>;
+ };
+
+ stdclk: stdclk {
+ compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ apb-bridge@47000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x47000000 0x1000000>;
+
+ scu: scu@0 {
+ compatible = "arm,arm11mp-scu";
+ reg = <0x0 0x100>;
+ };
+
+ local-timer@600 {
+ compatible = "arm,arm11mp-twd-timer";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&armclk>;
+ };
+
+ gic: gic@1000 {
+ compatible = "arm,arm11mp-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1000 0x1000>,
+ <0x100 0x500>;
+ };
+ };
+ };
+};
--
2.7.0
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: OX810: Update with dt-bindings includes
From: Neil Armstrong @ 2016-10-21 15:10 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-oxnas-Xt5XgHjqiBU06sgRBLv0+0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Neil Armstrong
In-Reply-To: <20161021151037.20112-1-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Add OX810SE dt-bindings includes files for clocks and resets, replace
resets numbers by human readable defines.
Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/ox810se.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi
index ce13705..46aa6db 100644
--- a/arch/arm/boot/dts/ox810se.dtsi
+++ b/arch/arm/boot/dts/ox810se.dtsi
@@ -7,6 +7,8 @@
*/
/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/oxsemi,ox810se.h>
+#include <dt-bindings/reset/oxsemi,ox810se.h>
/ {
compatible = "oxsemi,ox810se";
@@ -242,7 +244,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 17>;
+ resets = <&reset RESET_UART1>;
};
uart1: serial@300000 {
@@ -256,7 +258,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 18>;
+ resets = <&reset RESET_UART2>;
};
uart2: serial@900000 {
@@ -270,7 +272,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 22>;
+ resets = <&reset RESET_UART3>;
};
uart3: serial@a00000 {
@@ -284,7 +286,7 @@
current-speed = <115200>;
no-loopback-test;
status = "disabled";
- resets = <&reset 23>;
+ resets = <&reset RESET_UART4>;
};
};
--
2.7.0
--
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^ permalink raw reply related
* [PATCH 3/3] MAINTAINERS: oxnas: Add new files definitions
From: Neil Armstrong @ 2016-10-21 15:10 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, linux-oxnas, devicetree; +Cc: Neil Armstrong
In-Reply-To: <20161021151037.20112-1-narmstrong@baylibre.com>
Fix the dts files maintained by the OXNAS platform, add a new board.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..29d8853 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1478,8 +1478,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-oxnas/
-F: arch/arm/boot/dts/oxnas*
+F: arch/arm/boot/dts/ox8*.dtsi
F: arch/arm/boot/dts/wd-mbwe.dts
+F: arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
N: oxnas
ARM/Mediatek RTC DRIVER
--
2.7.0
^ permalink raw reply related
* Re: [PATCH v2 1/4] cpufreq: pxa: use generic platdev driver for device-tree
From: Robert Jarzmik @ 2016-10-21 15:17 UTC (permalink / raw)
To: Viresh Kumar
Cc: Daniel Mack, Haojian Zhuang, Rob Herring, Mark Rutland,
Rafael Wysocki, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161020033435.GD11766@vireshk-i7>
Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> writes:
> On 19-10-16, 22:06, Robert Jarzmik wrote:
>> Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> writes:
>>
>> >> >> + { .compatible = "marvell,pxa250", },
>> >> >> + { .compatible = "marvell,pxa270", },
>> >> >>
>> >> >> { .compatible = "samsung,exynos3250", },
>> >> >> { .compatible = "samsung,exynos4210", },
>> >> >
>> >> > Isn't there a race between cpufreq-dt and the platform driver to
>> >> > register first ?
>> >> Ah, could you be more specific about the race you're talking of ?
>> >>
>> >> My understanding was that cpufreq-dt-platdev does create the device, and
>> >> cpufreq-dt is a driver for it, so there is no race but a direct relationship
>> >> AFAIU.
>> >
>> > I mean that both the driver may try to register to the cpufreq core if
>> > they are both compiled in a single image.
>> Euh I still don't follow you. The only driver that can register to the cpufreq
>> core is cpufreq-dt.
>
> I was wondering on what will happen if both cpufreq-dt and your pxa2xx-cpufreq
> driver are present in the same kernel image. In that case the init routines of
> both of them will try to call cpufreq_register_driver().
Right.
In my case, cpufreq-dt comes first, and wins.
pxa_cpu_init() calls cpufreq_register_driver() and returns -EEXIST.
Cheers.
--
Robert
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^ permalink raw reply
* Re: [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Stefan Wahren @ 2016-10-21 15:24 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, Marek Vasut, Arnd Bergmann,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jörg Krause, Rob Herring,
Sascha Hauer, Fabio Estevam,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lothar Waßmann
In-Reply-To: <20161021150336.GJ30578@tiger>
Am 21.10.2016 um 17:03 schrieb Shawn Guo:
> On Fri, Oct 21, 2016 at 04:05:59PM +0200, Stefan Wahren wrote:
>> Am 21.10.2016 um 15:53 schrieb Shawn Guo:
>>> On Tue, Sep 13, 2016 at 05:51:02PM +0000, Stefan Wahren wrote:
>>>> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
>>>> for suspend to RAM and standby mode. But before we need to remove the fake reg
>>>> properties of all internal bus nodes as discussed in this thread [1].
>>>>
>>>> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
>>>> Remove skeleton.dtsi inclusion" [2].
>>>>
>>>> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
>>> The page cannot be reached. I would like to understand the
>>> background for this change.
>> Strange, because i don't have any problems while clicking on the URL.
>>
>> It's an older discussion on the devicetree / kernel newbie mailing list
>> with subject "strange dtc errors after adding sram node". Arnd suggested
>> in the discussion to remove the reg property from the ahb node.
>>
>> Please try this one: http://www.spinics.net/lists/newbies/msg57652.html
> If you go through 'Table 4-1. Address Map for i.MX28' of MCIMX28RM, you
> should be able to find there are 3 AHB buses: ahb@0, ahb@80080000 and
> ahb@c0000000. The ocram goes to ahb@0. The following change should be
> the right one for ocram addition.
Correct me if i'm wrong, but there is only one AHB bus and only the
connected peripheral devices like ocram or USB controller have a memory
mapped start address not the bus itself.
>
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 0ad893bf5f43..8e5718df06b2 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -47,6 +47,19 @@
> };
> };
>
> + ahb@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0 0x80000000>;
> + ranges;
> +
> + ocram: sram@0 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x20000>;
> + };
> + };
> +
> apb@80000000 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
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^ permalink raw reply
* Re: [RFC] ARM: dts: exynos: Remove exynos4415.dtsi
From: Javier Martinez Canillas @ 2016-10-21 15:28 UTC (permalink / raw)
To: Sylwester Nawrocki, Krzysztof Kozlowski
Cc: Rob Herring, Mark Rutland, Kukjin Kim, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel,
Marek Szyprowski, Bartlomiej Zolnierkiewicz, Tomasz Figa,
Arnd Bergmann, Olof Johansson, Kevin Hilman
In-Reply-To: <c8576159-347c-42df-6a8d-8620ba4be8a1@samsung.com>
On 10/21/2016 11:33 AM, Sylwester Nawrocki wrote:
> On 10/21/2016 04:15 PM, Krzysztof Kozlowski wrote:
>> There are no boards in mainline using exynos4415.dtsi. This is DTS
>> was not tested for long. I am also not aware of any popular out-of-tree
>> boards using this (except consumer devices released by Samsung but those
>> cannot use mainline).
>>
>> Keeping Exynos4415 costs some useless effort so remove it.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> It seems a sane thing to do, I don't know of any active platform that
> uses Exynos4415.
>
> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* Re: [PATCH] dt-bindings: video: exynos7-decon: Remove obsolete samsung,power-domain property
From: Javier Martinez Canillas @ 2016-10-21 15:28 UTC (permalink / raw)
To: Sylwester Nawrocki, Krzysztof Kozlowski, Inki Dae
Cc: Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, David Airlie,
Kukjin Kim, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <7e80b5ee-41a9-8c35-ff0d-e1b8b7a4e429-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
On 10/21/2016 11:36 AM, Sylwester Nawrocki wrote:
> On 10/21/2016 04:05 PM, Krzysztof Kozlowski wrote:
>> The samsung,power-domain property is obsolete since commit 0da658704136
>> ("ARM: dts: convert to generic power domain bindings for exynos DT").
>> Replace it with generic one.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>
Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
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^ permalink raw reply
* Re: [PATCH 0/4] ARM: boot: mxs: Add On-Chip RAM
From: Stefan Wahren @ 2016-10-21 15:30 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, Marek Vasut, Arnd Bergmann,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jörg Krause, Rob Herring,
Sascha Hauer, Fabio Estevam,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lothar Waßmann
In-Reply-To: <e472fb62-00d2-359d-2126-ce2727fe3bed-eS4NqCHxEME@public.gmane.org>
Am 21.10.2016 um 17:24 schrieb Stefan Wahren:
> Am 21.10.2016 um 17:03 schrieb Shawn Guo:
>> On Fri, Oct 21, 2016 at 04:05:59PM +0200, Stefan Wahren wrote:
>>> Am 21.10.2016 um 15:53 schrieb Shawn Guo:
>>>> On Tue, Sep 13, 2016 at 05:51:02PM +0000, Stefan Wahren wrote:
>>>>> The i.MX23 / i.MX28 have a small amount of On-Chip RAM which is also necessary
>>>>> for suspend to RAM and standby mode. But before we need to remove the fake reg
>>>>> properties of all internal bus nodes as discussed in this thread [1].
>>>>>
>>>>> This patch series requires Fabio Estevam's recent series "ARM: dts: imx23:
>>>>> Remove skeleton.dtsi inclusion" [2].
>>>>>
>>>>> [1] - https://marc.info/?l=devicetree&m=146139948426520&w=2
>>>> The page cannot be reached. I would like to understand the
>>>> background for this change.
>>> Strange, because i don't have any problems while clicking on the URL.
>>>
>>> It's an older discussion on the devicetree / kernel newbie mailing list
>>> with subject "strange dtc errors after adding sram node". Arnd suggested
>>> in the discussion to remove the reg property from the ahb node.
>>>
>>> Please try this one: http://www.spinics.net/lists/newbies/msg57652.html
>> If you go through 'Table 4-1. Address Map for i.MX28' of MCIMX28RM, you
>> should be able to find there are 3 AHB buses: ahb@0, ahb@80080000 and
>> ahb@c0000000. The ocram goes to ahb@0. The following change should be
>> the right one for ocram addition.
> Correct me if i'm wrong, but there is only one AHB bus and only the
> connected peripheral devices like ocram or USB controller have a memory
> mapped start address not the bus itself.
Please forget about that. According to the reference manual there are 3
AHB bus layers.
>
>> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
>> index 0ad893bf5f43..8e5718df06b2 100644
>> --- a/arch/arm/boot/dts/imx28.dtsi
>> +++ b/arch/arm/boot/dts/imx28.dtsi
>> @@ -47,6 +47,19 @@
>> };
>> };
>>
>> + ahb@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x0 0x80000000>;
>> + ranges;
>> +
>> + ocram: sram@0 {
>> + compatible = "mmio-sram";
>> + reg = <0x0 0x20000>;
>> + };
>> + };
>> +
>> apb@80000000 {
>> compatible = "simple-bus";
>> #address-cells = <1>;
>>
>
--
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^ permalink raw reply
* Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Philipp Zabel @ 2016-10-21 15:45 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Simon Horman, Magnus Damm,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477055857-17936-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
A. Hi Geert,
Am Freitag, den 21.10.2016, 15:17 +0200 schrieb Geert Uytterhoeven:
> Hi Philipp, Mike, Stephen, Simon, Magnus,
> (see questions *** below!)
>
> Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
> state of the mode pins either by a call from the platform code, or
> directly by using a hardcoded register access. This is a bit messy, and
> creates a dependency between driver and platform code.
>
> This patch series converts the various Renesas R-Car clock drivers
> and support code from reading the mode pin states using a hardcoded
> register access to using a new minimalistic R-Car RST driver.
>
> All R-Car clock drivers will rely on the presence in DT of a device node
> for the RST module. Backwards compatibility with old DTBs is retained
> only for R-Car Gen2, which has fallback code using its own private copy
> of rcar_gen2_read_mode_pins().
I think you should add a binding doc even though the DT bindings are
still trivial.
> After this, there is still one remaining user of
> rcar_gen2_read_mode_pins() left in platform code. A patch series to
> remove that user has already been posted, though ("[PATCH/RFT 0/4] ARM:
> shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode").
> Since v3, the other user has been removed in commit 9f5ce39ddb8f68b3
> ("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT").
>
> This series consists of 5 parts:
> A. Patches 1 and 2 add DT bindings and driver code for the R-Car RST
> driver,
> B. Patches 3-11 add device nodes for the RST modules to the R-Car DTS
> files,
> C. Patches 12-17 convert the clock drivers to call into the new R-Car
> RST driver,
> D. Patches 18-20 remove passing mode pin state to the clock drivers
> from the platform code,
> E. Patches 21-23 remove dead code from the clock drivers.
>
> As is usually the case with moving functionality from platform code to
> DT, there are lots of hard dependencies:
> - The DT updates in Part B can be merged as soon as the DT bindings in
> Part A have been approved,
> - The clock driver updates in Part C depend functionally on the driver
> code in Part A, and on the DT updates in Part B,
> - The board code cleanups in Part D depend on the clock driver updates
> in Part C,
> - The block driver cleanups in part E depend on the board code
> cleanups in part D.
>
> Hence to maintain the required lockstep between SoC driver, clock
> drivers, shmobile platform code, and shmobile DT, I propose to queue up
> all patches in a single branch against v4.9-rc1, and send pull requests
> to both Mike/Stephen (clock) and Simon (rest).
>
> ***
>
> - Philip: While this is a driver for a reset-controller, currently it
> doesn't provide any reset-controller functionality. Hence I added it
> to drivers/soc/renesas/. Is that OK for you?
Absolutely, as long as the driver isn't even a reset controller
provider, this is the right place.
regards
Philipp
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^ permalink raw reply
* Re: [RFC PATCH 08/13] dwmac-meson8b: add support for phy selection
From: Andrew Lunn @ 2016-10-21 15:46 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, carlo, linus.walleij, linux-gpio, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel, netdev
In-Reply-To: <1477060838-14164-9-git-send-email-narmstrong@baylibre.com>
On Fri, Oct 21, 2016 at 04:40:33PM +0200, Neil Armstrong wrote:
> The Meson GXL dwmac Glue Layer also provides switching between an external PHY
> and an internal RMII 10/100 PHY.
> Add a way to setup the correct PHY switching from a device tree attribute.
Hi Neil
Can this be made automatic?
The internal PHY appears to be on address 8. Can there also be an
external PHY on address 8? Could you follow the phy-handle link to the
phy node, check the address, and if it is 8, configure for an internal
PHY?
Andrew
^ permalink raw reply
* Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Philipp Zabel @ 2016-10-21 15:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Simon Horman, Magnus Damm,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477064730.2508.24.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Am Freitag, den 21.10.2016, 17:45 +0200 schrieb Philipp Zabel:
> A. Hi Geert,
>
> Am Freitag, den 21.10.2016, 15:17 +0200 schrieb Geert Uytterhoeven:
> > Hi Philipp, Mike, Stephen, Simon, Magnus,
> > (see questions *** below!)
> >
> > Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
> > state of the mode pins either by a call from the platform code, or
> > directly by using a hardcoded register access. This is a bit messy, and
> > creates a dependency between driver and platform code.
> >
> > This patch series converts the various Renesas R-Car clock drivers
> > and support code from reading the mode pin states using a hardcoded
> > register access to using a new minimalistic R-Car RST driver.
> >
> > All R-Car clock drivers will rely on the presence in DT of a device node
> > for the RST module. Backwards compatibility with old DTBs is retained
> > only for R-Car Gen2, which has fallback code using its own private copy
> > of rcar_gen2_read_mode_pins().
>
> I think you should add a binding doc even though the DT bindings are
> still trivial.
Disregard that, I literally sent this mail and a second later noticed
patch 1 for the first time.
regards
Philipp
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^ permalink raw reply
* Re: [PATCH v4 01/23] reset: Add renesas,rst DT bindings
From: Philipp Zabel @ 2016-10-21 15:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Simon Horman, Magnus Damm,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477055857-17936-2-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Am Freitag, den 21.10.2016, 15:17 +0200 schrieb Geert Uytterhoeven:
> Add DT bindings for the Renesas R-Car Reset Controller (R-Car Gen1
> RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST).
>
> As the features provided by the hardware module differ a lot across the
> various SoC families and members, only SoC-specific compatible values
> are defined.
>
> For now we use the RST only for providing access to the state of the
> mode pins, which is needed by the clock driver.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> Acked-by: Magnus Damm <damm+renesas-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>
> Acked-by: Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org>
> Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> ---
> v4:
> - Add Acked-by,
> - Fix comma and period in list,
> - Add RZ/G1M and RZ/G1E,
>
> v3:
> - Clarify current usage,
> - Use "renesas,<soctype>-rst" instead of "renesas,rst-<soctype>",
> - Drop "syscon" compatible value,
> - Add R-Car M3-W,
> - Add R-Car Gen1,
>
> v2:
> - Add Acked-by.
> ---
> .../devicetree/bindings/reset/renesas,rst.txt | 37 ++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rst.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
> new file mode 100644
> index 0000000000000000..fe5e0f37b3c93579
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
> @@ -0,0 +1,37 @@
> +DT bindings for the Renesas R-Car and RZ/G Reset Controllers
> +
> +The R-Car and RZ/G Reset Controllers provide reset control, and implement the
> +following functions:
> + - Latching of the levels on mode pins when PRESET# is negated,
> + - Mode monitoring register,
> + - Reset control of peripheral devices (on R-Car Gen1),
> + - Watchdog timer (on R-Car Gen1),
> + - Register-based reset control and boot address registers for the various CPU
> + cores (on R-Car Gen2 and Gen3, and on RZ/G).
> +
> +
> +Required properties:
> + - compatible: Should be
> + - "renesas,<soctype>-reset-wdt" for R-Car Gen1,
> + - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G
> + Examples with soctypes are:
> + - "renesas,r8a7743-rst" (RZ/G1M)
> + - "renesas,r8a7745-rst" (RZ/G1E)
> + - "renesas,r8a7778-reset-wdt" (R-Car M1A)
> + - "renesas,r8a7779-reset-wdt" (R-Car H1)
> + - "renesas,r8a7790-rst" (R-Car H2)
> + - "renesas,r8a7791-rst" (R-Car M2-W)
> + - "renesas,r8a7792-rst" (R-Car V2H
> + - "renesas,r8a7793-rst" (R-Car M2-N)
> + - "renesas,r8a7794-rst" (R-Car E2)
> + - "renesas,r8a7795-rst" (R-Car H3)
> + - "renesas,r8a7796-rst" (R-Car M3-W)
> + - reg: Address start and address range for the device.
> +
> +
> +Example:
> +
> + rst: reset-controller@e6160000 {
> + compatible = "renesas,r8a7795-rst";
> + reg = <0 0xe6160000 0 0x0200>;
> + };
Acked-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
regards
Philipp
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^ permalink raw reply
* Re: [RFC PATCH 08/13] dwmac-meson8b: add support for phy selection
From: Andrew Lunn @ 2016-10-21 15:54 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, carlo, linus.walleij, linux-gpio, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel, netdev
In-Reply-To: <1477060838-14164-9-git-send-email-narmstrong@baylibre.com>
On Fri, Oct 21, 2016 at 04:40:33PM +0200, Neil Armstrong wrote:
> The Meson GXL dwmac Glue Layer also provides switching between an external PHY
> and an internal RMII 10/100 PHY.
> Add a way to setup the correct PHY switching from a device tree attribute.
Humm, actually. Maybe PHY_IS_INTERNAL in the phydrv->flags is the
better solution. The MAC can then use phy_is_internal(ndev->phydev) to
decide if this register needs programming.
Andrew
^ permalink raw reply
* Re: [PATCH V6 00/10] dmaengine: qcom_hidma: add MSI interrupt support
From: Sinan Kaya @ 2016-10-21 15:56 UTC (permalink / raw)
To: Vinod Koul
Cc: dmaengine, timur, devicetree, cov, jcm, agross, arnd,
linux-arm-msm, linux-arm-kernel
In-Reply-To: <20161021065723.GA2467@localhost>
On 10/20/2016 11:57 PM, Vinod Koul wrote:
>> It looks like patches were applied out of order.
> When applying, if I get a conflict I try to skip them. Typically subsequent
> patches fail, sometimes they apply. I think couple of them did in this case
>
> It built for me, 0day also gave me success report, so unless we have bisect
> regression, I would like rest of the patches on top of this please..
>
OK. Let me work on it.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 0/5] Remove STiH415/416 SoC platform support remaining parts
From: patrice.chotard @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, devicetree
Cc: peter.griffin, lee.jones, kernel, patrice.chotard
From: Patrice Chotard <patrice.chotard@st.com>
ST have sent patches which remove clock support for these SoCs [1]
which once applied mean the platform will no longer boot.
This series cleans up remaining STi drivers which have
support for these SoC's, by removing code, and updating the DT
documentation accordingly. Some drivers such as st_thermal_syscfg
can be removed completely because the IP is only found on these
legacy SoC's.
Patrice Chotard (5):
thermal: st_thermal_syscfg: Remove obsolete STiH415/416 platform
support.
ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol
ARM: multi_v7_defconfig: Remove CONFIG_ST_THERMAL_MEMMAP Kconfig
symbol
irqchip: st: remove STiH415/416 irqchip support
irqchip: st: Remove obsolete platforms from dt binding doc
.../interrupt-controller/st,sti-irq-syscfg.txt | 6 +-
arch/arm/configs/multi_v7_defconfig | 2 -
drivers/irqchip/irq-st.c | 10 --
drivers/thermal/st/Kconfig | 4 -
drivers/thermal/st/Makefile | 1 -
drivers/thermal/st/st_thermal_syscfg.c | 178 ---------------------
6 files changed, 2 insertions(+), 199 deletions(-)
delete mode 100644 drivers/thermal/st/st_thermal_syscfg.c
--
1.9.1
^ permalink raw reply
* [PATCH 1/5] thermal: st_thermal_syscfg: Remove obsolete STiH415/416 platform support.
From: patrice.chotard-qxv4g6HH51o @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
patrice.chotard-qxv4g6HH51o, rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
STiH415/6 SoC support is being removed from the kernel.
This patch removes support from the syscfg thermal driver.
This driver also supports STiD127 SoC which has never been
upstreamed.
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Cc: <rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: <edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/thermal/st/Kconfig | 4 -
drivers/thermal/st/Makefile | 1 -
drivers/thermal/st/st_thermal_syscfg.c | 178 ---------------------------------
3 files changed, 183 deletions(-)
delete mode 100644 drivers/thermal/st/st_thermal_syscfg.c
diff --git a/drivers/thermal/st/Kconfig b/drivers/thermal/st/Kconfig
index 490fdbe..ce84267 100644
--- a/drivers/thermal/st/Kconfig
+++ b/drivers/thermal/st/Kconfig
@@ -3,10 +3,6 @@ config ST_THERMAL
help
Support for thermal sensors on STMicroelectronics STi series of SoCs.
-config ST_THERMAL_SYSCFG
- select ST_THERMAL
- tristate "STi series syscfg register access based thermal sensors"
-
config ST_THERMAL_MEMMAP
select ST_THERMAL
tristate "STi series memory mapped access based thermal sensors"
diff --git a/drivers/thermal/st/Makefile b/drivers/thermal/st/Makefile
index b388789..27197e1 100644
--- a/drivers/thermal/st/Makefile
+++ b/drivers/thermal/st/Makefile
@@ -1,3 +1,2 @@
obj-$(CONFIG_ST_THERMAL) := st_thermal.o
-obj-$(CONFIG_ST_THERMAL_SYSCFG) += st_thermal_syscfg.o
obj-$(CONFIG_ST_THERMAL_MEMMAP) += st_thermal_memmap.o
diff --git a/drivers/thermal/st/st_thermal_syscfg.c b/drivers/thermal/st/st_thermal_syscfg.c
deleted file mode 100644
index 3df5b789..0000000
--- a/drivers/thermal/st/st_thermal_syscfg.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * ST Thermal Sensor Driver for syscfg based sensors.
- * Author: Ajit Pal Singh <ajitpal.singh-qxv4g6HH51o@public.gmane.org>
- *
- * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/mfd/syscon.h>
-
-#include "st_thermal.h"
-
-/* STiH415 */
-#define STIH415_SYSCFG_FRONT(num) ((num - 100) * 4)
-#define STIH415_SAS_THSENS_CONF STIH415_SYSCFG_FRONT(178)
-#define STIH415_SAS_THSENS_STATUS STIH415_SYSCFG_FRONT(198)
-#define STIH415_SYSCFG_MPE(num) ((num - 600) * 4)
-#define STIH415_MPE_THSENS_CONF STIH415_SYSCFG_MPE(607)
-#define STIH415_MPE_THSENS_STATUS STIH415_SYSCFG_MPE(667)
-
-/* STiH416 */
-#define STIH416_SYSCFG_FRONT(num) ((num - 1000) * 4)
-#define STIH416_SAS_THSENS_CONF STIH416_SYSCFG_FRONT(1552)
-#define STIH416_SAS_THSENS_STATUS1 STIH416_SYSCFG_FRONT(1554)
-#define STIH416_SAS_THSENS_STATUS2 STIH416_SYSCFG_FRONT(1594)
-
-/* STiD127 */
-#define STID127_SYSCFG_CPU(num) ((num - 700) * 4)
-#define STID127_THSENS_CONF STID127_SYSCFG_CPU(743)
-#define STID127_THSENS_STATUS STID127_SYSCFG_CPU(767)
-
-static const struct reg_field st_415sas_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH415_SAS_THSENS_CONF, 9, 9),
- [DCORRECT] = REG_FIELD(STIH415_SAS_THSENS_CONF, 4, 8),
- [OVERFLOW] = REG_FIELD(STIH415_SAS_THSENS_STATUS, 8, 8),
- [DATA] = REG_FIELD(STIH415_SAS_THSENS_STATUS, 10, 16),
-};
-
-static const struct reg_field st_415mpe_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH415_MPE_THSENS_CONF, 8, 8),
- [DCORRECT] = REG_FIELD(STIH415_MPE_THSENS_CONF, 3, 7),
- [OVERFLOW] = REG_FIELD(STIH415_MPE_THSENS_STATUS, 9, 9),
- [DATA] = REG_FIELD(STIH415_MPE_THSENS_STATUS, 11, 18),
-};
-
-static const struct reg_field st_416sas_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH416_SAS_THSENS_CONF, 9, 9),
- [DCORRECT] = REG_FIELD(STIH416_SAS_THSENS_CONF, 4, 8),
- [OVERFLOW] = REG_FIELD(STIH416_SAS_THSENS_STATUS1, 8, 8),
- [DATA] = REG_FIELD(STIH416_SAS_THSENS_STATUS2, 10, 16),
-};
-
-static const struct reg_field st_127_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STID127_THSENS_CONF, 7, 7),
- [DCORRECT] = REG_FIELD(STID127_THSENS_CONF, 2, 6),
- [OVERFLOW] = REG_FIELD(STID127_THSENS_STATUS, 9, 9),
- [DATA] = REG_FIELD(STID127_THSENS_STATUS, 11, 18),
-};
-
-/* Private OPs for System Configuration Register based thermal sensors */
-static int st_syscfg_power_ctrl(struct st_thermal_sensor *sensor,
- enum st_thermal_power_state power_state)
-{
- return regmap_field_write(sensor->pwr, power_state);
-}
-
-static int st_syscfg_alloc_regfields(struct st_thermal_sensor *sensor)
-{
- struct device *dev = sensor->dev;
-
- sensor->pwr = devm_regmap_field_alloc(dev, sensor->regmap,
- sensor->cdata->reg_fields[TEMP_PWR]);
-
- if (IS_ERR(sensor->pwr)) {
- dev_err(dev, "failed to alloc syscfg regfields\n");
- return PTR_ERR(sensor->pwr);
- }
-
- return 0;
-}
-
-static int st_syscfg_regmap_init(struct st_thermal_sensor *sensor)
-{
- sensor->regmap =
- syscon_regmap_lookup_by_compatible(sensor->cdata->sys_compat);
- if (IS_ERR(sensor->regmap)) {
- dev_err(sensor->dev, "failed to find syscfg regmap\n");
- return PTR_ERR(sensor->regmap);
- }
-
- return 0;
-}
-
-static const struct st_thermal_sensor_ops st_syscfg_sensor_ops = {
- .power_ctrl = st_syscfg_power_ctrl,
- .alloc_regfields = st_syscfg_alloc_regfields,
- .regmap_init = st_syscfg_regmap_init,
-};
-
-/* Compatible device data for stih415 sas thermal sensor */
-static const struct st_thermal_compat_data st_415sas_cdata = {
- .sys_compat = "st,stih415-front-syscfg",
- .reg_fields = st_415sas_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = 20,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stih415 mpe thermal sensor */
-static const struct st_thermal_compat_data st_415mpe_cdata = {
- .sys_compat = "st,stih415-system-syscfg",
- .reg_fields = st_415mpe_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = -103,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stih416 sas thermal sensor */
-static const struct st_thermal_compat_data st_416sas_cdata = {
- .sys_compat = "st,stih416-front-syscfg",
- .reg_fields = st_416sas_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = 20,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stid127 thermal sensor */
-static const struct st_thermal_compat_data st_127_cdata = {
- .sys_compat = "st,stid127-cpu-syscfg",
- .reg_fields = st_127_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 8,
- .temp_adjust_val = -103,
- .crit_temp = 120,
-};
-
-static const struct of_device_id st_syscfg_thermal_of_match[] = {
- { .compatible = "st,stih415-sas-thermal", .data = &st_415sas_cdata },
- { .compatible = "st,stih415-mpe-thermal", .data = &st_415mpe_cdata },
- { .compatible = "st,stih416-sas-thermal", .data = &st_416sas_cdata },
- { .compatible = "st,stid127-thermal", .data = &st_127_cdata },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, st_syscfg_thermal_of_match);
-
-static int st_syscfg_probe(struct platform_device *pdev)
-{
- return st_thermal_register(pdev, st_syscfg_thermal_of_match);
-}
-
-static int st_syscfg_remove(struct platform_device *pdev)
-{
- return st_thermal_unregister(pdev);
-}
-
-static struct platform_driver st_syscfg_thermal_driver = {
- .driver = {
- .name = "st_syscfg_thermal",
- .pm = &st_thermal_pm_ops,
- .of_match_table = st_syscfg_thermal_of_match,
- },
- .probe = st_syscfg_probe,
- .remove = st_syscfg_remove,
-};
-module_platform_driver(st_syscfg_thermal_driver);
-
-MODULE_AUTHOR("STMicroelectronics (R&D) Limited <ajitpal.singh-qxv4g6HH51o@public.gmane.org>");
-MODULE_DESCRIPTION("STMicroelectronics STi SoC Thermal Sensor Driver");
-MODULE_LICENSE("GPL v2");
--
1.9.1
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