* [PATCH v5 0/7] ARM: ASoC: drm: sun8i: Add DE2 HDMI audio and video
From: Jean-Francois Moine @ 2016-10-22 13:28 UTC (permalink / raw)
To: Dave Airlie, Liam Girdwood, Mark Brown, Maxime Ripard,
Rob Herring
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
This patchset series adds HDMI audio and video support to the Allwinner
sun8i SoCs which include the display engine 2 (DE2).
A first submission in January for video on the H3 could not enter into
the mainline kernel due to the lack of license headers in Allwinner's
sources.
Recently, an announce about Tina OS for the R series
https://www.youtube.com/watch?v=h7KD-6HblAU
was followed by the upload of a new linux-3.4 source tree
https://github.com/tinalinux/linux-3.4
with files containing GPL headers.
Well, I don't know if these sources are really from Allwinner, but
anyway, this is the opportunity to propose a new version of my DRM
HDMI driver.
v5:
- add overlay plane
- add audio support
- add support for the A83T
- add back the HDMI driver
- many bug fixes
v4:
- drivers/clk/sunxi/Makefile was missing (Emil Velikov)
v3:
- add the hardware cursor
- simplify and fix the DE2 init sequences
- generation for all SUNXI SoCs (Andre Przywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added
Jean-Francois Moine (7):
drm: sunxi: Add a basic DRM driver for Allwinner DE2
ASoC: sunxi: Add a simple HDMI CODEC
drm: sunxi: add DE2 HDMI support
ASoC: sunxi: Add sun8i I2S driver
ARM: dts: sun8i-h3: add HDMI audio and video nodes
ARM: dts: sun8i-h3: Add HDMI audio and video to the Banana Pi M2+
ARM: dts: sun8i-h3: Add HDMI audio and video to the Orange PI 2
.../devicetree/bindings/display/sunxi/hdmi.txt | 52 ++
.../bindings/display/sunxi/sunxi-de2.txt | 83 ++
.../devicetree/bindings/sound/sun4i-i2s.txt | 38 +-
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +
arch/arm/boot/dts/sun8i-h3.dtsi | 67 ++
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/sunxi/Kconfig | 29 +
drivers/gpu/drm/sunxi/Makefile | 9 +
drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++
drivers/gpu/drm/sunxi/de2_crtc.h | 63 ++
drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++
drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++
drivers/gpu/drm/sunxi/de2_hdmi.c | 396 +++++++++
drivers/gpu/drm/sunxi/de2_hdmi.h | 40 +
drivers/gpu/drm/sunxi/de2_hdmi_io.c | 927 +++++++++++++++++++++
drivers/gpu/drm/sunxi/de2_hdmi_io.h | 25 +
drivers/gpu/drm/sunxi/de2_plane.c | 119 +++
include/sound/sunxi_hdmi.h | 23 +
sound/soc/codecs/Kconfig | 9 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/sunxi-hdmi.c | 106 +++
sound/soc/sunxi/Kconfig | 8 +
sound/soc/sunxi/Makefile | 3 +
sound/soc/sunxi/sun8i-i2s.c | 700 ++++++++++++++++
27 files changed, 4222 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
create mode 100644 drivers/gpu/drm/sunxi/Kconfig
create mode 100644 drivers/gpu/drm/sunxi/Makefile
create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.h
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.c
create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.h
create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
create mode 100644 include/sound/sunxi_hdmi.h
create mode 100644 sound/soc/codecs/sunxi-hdmi.c
create mode 100644 sound/soc/sunxi/sun8i-i2s.c
--
2.10.1
--
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^ permalink raw reply
* [PATCH 2/2] ARM64: dts: rockchip: use pin constants to describe gpios
From: Andy Yan @ 2016-10-22 12:59 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
arnd-r2nGTMty4D4, will.deacon-5wv7dgnIgG8, Andy Yan
In-Reply-To: <1477140706-6886-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Use macros to describe gpios will make the dts easier to
read and write.
Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 10 +++++-----
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 8 ++++----
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 14 +++++++-------
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 4 ++--
arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 16 ++++++++--------
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 6 +++---
6 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index fff8b19..4772917 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -90,7 +90,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
@@ -101,7 +101,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
keys: gpio-keys {
@@ -111,7 +111,7 @@
power {
wakeup-source;
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -121,7 +121,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -166,7 +166,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rmii";
clock_in_out = "output";
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
index e5eeca2..e5b92d2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
@@ -66,7 +66,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -77,7 +77,7 @@
pinctrl-0 = <&pwr_key>;
power {
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
@@ -88,13 +88,13 @@
compatible = "gpio-leds";
blue {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "geekbox:blue:led";
default-state = "on";
};
red {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
label = "geekbox:red:led";
default-state = "off";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index ea0a8ec..2e431f13 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -61,7 +61,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
ext_gmac: external-gmac-clock {
@@ -78,7 +78,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -88,7 +88,7 @@
compatible = "gpio-leds";
red {
- gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
label = "orion:red:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -96,7 +96,7 @@
};
blue {
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
label = "orion:blue:led";
pinctrl-names = "default";
pinctrl-0 = <&stby_pwren>;
@@ -117,7 +117,7 @@
/* supplies both host and otg */
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -149,7 +149,7 @@
vcc_sd: vcc-sd-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sd";
- gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
@@ -217,7 +217,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 85f7a24..62919c4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -63,7 +63,7 @@
pinctrl-0 = <&pwr_key>;
power {
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
@@ -248,7 +248,7 @@
reg = <0x40>;
interrupt-parent = <&gpio3>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
- power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
silead,max-fingers = <5>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index eed1ef6..7134181 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -61,7 +61,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
keys: gpio-keys {
@@ -71,7 +71,7 @@
power {
wakeup-source;
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
@@ -81,7 +81,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
label = "r88:green:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -90,7 +90,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -104,10 +104,10 @@
reset-gpios =
/* BT_RST_N */
- <&gpio3 5 GPIO_ACTIVE_LOW>,
+ <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>,
/* WL_REG_ON */
- <&gpio3 4 GPIO_ACTIVE_LOW>;
+ <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
};
vcc_18: vcc18-regulator {
@@ -124,7 +124,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -199,7 +199,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rmii";
clock_in_out = "output";
- snps,reset-gpio = <&gpio3 12 0>;
+ snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 8e82497..f00e0d5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -88,7 +88,7 @@
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
@@ -123,7 +123,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
@@ -156,7 +156,7 @@
};
&pcie0 {
- ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 1/2] ARM: dts: rockchip: use pin constants to describe gpios
From: Andy Yan @ 2016-10-22 12:54 UTC (permalink / raw)
To: heiko, linux-kernel
Cc: linux-rockchip, devicetree, robh+dt, mark.rutland, linux,
linux-arm-kernel, Andy Yan
In-Reply-To: <1477140706-6886-1-git-send-email-andy.yan@rock-chips.com>
Use macros to describe gpios will make the dts easier to
read and write.
All the modifications done with sed:
sed -i -e 's/ 0 GPIO_ACTIVE_/ RK_PA0 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 1 GPIO_ACTIVE_/ RK_PA1 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 2 GPIO_ACTIVE_/ RK_PA2 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
.......
.......
sed -i -e 's/ 30 GPIO_ACTIVE_/ RK_PD6 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 31 GPIO_ACTIVE_/ RK_PD7 GPIO_ACTIVE_/' arch/arm/boot/dts/rk*
Tested with:
for i in dts-old/*dtb; do scripts/dtc/dtx_diff $i dts-new/$(basename $i); done
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 10 +++++-----
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++---
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-mk808.dts | 10 +++++-----
arch/arm/boot/dts/rk3066a-rayeager.dts | 12 ++++++------
arch/arm/boot/dts/rk3188-px3-evb.dts | 4 ++--
arch/arm/boot/dts/rk3188-radxarock.dts | 16 +++++++--------
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 ++--
arch/arm/boot/dts/rk3288-evb.dtsi | 14 ++++++-------
arch/arm/boot/dts/rk3288-fennec.dts | 4 ++--
arch/arm/boot/dts/rk3288-firefly-beta.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload.dts | 24 +++++++++++------------
arch/arm/boot/dts/rk3288-firefly.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 16 +++++++--------
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
arch/arm/boot/dts/rk3288-r89.dts | 12 ++++++------
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-rock2-square.dts | 12 ++++++------
arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 ++++----
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 ++++++-------
arch/arm/boot/dts/rk3288-veyron-jerry.dts | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 16 +++++++--------
arch/arm/boot/dts/rk3288-veyron-pinky.dts | 4 ++--
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron-speedy.dts | 10 +++++-----
arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++----
33 files changed, 131 insertions(+), 131 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 2f5f155..c095341 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -56,7 +56,7 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 3de958e..2518259 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -55,7 +55,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
label = "kylin:red:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
@@ -74,9 +74,9 @@
* - SDIO_RESET_L_WL_RST
* - SDIO_RESET_L_BT_EN
*/
- reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
- <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */
- <&gpio2 9 GPIO_ACTIVE_LOW>; /* BT_EN */
+ reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
+ <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */
+ <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */
};
sound {
@@ -121,7 +121,7 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index c0d8b54..9e852c6 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -71,7 +71,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -81,7 +81,7 @@
autorepeat;
power {
- gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
+ gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -89,7 +89,7 @@
debounce-interval = <100>;
};
volume-down {
- gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <KEY_VOLUMEDOWN>;
label = "GPIO Key Vol-";
linux,input-type = <1>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index 0a54c4b..cdf0a88 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -69,7 +69,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 658eb7d..7ca1cf5 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -61,7 +61,7 @@
blue {
label = "mk808:blue:power";
- gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "default-on";
};
@@ -77,7 +77,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&host_drv>;
pinctrl-names = "default";
regulator-always-on;
@@ -91,7 +91,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&otg_drv>;
pinctrl-names = "default";
regulator-always-on;
@@ -104,7 +104,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdmmc_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_sd";
@@ -117,7 +117,7 @@
vcc_wifi: sdio-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&wifi_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_wifi";
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 82465b6..7c05e8b 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -55,7 +55,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -65,7 +65,7 @@
power {
wakeup-source;
- gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -115,7 +115,7 @@
vcc_sata: sata-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sata_pwr>;
regulator-name = "usb_5v";
@@ -127,7 +127,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -140,7 +140,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_drv>;
regulator-name = "host-pwr";
@@ -153,7 +153,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_drv>;
regulator-name = "vcc_otg";
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index df727ba..4afd9d8 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -62,7 +62,7 @@
autorepeat;
power {
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -248,7 +248,7 @@
reg = <0x40>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
silead,max-fingers = <5>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 5e8a235..28a2931 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -58,7 +58,7 @@
autorepeat;
power {
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -72,19 +72,19 @@
green {
label = "rock:green:user1";
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
blue {
label = "rock:blue:user2";
- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
sleep {
label = "rock:red:power";
- gpios = <&gpio0 15 0>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
@@ -106,7 +106,7 @@
ir_recv: gpio-ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio0 10 1>;
+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_recv_pin>;
};
@@ -114,7 +114,7 @@
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "otg-vbus";
@@ -129,7 +129,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -137,7 +137,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "host-pwr";
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index dcdd0ce..275092a 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -77,7 +77,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 041dd5d..f4f29fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -47,7 +47,7 @@
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
regulator-name = "vcc_lcd";
@@ -57,7 +57,7 @@
vcc_wl: vcc-wl {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pwr>;
regulator-name = "vcc_wl";
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index bf7ccfa..0dec94c 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -84,7 +84,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
@@ -100,7 +100,7 @@
panel: panel {
compatible ="lg,lp079qx1-sp0v", "simple-panel";
backlight = <&backlight>;
- enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
ports {
@@ -120,7 +120,7 @@
pinctrl-0 = <&pwrbtn>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -133,7 +133,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -144,7 +144,7 @@
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <ð_phy_pwr>;
regulator-name = "vcc_phy";
@@ -170,7 +170,7 @@
*/
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -236,7 +236,7 @@
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index 805c0d2..dc00f12 100644
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -93,7 +93,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
@@ -345,7 +345,7 @@
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&host_drv>;
- vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ vbus_drv-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts
index 75d77e3..0195d97 100644
--- a/arch/arm/boot/dts/rk3288-firefly-beta.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts
@@ -49,7 +49,7 @@
};
&ir {
- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
};
&pinctrl {
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
index d242588..8134966 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
@@ -96,7 +96,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 751bee8..d28c8c3 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -53,7 +53,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -63,14 +63,14 @@
ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
power {
- gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:blue:power";
pinctrl-names = "default";
pinctrl-0 = <&power_led>;
@@ -78,7 +78,7 @@
};
work {
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
@@ -92,7 +92,7 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable>;
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
sound {
@@ -112,7 +112,7 @@
vcc_host_5v: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host_5v";
@@ -133,7 +133,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -146,7 +146,7 @@
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
@@ -159,7 +159,7 @@
dovdd_1v8: dovdd-1v8-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "dovdd_1v8";
@@ -171,7 +171,7 @@
vcc28_dvp: vcc28-dvp-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "vcc28_dvp";
@@ -183,7 +183,7 @@
af_28: af_28-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "af_28";
@@ -195,7 +195,7 @@
dvdd_1v2: af_28-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cif_pwr>;
regulator-name = "dvdd_1v2";
diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts
index c07fe92..14271be 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dts
+++ b/arch/arm/boot/dts/rk3288-firefly.dts
@@ -49,7 +49,7 @@
};
&ir {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
};
&pinctrl {
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 44935af..e4dd758 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -75,7 +75,7 @@
power {
wakeup-source;
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
pinctrl-names = "default";
@@ -87,7 +87,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
@@ -95,7 +95,7 @@
};
power {
- gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";
pinctrl-names = "default";
@@ -114,7 +114,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -145,7 +145,7 @@
vcc_host_5v: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host_5v";
@@ -158,7 +158,7 @@
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
@@ -175,7 +175,7 @@
vcc28_dvp: vcc28-dvp-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_pwr>;
regulator-name = "vcc28_dvp";
@@ -213,7 +213,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 441d450..21326f3 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -68,7 +68,7 @@
compatible = "gpio-leds";
work {
- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_LOW>;
label = "miqi:green:user";
linux,default-trigger = "default-on";
pinctrl-names = "default";
@@ -87,7 +87,7 @@
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -99,7 +99,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -146,7 +146,7 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index bc6d100..e0b5e84 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -180,7 +180,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 RK_PB0 0>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 04faa72..54a0fc0 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -68,7 +68,7 @@
pinctrl-0 = <&pwrbtn>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
@@ -79,7 +79,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -87,7 +87,7 @@
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
@@ -98,7 +98,7 @@
vcc_otg: vcc-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg";
@@ -111,7 +111,7 @@
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
@@ -134,7 +134,7 @@
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index b25ba80..1c0bbc9 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -51,7 +51,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
};
ext_gmac: external-gmac-clock {
@@ -106,7 +106,7 @@
phy-supply = <&vccio_pmu>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &phy_rst>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
rx_delay = <0x10>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index dd3ad2e..6cc83fe 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -53,13 +53,13 @@
compatible = "gpio-leds";
heartbeat {
- gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>;
label = "rock2:green:state1";
linux,default-trigger = "heartbeat";
};
mmc {
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
label = "rock2:blue:state2";
linux,default-trigger = "mmc0";
};
@@ -67,7 +67,7 @@
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -92,13 +92,13 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable>;
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_usb_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
/* Always on as the rockchip usb phy doesn't have a vbus-supply
@@ -110,7 +110,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
index 6d105914..f8c5a47 100644
--- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
@@ -17,8 +17,8 @@
rockchip,model = "VEYRON-I2S";
rockchip,i2s-controller = <&i2s>;
rockchip,audio-codec = <&max98090>;
- rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
- rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
+ rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
rockchip,headset-codec = <&headsetcodec>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts
index cf5311d..ed42552 100644
--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts
@@ -67,7 +67,7 @@
vcc5_host2: vcc5-host2-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_pwr_en>;
regulator-name = "vcc5_host2";
@@ -103,8 +103,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
/delete-property/ vcc6-supply;
@@ -133,7 +133,7 @@
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index ce1f879..9e882f3 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -91,7 +91,7 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
- enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
backlight-boot-off;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
@@ -102,7 +102,7 @@
gpio-charger {
compatible = "gpio-charger";
charger-type = "mains";
- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ac_present_ap>;
};
@@ -142,7 +142,7 @@
vcc5_host1: vcc5-host1-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host1_pwr_en>;
regulator-name = "vcc5_host1";
@@ -154,7 +154,7 @@
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usbotg_pwren_h>;
regulator-name = "vcc5_host2";
@@ -190,7 +190,7 @@
pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
lid {
label = "Lid";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <0>; /* SW_LID */
linux,input-type = <5>; /* EV_SW */
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 3748abf..d33f576 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -57,7 +57,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -68,7 +68,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -80,7 +80,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -134,8 +134,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
regulators {
mic_vcc: LDO_REG2 {
@@ -160,14 +160,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index f6b2eaa..6107f76 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -56,7 +56,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -67,7 +67,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -79,7 +79,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -123,14 +123,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
index f36f6f4..f0994f0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
@@ -182,8 +182,8 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
/delete-property/ vcc6-supply;
/delete-property/ vcc12-supply;
@@ -244,7 +244,7 @@
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&power_hdmi_on>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index f72d616d..53c7205 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -55,7 +55,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -66,7 +66,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -77,7 +77,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -134,14 +134,14 @@
volum_down {
label = "Volum_down";
- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <100>;
};
volum_up {
label = "Volum_up";
- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <100>;
};
@@ -168,7 +168,7 @@
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int &touch_rst>;
- reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
vcc33-supply = <&vcc33_touch>;
vccio-supply = <&vcc33_touch>;
};
@@ -211,14 +211,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index d44351e..995cff4 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -76,7 +76,7 @@
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
power {
- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
};
};
@@ -126,7 +126,7 @@
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_wp_gpio &sdmmc_bus4>;
- wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
};
&tsadc {
diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index fec076e..aef0710 100644
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -115,7 +115,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
- cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
rockchip,default-sample-phase = <90>;
num-slots = <1>;
sd-uhs-sdr12;
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index a0d033f..cc0b78c 100644
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -57,7 +57,7 @@
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
@@ -68,7 +68,7 @@
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
@@ -80,7 +80,7 @@
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
@@ -126,14 +126,14 @@
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 2251d28..e2ecd57 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -61,7 +61,7 @@
pinctrl-0 = <&pwr_key_l>;
power {
label = "Power";
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
wakeup-source;
@@ -70,7 +70,7 @@
gpio-restart {
compatible = "gpio-restart";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ap_warm_reset_h>;
priority = <200>;
@@ -80,7 +80,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
};
sdio_pwrseq: sdio-pwrseq {
@@ -96,7 +96,7 @@
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_5v: vcc-5v {
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] Use macros to describe gpios on rockchip platform
From: Andy Yan @ 2016-10-22 12:51 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Andy Yan
As patch 150696e2e3a4("Add GPIO pin index definition for rockchip pinctrl") has
been applied, now we can use these macros to describe the corresponding gpio
ranther than hard code numbers, this will make the dts easier to read and
write.
Some ideas from Krzysztof's patch on EXYNOS[0].
[0]https://lkml.org/lkml/2016/9/4/71
Andy Yan (2):
ARM: dts: rockchip: use pin constants to describe gpios
ARM64: dts: rockchip: use pin constants to describe gpios
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 10 ++++-----
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++---
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-mk808.dts | 10 ++++-----
arch/arm/boot/dts/rk3066a-rayeager.dts | 12 +++++------
arch/arm/boot/dts/rk3188-px3-evb.dts | 4 ++--
arch/arm/boot/dts/rk3188-radxarock.dts | 16 +++++++--------
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 ++--
arch/arm/boot/dts/rk3288-evb.dtsi | 14 ++++++-------
arch/arm/boot/dts/rk3288-fennec.dts | 4 ++--
arch/arm/boot/dts/rk3288-firefly-beta.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload.dts | 24 +++++++++++-----------
arch/arm/boot/dts/rk3288-firefly.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 16 +++++++--------
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
arch/arm/boot/dts/rk3288-r89.dts | 12 +++++------
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-rock2-square.dts | 12 +++++------
arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 4 ++--
arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 ++++----
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 ++++++-------
arch/arm/boot/dts/rk3288-veyron-jerry.dts | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 16 +++++++--------
arch/arm/boot/dts/rk3288-veyron-pinky.dts | 4 ++--
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron-speedy.dts | 10 ++++-----
arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++----
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 10 ++++-----
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 8 ++++----
.../boot/dts/rockchip/rk3368-orion-r68-meta.dts | 14 ++++++-------
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 4 ++--
arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 16 +++++++--------
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 6 +++---
39 files changed, 160 insertions(+), 160 deletions(-)
--
2.7.4
--
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^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: dts: imx6qdl-apalis: Do not rely on DDC I2C bus bitbang for HDMI
From: Vladimir Zapolskiy @ 2016-10-22 12:43 UTC (permalink / raw)
To: Shawn Guo, Sanchayan Maity
Cc: marcel.ziswiler, stefan, linux-arm-kernel, devicetree,
linux-kernel, Philipp Zabel
In-Reply-To: <20161022032559.GL30578@tiger>
Hi Shawn,
On 10/22/2016 06:25 AM, Shawn Guo wrote:
> On Mon, Sep 19, 2016 at 10:41:51AM +0530, Sanchayan Maity wrote:
>> Remove the use of DDC I2C bus bitbang to support reading of EDID
>> and rely on support from internal HDMI I2C master controller instead.
>> As a result remove the device tree property ddc-i2c-bus.
>>
>> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
>
> I think that the dw-hdmi i2c support [1] is a prerequisite of this
> patch. I do not see it lands on v4.9-rc1. Or am I missing something?
>
> Shawn
>
> [1] https://patchwork.kernel.org/patch/9296883/
>
I'm adding Philipp to Cc, since he is the last one who tested the change
and helped me to push the change to the mainline:
https://lists.freedesktop.org/archives/dri-devel/2016-September/118569.html
The problem is that there is no official DW HDMI bridge maintainer, may be
you can review the change, and if you find it satisfactory push it through
ARM/iMX tree.
--
With best wishes,
Vladimir
^ permalink raw reply
* Re: [PATCH v2] mtd: nand: Add OX820 NAND Support
From: Boris Brezillon @ 2016-10-22 12:36 UTC (permalink / raw)
To: Neil Armstrong
Cc: dwmw2, computersforpeace, richard, devicetree, linux-oxnas,
linux-kernel, daniel, linux-mtd, linux-arm-kernel
In-Reply-To: <20161020084901.6486-1-narmstrong@baylibre.com>
On Thu, 20 Oct 2016 10:49:01 +0200
Neil Armstrong <narmstrong@baylibre.com> wrote:
> Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
> This is a simple memory mapped NAND controller with single chip select and
> software ECC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Applied.
Thanks,
Boris
> ---
> .../devicetree/bindings/mtd/oxnas-nand.txt | 41 +++++
> drivers/mtd/nand/Kconfig | 5 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/oxnas_nand.c | 196 +++++++++++++++++++++
> 4 files changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> create mode 100644 drivers/mtd/nand/oxnas_nand.c
>
> Changes since v1 http://lkml.kernel.org/r/20161019145523.6763-1-narmstrong@baylibre.com :
> - Simplify cmd_ctrl command and drop the ctrl address offset
> - Change oxnas_nand struct name to oxnas_nand_ctrl
> - Update DT-Bindings example to reflect the ctrl->chip->partitions hierarchy
>
> Changes since RFC http://lkml.kernel.org/r/20161018090927.1990-1-narmstrong@baylibre.com :
> - Avoid using chip->IO_ADDR*
> - Use new DT structure
> - Assign a chip for the subnode
> - Use the nand_hw_control structure
> - Cleanup probe
> - Cleanup cmd_ctrl by using a context ctrl offset used in write_bytes
>
> diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> new file mode 100644
> index 0000000..33a77b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
> @@ -0,0 +1,41 @@
> +* Oxford Semiconductor OXNAS NAND Controller
> +
> +Please refer to nand.txt for generic information regarding MTD NAND bindings.
> +
> +Required properties:
> + - compatible: "oxsemi,ox820-nand"
> + - reg: Base address and length for NAND mapped memory.
> +
> +Optional Properties:
> + - clocks: phandle to the NAND gate clock if needed.
> + - resets: phandle to the NAND reset control if needed.
> +
> +Example:
> +
> +nand: nand-controller@41000000 {
> + compatible = "oxsemi,ox820-nand";
> + reg = <0x41000000 0x100000>;
> + clocks = <&stdclk CLK_820_NAND>;
> + resets = <&reset RESET_NAND>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nand@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-mode = "soft";
> + nand-ecc-algo = "hamming";
> +
> + partition@0 {
> + label = "boot";
> + reg = <0x00000000 0x00e00000>;
> + read-only;
> + };
> +
> + partition@e00000 {
> + label = "ubi";
> + reg = <0x00e00000 0x07200000>;
> + };
> + };
> +};
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 7b7a887..c023125 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -426,6 +426,11 @@ config MTD_NAND_ORION
> No board specific support is done by this driver, each board
> must advertise a platform_device for the driver to attach.
>
> +config MTD_NAND_OXNAS
> + tristate "NAND Flash support for Oxford Semiconductor SoC"
> + help
> + This enables the NAND flash controller on Oxford Semiconductor SoCs.
> +
> config MTD_NAND_FSL_ELBC
> tristate "NAND support for Freescale eLBC controllers"
> depends on FSL_SOC
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index cafde6f..05fc054 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
> obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
> obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
> obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
> +obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
> obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
> diff --git a/drivers/mtd/nand/oxnas_nand.c b/drivers/mtd/nand/oxnas_nand.c
> new file mode 100644
> index 0000000..35c94af
> --- /dev/null
> +++ b/drivers/mtd/nand/oxnas_nand.c
> @@ -0,0 +1,196 @@
> +/*
> + * Oxford Semiconductor OXNAS NAND driver
> +
> + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
> + * Heavily based on plat_nand.c :
> + * Author: Vitaly Wool <vitalywool@gmail.com>
> + * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
> + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of.h>
> +
> +/* Nand commands */
> +#define OXNAS_NAND_CMD_ALE BIT(18)
> +#define OXNAS_NAND_CMD_CLE BIT(19)
> +
> +#define OXNAS_NAND_MAX_CHIPS 1
> +
> +struct oxnas_nand_ctrl {
> + struct nand_hw_control base;
> + void __iomem *io_base;
> + struct clk *clk;
> + struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
> +};
> +
> +static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + return readb(oxnas->io_base);
> +}
> +
> +static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + ioread8_rep(oxnas->io_base, buf, len);
> +}
> +
> +static void oxnas_nand_write_buf(struct mtd_info *mtd,
> + const uint8_t *buf, int len)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + iowrite8_rep(oxnas->io_base, buf, len);
> +}
> +
> +/* Single CS command control */
> +static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
> + unsigned int ctrl)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
> +
> + if (ctrl & NAND_CLE)
> + writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
> + else if (ctrl & NAND_ALE)
> + writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
> +}
> +
> +/*
> + * Probe for the NAND device.
> + */
> +static int oxnas_nand_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device_node *nand_np;
> + struct oxnas_nand_ctrl *oxnas;
> + struct nand_chip *chip;
> + struct mtd_info *mtd;
> + struct resource *res;
> + int nchips = 0;
> + int count = 0;
> + int err = 0;
> +
> + /* Allocate memory for the device structure (and zero it) */
> + oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
> + GFP_KERNEL);
> + if (!oxnas)
> + return -ENOMEM;
> +
> + nand_hw_control_init(&oxnas->base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(oxnas->io_base))
> + return PTR_ERR(oxnas->io_base);
> +
> + oxnas->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(oxnas->clk))
> + oxnas->clk = NULL;
> +
> + /* Only a single chip node is supported */
> + count = of_get_child_count(np);
> + if (count > 1)
> + return -EINVAL;
> +
> + clk_prepare_enable(oxnas->clk);
> + device_reset_optional(&pdev->dev);
> +
> + for_each_child_of_node(np, nand_np) {
> + chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
> + GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + chip->controller = &oxnas->base;
> +
> + nand_set_flash_node(chip, nand_np);
> + nand_set_controller_data(chip, oxnas);
> +
> + mtd = nand_to_mtd(chip);
> + mtd->dev.parent = &pdev->dev;
> + mtd->priv = chip;
> +
> + chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
> + chip->read_buf = oxnas_nand_read_buf;
> + chip->read_byte = oxnas_nand_read_byte;
> + chip->write_buf = oxnas_nand_write_buf;
> + chip->chip_delay = 30;
> +
> + /* Scan to find existence of the device */
> + err = nand_scan(mtd, 1);
> + if (err)
> + return err;
> +
> + err = mtd_device_register(mtd, NULL, 0);
> + if (err) {
> + nand_release(mtd);
> + return err;
> + }
> +
> + oxnas->chips[nchips] = chip;
> + ++nchips;
> + }
> +
> + /* Exit if no chips found */
> + if (!nchips)
> + return -ENODEV;
> +
> + platform_set_drvdata(pdev, oxnas);
> +
> + return 0;
> +}
> +
> +static int oxnas_nand_remove(struct platform_device *pdev)
> +{
> + struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
> +
> + if (oxnas->chips[0])
> + nand_release(nand_to_mtd(oxnas->chips[0]));
> +
> + clk_disable_unprepare(oxnas->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id oxnas_nand_match[] = {
> + { .compatible = "oxsemi,ox820-nand" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, oxnas_nand_match);
> +
> +static struct platform_driver oxnas_nand_driver = {
> + .probe = oxnas_nand_probe,
> + .remove = oxnas_nand_remove,
> + .driver = {
> + .name = "oxnas_nand",
> + .of_match_table = oxnas_nand_match,
> + },
> +};
> +
> +module_platform_driver(oxnas_nand_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> +MODULE_DESCRIPTION("Oxnas NAND driver");
> +MODULE_ALIAS("platform:oxnas_nand");
^ permalink raw reply
* Re: [PATCH v3 1/3] mtd: s3c2410: make ecc mode configurable via platform data
From: Boris Brezillon @ 2016-10-22 12:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sergio Prado, kgene, javier, linux, linux, richard, dwmw2,
computersforpeace, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-mtd, robh+dt, mark.rutland, devicetree
In-Reply-To: <20161021182710.GA17279@kozik-lap>
Hi Krzysztof,
On Fri, 21 Oct 2016 21:27:10 +0300
Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Thu, Oct 20, 2016 at 07:42:44PM -0200, Sergio Prado wrote:
> > Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
> > field in the drivers's platform data structure so it can be selectable
> > via platform data.
> >
> > Also setting this field to NAND_ECC_SOFT in all boards using this
> > driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
> >
> > Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> > ---
> > arch/arm/mach-s3c24xx/common-smdk.c | 1 +
> > arch/arm/mach-s3c24xx/mach-anubis.c | 1 +
> > arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 +
> > arch/arm/mach-s3c24xx/mach-bast.c | 1 +
> > arch/arm/mach-s3c24xx/mach-gta02.c | 1 +
> > arch/arm/mach-s3c24xx/mach-jive.c | 1 +
> > arch/arm/mach-s3c24xx/mach-mini2440.c | 1 +
> > arch/arm/mach-s3c24xx/mach-osiris.c | 1 +
> > arch/arm/mach-s3c24xx/mach-qt2410.c | 1 +
> > arch/arm/mach-s3c24xx/mach-rx1950.c | 1 +
> > arch/arm/mach-s3c24xx/mach-rx3715.c | 1 +
> > arch/arm/mach-s3c24xx/mach-vstms.c | 1 +
> > arch/arm/mach-s3c64xx/mach-hmt.c | 1 +
> > arch/arm/mach-s3c64xx/mach-mini6410.c | 1 +
> > arch/arm/mach-s3c64xx/mach-real6410.c | 1 +
> > drivers/mtd/nand/Kconfig | 9 --
> > drivers/mtd/nand/s3c2410.c | 119 +++++++++++++------------
> > include/linux/platform_data/mtd-nand-s3c2410.h | 6 +-
> > 18 files changed, 79 insertions(+), 70 deletions(-)
> >
>
> I acked this twice (v1 and v2)... and still you are ignoring them. I am
> sorry, I am not gonna to ack this third time!
>
> For v2 I acked also other patches but it it is not there as well...
I'll collect your acks (and Rob ones) when applying the patches. BTW,
how should I proceed with patch 1? Do you want an topic branch
containing this patch?
Regards,
Boris
^ permalink raw reply
* [PATCH v5 7/7] ARM: dts: sun8i-h3: Add HDMI audio and video to the Orange PI 2
From: Jean-Francois Moine @ 2016-10-22 11:06 UTC (permalink / raw)
To: Dave Airlie, Liam Girdwood, Mark Brown, Maxime Ripard,
Rob Herring
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <cover.1477142934.git.moinejf-GANU6spQydw@public.gmane.org>
Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
---
The same patch may be applied to other H3 based boards (Orange PI xx).
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index e5bcaba..799ceb9 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -56,6 +56,7 @@
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet1 = &rtl8189;
+ lcd0 = &lcd0;
};
chosen {
@@ -105,16 +106,32 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&lcd0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.10.1
^ permalink raw reply related
* Re: [PATCH v3 3/6] pwm: imx: support output polarity inversion
From: Boris Brezillon @ 2016-10-22 10:33 UTC (permalink / raw)
To: Bhuvanchandra DV
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w, mark.rutland-5wv7dgnIgG8,
linux-pwm-u79uwXL29TY76Z2rM5mHXA,
l.majewski-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, stefan-XLVq0VzYD2Y,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Lothar Wassmann
In-Reply-To: <20161007151129.6043-4-bhuvanchandra.dv-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
On Fri, 7 Oct 2016 20:41:26 +0530
Bhuvanchandra DV <bhuvanchandra.dv-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org> wrote:
> From: Lothar Wassmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
>
> The i.MX pwm unit on i.MX27 and newer SoCs provides a configurable output
> polarity. This patch adds support to utilize this feature where available.
>
> Signed-off-by: Lothar Waßmann <LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org>
> Signed-off-by: Lukasz Majewski <l.majewski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Reviewed-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> Documentation/devicetree/bindings/pwm/imx-pwm.txt | 6 +--
> drivers/pwm/pwm-imx.c | 51 +++++++++++++++++++++--
> 2 files changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> index e00c2e9..c61bdf8 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> @@ -6,8 +6,8 @@ Required properties:
> - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
> - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
> - reg: physical base address and length of the controller's registers
> -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
> - the cells format.
> +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt
> + in this directory for a description of the cells format.
> - clocks : Clock specifiers for both ipg and per clocks.
> - clock-names : Clock names should include both "ipg" and "per"
> See the clock consumer binding,
> @@ -17,7 +17,7 @@ See the clock consumer binding,
> Example:
>
> pwm1: pwm@53fb4000 {
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> reg = <0x53fb4000 0x4000>;
> clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index d600fd5..c37d223 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -38,6 +38,7 @@
> #define MX3_PWMCR_DOZEEN (1 << 24)
> #define MX3_PWMCR_WAITEN (1 << 23)
> #define MX3_PWMCR_DBGEN (1 << 22)
> +#define MX3_PWMCR_POUTC (1 << 18)
> #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> #define MX3_PWMCR_SWR (1 << 3)
> @@ -180,6 +181,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
> if (enable)
> cr |= MX3_PWMCR_EN;
>
> + if (pwm->args.polarity == PWM_POLARITY_INVERSED)
> + cr |= MX3_PWMCR_POUTC;
> +
> writel(cr, imx->mmio_base + MX3_PWMCR);
>
> return 0;
> @@ -240,27 +244,62 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> clk_disable_unprepare(imx->clk_per);
> }
>
> -static struct pwm_ops imx_pwm_ops = {
> +static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> + enum pwm_polarity polarity)
> +{
> + struct imx_chip *imx = to_imx_chip(chip);
> + u32 val;
> +
> + if (polarity == pwm->args.polarity)
> + return 0;
> +
> + val = readl(imx->mmio_base + MX3_PWMCR);
> +
> + if (polarity == PWM_POLARITY_INVERSED)
> + val |= MX3_PWMCR_POUTC;
> + else
> + val &= ~MX3_PWMCR_POUTC;
> +
> + writel(val, imx->mmio_base + MX3_PWMCR);
> +
> + dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
> + polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
> +
> + return 0;
> +}
I'll read the discussion Lukasz and Stefan had before reviewing this
part ;-).
> +
> +static struct pwm_ops imx_pwm_ops_v1 = {
> .enable = imx_pwm_enable,
> .disable = imx_pwm_disable,
> .config = imx_pwm_config,
> .owner = THIS_MODULE,
> };
>
> +static struct pwm_ops imx_pwm_ops_v2 = {
> + .enable = imx_pwm_enable,
> + .disable = imx_pwm_disable,
> + .set_polarity = imx_pwm_set_polarity,
> + .config = imx_pwm_config,
> + .owner = THIS_MODULE,
> +};
> +
> struct imx_pwm_data {
> int (*config)(struct pwm_chip *chip,
> struct pwm_device *pwm, int duty_ns, int period_ns);
> void (*set_enable)(struct pwm_chip *chip, bool enable);
> + struct pwm_ops *pwm_ops;
Probably better to make that consistent: drop the ->config() and
->set_enable() hooks, and make both v1 and v2 define their own pwm_ops.
If you have common logic that is shared between v1 and v2, you can just
create helper functions implementing this common logic and call them
from your version-specific implementation.
> };
>
> static struct imx_pwm_data imx_pwm_data_v1 = {
> .config = imx_pwm_config_v1,
> .set_enable = imx_pwm_set_enable_v1,
> + .pwm_ops = &imx_pwm_ops_v1,
> };
>
> static struct imx_pwm_data imx_pwm_data_v2 = {
> .config = imx_pwm_config_v2,
> .set_enable = imx_pwm_set_enable_v2,
> + .pwm_ops = &imx_pwm_ops_v2,
> };
>
> static const struct of_device_id imx_pwm_dt_ids[] = {
> @@ -282,6 +321,8 @@ static int imx_pwm_probe(struct platform_device *pdev)
> if (!of_id)
> return -ENODEV;
>
> + data = of_id->data;
> +
> imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
> if (imx == NULL)
> return -ENOMEM;
> @@ -300,18 +341,22 @@ static int imx_pwm_probe(struct platform_device *pdev)
> return PTR_ERR(imx->clk_ipg);
> }
>
> - imx->chip.ops = &imx_pwm_ops;
> + imx->chip.ops = data->pwm_ops;
> imx->chip.dev = &pdev->dev;
> imx->chip.base = -1;
> imx->chip.npwm = 1;
> imx->chip.can_sleep = true;
> + if (data->pwm_ops->set_polarity) {
> + dev_dbg(&pdev->dev, "PWM supports output inversion\n");
> + imx->chip.of_xlate = of_pwm_xlate_with_flags;
> + imx->chip.of_pwm_n_cells = 3;
> + }
Not that I really care, but you are breaking the DT ABI here. One
solution to avoid that would be to retrieve #pwm-cells here and
decide which ->of_xlate should be used based on this information.
>
> r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
> if (IS_ERR(imx->mmio_base))
> return PTR_ERR(imx->mmio_base);
>
> - data = of_id->data;
> imx->config = data->config;
> imx->set_enable = data->set_enable;
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v5 6/7] ARM: dts: sun8i-h3: Add HDMI audio and video to the Banana Pi M2+
From: Jean-Francois Moine @ 2016-10-22 10:29 UTC (permalink / raw)
To: Dave Airlie, Liam Girdwood, Mark Brown, Maxime Ripard,
Rob Herring
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <cover.1477142934.git.moinejf-GANU6spQydw@public.gmane.org>
Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
---
The patch for the Banana Pi M3 (A83T) is the same as this one.
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 06fddaa..2e81de8 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
serial1 = &uart1;
+ lcd0 = &lcd0;
};
chosen {
@@ -93,6 +94,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -101,12 +106,24 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&lcd0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.10.1
^ permalink raw reply related
* Re: [PATCH v2 11/14] MIPS: Malta: Use syscon-reboot driver to reboot
From: Maciej W. Rozycki @ 2016-10-22 9:08 UTC (permalink / raw)
To: Paul Burton
Cc: linux-mips, Ralf Baechle, devicetree, Stephan Linz,
Jacek Anaszewski, Bartlomiej Zolnierkiewicz, linux-kernel,
Rob Herring, Mark Rutland
In-Reply-To: <20160919212132.28893-12-paul.burton@imgtec.com>
[-- Attachment #1: Type: text/plain, Size: 540 bytes --]
On Mon, 19 Sep 2016, Paul Burton wrote:
> Make use of the generic syscon-reboot driver to reboot the Malta board,
> reducing the amount of platform code it requires.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
This has broken reboot support, all I get now is:
reboot: Restarting system
Unable to restart system
Reboot failed -- System halted
at which point I need to issue a serial BREAK to regain control of the
board and get back to YAMON; fortunately the board is wired for that.
See attached config.
Maciej
[-- Attachment #2: Type: text/plain, Size: 50815 bytes --]
CONFIG_MIPS=y
CONFIG_MIPS_MALTA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_BOOT_RAW=y
CONFIG_CEVT_R4K=y
CONFIG_CSRC_R4K=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_DMA_MAYBE_COHERENT=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_MIPS_BONITO64=y
CONFIG_MIPS_MSC=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_ISA_DMA_API=y
CONFIG_SYS_SUPPORTS_RELOCATABLE=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_PCI_GT64XXX_PCI0=y
CONFIG_MIPS_SPRAM=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_MIPS_L1_CACHE_SHIFT_6=y
CONFIG_MIPS_L1_CACHE_SHIFT=6
CONFIG_CPU_MIPS32_R2=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
CONFIG_SYS_HAS_CPU_MIPS32_R5=y
CONFIG_SYS_HAS_CPU_MIPS32_R6=y
CONFIG_SYS_HAS_CPU_MIPS64_R1=y
CONFIG_SYS_HAS_CPU_MIPS64_R2=y
CONFIG_SYS_HAS_CPU_MIPS64_R6=y
CONFIG_SYS_HAS_CPU_NEVADA=y
CONFIG_SYS_HAS_CPU_RM7000=y
CONFIG_MIPS_MALTA_PM=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPSR2=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_32BIT=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_BOARD_SCACHE=y
CONFIG_MIPS_CPU_SCACHE=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_MIPS_CM=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_MIPS_ASID_SHIFT=0
CONFIG_MIPS_ASID_BITS=8
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_SYS_SUPPORTS_HIGHMEM=y
CONFIG_SYS_SUPPORTS_SMARTMIPS=y
CONFIG_SYS_SUPPORTS_MICROMIPS=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_NEED_PER_CPU_KM=y
CONFIG_SYS_SUPPORTS_MIPS_CMP=y
CONFIG_SYS_SUPPORTS_MIPS_CPS=y
CONFIG_HZ_100=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_CRASH_DUMP=y
CONFIG_PHYSICAL_START=0x84000000
CONFIG_SECCOMP=y
CONFIG_USE_OF=y
CONFIG_BUILTIN_DTB=y
CONFIG_MIPS_NO_APPENDED_DTB=y
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE="mips-linux-gnu-"
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_PREEMPT_RCU=y
CONFIG_SRCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_NMI_LOG_BUF_SHIFT=10
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_BPF_SYSCALL=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_USERFAULTFD=y
CONFIG_PCI_QUIRKS=y
CONFIG_MEMBARRIER=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PERF_EVENTS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_HAVE_OPROFILE=y
CONFIG_UPROBES=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_CC_STACKPROTECTOR_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_LBDAF=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_ASN1=m
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y
CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_MMU=y
CONFIG_I8253=y
CONFIG_ZONE_DMA=y
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
CONFIG_TRAD_SIGNALS=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_MIPS_EXTERNAL_TIMER=y
CONFIG_NET=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=m
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_UDP_TUNNEL=m
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_COMMON=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_GRE=m
CONFIG_NF_CT_PROTO_SCTP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_NEEDED=y
CONFIG_NF_NAT_PROTO_DCCP=m
CONFIG_NF_NAT_PROTO_UDPLITE=m
CONFIG_NF_NAT_PROTO_SCTP=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=m
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NETFILTER_XTABLES=m
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
CONFIG_IP_VS_TAB_BITS=12
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
CONFIG_IP_VS_SH_TAB_BITS=8
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_CONNTRACK_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_IPV4=m
CONFIG_NF_NAT_MASQUERADE_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PROTO_GRE=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_CONNTRACK_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_NF_NAT_IPV6=m
CONFIG_NF_NAT_MASQUERADE_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m
CONFIG_IP_DCCP_CCID3=y
CONFIG_IP_DCCP_TFRC_LIB=y
CONFIG_IP_SCTP=m
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_L2TP=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_HAVE_NET_DSA=y
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_DECNET=m
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_IPX=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_PHONET=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_CLS_IND=y
CONFIG_NET_SCH_FIFO=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_AF_RXRPC=m
CONFIG_AF_KCM=m
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL_HT=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_NET_9P=m
CONFIG_CEPH_LIB=m
CONFIG_LWTUNNEL=y
CONFIG_DST_CACHE=y
CONFIG_MAY_USE_DEVLINK=y
CONFIG_HAVE_CBPF_JIT=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=m
CONFIG_REGMAP_MMIO=y
CONFIG_CONNECTOR=m
CONFIG_MTD=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_OOPS=m
CONFIG_MTD_PARTITIONED_MASTER=y
CONFIG_MTD_CFI=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=m
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_OF_MTD=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
CONFIG_PARPORT_SERIAL=m
CONFIG_PARPORT_AX88796=m
CONFIG_PARPORT_NOT_PC=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_FD=m
CONFIG_PARIDE=m
CONFIG_PARIDE_PD=m
CONFIG_PARIDE_PCD=m
CONFIG_PARIDE_PF=m
CONFIG_PARIDE_PT=m
CONFIG_PARIDE_PG=m
CONFIG_PARIDE_ATEN=m
CONFIG_PARIDE_BPCK=m
CONFIG_PARIDE_BPCK6=m
CONFIG_PARIDE_COMM=m
CONFIG_PARIDE_DSTR=m
CONFIG_PARIDE_FIT2=m
CONFIG_PARIDE_FIT3=m
CONFIG_PARIDE_EPAT=m
CONFIG_PARIDE_EPIA=m
CONFIG_PARIDE_FRIQ=m
CONFIG_PARIDE_FRPW=m
CONFIG_PARIDE_KBIC=m
CONFIG_PARIDE_KTTI=m
CONFIG_PARIDE_ON20=m
CONFIG_PARIDE_ON26=m
CONFIG_BLK_CPQ_CISS_DA=m
CONFIG_BLK_DEV_DAC960=m
CONFIG_BLK_DEV_UMEM=m
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_DRBD=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_SX8=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
CONFIG_ATA_OVER_ETH=m
CONFIG_BLK_DEV_RBD=m
CONFIG_PHANTOM=m
CONFIG_SGI_IOC4=m
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
CONFIG_ENCLOSURE_SERVICES=m
CONFIG_HP_ILO=m
CONFIG_C2PORT=m
CONFIG_EEPROM_93CX6=m
CONFIG_CB710_CORE=m
CONFIG_CB710_DEBUG_ASSUMPTIONS=y
CONFIG_HAVE_IDE=y
CONFIG_IDE=y
CONFIG_IDE_XFER_MODE=y
CONFIG_IDE_ATAPI=y
CONFIG_IDE_GD=y
CONFIG_IDE_GD_ATA=y
CONFIG_BLK_DEV_IDECD=y
CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
CONFIG_IDE_PROC_FS=y
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_IDEDMA_SFF=y
CONFIG_BLK_DEV_IDEPCI=y
CONFIG_IDEPCI_PCIBUS_ORDER=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_IDEDMA_PCI=y
CONFIG_BLK_DEV_PIIX=y
CONFIG_BLK_DEV_IT8213=m
CONFIG_BLK_DEV_TC86C001=m
CONFIG_BLK_DEV_IDEDMA=y
CONFIG_SCSI_MOD=m
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=m
CONFIG_SCSI_DMA=y
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m
CONFIG_CHR_DEV_OSST=m
CONFIG_BLK_DEV_SR=m
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=m
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_ATTRS=m
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_BLK_DEV_3W_XXXX_RAID=m
CONFIG_SCSI_3W_9XXX=m
CONFIG_SCSI_ACARD=m
CONFIG_SCSI_AACRAID=m
CONFIG_SCSI_AIC7XXX=m
CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
CONFIG_AIC7XXX_DEBUG_MASK=0
CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
CONFIG_SCSI_OSD_INITIATOR=m
CONFIG_SCSI_OSD_ULD=m
CONFIG_SCSI_OSD_DPRINT_SENSE=1
CONFIG_ATA=m
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_SATA_PMP=y
CONFIG_SATA_AHCI=m
CONFIG_SATA_AHCI_PLATFORM=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y
CONFIG_ATA_PIIX=m
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m
CONFIG_PATA_ALI=m
CONFIG_PATA_AMD=m
CONFIG_PATA_ARTOP=m
CONFIG_PATA_ATIIXP=m
CONFIG_PATA_ATP867X=m
CONFIG_PATA_CMD64X=m
CONFIG_PATA_CS5536=m
CONFIG_PATA_CYPRESS=m
CONFIG_PATA_EFAR=m
CONFIG_PATA_HPT366=m
CONFIG_PATA_HPT37X=m
CONFIG_PATA_HPT3X2N=m
CONFIG_PATA_HPT3X3=m
CONFIG_PATA_IT8213=m
CONFIG_PATA_IT821X=m
CONFIG_PATA_JMICRON=m
CONFIG_PATA_MARVELL=m
CONFIG_PATA_NETCELL=m
CONFIG_PATA_NINJA32=m
CONFIG_PATA_NS87415=m
CONFIG_PATA_OLDPIIX=m
CONFIG_PATA_OPTIDMA=m
CONFIG_PATA_PDC2027X=m
CONFIG_PATA_PDC_OLD=m
CONFIG_PATA_RADISYS=m
CONFIG_PATA_RDC=m
CONFIG_PATA_SCH=m
CONFIG_PATA_SERVERWORKS=m
CONFIG_PATA_SIL680=m
CONFIG_PATA_SIS=m
CONFIG_PATA_TOSHIBA=m
CONFIG_PATA_TRIFLEX=m
CONFIG_PATA_VIA=m
CONFIG_PATA_WINBOND=m
CONFIG_PATA_CMD640_PCI=m
CONFIG_PATA_MPIIX=m
CONFIG_PATA_NS87410=m
CONFIG_PATA_OPTI=m
CONFIG_PATA_PLATFORM=m
CONFIG_PATA_RZ1000=m
CONFIG_ATA_GENERIC=m
CONFIG_PATA_LEGACY=m
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
CONFIG_DM_MQ_DEFAULT=y
CONFIG_DM_BUFIO=m
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
CONFIG_TCM_USER2=m
CONFIG_LOOPBACK_TARGET=m
CONFIG_ISCSI_TARGET=m
CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_EQUALIZER=m
CONFIG_IFB=m
CONFIG_MACVLAN=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_VETH=m
CONFIG_SUNGEM_PHY=m
CONFIG_ATM_DRIVERS=y
CONFIG_ETHERNET=y
CONFIG_MDIO=m
CONFIG_NET_VENDOR_ADAPTEC=y
CONFIG_ADAPTEC_STARFIRE=m
CONFIG_NET_VENDOR_AGERE=y
CONFIG_NET_VENDOR_ALTEON=y
CONFIG_ACENIC=m
CONFIG_NET_VENDOR_AMD=y
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=m
CONFIG_ATL1=m
CONFIG_ATL1E=m
CONFIG_ATL1C=m
CONFIG_NET_VENDOR_AURORA=y
CONFIG_AURORA_NB8800=m
CONFIG_NET_CADENCE=y
CONFIG_MACB=m
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
CONFIG_BNX2X=m
CONFIG_BNXT=m
CONFIG_NET_VENDOR_BROCADE=y
CONFIG_BNA=m
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CHELSIO=y
CONFIG_CHELSIO_T1=m
CONFIG_CHELSIO_T3=m
CONFIG_CHELSIO_T4=m
CONFIG_CHELSIO_T4VF=m
CONFIG_NET_VENDOR_CISCO=y
CONFIG_ENIC=m
CONFIG_DM9000=m
CONFIG_DNET=m
CONFIG_NET_VENDOR_DEC=y
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=m
CONFIG_SUNDANCE=m
CONFIG_NET_VENDOR_EMULEX=y
CONFIG_BE2NET=m
CONFIG_BE2NET_HWMON=y
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_NET_VENDOR_EXAR=y
CONFIG_S2IO=m
CONFIG_VXGE=m
CONFIG_NET_VENDOR_HP=y
CONFIG_HP100=m
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
CONFIG_IXGB=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_NET_VENDOR_I825XX=y
CONFIG_JME=m
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_SKGE=m
CONFIG_SKY2=m
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_NET_VENDOR_MICREL=y
CONFIG_KS8851_MLL=m
CONFIG_KSZ884X_PCI=m
CONFIG_NET_VENDOR_MYRI=y
CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_NET_VENDOR_NETRONOME=y
CONFIG_NET_VENDOR_8390=y
CONFIG_AX88796=m
CONFIG_NE2K_PCI=m
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=m
CONFIG_NET_VENDOR_OKI=y
CONFIG_ETHOC=m
CONFIG_NET_VENDOR_QLOGIC=y
CONFIG_QLA3XXX=m
CONFIG_QLCNIC=m
CONFIG_QLCNIC_HWMON=y
CONFIG_QLGE=m
CONFIG_NETXEN_NIC=m
CONFIG_QED=m
CONFIG_QEDE=m
CONFIG_NET_VENDOR_QUALCOMM=y
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_8139CP=m
CONFIG_8139TOO=m
CONFIG_8139TOO_PIO=y
CONFIG_R8169=m
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_RDC=y
CONFIG_R6040=m
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=m
CONFIG_NET_VENDOR_SIS=y
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_SFC=m
CONFIG_SFC_MTD=y
CONFIG_SFC_MCDI_MON=y
CONFIG_SFC_MCDI_LOGGING=y
CONFIG_NET_VENDOR_SMSC=y
CONFIG_EPIC100=m
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=m
CONFIG_STMMAC_PLATFORM=m
CONFIG_DWMAC_GENERIC=m
CONFIG_NET_VENDOR_SUN=y
CONFIG_HAPPYMEAL=m
CONFIG_SUNGEM=m
CONFIG_CASSINI=m
CONFIG_NIU=m
CONFIG_NET_VENDOR_SYNOPSYS=y
CONFIG_SYNOPSYS_DWC_ETH_QOS=m
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=m
CONFIG_NET_VENDOR_TI=y
CONFIG_TLAN=m
CONFIG_NET_VENDOR_TOSHIBA=y
CONFIG_TC35815=m
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=m
CONFIG_VIA_VELOCITY=m
CONFIG_NET_VENDOR_WIZNET=y
CONFIG_PHYLIB=m
CONFIG_SWPHY=y
CONFIG_AQUANTIA_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_DAVICOM_PHY=m
CONFIG_QSEMI_PHY=m
CONFIG_LXT_PHY=m
CONFIG_CICADA_PHY=m
CONFIG_VITESSE_PHY=m
CONFIG_TERANETICS_PHY=m
CONFIG_SMSC_PHY=m
CONFIG_BCM_NET_PHYLIB=m
CONFIG_BROADCOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_REALTEK_PHY=m
CONFIG_NATIONAL_PHY=m
CONFIG_STE10XP=m
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MICREL_PHY=m
CONFIG_DP83848_PHY=m
CONFIG_DP83867_PHY=m
CONFIG_MICROCHIP_PHY=m
CONFIG_FIXED_PHY=m
CONFIG_MDIO_BITBANG=m
CONFIG_INTEL_XWAY_PHY=m
CONFIG_PLIP=m
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_MPPE=m
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH5K=m
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_HTC=m
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_USB=m
CONFIG_AR5523=m
CONFIG_WIL6210=m
CONFIG_WIL6210_ISR_COR=y
CONFIG_ATH10K=m
CONFIG_ATH10K_PCI=m
CONFIG_WCN36XX=m
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=m
CONFIG_PCI_ATMEL=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
CONFIG_BRCMUTIL=m
CONFIG_BRCMSMAC=m
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_AIRO=m
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
CONFIG_IPW2100_MONITOR=y
CONFIG_IPW2200=m
CONFIG_IPW2200_MONITOR=y
CONFIG_IPW2200_RADIOTAP=y
CONFIG_IPW2200_PROMISCUOUS=y
CONFIG_IPW2200_QOS=y
CONFIG_LIBIPW=m
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m
CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y
CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_P54_COMMON=m
CONFIG_P54_PCI=m
CONFIG_P54_LEDS=y
CONFIG_PRISM54=m
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_THINFIRM=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8XXXU=m
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_MAC80211_HWSIM=m
CONFIG_VMXNET3=m
CONFIG_NVM=y
CONFIG_NVM_GENNVM=m
CONFIG_NVM_RRPC=m
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_POLLDEV=m
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_GTCO=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_PCSPKR=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_MPU3050=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_UINPUT=m
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_RMI4_CORE=m
CONFIG_RMI4_I2C=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_DEVMEM=y
CONFIG_DEVKMEM=y
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_PRINTER=m
CONFIG_PPDEV=m
CONFIG_HW_RANDOM=m
CONFIG_DEVPORT=y
CONFIG_I2C=m
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX=m
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_ALI1535=m
CONFIG_I2C_ALI1563=m
CONFIG_I2C_ALI15X3=m
CONFIG_I2C_AMD756=m
CONFIG_I2C_AMD8111=m
CONFIG_I2C_I801=m
CONFIG_I2C_ISCH=m
CONFIG_I2C_PIIX4=m
CONFIG_I2C_NFORCE2=m
CONFIG_I2C_SIS5595=m
CONFIG_I2C_SIS630=m
CONFIG_I2C_SIS96X=m
CONFIG_I2C_VIA=m
CONFIG_I2C_VIAPRO=m
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_PCI=m
CONFIG_I2C_OCORES=m
CONFIG_I2C_PCA_PLATFORM=m
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_XILINX=m
CONFIG_I2C_DIOLAN_U2C=m
CONFIG_I2C_PARPORT=m
CONFIG_I2C_PARPORT_LIGHT=m
CONFIG_I2C_TAOS_EVM=m
CONFIG_I2C_TINY_USB=m
CONFIG_I2C_STUB=m
CONFIG_PPS=m
CONFIG_PTP_1588_CLOCK=m
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_OF_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=m
CONFIG_GPIO_GENERIC_PLATFORM=m
CONFIG_W1=m
CONFIG_W1_CON=y
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2760=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_BQ27000=m
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_HWMON=m
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_MFD_CORE=m
CONFIG_LPC_SCH=m
CONFIG_MFD_SYSCON=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_FB=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CIRRUS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_GENERIC=m
CONFIG_BACKLIGHT_PM8941_WLED=m
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_HID=m
CONFIG_HID_GENERIC=m
CONFIG_USB_HID=m
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=m
CONFIG_USB_DEFAULT_PERSIST=y
CONFIG_USB_MON=m
CONFIG_USB_WUSB=m
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PLATFORM=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=m
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_ISP1362_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_WHCI_HCD=m
CONFIG_USB_HWA_HCD=m
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=m
CONFIG_USB_DWC3=m
CONFIG_USB_DWC3_DUAL_ROLE=y
CONFIG_USB_DWC3_PCI=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_XIRCOM=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_RIO500=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_ATM=m
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_UWB=m
CONFIG_UWB_HWA=m
CONFIG_UWB_WHCI=m
CONFIG_MMC=m
CONFIG_PWRSEQ_EMMC=m
CONFIG_PWRSEQ_SIMPLE=m
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=m
CONFIG_MMC_TEST=m
CONFIG_MMC_SDHCI=m
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_SDHCI_PLTFM=m
CONFIG_MMC_WBSD=m
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MEMSTICK=m
CONFIG_MSPRO_BLOCK=m
CONFIG_MEMSTICK_TIFM_MS=m
CONFIG_MEMSTICK_JMICRON_38X=m
CONFIG_MEMSTICK_R592=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_I2C_AND_SPI=m
CONFIG_RTC_DRV_CMOS=y
CONFIG_UIO=m
CONFIG_UIO_CIF=m
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
CONFIG_UIO_NETX=m
CONFIG_VIRTIO=m
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
CONFIG_MIPS_PLATFORM_DEVICES=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_PROBE=y
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
CONFIG_CLKSRC_MIPS_GIC=y
CONFIG_IOMMU_SUPPORT=y
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_I8259=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_MIPS_GIC=y
CONFIG_RESET_CONTROLLER=y
CONFIG_GENERIC_PHY=y
CONFIG_RAS=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_JBD2=y
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
CONFIG_XFS_FS=m
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_NILFS2_FS=m
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=m
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_QUOTA=y
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_QUOTA_TREE=y
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=m
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_FSCACHE=m
CONFIG_CACHEFILES=m
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
CONFIG_JFFS2_CMODE_PRIORITY=y
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_FILE_CACHE=y
CONFIG_SQUASHFS_DECOMP_SINGLE=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_MINIX_FS_NATIVE_ENDIAN=y
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFSD=y
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_CEPH_FS=m
CONFIG_CIFS=m
CONFIG_CIFS_DEBUG=y
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
CONFIG_9P_FS=m
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_DLM=m
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_WORK=y
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_SCHED_DEBUG=y
CONFIG_DEBUG_PREEMPT=y
CONFIG_STACKTRACE=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_BRANCH_PROFILE_NONE=y
CONFIG_UPROBE_EVENT=y
CONFIG_BPF_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KEYS=y
CONFIG_ENCRYPTED_KEYS=m
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=m
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=m
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_RSA=m
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_POLY1305=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_DRBG_MENU=m
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_JITTERENTROPY=m
CONFIG_CRYPTO_HW=y
CONFIG_BINARY_PRINTF=y
CONFIG_RAID6_PQ=m
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_CRC8=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_DQL=y
CONFIG_GLOB=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_CORDIC=m
CONFIG_MPILIB=m
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_FONT_SUPPORT=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_HAVE_KVM=y
^ permalink raw reply
* [PATCH] i2c: rk3x: Give the tuning value 0 during rk3x_i2c_v0_calc_timings
From: David Wu @ 2016-10-22 8:43 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, wsa-z923LK4zBo2bacvFa/9K2g
Cc: dianders-F7+t8E8rja9g9hUCZPvPmw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, David Wu
We found a bug that i2c transfer sometimes failed on 3066a board with
stabel-4.8, the con register would be updated by uninitialized tuning
value, it made the i2c transfer failed.
So give the tuning value to be zero during rk3x_i2c_v0_calc_timings.
Signed-off-by: David Wu <david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/i2c/busses/i2c-rk3x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 50702c7..df22066 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -694,6 +694,8 @@ static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
t_calc->div_low--;
t_calc->div_high--;
+ /* Give the tuning value 0, that would not update con register */
+ t_calc->tuning = 0;
/* Maximum divider supported by hw is 0xffff */
if (t_calc->div_low > 0xffff) {
t_calc->div_low = 0xffff;
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH] ARM: dts: rockchip: add i2c-bus subnode to edp
From: ayaka @ 2016-10-22 3:52 UTC (permalink / raw)
To: Heiko Stuebner, Tomeu Vizoso
Cc: Mark Rutland, devicetree, Russell King, linux-kernel,
linux-rockchip, Rob Herring, Jon Hunter, linux-arm-kernel
In-Reply-To: <1681294.eoXpQL8f8l@phil>
On 10/21/2016 04:25 PM, Heiko Stuebner wrote:
> Am Donnerstag, 20. Oktober 2016, 15:47:56 CEST schrieb Tomeu Vizoso:
>> On 10/20/2016 03:45 PM, Heiko Stübner wrote:
>>> Am Donnerstag, 20. Oktober 2016, 10:07:25 schrieb Tomeu Vizoso:
>>>> Add an empty 'i2c-bus' subnode to the edp node just so that the I2C core
>>>> doesn't attemp to parse the 'ports' subnode as containing i2c devices.
>>>>
>>>> This is to avoid spurious failure messages such as:
>>>>
>>>> i2c i2c-6: of_i2c: modalias failure on /dp@ff970000/ports
>>> On the one hand, the edp really has an i2c bus - with its only client the
>>> EDID listening at 0x50 (and maybe 0x30).
>>>
>>> On the other hand, adding an empty bus to the (implementation independent)
>>> devicetree just to make the Linux i2c subsystem happy sounds heavily like
>>> a
>>> implementation-specific hack, as the edp i2c bus doesn't leak into the
>>> outside world otherwise.
>>>
>>> I guess this empty i2c bus not being part of the binding document points
>>> heavily into the implementation-specific corner :-) .
>>>
>>> My short search on other patches touching this didn't reveal anything but
>>> maybe this was already discussed somewhere and found to be ok?
>> Here it is:
>>
>> http://www.spinics.net/lists/linux-tegra/msg27862.html
> thanks ... I'm still not sure about the placeholder though, aka needing an
> undocumented subnode to make a Linux error message silent.
Sorry, I report the error result, it would work.
And about the problem at this thread beginning, I found I have to use
something like Xserver to access DRM or the panel would not be power on.
The legacy fbdev won't help.
But there is still problem to be solved, so the eDP panel for firefly is
not ready yet.
>
> In the thread you pointed to I also did not see any dt-maintainer involvement
> pointing one way or another, but spinics is often not easy to navigate
> threads, so I may have missed that.
>
>
>>> Another option could be to just make of_i2c_register_device silent if
>>> of_modalias_node returns -ENODEV?
>
> Heiko
>
>>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>>> Cc: Randy Li <randy.li@rock-chips.com>
>>>> Cc: Jon Hunter <jonathanh@nvidia.com>
>>>> ---
>>>>
>>>> arch/arm/boot/dts/rk3288.dtsi | 5 +++++
>>>> 1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rk3288.dtsi
>>>> b/arch/arm/boot/dts/rk3288.dtsi
>>>> index 2f814ffeb605..94f4b7eecca2 100644
>>>> --- a/arch/arm/boot/dts/rk3288.dtsi
>>>> +++ b/arch/arm/boot/dts/rk3288.dtsi
>>>> @@ -1075,6 +1075,11 @@
>>>>
>>>> };
>>>>
>>>> };
>>>>
>>>> };
>>>>
>>>> +
>>>> + i2c-bus {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>>
>>>> };
>>>>
>>>> hdmi: hdmi@ff980000 {
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
^ permalink raw reply
* Re: [PATCH v2 3/3] ARM: dts: imx6qdl-apalis: Use enable-gpios property for backlight
From: Shawn Guo @ 2016-10-22 3:32 UTC (permalink / raw)
To: Sanchayan Maity
Cc: marcel.ziswiler, stefan, linux-arm-kernel, devicetree,
linux-kernel
In-Reply-To: <2206aa18153f33a2b6763e2bc6c87bf83eadb674.1474260360.git.maitysanchayan@gmail.com>
On Mon, Sep 19, 2016 at 10:41:53AM +0530, Sanchayan Maity wrote:
> Use enable-gpios property of PWM backlight driver for backlight
> control.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v2 2/3] ARM: dts: imx6q-apalis-ixora: Remove use of pwm-leds
From: Shawn Guo @ 2016-10-22 3:32 UTC (permalink / raw)
To: Sanchayan Maity
Cc: marcel.ziswiler, stefan, linux-arm-kernel, devicetree,
linux-kernel
In-Reply-To: <1c9c910104414bdfbad077ccc3baca57974ba8c7.1474260360.git.maitysanchayan@gmail.com>
On Mon, Sep 19, 2016 at 10:41:52AM +0530, Sanchayan Maity wrote:
> Remove use of pwm-leds and use the standard /sys/class/pwm
> interface from PWM subsystem.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: dts: imx6qdl-apalis: Do not rely on DDC I2C bus bitbang for HDMI
From: Shawn Guo @ 2016-10-22 3:25 UTC (permalink / raw)
To: Sanchayan Maity
Cc: marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ, stefan-XLVq0VzYD2Y,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2263d508999ada9476268138b2922702eb50131f.1474260360.git.maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Sep 19, 2016 at 10:41:51AM +0530, Sanchayan Maity wrote:
> Remove the use of DDC I2C bus bitbang to support reading of EDID
> and rely on support from internal HDMI I2C master controller instead.
> As a result remove the device tree property ddc-i2c-bus.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
I think that the dw-hdmi i2c support [1] is a prerequisite of this
patch. I do not see it lands on v4.9-rc1. Or am I missing something?
Shawn
[1] https://patchwork.kernel.org/patch/9296883/
> ---
> Changes since v1:
>
> Change the ranking in i2c aliases
>
> v1: https://lkml.org/lkml/2016/9/14/55
> ---
> arch/arm/boot/dts/imx6q-apalis-ixora.dts | 12 +++---------
> arch/arm/boot/dts/imx6qdl-apalis.dtsi | 25 +++++++++----------------
> 2 files changed, 12 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> index 207b85b..82b81e0 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> @@ -55,10 +55,9 @@
> "fsl,imx6q";
>
> aliases {
> - i2c0 = &i2cddc;
> - i2c1 = &i2c1;
> - i2c2 = &i2c2;
> - i2c3 = &i2c3;
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> };
>
> aliases {
> @@ -186,11 +185,6 @@
> };
>
> &hdmi {
> - ddc-i2c-bus = <&i2cddc>;
> - status = "okay";
> -};
> -
> -&i2cddc {
> status = "okay";
> };
>
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index 99e323b..8c67dd8 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -53,18 +53,6 @@
> status = "disabled";
> };
>
> - /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
> - i2cddc: i2c@0 {
> - compatible = "i2c-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_i2c_ddc>;
> - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
> - &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
> - >;
> - i2c-gpio,delay-us = <2>; /* ~100 kHz */
> - status = "disabled";
> - };
> -
> reg_1p8v: regulator-1p8v {
> compatible = "regulator-fixed";
> regulator-name = "1P8V";
> @@ -209,6 +197,12 @@
> };
> };
>
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> /*
> * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
> * board)
> @@ -633,11 +627,10 @@
> >;
> };
>
> - pinctrl_i2c_ddc: gpioi2cddcgrp {
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> fsl,pins = <
> - /* DDC bitbang */
> - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
> - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
> + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
> >;
> };
>
> --
> 2.9.3
>
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^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
From: Shawn Guo @ 2016-10-22 3:18 UTC (permalink / raw)
To: Sanchayan Maity
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, stefan-XLVq0VzYD2Y,
marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <20160921112438.8661-1-maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Wed, Sep 21, 2016 at 04:54:38PM +0530, Sanchayan Maity wrote:
> Add support for Toradex Colibri iMX6 module.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Applied, thanks.
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^ permalink raw reply
* Re: [RFC V2 PATCH 10/12] arm64: dts: msm8994 issolate non standard bootloader/LK entries
From: Bjorn Andersson @ 2016-10-22 1:14 UTC (permalink / raw)
To: Stephen Boyd
Cc: Arnd Bergmann, Andy Gross, Rob Herring, Jeremy McNicoll,
git-LJ92rlH3Dns, Jeremy McNicoll, linux-arm-msm,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161022000733.GO26139-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Fri 21 Oct 17:07 PDT 2016, Stephen Boyd wrote:
> On 10/21, Arnd Bergmann wrote:
> > On Friday, October 21, 2016 1:04:09 PM CEST Stephen Boyd wrote:
> > > I'm pushing the bootloader team to do the deep scan of the dtb to
> > > match up board compatible and pmic compatible strings so that we
> > > don't have to keep these numbers around. Basically put what
> > > dtbtool is doing into the bootloader so we don't have to post
> > > process the dtb anymore. We're currently discussing how to
> > > implement it and how to move the internal codebase to the new
> > > scheme.
> > >
> > > At least for 96boards I think we can update the lk bootloaders on
> > > there to adopt this code. For other platforms like nexus though I
> > > don't see a way we can update those bootloaders, and those
> > > bootloaders require these properties exist in the dtbs, so we
> > > should just throw the numbers into the dts files there and be
> > > done with post processing. For bootloaders that require the QCDT
> > > header, we'll have to keep running dtbtool there to generate the
> > > header. Having the ids in the dts file or not doesn't really
> > > matter there.
> >
> > I think part of the problem here is the way that the bootloader
> > expects multiple dtbs to be appended to the kernel binary, and
> > then pick one of them based on its contents. That doesn't really
> > change at all when changing the parser from looking at nonstandard
> > properties to looking at the compatible strings.
> >
> > It still breaks the last-resort workaround for broken bootloaders
> > that we have in the form of appending the DT to the kernel
> > with CONFIG_ARM_APPENDED_DTB.
>
> That can be "fixed" by having the bootloader use the single
> appended DTB regardless of the properties existing or not. That's
> a few lines of code to count the number of appended blobs and
> then special case there being one.
>
This is already the case on at least 8974; if the ids are present they
must be the right ones, otherwise it will just pick the dtb that's
there.
[..]
> > Ideally this is done
> > by storing all files on a file system that can also be mounted
> > to /boot, but there are probably other options that work equally well.
> >
>
> Some bootloaders *cough* LK *cough* aren't always able to read
> filesystems. All they can do is read raw data from partitions.
> That's probably why nobody has thought about reading files from
> some place like /boot (which doesn't even exist in android)
> because these bootloaders don't have filesystem support.
>
Well, your version of LK has ext2 support - just not in the code path
that loads the kernel. But that's still only a different way to
represent what we today have in QCDT, it doesn't change anything related
to these ids.
Regards,
Bjorn
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^ permalink raw reply
* Re: [RFC V2 PATCH 10/12] arm64: dts: msm8994 issolate non standard bootloader/LK entries
From: Stephen Boyd @ 2016-10-22 0:36 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Arnd Bergmann, Jeremy McNicoll,
git-LJ92rlH3Dns, Jeremy McNicoll, linux-arm-msm,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161021224244.GC7509@tuxbot>
On 10/21, Bjorn Andersson wrote:
> On Fri 21 Oct 13:04 PDT 2016, Stephen Boyd wrote:
>
> > On 10/21, Bjorn Andersson wrote:
> > > On Wed 19 Oct 20:17 PDT 2016, Andy Gross wrote:
> > >
> > > > On Wed, Oct 19, 2016 at 08:07:25PM -0500, Rob Herring wrote:
> > > [..]
> > > > > Makes sense to me for things like Nexus phones here. What about DB410
> > > > > for example? Is there hope for a fix there? My bootloader is only a
> > > > > couple of months old and needs the properties still.
> > > >
> > > > There won't be a fix for the 410c. We barely got them to respin to use PSCI.
> > > > Stephen can correct me if I am wrong on this.
> > > >
> > > > If this is fixed, it would be 8996+. If..........
> > > >
> > > > So this means introducing the msm-id's for the boards that currently require it,
> > > > and for the boards that will require it in the future. And this would stay in
> > > > effect until the bootloader is able to parse the compatible strings or figure
> > > > this out without the msm-ids.
> > > >
> > >
> > > But if the bootloader at any point in the future would support picking a
> > > dtb by compatible strings instead of {msm,board,pmic}-id we wouldn't we
> > > just be back to the ridiculous compatible strings that tipped over into
> > > acceptance to these ids in the first place.
> > >
> > > Or do we expect the boot loader to do a deep scan of the dtb to match on
> > > multiple nodes from the tree?
> >
> > I'm pushing the bootloader team to do the deep scan of the dtb to
> > match up board compatible and pmic compatible strings so that we
> > don't have to keep these numbers around. Basically put what
> > dtbtool is doing into the bootloader so we don't have to post
> > process the dtb anymore. We're currently discussing how to
> > implement it and how to move the internal codebase to the new
> > scheme.
> >
>
> Based on the variations described in your "Document qcom board
> compatible format" patch you would need to scan the DTB for:
I think you're looking at an outdated doc?
>
> * SoC, Platform type and Version
> All part of /compatible, so that's simple
>
> * Memory size
> Look at second cell of /memory/reg ? Or just reject this variable?
We dropped this one. I don't know if we'll have users so we
punted.
>
> * PMIC
> Find the qcom,spmi-pmic-arb and iterate over each child and match the
> compatible of with some predefined list. We need to add all version
> variations of these in the compatibles to make this work as well.
We find it based on aliases. usid0,2,4,6 are found from the
aliases node and then we look at the pmic compatible string. I've
been trying to keep people honest there and have them put the
actual compatible string for the pmic in the pmic node.
>
> * Main storage technology
> Look for an active node compatible with qcom,ufshc and if not found
> fall back to expecting this was a eMMC only DTB?
>
> * Display panel
> Find the qcom,mdss compatible, follow the qcom,mdp5 compatible child
> to extract ports/port@0 to get the of_graph handle to some connector
> node, then in ../port@1 we can find a phandle to the panel which we
> can find and then match against a predefined set of compatibles.
We punted on these ones too. I don't know if we care. The panel
sounds especially painful.
>
> > At least for 96boards I think we can update the lk bootloaders on
> > there to adopt this code. For other platforms like nexus though I
> > don't see a way we can update those bootloaders, and those
> > bootloaders require these properties exist in the dtbs, so we
> > should just throw the numbers into the dts files there and be
> > done with post processing. For bootloaders that require the QCDT
> > header, we'll have to keep running dtbtool there to generate the
> > header. Having the ids in the dts file or not doesn't really
> > matter there.
> >
>
> At the time we introduced the Xperia Z1 (Honami) our boot loader only
> supported QCDT, so I experimented with a version of dtbTool that kept a
> compatible to id table mapping hardcoded (very much like your existing
> dtbTool). And as expected it turns into an unmaintainable mess to track
> this information on the side.
>
I think msm-id and pmic-ids are fairly simple. The problems
really come from the slight board variants and how to handle
those. The scheme we have today with dtbtool attempts to keep
things simple but it may need to be more complicated on Honami. I
don't really have a problem continuing to update the tool with
new SoC and PMIC models, but I don't see much point in it now
(see below).
>
> I'm sorry, but to me that just sounds like a lot of work to find an
> alternative to the functional and pragmatic solution that exists today,
> just for the sake of hiding these non-standard ids in an even more
> non-standard way.
>
I agree. This has all been a lot of effort to figure out some
alternative to having the numbers in the dts files. I won't argue
that the numbers are pretty, or that they don't duplicate
information that's already there in some other form of board/pmic
compatible strings, but the truth is we have bootloaders that are
looking inside the dtbs for these magic numbers now. The approach
that Nexus devices take has been pushed as the only method of dtb
picking inside the company so QCDT support is going away soon.
So going through the work to post process and then add in the
properties that could have been added in the dts in the first
place seems like a big waste of time. I'd rather we just leave
the numbers there and everything just works. We do have the
possibility of two different dtbs aliasing on the qcom,board-id
property, but I'd rather just let that problem happen and rely on
users to only append dtbs with different ids to their kernel.
--
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a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [RFC V2 PATCH 10/12] arm64: dts: msm8994 issolate non standard bootloader/LK entries
From: Stephen Boyd @ 2016-10-22 0:07 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Bjorn Andersson, Andy Gross, Rob Herring, Jeremy McNicoll,
git-LJ92rlH3Dns, Jeremy McNicoll, linux-arm-msm,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <3979420.yzJRfAtfpN@wuerfel>
On 10/21, Arnd Bergmann wrote:
> On Friday, October 21, 2016 1:04:09 PM CEST Stephen Boyd wrote:
> > I'm pushing the bootloader team to do the deep scan of the dtb to
> > match up board compatible and pmic compatible strings so that we
> > don't have to keep these numbers around. Basically put what
> > dtbtool is doing into the bootloader so we don't have to post
> > process the dtb anymore. We're currently discussing how to
> > implement it and how to move the internal codebase to the new
> > scheme.
> >
> > At least for 96boards I think we can update the lk bootloaders on
> > there to adopt this code. For other platforms like nexus though I
> > don't see a way we can update those bootloaders, and those
> > bootloaders require these properties exist in the dtbs, so we
> > should just throw the numbers into the dts files there and be
> > done with post processing. For bootloaders that require the QCDT
> > header, we'll have to keep running dtbtool there to generate the
> > header. Having the ids in the dts file or not doesn't really
> > matter there.
>
> I think part of the problem here is the way that the bootloader
> expects multiple dtbs to be appended to the kernel binary, and
> then pick one of them based on its contents. That doesn't really
> change at all when changing the parser from looking at nonstandard
> properties to looking at the compatible strings.
>
> It still breaks the last-resort workaround for broken bootloaders
> that we have in the form of appending the DT to the kernel
> with CONFIG_ARM_APPENDED_DTB.
That can be "fixed" by having the bootloader use the single
appended DTB regardless of the properties existing or not. That's
a few lines of code to count the number of appended blobs and
then special case there being one.
>
> I think a better long-term strategy would be to make the bootloader
> load the dtb separately from the kernel and finding the right file
> using some information outside of the dtb.
Can you please explain why that's a better long term strategy? So
far I've had a hard time selling this internally so I could use
the help to come up with a laundry list of reasons why this is a
better design than what we have today.
> Ideally this is done
> by storing all files on a file system that can also be mounted
> to /boot, but there are probably other options that work equally well.
>
Some bootloaders *cough* LK *cough* aren't always able to read
filesystems. All they can do is read raw data from partitions.
That's probably why nobody has thought about reading files from
some place like /boot (which doesn't even exist in android)
because these bootloaders don't have filesystem support.
If the bootloader supports filesystems, then it would work to
encode the qcom,{msm-id,board-id,pmic-id} properties into some
long filename and then have the bootloader pick the right file
based on that. Fuzzy matching would be interesting, but it should
still work.
--
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a Linux Foundation Collaborative Project
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^ permalink raw reply
* [PATCH v3 4/4] arm64: dts: msm8996: Add SMP2P and APCS nodes
From: Sarangdhar Joshi @ 2016-10-21 23:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: Sarangdhar Joshi, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, Stephen Boyd, Trilok Soni
In-Reply-To: <1477091959-19580-1-git-send-email-spjoshi@codeaurora.org>
Add SMP2P and APCS DT nodes required for Qualcomm ADSP
Peripheral Image Loader.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 60d2d20c..9e960c1 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -175,6 +175,30 @@
method = "smc";
};
+ adsp-smp2p {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+
+ interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 16 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
@@ -203,6 +227,11 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ apcs: syscon@9820000 {
+ compatible = "syscon";
+ reg = <0x9820000 0x1000>;
+ };
+
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v3 3/4] arm64: dts: msm8996: Add SMEM DT nodes
From: Sarangdhar Joshi @ 2016-10-21 23:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: linux-arm-msm, linux-soc, devicetree, linux-arm-kernel,
linux-kernel, Stephen Boyd, Trilok Soni, Sarangdhar Joshi
In-Reply-To: <1477091959-19580-1-git-send-email-spjoshi@codeaurora.org>
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Add SMEM and TCSR DT nodes on MSM8996.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 949b096..60d2d20c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -164,17 +164,34 @@
};
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
+ tcsr_mutex_regs: syscon@740000 {
+ compatible = "syscon";
+ reg = <0x740000 0x20000>;
+ };
+
intc: interrupt-controller@9bc0000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v3 2/4] arm64: dts: msm8996: Add reserve-memory nodes
From: Sarangdhar Joshi @ 2016-10-21 23:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: Sarangdhar Joshi, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, Stephen Boyd, Trilok Soni
In-Reply-To: <1477091959-19580-1-git-send-email-spjoshi@codeaurora.org>
Add reserve-memory nodes required for Qualcomm
Peripheral Image Loaders
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 36216ae..949b096 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -36,6 +36,31 @@
#size-cells = <2>;
ranges;
+ mba_region: mba@91500000 {
+ reg = <0x0 0x91500000 0x0 0x200000>;
+ no-map;
+ };
+
+ slpi_region: slpi@90b00000 {
+ reg = <0x0 0x90b00000 0xa00000>;
+ no-map;
+ };
+
+ venus_region: venus@90400000 {
+ reg = <0x0 0x90400000 0x0 0x700000>;
+ no-map;
+ };
+
+ adsp_region: adsp@8ea00000 {
+ reg = <0x0 0x8ea00000 0x0 0x1a00000>;
+ no-map;
+ };
+
+ mpss_region: mpss@88800000 {
+ reg = <0x0 0x88800000 0x0 0x6200000>;
+ no-map;
+ };
+
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v3 1/4] arm64: dts: msm8996: Add SMEM reserve-memory node
From: Sarangdhar Joshi @ 2016-10-21 23:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: Sarangdhar Joshi, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, Stephen Boyd, Trilok Soni
In-Reply-To: <1477091959-19580-1-git-send-email-spjoshi@codeaurora.org>
Add DT node to carveout memory for shared memory region.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index d6da223..36216ae 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -31,6 +31,17 @@
reg = <0 0 0 0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_mem: smem-mem@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v3 0/4] MSM8996 DT Support for ADSP PIL
From: Sarangdhar Joshi @ 2016-10-21 23:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: Sarangdhar Joshi, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Stephen Boyd, Trilok Soni
Add various device tree nodes to lay the groundwork for
Qualcomm ADSP Peripheral Image Loader.
Sorry, I didn't send any cover letter for v1.
Changes since v2:
- Remove empty lines from smem DT node (Stephen)
Changes since v1:
- Move hwlock DT node under root (/) (Bjorn and Andy)
- Rename smp2p-adsp to adsp-smp2p (Bjorn)
- Remove interrupt-parent property from node (Bjorn)
Bjorn Andersson (1):
arm64: dts: msm8996: Add SMEM DT nodes
Sarangdhar Joshi (3):
arm64: dts: msm8996: Add SMEM reserve-memory node
arm64: dts: msm8996: Add reserve-memory nodes
arm64: dts: msm8996: Add SMP2P and APCS nodes
arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 +++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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