* Re: mbox-name vs. mbox-names (was: Re: [PATCH v4 1/5] mailbox: dt: Supply bindings for ST's Mailbox IP)
From: Lee Jones @ 2016-10-24 8:41 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, Maxime Coquelin, Jassi Brar,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdXqOZ=eKJ=SkY4TM=fu8qnZ2gLmh-2iH0jB2pAu_v2vNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, 21 Oct 2016, Geert Uytterhoeven wrote:
> On Fri, Oct 16, 2015 at 9:21 AM, Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > Signed-off-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > ---
> > .../devicetree/bindings/mailbox/sti-mailbox.txt | 51 ++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > new file mode 100644
> > index 0000000..b61eec9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
> > @@ -0,0 +1,51 @@
> > +ST Microelectronics Mailbox Driver
> > +
> > +Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
> > +are passed between Application and Remote processors using shared memory.
> > +
> > +Controller
> > +----------
> > +
> > +Required properties:
> > +- compatible : Should be "st,stih407-mailbox"
> > +- reg : Offset and length of the device's register set
> > +- mbox-name : Name of the mailbox
>
> All other mailbox drivers use "mbox-names". Oops, it's in v4.9-rc1...
>
> Can we still fix that?
So long as all the fixes; changes to the driver and DT are merged in a
single kernel release, we can change it.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: stm32f429: remove Ethernet wake on Lan support
From: Alexandre TORGUE @ 2016-10-24 8:40 UTC (permalink / raw)
To: peppe.cavallaro, Maxime Coquelin, arnd, robh
Cc: netdev, linux-arm-kernel, devicetree
In-Reply-To: <1477298406-22805-1-git-send-email-alexandre.torgue@st.com>
This patch removes WoL (Wake on Lan) support as it is not yet
fully supported and tested.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 6350117b..ad0bc6a 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -377,8 +377,8 @@
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
- interrupts = <61>, <62>;
- interrupt-names = "macirq", "eth_wake_irq";
+ interrupts = <61>;
+ interrupt-names = "macirq";
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: stm32f429: Fix Ethernet node on Eval Board
From: Alexandre TORGUE @ 2016-10-24 8:40 UTC (permalink / raw)
To: peppe.cavallaro-qxv4g6HH51o, Maxime Coquelin, arnd-r2nGTMty4D4,
robh-DgEjT+Ai2ygdnm+yROfE0A
Cc: netdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477298406-22805-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
"phy-handle" entry is mandatory when mdio subnode is used in
Ethernet node.
Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index fa30bf1..a11b108 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -99,7 +99,7 @@
pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
phy-mode = "mii";
-
+ phy-handle = <&phy1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
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* [PATCH v2 1/3] ARM: dts: stm32f429: Align Ethernet node with new bindings properties
From: Alexandre TORGUE @ 2016-10-24 8:40 UTC (permalink / raw)
To: peppe.cavallaro-qxv4g6HH51o, Maxime Coquelin, arnd-r2nGTMty4D4,
robh-DgEjT+Ai2ygdnm+yROfE0A
Cc: netdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477298406-22805-1-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org>
This patch aligns clocks names and node reference according to new
stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle
(indeed there is no need to add 0 as Ethernet instance as there is only
one IP in SOC).
Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 13c7cd2..fa30bf1 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -94,11 +94,12 @@
clock-frequency = <25000000>;
};
-ðernet0 {
+&mac {
status = "okay";
- pinctrl-0 = <ðernet0_mii>;
+ pinctrl-0 = <ðernet_mii>;
pinctrl-names = "default";
- phy-mode = "mii-id";
+ phy-mode = "mii";
+
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 336ee4f..6350117b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -313,7 +313,7 @@
};
};
- ethernet0_mii: mii@0 {
+ ethernet_mii: mii@0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
@@ -373,13 +373,13 @@
st,mem2mem;
};
- ethernet0: dwmac@40028000 {
+ mac: ethernet@40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth", "tx-clk", "rx-clk";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
st,syscon = <&syscfg 0x4>;
snps,pbl = <8>;
--
1.9.1
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^ permalink raw reply related
* [PATCH v2 0/3] STM32F429: Add Ethernet fixes
From: Alexandre TORGUE @ 2016-10-24 8:40 UTC (permalink / raw)
To: peppe.cavallaro-qxv4g6HH51o, Maxime Coquelin, arnd-r2nGTMty4D4,
robh-DgEjT+Ai2ygdnm+yROfE0A
Cc: netdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
This v2 to avoid build issue when only patch 1 (of first series)
was build.
This series adds several fixes for Ethernet for stm32f429 MCU.
First patch has already been reviewed some months ago when
stm32 Ethernet glue has been pushed (I added in this series to keep
history). Fixes are:
-Change DT to be compliant to stm32 ethernet glue binding
-Add phy-handle to correctly use mdio subnode
-Remove WoL support
changes since v1:
-squash patch1 and patch2.
Regards
Alex
Alexandre TORGUE (3):
ARM: dts: stm32f429: Align Ethernet node with new bindings properties
ARM: dts: stm32f429: Fix Ethernet node on Eval Board
ARM: dts: stm32f429: remove Ethernet wake on Lan support
arch/arm/boot/dts/stm32429i-eval.dts | 7 ++++---
arch/arm/boot/dts/stm32f429.dtsi | 10 +++++-----
2 files changed, 9 insertions(+), 8 deletions(-)
--
1.9.1
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* Re: [PATCH V2 1/5] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Shawn Guo @ 2016-10-24 8:36 UTC (permalink / raw)
To: Jia Hongtao
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
scott.wood-3arQi8VN3Tc, devicetree-u79uwXL29TY76Z2rM5mHXA,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1475995626-14049-1-git-send-email-hongtao.jia-3arQi8VN3Tc@public.gmane.org>
On Sun, Oct 09, 2016 at 02:47:02PM +0800, Jia Hongtao wrote:
> From: Hongtao Jia <hongtao.jia-3arQi8VN3Tc@public.gmane.org>
>
> SoC compatible string and endianness property are added according to the
> new bindings.
The commit log doesn't seem to match the actual changes. Same for patch
2/5.
Shawn
>
> Signed-off-by: Jia Hongtao <hongtao.jia-3arQi8VN3Tc@public.gmane.org>
> ---
> Changes for V2:
> * Rebase on latest linux-next tree (next-20161006).
>
> arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> index 44e399b..145c7f4 100644
> --- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> @@ -526,7 +526,7 @@
>
> 0x00030000 0x00000012
> 0x00030001 0x0000001d>;
> - #thermal-sensor-cells = <0>;
> + #thermal-sensor-cells = <1>;
> };
>
> thermal-zones {
> @@ -534,7 +534,7 @@
> polling-delay-passive = <1000>;
> polling-delay = <5000>;
>
> - thermal-sensors = <&tmu>;
> + thermal-sensors = <&tmu 2>;
>
> trips {
> cpu_alert: cpu-alert {
> --
> 2.1.0.27.g96db324
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Marc Zyngier @ 2016-10-24 8:36 UTC (permalink / raw)
To: Ding Tianhong, Catalin Marinas, Will Deacon, Mark Rutland
Cc: Scott Wood, devicetree-u79uwXL29TY76Z2rM5mHXA, Shawn Guo,
stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <962ea92f-870b-e1d0-5bb7-1a6d66c35122-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On 23/10/16 04:21, Ding Tianhong wrote:
> This erratum describes a bug in logic outside the core, so MIDR can't be
> used to identify its presence, and reading an SoC-specific revision
> register from common arch timer code would be awkward. So, describe it
> in the device tree.
>
> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
> index ef5fbe9..26bc837 100644
> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
> @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
> This also affects writes to the tval register, due to the implicit
> counter read.
>
> +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of
> + QorIQ erratum 161201, which says that reading the counter is
Other than the copy/paste of the FSL erratum, please document the actual
erratum number. Is that 161x01 or 161201?
> + unreliable unless the small range of value is returned by back-to-back reads.
That's a detail that doesn't belong in the DT, but that would be much
better next to the code doing the actual handling.
> + This also affects writes to the tval register, due to the implicit
> + counter read.
> +
> ** Optional properties:
>
> - arm,cpu-registers-not-fw-configured : Firmware does not initialize
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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* Re: [RFC v2 2/2] mmc: sdhci: Ignore capability register when it comes to speeds and use DT binding instead when sdhci-cap-speed-modes-broken is set.
From: Adrian Hunter @ 2016-10-24 7:34 UTC (permalink / raw)
To: Zach Brown, ulf.hansson
Cc: robh+dt, mark.rutland, linux-mmc, devicetree, linux-kernel
In-Reply-To: <1477085715-30213-3-git-send-email-zach.brown@ni.com>
On 22/10/16 00:35, Zach Brown wrote:
> When the sdhci-cap-speed-modes-broken DT property is set, the driver
> will ignore the bits of the capability registers that correspond to
> speed modes.
>
> Signed-off-by: Zach Brown <zach.brown@ni.com>
> ---
> drivers/mmc/host/sdhci.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 1e25b01..59c62d3 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -22,6 +22,7 @@
> #include <linux/scatterlist.h>
> #include <linux/regulator/consumer.h>
> #include <linux/pm_runtime.h>
> +#include <linux/of.h>
>
> #include <linux/leds.h>
>
> @@ -3013,10 +3014,19 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
>
> host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
>
> + if (of_property_read_bool(mmc_dev(host->mmc)->of_node,
> + "sdhci-cap-speed-modes-broken"))
It rather begs the question: if you are going to do something sdhci
specific, why not just read the whole of the caps register from DT?
> + host->caps &= ~SDHCI_CAN_DO_HISPD;
> +
> if (host->version < SDHCI_SPEC_300)
> return;
>
> host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
> +
> + if (of_property_read_bool(mmc_dev(host->mmc)->of_node,
> + "sdhci-cap-speed-modes-broken"))
Why read it twice?
> + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
> + SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_HS400);
> }
> EXPORT_SYMBOL_GPL(__sdhci_read_caps);
>
>
^ permalink raw reply
* Re: [PATCH 0/4] STM32F429: Add Ethernet fixes
From: Alexandre Torgue @ 2016-10-24 7:30 UTC (permalink / raw)
To: David Miller
Cc: peppe.cavallaro-qxv4g6HH51o,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w, arnd-r2nGTMty4D4,
robh-DgEjT+Ai2ygdnm+yROfE0A, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161020.144140.1794871934594140769.davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
Hi David,
On 10/20/2016 08:41 PM, David Miller wrote:
> From: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
> Date: Thu, 20 Oct 2016 17:21:22 +0200
>
>> This series adds several fixes for Ethernet for stm32f429 MCU.
>> First 2 patches have already been reviewed some months ago when
>> stm32 Ethernet glue has been pushed (I added in this series to keep
>> history). Fixes are:
>> -Change DT to be compliant to stm32 ethernet glue binding
>> -Add phy-handle to correctly use mdio subnode
>> -Remove WoL support
>
> I'm assuming this will be merged via the ARM tree.
Yes, I will take it in my next pull request (if no issues).
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* Re: [PATCH V7 4/4] dmaengine: qcom_hidma: add MSI support for interrupts
From: Andy Shevchenko @ 2016-10-24 7:30 UTC (permalink / raw)
To: Sinan Kaya
Cc: dmaengine, Timur Tabi, devicetree, Christopher Covington,
Vinod Koul, Jon Masters, Andy Gross, Arnd Bergmann,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, linux-arm Mailing List,
Dan Williams, Dave Jiang, Lars-Peter Clausen,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <36163853-ac4a-e146-0c1b-eaf42e8b234d-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Mon, Oct 24, 2016 at 5:55 AM, Sinan Kaya <okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> On 10/21/2016 12:11 PM, Andy Shevchenko wrote:
>>> +static void hidma_free_msis(struct hidma_dev *dmadev)
>>> > +{
>>> > +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
>> Perhaps one #ifdef and two definitions of functions?
>
> I don't think it will make a difference. I'll have to move
> #ifdef around the caller of hidma_free_msis instead which
> I think is uglier.
>
> The hidma_write_msi_msg function gets called only when
> CONFIG_GENERIC_MSI_IRQ_DOMAIN is defined. If I don't put
> this around the function definition, I get unused function
> warning from the compiler. This is the reason why preprocessor
> definition is outside of the function definition.
I am talking about something like below:
#ifdef UGLY_DEFINE
myfunc_a()
{
}
myfunc_b()
{
}
#else
static inline myfunc_a() {}
static inline myfunc_b() {}
#endif
There is another way as well, namely use of IS_ENABLED(), IS_BUILTIN()
macros (I don't remember how exactly second one is spelt).
--
With Best Regards,
Andy Shevchenko
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* Re: [PATCH v1 1/2] ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid
From: Shawn Guo @ 2016-10-24 7:23 UTC (permalink / raw)
To: Sanchayan Maity
Cc: broonie-DgEjT+Ai2ygdnm+yROfE0A, linux-spi-u79uwXL29TY76Z2rM5mHXA,
stefan-XLVq0VzYD2Y,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bhuvanchandra.dv-2KBjVHiyJgBBDgjK7y7TUQ
In-Reply-To: <63fc108e2df00d2297a9b7014955f203bc802f34.1475498805.git.maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Oct 03, 2016 at 06:20:37PM +0530, Sanchayan Maity wrote:
> Enable DMA for DSPI on Vybrid.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This is a hardware description which looks correct, regardless of the
DSPI driver readiness. So I applied it.
Shawn
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^ permalink raw reply
* Re: [PATCH 0/5] ARM: dts: renesas: Remove skeleton.dtsi inclusion
From: Simon Horman @ 2016-10-24 7:03 UTC (permalink / raw)
To: Mark Rutland
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Arnd Bergmann,
Olof Johansson, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161021095319.GC15372@leverpostej>
On Fri, Oct 21, 2016 at 10:53:19AM +0100, Mark Rutland wrote:
> On Fri, Oct 21, 2016 at 11:16:05AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon, Magnus,
> >
> > As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
> > as deprecated"), including skeleton.dtsi is deprecated.
> > Hence this series removes its use for all Renesas 32-bit ARM SoCs.
>
> Thanks for doing this! FWIW, for the series:
>
> Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Thanks, I have queued these up.
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^ permalink raw reply
* Re: [PATCH] gpio: mcp23s08: Add option to configure pullups.
From: Alexander Stein @ 2016-10-24 6:13 UTC (permalink / raw)
To: Linus Walleij
Cc: Enric Balletbo i Serra, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-gpio@vger.kernel.org,
Rob Herring
In-Reply-To: <CACRpkdY15Hv_ydHyOXRM6G0ewVTHkVa1w3Z89AdvSDR=eyi7sQ@mail.gmail.com>
On Monday 24 October 2016 02:53:31, Linus Walleij wrote:
> On Fri, Oct 21, 2016 at 5:00 PM, Enric Balletbo i Serra
>
> <enric.balletbo@collabora.com> wrote:
> > Default is without pullups, but if property is specified in DT and the bit
> > is set, set a pullup on GPIO-n.
> >
> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> I don't generally like this.
>
> In device tree it is the consumer that specifies how the line is used,
> not the producer (gpiochip).
>
> We currently only specify polarity, open drain and open source
> for consumers though.
>
> And the entire pin control system came into being *exactly* because
> Grant didn't like me adding these things to the GPIO drivers.
>
> So how many other things does the MCP support? Drive strength?
> Schmitt trigger? Is there a datasheet?
Some unsupported features (AFAIK):
* Input polarity (IPOL register)
* open-drain interrupt pin
* pullup on pins (proposed patch)
Datasheet is here: http://ww1.microchip.com/downloads/en/DeviceDoc/21919e.pdf
Best regards,
Alexander
^ permalink raw reply
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Ding Tianhong @ 2016-10-24 5:46 UTC (permalink / raw)
To: Shawn Guo
Cc: Catalin Marinas, Will Deacon, Marc Zyngier, Mark Rutland,
Scott Wood, devicetree-u79uwXL29TY76Z2rM5mHXA,
stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161023120423.GO30578@tiger>
On 2016/10/23 20:04, Shawn Guo wrote:
> On Sun, Oct 23, 2016 at 11:21:10AM +0800, Ding Tianhong wrote:
>> This erratum describes a bug in logic outside the core, so MIDR can't be
>> used to identify its presence, and reading an SoC-specific revision
>> register from common arch timer code would be awkward. So, describe it
>> in the device tree.
>>
>> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> index ef5fbe9..26bc837 100644
>> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
>> This also affects writes to the tval register, due to the implicit
>> counter read.
>>
>> +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of
>> + QorIQ erratum 161201, which says that reading the counter is
>
> QorIQ is a Freescale/NXP specific name, and shouldn't be there.
>
> Shawn
>
Got it, will wait other feedback and fix them together, thanks.
Ding
>> + unreliable unless the small range of value is returned by back-to-back reads.
>> + This also affects writes to the tval register, due to the implicit
>> + counter read.
>> +
>> ** Optional properties:
>>
>> - arm,cpu-registers-not-fw-configured : Firmware does not initialize
>> --
>> 1.9.0
>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> .
>
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^ permalink raw reply
* Re: [PATCH v3] pinctrl: Add SX150X GPIO Extender Pinctrl Driver
From: Andrey Smirnov @ 2016-10-24 4:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Neil Armstrong, Peter Rosin, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
Roland Stigge, Vladimir Zapolskiy
In-Reply-To: <CACRpkdbwqFRtFN1gx1G7BuFe44mvPyCSeoQ5g9_FR11j_ZO4ug@mail.gmail.com>
On Sun, Oct 23, 2016 at 3:47 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Sun, Oct 23, 2016 at 4:50 AM, Andrey Smirnov
> <andrew.smirnov@gmail.com> wrote:
>> On Fri, Oct 21, 2016 at 2:09 AM, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>> Since the I2C sx150x GPIO expander driver uses platform_data to manage
>>> the pins configurations, rewrite the driver as a pinctrl driver using
>>> pinconf to get/set pin configurations from DT or debugfs.
>>>
>>> The pinctrl driver is functionnally equivalent as the gpio-only driver
>>> and can use DT for pinconf. The platform_data confirmation is dropped.
>>>
>>> This patchset removed the gpio-only driver and selects the Pinctrl driver
>>> config instead. This patchset also migrates the gpio dt-bindings to pinctrl
>>> and add the pinctrl optional properties.
>>>
>>> The driver was tested with a SX1509 device on a BeagleBone black with
>>> interrupt support and on an X86_64 machine over an I2C to USB converter.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> (...)
>
>>> + ret = gpiochip_irqchip_add(&pctl->gpio,
>>> + &pctl->irq_chip, 0,
>>> + handle_edge_irq, IRQ_TYPE_EDGE_BOTH);
>>
>> Adding irqchip with IRQ_TYPE_EDGE_BOTH triggers a WARN in
>> drivers/gpio/gpiolib.c:1671, on a custom Vybrid board that I have with
>> the chip, so maybe it should be replaced with IRQ_TYPE_NONE? That's
>> what I did for my testing and with that change
>
> I fixed this up when applying. It is corect, it should always be IRQ_TYPE_NONE
> unless it is a very old driver using boardfiles. The proper type is set up
> when the driver using it requests the IRQ.
>
> Some drivers also need to set the default handler to handle_bad_irq
> and then also set that up in the irqchip .set_type() callback, especially
> those hardwares that have an ACK register for edge IRQs so that a second
> edge irq can come in when handling a first edge IRQ. Level IRQs don't
> have this problem for obvious reasons, so we need to select between
> handle_edge_irq() or handle_level_irq() on these hardwares.
>
> Could you or Neil or both check if this applies to sx150x?
These chips only support edge triggered interrupts, so I doesn't seem
to me that it does. However, trying to answer that question lead me to
read IRQ related code of the driver, some of which didn't make as much
sense as I'd like it to. It may be due to my ignorance of how some of
the irqchip internals work, but I'll mention it anyway just in case.
It seem strange to me that the driver uses "handle_edge_irq", given
how none of the individual interrupts seem to require any ACKing,
since it is all handled in sx150x_irq_thread_fn(), line 533. More so,
I had trouble finding who/where sets .irq_ack() callback, which AFAIU
is mandatory for handle_edge_irq().
Unfortunately sx150x HW setup that I have doesn't permit to do any
testing of IRQ functionality (the chip is mostly used as GPO), so I
wasn't able to experiment with any of the code in question and shed
any light on my confusion. Apologies if it is just a false alarm.
Thanks,
Andrey Smirnov
^ permalink raw reply
* [v2 2/2] fpga: Add support for Lattice iCE40 FPGAs
From: Joel Holdsworth @ 2016-10-24 4:39 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Joel Holdsworth
In-Reply-To: <1477283989-21947-1-git-send-email-joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
and very regular structure, designed for low-cost, high-volume consumer
and system applications.
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.
The iCE40 family is notable because it is the first FPGA family to have
complete reverse engineered bit-stream documentation for the iCE40LP and
iCE40HX devices. Furthermore, there is now a Free Software Verilog
synthesis tool-chain: the "IceStorm" tool-chain.
This project is the work of Clifford Wolf, who is the maintainer of
Yosys Verilog RTL synthesis framework, and Mathias Lasser, with notable
contributions from "Cotton Seed", the main author of "arachne-pnr"; a
place-and-route tool for iCE40 FPGAs.
Having a Free Software synthesis tool-chain offers interesting
opportunities for embedded devices that are able reconfigure themselves
with open firmware that is generated on the device itself. For example
a mobile device might have an application processer with an iCE40 FPGA
attached, which implements slave devices, or through which the processor
communicates with other devices through the FPGA fabric.
A kernel driver for the iCE40 is useful, because in some cases, the FPGA
may need to be configured before other devices can be accessed.
An example of such a device is the icoBOARD; a RaspberryPI HAT which
features an iCE40HX8K with a 1 or 8 MBit SRAM and ports for
Digilent-compatible PMOD modules. A PMOD module may contain a device
with which the kernel communicates, via the FPGA.
---
.../bindings/fpga/lattice-ice40-fpga-mgr.txt | 23 +++
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/ice40spi.c | 212 +++++++++++++++++++++
4 files changed, 242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
create mode 100644 drivers/fpga/ice40spi.c
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
new file mode 100644
index 0000000..b253ac8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
@@ -0,0 +1,23 @@
+Lattice iCE40 FPGA Manager
+
+Required properties:
+- compatible: should contain "lattice,ice40-fpga-mgr"
+- reg: SPI chip select
+- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
+- cdone-gpios: GPIO connected to CDONE pin
+- creset_b-gpios: GPIO connected to CRESET_B pin. Note that CRESET_B is
+ treated as an active-low output because the signal is
+ treated as an enable signal, rather than a reset. This
+ is necessary because the FPGA will enter Master SPI
+ mode and drive SCK with a clock signal, potentially
+ jamming other devices on the bus, unless CRESET_B is
+ held high until the firmware is loaded.
+
+Example:
+ ice40: ice40@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ creset_b-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d614102..85ff429 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -13,6 +13,12 @@ config FPGA
if FPGA
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
config FPGA_MGR_SOCFPGA
tristate "Altera SOCFPGA FPGA Manager"
depends on ARCH_SOCFPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8d83fc6..6c809cc 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
diff --git a/drivers/fpga/ice40spi.c b/drivers/fpga/ice40spi.c
new file mode 100644
index 0000000..ab5ee86
--- /dev/null
+++ b/drivers/fpga/ice40spi.c
@@ -0,0 +1,212 @@
+/*
+ * FPGA Manager Driver for Lattice iCE40.
+ *
+ * Copyright (c) 2016 Joel Holdsworth
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This driver adds support to the FPGA manager for configuring the SRAM of
+ * Lattice iCE40 FPGAs through slave SPI.
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_gpio.h>
+#include <linux/spi/spi.h>
+
+struct ice40_fpga_priv {
+ struct spi_device *dev;
+ struct gpio_desc *creset_b;
+ struct gpio_desc *cdone;
+ enum fpga_mgr_states state;
+};
+
+static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return mgr->state;
+}
+
+static void set_cs(struct spi_device *spi, bool enable)
+{
+ if (gpio_is_valid(spi->cs_gpio))
+ gpio_set_value(spi->cs_gpio, !enable);
+ else if (spi->master->set_cs)
+ spi->master->set_cs(spi, !enable);
+}
+
+static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret;
+
+ if ((flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+ dev_err(&dev->dev,
+ "Partial reconfiguration is not supported\n");
+ return -EINVAL;
+ }
+
+ /* Lock the bus, assert SS_B and CRESET_B */
+ ret = spi_bus_lock(dev->master);
+ if (ret) {
+ dev_err(&dev->dev, "Failed to lock SPI bus, ret: %d\n", ret);
+ return ret;
+ }
+
+ set_cs(dev, 1);
+ gpiod_set_value(priv->creset_b, 1);
+
+ /* Delay for >200ns */
+ udelay(1);
+
+ /* Come out of reset */
+ gpiod_set_value(priv->creset_b, 0);
+
+ /* Check CDONE is de-asserted i.e. the FPGA is reset */
+ if (gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
+ ret = -EIO;
+ }
+
+ /* Wait for the housekeeping to complete */
+ if (!ret)
+ udelay(1200);
+
+ /* Release the SS_B */
+ set_cs(dev, 0);
+ spi_bus_unlock(dev->master);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret;
+
+ ret = spi_write(dev, buf, count);
+ if (ret)
+ dev_err(&dev->dev, "Error sending SPI data, ret: %d\n", ret);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret = 0;
+
+ /* Check CDONE is asserted */
+ if (!gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev,
+ "CDONE was not asserted after firmware transfer\n");
+ return -EIO;
+ }
+
+ /* Send >49-bits of zero-padding to activate the firmware */
+ ret = spi_write(dev, NULL, 7);
+ if (ret) {
+ dev_err(&dev->dev, "Error sending zero padding, ret: %d\n",
+ ret);
+ return ret;
+ }
+
+ /* Success */
+ return 0;
+}
+
+static const struct fpga_manager_ops ice40_fpga_ops = {
+ .state = ice40_fpga_ops_state,
+ .write_init = ice40_fpga_ops_write_init,
+ .write = ice40_fpga_ops_write,
+ .write_complete = ice40_fpga_ops_write_complete,
+};
+
+static int ice40_fpga_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct device_node *np = spi->dev.of_node;
+ struct ice40_fpga_priv *priv;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "No Device Tree entry\n");
+ return -EINVAL;
+ }
+
+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = spi;
+
+ /* Check board setup data. */
+ if (spi->max_speed_hz > 25000000) {
+ dev_err(dev, "speed is too high\n");
+ return -EINVAL;
+ } else if (spi->mode & SPI_CPHA) {
+ dev_err(dev, "bad mode\n");
+ return -EINVAL;
+ }
+
+ /* Set up the GPIOs */
+ priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
+ if (IS_ERR(priv->cdone)) {
+ dev_err(dev, "Failed to get CDONE GPIO: %ld\n",
+ PTR_ERR(priv->cdone));
+ return ret;
+ }
+
+ priv->creset_b = devm_gpiod_get(dev, "creset_b", GPIOD_OUT_HIGH);
+ if (IS_ERR(priv->creset_b)) {
+ dev_err(dev, "Failed to get CRESET_B GPIO: %ld\n",
+ PTR_ERR(priv->creset_b));
+ return ret;
+ }
+
+ /* Register with the FPGA manager */
+ ret = fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
+ &ice40_fpga_ops, priv);
+ if (ret) {
+ dev_err(dev, "unable to register FPGA manager");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ice40_fpga_remove(struct spi_device *spi)
+{
+ fpga_mgr_unregister(&spi->dev);
+ return 0;
+}
+
+static const struct of_device_id ice40_fpga_of_match[] = {
+ { .compatible = "lattice,ice40-fpga-mgr", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
+
+static struct spi_driver ice40_fpga_driver = {
+ .probe = ice40_fpga_probe,
+ .remove = ice40_fpga_remove,
+ .driver = {
+ .name = "ice40spi",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ice40_fpga_of_match),
+ },
+};
+
+module_spi_driver(ice40_fpga_driver);
+
+MODULE_AUTHOR("Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>");
+MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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^ permalink raw reply related
* [v2 1/2] of: Add vendor prefix for Lattice Semiconductor
From: Joel Holdsworth @ 2016-10-24 4:39 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Joel Holdsworth
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa9..d64a835 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -146,6 +146,7 @@ kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
lantiq Lantiq Semiconductor
+lattice Lattice Semiconductor
lenovo Lenovo Group Ltd.
lg LG Corporation
linux Linux-specific binding
--
2.7.4
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* [PATCH 2/2] fpga: Add support for Lattice iCE40 FPGAs
From: Joel Holdsworth @ 2016-10-24 4:29 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Joel Holdsworth
In-Reply-To: <1477283341-20118-1-git-send-email-joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
and very regular structure, designed for low-cost, high-volume consumer
and system applications.
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.
The iCE40 family is notable because it is the first FPGA family to have
complete reverse engineered bit-stream documentation for the iCE40LP and
iCE40HX devices. Furthermore, there is now a Free Software Verilog
synthesis tool-chain: the "IceStorm" tool-chain.
This project is the work of Clifford Wolf, who is the maintainer of
Yosys Verilog RTL synthesis framework, and Mathias Lasser, with notable
contributions from "Cotton Seed", the main author of "arachne-pnr"; a
place-and-route tool for iCE40 FPGAs.
Having a Free Software synthesis tool-chain offers interesting
opportunities for embedded devices that are able reconfigure themselves
with open firmware that is generated on the device itself. For example
a mobile device might have an application processer with an iCE40 FPGA
attached, which implements slave devices, or through which the processor
communicates with other devices through the FPGA fabric.
A kernel driver for the iCE40 is useful, because in some cases, the FPGA
may need to be configured before other devices can be accessed.
An example of such a device is the icoBOARD; a RaspberryPI HAT which
features an iCE40HX8K with a 1 or 8 MBit SRAM and ports for
Digilent-compatible PMOD modules. A PMOD module may contain a device
with which the kernel communicates, via the FPGA.
---
.../bindings/fpga/lattice-ice40-fpga-mgr.txt | 23 +++
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/ice40spi.c | 212 +++++++++++++++++++++
4 files changed, 242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
create mode 100644 drivers/fpga/ice40spi.c
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
new file mode 100644
index 0000000..b253ac8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
@@ -0,0 +1,23 @@
+Lattice iCE40 FPGA Manager
+
+Required properties:
+- compatible: should contain "lattice,ice40-fpga-mgr"
+- reg: SPI chip select
+- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
+- cdone-gpios: GPIO connected to CDONE pin
+- creset_b-gpios: GPIO connected to CRESET_B pin. Note that CRESET_B is
+ treated as an active-low output because the signal is
+ treated as an enable signal, rather than a reset. This
+ is necessary because the FPGA will enter Master SPI
+ mode and drive SCK with a clock signal, potentially
+ jamming other devices on the bus, unless CRESET_B is
+ held high until the firmware is loaded.
+
+Example:
+ ice40: ice40@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ creset_b-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d614102..85ff429 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -13,6 +13,12 @@ config FPGA
if FPGA
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
config FPGA_MGR_SOCFPGA
tristate "Altera SOCFPGA FPGA Manager"
depends on ARCH_SOCFPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8d83fc6..6c809cc 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
diff --git a/drivers/fpga/ice40spi.c b/drivers/fpga/ice40spi.c
new file mode 100644
index 0000000..ab5ee86
--- /dev/null
+++ b/drivers/fpga/ice40spi.c
@@ -0,0 +1,212 @@
+/*
+ * FPGA Manager Driver for Lattice iCE40.
+ *
+ * Copyright (c) 2016 Joel Holdsworth
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This driver adds support to the FPGA manager for configuring the SRAM of
+ * Lattice iCE40 FPGAs through slave SPI.
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_gpio.h>
+#include <linux/spi/spi.h>
+
+struct ice40_fpga_priv {
+ struct spi_device *dev;
+ struct gpio_desc *creset_b;
+ struct gpio_desc *cdone;
+ enum fpga_mgr_states state;
+};
+
+static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return mgr->state;
+}
+
+static void set_cs(struct spi_device *spi, bool enable)
+{
+ if (gpio_is_valid(spi->cs_gpio))
+ gpio_set_value(spi->cs_gpio, !enable);
+ else if (spi->master->set_cs)
+ spi->master->set_cs(spi, !enable);
+}
+
+static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret;
+
+ if ((flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+ dev_err(&dev->dev,
+ "Partial reconfiguration is not supported\n");
+ return -EINVAL;
+ }
+
+ /* Lock the bus, assert SS_B and CRESET_B */
+ ret = spi_bus_lock(dev->master);
+ if (ret) {
+ dev_err(&dev->dev, "Failed to lock SPI bus, ret: %d\n", ret);
+ return ret;
+ }
+
+ set_cs(dev, 1);
+ gpiod_set_value(priv->creset_b, 1);
+
+ /* Delay for >200ns */
+ udelay(1);
+
+ /* Come out of reset */
+ gpiod_set_value(priv->creset_b, 0);
+
+ /* Check CDONE is de-asserted i.e. the FPGA is reset */
+ if (gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
+ ret = -EIO;
+ }
+
+ /* Wait for the housekeeping to complete */
+ if (!ret)
+ udelay(1200);
+
+ /* Release the SS_B */
+ set_cs(dev, 0);
+ spi_bus_unlock(dev->master);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret;
+
+ ret = spi_write(dev, buf, count);
+ if (ret)
+ dev_err(&dev->dev, "Error sending SPI data, ret: %d\n", ret);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ int ret = 0;
+
+ /* Check CDONE is asserted */
+ if (!gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev,
+ "CDONE was not asserted after firmware transfer\n");
+ return -EIO;
+ }
+
+ /* Send >49-bits of zero-padding to activate the firmware */
+ ret = spi_write(dev, NULL, 7);
+ if (ret) {
+ dev_err(&dev->dev, "Error sending zero padding, ret: %d\n",
+ ret);
+ return ret;
+ }
+
+ /* Success */
+ return 0;
+}
+
+static const struct fpga_manager_ops ice40_fpga_ops = {
+ .state = ice40_fpga_ops_state,
+ .write_init = ice40_fpga_ops_write_init,
+ .write = ice40_fpga_ops_write,
+ .write_complete = ice40_fpga_ops_write_complete,
+};
+
+static int ice40_fpga_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct device_node *np = spi->dev.of_node;
+ struct ice40_fpga_priv *priv;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "No Device Tree entry\n");
+ return -EINVAL;
+ }
+
+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = spi;
+
+ /* Check board setup data. */
+ if (spi->max_speed_hz > 25000000) {
+ dev_err(dev, "speed is too high\n");
+ return -EINVAL;
+ } else if (spi->mode & SPI_CPHA) {
+ dev_err(dev, "bad mode\n");
+ return -EINVAL;
+ }
+
+ /* Set up the GPIOs */
+ priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
+ if (IS_ERR(priv->cdone)) {
+ dev_err(dev, "Failed to get CDONE GPIO: %ld\n",
+ PTR_ERR(priv->cdone));
+ return ret;
+ }
+
+ priv->creset_b = devm_gpiod_get(dev, "creset_b", GPIOD_OUT_HIGH);
+ if (IS_ERR(priv->creset_b)) {
+ dev_err(dev, "Failed to get CRESET_B GPIO: %ld\n",
+ PTR_ERR(priv->creset_b));
+ return ret;
+ }
+
+ /* Register with the FPGA manager */
+ ret = fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
+ &ice40_fpga_ops, priv);
+ if (ret) {
+ dev_err(dev, "unable to register FPGA manager");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ice40_fpga_remove(struct spi_device *spi)
+{
+ fpga_mgr_unregister(&spi->dev);
+ return 0;
+}
+
+static const struct of_device_id ice40_fpga_of_match[] = {
+ { .compatible = "lattice,ice40-fpga-mgr", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
+
+static struct spi_driver ice40_fpga_driver = {
+ .probe = ice40_fpga_probe,
+ .remove = ice40_fpga_remove,
+ .driver = {
+ .name = "ice40spi",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ice40_fpga_of_match),
+ },
+};
+
+module_spi_driver(ice40_fpga_driver);
+
+MODULE_AUTHOR("Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>");
+MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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^ permalink raw reply related
* [PATCH 1/2] of: Add vendor prefix for Lattice Semiconductor
From: Joel Holdsworth @ 2016-10-24 4:29 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Joel Holdsworth
From: Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDBza1y+JCXck5@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa9..d64a835 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -146,6 +146,7 @@ kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
lantiq Lantiq Semiconductor
+lattice Lattice Semiconductor
lenovo Lenovo Group Ltd.
lg LG Corporation
linux Linux-specific binding
--
2.7.4
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^ permalink raw reply related
* Re: FW: [PATCH] mtk-vcodec: fix some smatch warnings
From: Tiffany Lin @ 2016-10-24 3:49 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: daniel.thompson-QSEj5FYQhm4dnm+yROfE0A, Hans Verkuil, Rob Herring,
Matthias Brugger, Daniel Kurtz, Pawel Osciak, Eddie Huang,
Yingjoe Chen, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
PoChun.Lin-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <6D1A1B40F9E1B64689A7C1952F8B336792FED2F0@mtkmbs08n1>
> Fix this bug:
> drivers/media/platform/mtk-vcodec/vdec_drv_if.c:38 vdec_if_init() info: ignoring unreachable code.
>
> With is indeed a real problem that prevents the driver to work!
>
> While here, also remove an used var, as reported by smatch:
>
> drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c: In function 'mtk_vcodec_init_dec_pm':
> drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c:29:17: warning: variable 'dev' set but not used [-Wunused-but-set-variable]
> struct device *dev;
> ^~~
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab-JsYNTwtnfakRB7SZvlqPiA@public.gmane.org>
Acked-by: Tiffany Lin <tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 2 --
> drivers/media/platform/mtk-vcodec/vdec_drv_if.c | 1 +
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> index 18182f5676d8..79ca03ac449c 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> @@ -26,14 +26,12 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev) {
> struct device_node *node;
> struct platform_device *pdev;
> - struct device *dev;
> struct mtk_vcodec_pm *pm;
> int ret = 0;
>
> pdev = mtkdev->plat_dev;
> pm = &mtkdev->pm;
> pm->mtkdev = mtkdev;
> - dev = &pdev->dev;
> node = of_parse_phandle(pdev->dev.of_node, "mediatek,larb", 0);
> if (!node) {
> mtk_v4l2_err("of_parse_phandle mediatek,larb fail!"); diff --git a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c
> index 3cb04ef45144..9813b2ffd5fa 100644
> --- a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c
> +++ b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c
> @@ -31,6 +31,7 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc)
> switch (fourcc) {
> case V4L2_PIX_FMT_H264:
> case V4L2_PIX_FMT_VP8:
> + break;
> default:
> return -EINVAL;
> }
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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^ permalink raw reply
* Re: [PATCH v2 4/4] cpufreq: pxa: convert to clock API
From: Viresh Kumar @ 2016-10-24 3:33 UTC (permalink / raw)
To: Robert Jarzmik
Cc: Daniel Mack, Haojian Zhuang, Rob Herring, Mark Rutland,
Rafael Wysocki, linux-arm-kernel, devicetree, linux-kernel,
linux-pm
In-Reply-To: <877f902hh6.fsf@belgarion.home>
On 22-10-16, 23:37, Robert Jarzmik wrote:
> Viresh Kumar <viresh.kumar@linaro.org> writes:
>
> > On 15-10-16, 21:57, Robert Jarzmik wrote:
> >> As the clock settings have been introduced into the clock pxa drivers,
> >> which are now available to change the CPU clock by themselves, remove
> >> the clock handling from this driver, and rely on pxa clock drivers.
> >>
> >> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
> >> ---
> >> Since v1: added !OF Kconfig dependency
> >> ---
> >> drivers/cpufreq/Kconfig.arm | 2 +-
> >> drivers/cpufreq/pxa2xx-cpufreq.c | 191 ++++++++-------------------------------
> >> 2 files changed, 40 insertions(+), 153 deletions(-)
> >
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>
> Okay, after some more testing, I'd like to remove the !OF for next iteration.
> The reason is that I have a usecase where I have a single kernel image with
> devictree support (ie CONFIG_OF=y), but with support for both devicetree and
> legacy platforms. In this case, a platform such as lubbock can boot :
> - with devicetree
> - with legacy arch/arm/mach-pxa/lubbock.c
>
> In this kernel, the !OF Kconfig prevents the legacy version from working, as
> pxa2xx-cpufreq is descarded even if it is needed in the legacy version.
>
> Therefore, I'd like to respin without this !OF.
I imagined this case last week as well :)
No issues.
--
viresh
^ permalink raw reply
* Re: [PATCH v5 3/9] vcodec: mediatek: Add Mediatek V4L2 Video Decoder Driver
From: Tiffany Lin @ 2016-10-24 3:22 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Hans Verkuil, daniel.thompson, Rob Herring, Matthias Brugger,
Daniel Kurtz, Pawel Osciak, Eddie Huang, Yingjoe Chen, devicetree,
linux-kernel, linux-arm-kernel, linux-media, linux-mediatek,
PoChun.Lin
In-Reply-To: <20161021110104.5733240e@vento.lan>
Hi Mauro,
On Fri, 2016-10-21 at 11:01 -0200, Mauro Carvalho Chehab wrote:
> Em Fri, 2 Sep 2016 20:19:54 +0800
> Tiffany Lin <tiffany.lin@mediatek.com> escreveu:
>
> > Add v4l2 layer decoder driver for MT8173
> >
> > Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
>
> > +int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc)
> > +{
> > + int ret = 0;
> > +
> > + switch (fourcc) {
> > + case V4L2_PIX_FMT_H264:
> > + case V4L2_PIX_FMT_VP8:
> > + default:
> > + return -EINVAL;
> > + }
>
> Did you ever test this driver? The above code will *always* return
> -EINVAL, with will cause vidioc_vdec_s_fmt() to always fail!
>
> I suspect that what you wanted to do, instead, is:
>
> switch (fourcc) {
> case V4L2_PIX_FMT_H264:
> case V4L2_PIX_FMT_VP8:
> break;
> default:
> return -EINVAL;
>
The original idea here is that vp8 and h264 are added in later patches.
If get this patch without later patches, it should return -EINVAL.
> Btw, this patch series has also several issues that were pointed by
> checkpatch. Please *always* run checkpatch when submitting your work.
>
> You should take a look at the Kernel documentation about how to
> submit patches, at:
> https://mchehab.fedorapeople.org/kernel_docs/process/index.html
>
> PS.: this time, I fixed the checkpatch issues for you. So, let me know
> if the patch below is OK, and I'll merge it at media upstream,
> assuming that the other patches in this series are ok.
>
I did run checkpatch, but I don't know why these issues missed.
probably I run checkpatch for all files not for patches.
I will take a look at the documentation and keep this in mind for future
upstream.
Appreciated for your help.
best regards,
Tiffany
^ permalink raw reply
* Re: [PATCH V7 4/4] dmaengine: qcom_hidma: add MSI support for interrupts
From: Sinan Kaya @ 2016-10-24 2:55 UTC (permalink / raw)
To: Andy Shevchenko
Cc: dmaengine, Timur Tabi, devicetree, Christopher Covington,
Vinod Koul, Jon Masters, Andy Gross, Arnd Bergmann, linux-arm-msm,
linux-arm Mailing List, Dan Williams, Dave Jiang,
Lars-Peter Clausen, linux-kernel@vger.kernel.org
In-Reply-To: <CAHp75Vd+u5va3kyqcapeF9JATUfv5gBnoEM_W+frDmMXs5f2Uw@mail.gmail.com>
On 10/21/2016 12:11 PM, Andy Shevchenko wrote:
>> +static void hidma_free_msis(struct hidma_dev *dmadev)
>> > +{
>> > +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
> Perhaps one #ifdef and two definitions of functions?
I don't think it will make a difference. I'll have to move
#ifdef around the caller of hidma_free_msis instead which
I think is uglier.
The hidma_write_msi_msg function gets called only when
CONFIG_GENERIC_MSI_IRQ_DOMAIN is defined. If I don't put
this around the function definition, I get unused function
warning from the compiler. This is the reason why preprocessor
definition is outside of the function definition.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* Re: [PATCH v5 23/23] phy: Add support for Qualcomm's USB HS phy
From: Peter Chen @ 2016-10-24 2:14 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-usb, Felipe Balbi, Arnd Bergmann, Neil Armstrong,
linux-arm-msm, linux-kernel, Bjorn Andersson, devicetree,
Rob Herring, Peter Chen, Andy Gross, Kishon Vijay Abraham I,
linux-arm-kernel
In-Reply-To: <147707842313.25848.12479294741874867656@sboyd-linaro>
On Fri, Oct 21, 2016 at 12:33:43PM -0700, Stephen Boyd wrote:
> Quoting Peter Chen (2016-10-20 19:20:30)
> > On Thu, Oct 20, 2016 at 04:20:38PM -0700, Stephen Boyd wrote:
> > > Quoting Stephen Boyd (2016-10-17 18:56:36)
> > > > +
> > > > +static int
> > > > +qcom_usb_hs_phy_vbus_notifier(struct notifier_block *nb, unsigned long event,
> > > > + void *ptr)
> > > > +{
> > > > + struct qcom_usb_hs_phy *uphy;
> > > > + int is_host;
> > > > + u8 addr;
> > > > +
> > > > + uphy = container_of(nb, struct qcom_usb_hs_phy, vbus_notify);
> > > > + is_host = extcon_get_cable_state_(uphy->id_edev, EXTCON_USB_HOST);
> > >
> > > Please don't apply this patch. This call now deadlocks on v4.9-rc1
> > > because of how extcon_get_cable_state_() now grabs a lock that is
> > > already held here when we're inside the notifier. It's not really
> > > required that we grab the lock in extcon there, but this has exposed a
> > > flaw in the logic anyway. We don't know if the id pin is going to toggle
> > > before or after this function is called, so we should really keep track
> > > of both vbus and id state in this driver and then do the same ulpi
> > > writes from two different notifiers for both vbus and id pin. We would
> > > be duplicating work sometimes, but that's pretty much the best solution
> > > I can come up with. Otherwise it's racy.
> > >
> >
> > Why you need to care id status? If EXTCON_USB event has happened, and
> > event is true, you can set, otherwise, it is clear operation, that's
> > to say you may not need have id extcon phandle, do you think so?
> >
>
> I need to add a comment to the code here because I forgot what was going
> on.
>
> Either way, this code is pulling D+ up when we're in device mode. We
> don't want to do the pullup if we're a host, and vbus extcon only tells
> us if the cable is attached so we can't just rely on that one bit of
> information.
>
> I suppose that's not really appropriate to do via extcon though in the
> phy driver though, so I'm thinking that it should be rewritten to use
> the phy_set_mode() feature of the phy framework. Basically,
> ci_udc_pullup() will call phy_set_mode() with PHY_MODE_USB_DEVICE or
> PHY_MODE_USB_HOST and then we can set or clear these bits in the ulpi
> register space. I think that will make things simpler here and things
> like soft-connect will work better. Sound good?
I agree with you, and you may notify controller role through
phy_set_mode at the controller probe and role switch routine.
--
Best Regards,
Peter Chen
^ permalink raw reply
* RE: [PATCH v2 3/6] arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/
From: Chanho Min @ 2016-10-24 2:00 UTC (permalink / raw)
To: 'Geert Uytterhoeven', 'Rob Herring',
'Mark Rutland', 'Liam Girdwood',
'Mark Brown', 'Patrice Chotard',
'Michael Ellerman'
Cc: devicetree, alsa-devel, linux-arm-kernel, kernel, linuxppc-dev,
linux-kernel, 이건호
In-Reply-To: <1477039877-20227-4-git-send-email-geert+renesas@glider.be>
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2:
> - New.
> ---
Acked-by: Chanho Min <chanho.min@lge.com>
^ permalink raw reply
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