* Re: [PATCH v2 3/3] clocksource: Add clockevent support to NPS400 driver
From: Daniel Lezcano @ 2016-11-01 20:01 UTC (permalink / raw)
To: Noam Camus
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Vineet Gupta
In-Reply-To: <DB6PR0501MB2518720A0F95ACBBBCB1CB27AAAE0-wTfl6qNNZ1PL+HUNrKNnF8DSnupUy6xnnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
On Mon, Oct 31, 2016 at 05:03:40PM +0000, Noam Camus wrote:
> >From: Daniel Lezcano [mailto:daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org]
> >Sent: Monday, October 31, 2016 12:53 PM
>
> >>
> >> The design idea is that for each core there is dedicated regirtser
>
> >s/regirtser/register/
>
> >Hey ! re-read yourself.
> Thanks, I do but sometimes reading over and over and still left with such typos
> Will Fix on next patch Set V4
>
> >> (TSI) serving all 16 HW threads.
> >> The register is a bitmask with one bit for each HW thread.
> >> When HW thread wants that next expiration of timer interrupt will hit
> >> it then the proper bit should be set in this dedicated register.
>
> >I'm not sure to understand this sentence. Do you mean each cpu/thread must
> >set a flag in the TSI register at BIT(phys_id) when they set a timer ?
> Correct, each thread needs to set its bit in TSI register, otherwise the he
> won't be interrupted by timer.
>
> >> When timer expires all HW threads within this core which their bit is
> >> set at the TSI register will be interrupted.
>
> >Does it mean some HW threads will be wake up for nothing ?
> See below after the example you gave
>
> >eg.
>
> >HWT1 sets the timer to expire within 2 seconds
> >HWT2 sets the timer to expire within 2 hours
>
> >When the first timer expires, that will wake up HWT1 *and* HWT2 ?
>
> You are correct, indeed not optimal but much simpler than managing book
> keeping of all 16 threads. Functionality wise one who registered this timer
> will notice that it expired too soon and will register a new one. This is how
> it works now in our machines.
Assuming cpu0 and cpu1 are sibling, does
taskset 0x1 time sleep 2 & taskset 0x2 time sleep 3
give a correct result without a dmesg log ?
Can you give the content of the /proc/timer_list ?
I'm not sure it is safe to have this kind of spurious interrupt for the time
framework.
> >The code is a bit confusing because of the very specific design of this timer.
>
> >Below more questions for clarification.
>
> ...
> >> diff --git a/drivers/clocksource/timer-nps.c
> >> b/drivers/clocksource/timer-nps.c index 6156e54..0757328 100644
> >> --- a/drivers/clocksource/timer-nps.c
> >> +++ b/drivers/clocksource/timer-nps.c
> >> @@ -46,7 +46,7 @@
> >> /* This array is per cluster of CPUs (Each NPS400 cluster got 256
> >> CPUs) */ static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM]
> >> __read_mostly;
> >>
> >> -static unsigned long nps_timer_rate;
> >> +static unsigned long nps_timer1_freq;
> >
> >Why declare a global static variable for a local use in nps_setup_clocksource ?
> Indeed no need. It will be fixed at V4
>
> ...
> >> +/* Timer related Aux registers */
> >> +#define AUX_REG_TIMER0_TSI 0xFFFFF850 /* timer 0 HW threads mask */
> >> +#define NPS_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
> >> +#define NPS_REG_TIMER0_CTRL 0x22 /* timer 0 control */
> >> +#define NPS_REG_TIMER0_CNT 0x21 /* timer 0 count */
> >> +
> >> +#define TIMER0_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
> >> +#define TIMER0_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
>
> >Please, use BIT(nr) macro.
> Will fix that on V4.
>
> >Can you elaborate "Count only when CPU NOT halted" ?
> The Idea here is:
> The Not Halted mode flag (NH) causes cycles to be counted only when the
> processor is running (not halted). When set to 0 the timer will count every
> clock cycle. When set to 1 the timer will only count when the processor is
> running. The NH flag is set to 0 when the processor is Reset.
When is the processor halted ? At idle time ?
There is an inconsistency here:
- If the power management of the CPU allows to power it down and the timer
belongs to the same power domain to the CPU, then it will be powered down
also. In this case, the C3STOP flag must be used and the CPU wakeup must be
delegated to a backup timer.
- If there is no power management on the CPU. The timer must continue to
count cycles in order to wake up the CPU if it is halted (assuming it
is clock gated).
In both cases, TIMER0_CTRL_NH is not needed.
Or is the CPU halted *only* when debugging it ?
> It may be used when working with JTAG (I never used it this way though).
>
> >> +static unsigned long nps_timer0_freq; static unsigned long
> >> +nps_timer0_irq;
> >> +
> >> +/*
> >> + * Arm the timer to interrupt after @cycles */ static void
> >> +nps_clkevent_timer_event_setup(unsigned int cycles) {
> >> + write_aux_reg(NPS_REG_TIMER0_LIMIT, cycles);
> >> + write_aux_reg(NPS_REG_TIMER0_CNT, 0); /* start from 0 */
> >> +
> >> + write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_IE | TIMER0_CTRL_NH);
> >> +}
> >> +
> >> +static void nps_clkevent_rm_thread(bool remove_thread) {
> >> + unsigned int cflags;
> >> + unsigned int enabled_threads;
> >> + unsigned long flags;
> >> + int thread;
> >> +
> >> + local_irq_save(flags);
> >> + hw_schd_save(&cflags);
> >
> >Can you explain why those two lines are needed ?
> The idea is that access to shared core registers (among threads) is not done
> in parallel to keep their consistency. For example Read Modified Write of TSI
> register is not atomic, so using two lines above avoid any interference during
> this code execution.
Mmmh, I'm not used to hardware scheduling. Why hw_schd_save() is needed ?
regmap provides the API to deal with read/write of shared register.
> >> +
> >> +static int nps_clkevent_set_next_event(unsigned long delta,
> >> + struct clock_event_device *dev) {
> >> + struct irq_desc *desc = irq_to_desc(nps_timer0_irq);
> >> + struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data);
> >> +
> >> + nps_clkevent_add_thread(true);
> >> + chip->irq_unmask(&desc->irq_data);
>
> >Can you explain why invoking low level IRQ callbacks is needed here ?
> I needed those callbacks functionality and didn't want to duplicate it here.
If you need these callbacks here, then there is probably an issue with the
driver design.
> >> +
> >> +static int nps_clkevent_set_periodic(struct clock_event_device *dev)
> >> +{
> >> + nps_clkevent_add_thread(false);
> >> + if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0)
> >> + nps_clkevent_timer_event_setup(nps_timer0_freq / HZ);
>
> >Please explain this. I read only CPU0 can set the periodic timer.
> When system works in periodic mode for clock events we just need to set for
> all HW threads within same core their respective bit at TSI register. We also
> need but only once to arm the shared timer control register. Since that for
> each core thread 0 is always available we choose HW thread 0 to do that. ...
I see. Please, add the explanation as a comment in the code.
> >> +static int __init nps_setup_clockevent(struct device_node *node) {
> >> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> >> + struct clk *clk;
>
> >clk = 0xDEADBEEF
> >> + int ret;
> >> +
> >> + nps_timer0_irq = irq_of_parse_and_map(node, 0);
> >> + if (nps_timer0_irq <= 0) {
> >> + pr_err("clockevent: missing irq");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + nps_get_timer_clk(node, &nps_timer0_freq, clk);
> >> +
> >> + /* Needs apriori irq_set_percpu_devid() done in intc map function */
> >> + ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
> >> + "Timer0 (per-cpu-tick)", evt);
> >> + if (ret) {
> >> + pr_err("Couldn't request irq\n");
> >> + clk_disable_unprepare(clk);
>
> >clk is on the stack, hence returning back from the function, clk is
> >undefined.
>
> >clk_disable_unprepare(0xDEADBEEF) ==> kernel panic
>
> >It does not make sense to add the nps_get_timer_clk() function.
>
> >Better to have a couple of duplicated lines and properly rollback from the
> >right place instead of rollbacking supposed actions taken from inside a
> >function.
> As I wrote above I will use **clk for the rollback, so nps_get_timer_clk()
> will make sense and avoid code duplication.
>
> >> + return ret;
> >> + }
> >> +
> >> + ret = cpuhp_setup_state(CPUHP_AP_NPS_TIMER_STARTING,
> >> + "AP_NPS_TIMER_STARTING",
> >> + nps_timer_starting_cpu,
> >> + nps_timer_dying_cpu);
> >> + if (ret) {
> >> + pr_err("Failed to setup hotplug state");
> >> + clk_disable_unprepare(clk);
> >> + return ret;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clkevt, "ezchip,nps400-timer0",
> >> + nps_setup_clockevent);
> >> +#endif /* CONFIG_EZNPS_MTM_EXT */
> >> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> >> index 34bd805..9efc1a3 100644
> >> --- a/include/linux/cpuhotplug.h
> >> +++ b/include/linux/cpuhotplug.h
> >> @@ -60,6 +60,7 @@ enum cpuhp_state {
> >> CPUHP_AP_MARCO_TIMER_STARTING,
> >> CPUHP_AP_MIPS_GIC_TIMER_STARTING,
> >> CPUHP_AP_ARC_TIMER_STARTING,
> >> + CPUHP_AP_NPS_TIMER_STARTING,
>
> >Oops, wait. Here, arch/arc/kernel/time.c should be moved in
> >drivers/clocksource and consolidated with this driver.
>
> >Very likely, CPUHP_AP_ARC_TIMER_STARTING can be used for all ARC timers.
>
> Indeed the ARC timer driver served as my inspiration but due to HW threads
> handling they are not the same. Moving drivers from arch/arc to
> driver/clocksource is not my call (Vineet Gupta is the maintainer of ARC) And
> I think they quiet differ now so consolidation gain is not obvious.
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^ permalink raw reply
* Re: [PATCH v3 0/6] add NS2 support to bgmac
From: Jon Mason @ 2016-11-01 20:01 UTC (permalink / raw)
To: Scott Branden
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli, rafal,
bcm-kernel-feedback-list, netdev, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <cc2554bf-2700-9d9b-b012-15e82681b31b@broadcom.com>
On Tue, Nov 01, 2016 at 11:01:19AM -0700, Scott Branden wrote:
> Hi Jon,
>
> On 16-11-01 10:51 AM, Jon Mason wrote:
> >Changes in v3:
> >* Clean-up the bgmac DT binding doc (per Rob Herring)
> >* Document the lane swap binding and make it generic (Per Andrew Lunn)
> Where is the documentation of the lane swap binding?
Sent out the wrong branch :(
Sending out v4 shortly with this patch.
>
> >
> >
> >Changes in v2:
> >* Remove the PHY power-on (per Andrew Lunn)
> >* Misc PHY clean-ups regarding comments and #defines (per Andrew Lunn)
> > This results on none of the original PHY code from Vikas being
> > present. So, I'm removing him as an author and giving him
> > "Inspired-by" credit.
> >* Move PHY lane swapping to PHY driver (per Andrew Lunn and Florian
> > Fainelli)
> >* Remove bgmac sleep (per Florian Fainelli)
> >* Re-add bgmac chip reset (per Florian Fainelli and Ray Jui)
> >* Rebased on latest net-next
> >* Added patch for bcm54xx_auxctl_read, which is used in the BCM54810
> >
> >
> >Add support for the amac found in the Broadcom Northstar2 SoC to the
> >bgmac driver. This necessitates adding support to connect to an
> >externally defined phy (as described in the device tree) in the driver.
> >These phy changes are in addition to the changes necessary to get NS2
> >working.
> >
> >
> >Jon Mason (6):
> > net: phy: broadcom: add bcm54xx_auxctl_read
> > net: phy: broadcom: Add BCM54810 PHY entry
> > Documentation: devicetree: net: add NS2 bindings to amac
> > net: ethernet: bgmac: device tree phy enablement
> > net: ethernet: bgmac: add NS2 support
> > arm64: dts: NS2: add AMAC ethernet support
> >
> > .../devicetree/bindings/net/brcm,amac.txt | 16 ++--
> > arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 ++
> > arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 +++
> > drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++
> > drivers/net/ethernet/broadcom/bgmac-platform.c | 100 ++++++++++++++++++++-
> > drivers/net/ethernet/broadcom/bgmac.c | 55 ++----------
> > drivers/net/ethernet/broadcom/bgmac.h | 8 ++
> > drivers/net/phy/Kconfig | 2 +-
> > drivers/net/phy/broadcom.c | 68 +++++++++++++-
> > include/linux/brcmphy.h | 11 +++
> > 10 files changed, 268 insertions(+), 57 deletions(-)
> >
^ permalink raw reply
* Re: [PATCH v3 2/6] net: phy: broadcom: Add BCM54810 PHY entry
From: Jon Mason @ 2016-11-01 19:59 UTC (permalink / raw)
To: Andrew Lunn
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree, netdev, linux-kernel, bcm-kernel-feedback-list, rafal,
linux-arm-kernel
In-Reply-To: <20161101184639.GI10785@lunn.ch>
On Tue, Nov 01, 2016 at 07:46:39PM +0100, Andrew Lunn wrote:
> Hi Jon
>
> > @@ -56,6 +57,8 @@
> > #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
> > #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
> > #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
> > +#define PHY_BRCM_EXP_LANE_SWAP 0x00010000
> > +
>
> You define this, but don't use it...
Good catch. Cruft from the last patch. I'll sendout a quick v4 to
address this and the missing Documentation patch.
>
> Andrew
^ permalink raw reply
* Re: [PATCH v12 RESEND 0/4] generic TEE subsystem
From: Andrew F. Davis @ 2016-11-01 19:20 UTC (permalink / raw)
To: Mark Brown
Cc: Jens Wiklander, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Greg Kroah-Hartman, Al Viro,
valentin.manea-hv44wF8Li93QT0dZR+AlfA,
jean-michel.delorme-qxv4g6HH51o, emmanuel.michel-qxv4g6HH51o,
javier-5MUHepqpBA1BDgjK7y7TUQ, Jason Gunthorpe, Mark Rutland,
Michal Simek, Rob Herring, Will Deacon, Arnd Bergmann,
Nishanth Menon
In-Reply-To: <20161028181914.xkse5orwwp42dvj3-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
On 10/28/2016 01:19 PM, Mark Brown wrote:
> On Fri, Oct 28, 2016 at 10:43:24AM -0500, Andrew F. Davis wrote:
>
>> Do we see this as a chicken and egg situation, or is there any harm
>> beyond the pains of supporting an out-of-tree driver for a while, to
>> wait until we have at least one other TEE to add to this subsystem
>> before merging?
>
> We haven't been overburneded with TEE vendors wanting to get their
> driver code into mainline - do we have any reasonable prospect of other
> TEE vendors with an interest in mainline turning up in any kind of
> reasonable timeframe?
>
Doesn't look like anyone has near-term plans for upstreaming non-OPTEE
TEEs, we don't at least (TI), so I guess I see no reason right now to
delay upstreaming of this TEE's driver on the off-chance it is
incompatible with a TEE that may or may not try to get upstreamed later.
I'll redact my objection for now.
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^ permalink raw reply
* Re: [PATCH v3 2/6] net: phy: broadcom: Add BCM54810 PHY entry
From: Andrew Lunn @ 2016-11-01 18:46 UTC (permalink / raw)
To: Jon Mason
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree, netdev, linux-kernel, bcm-kernel-feedback-list, rafal,
linux-arm-kernel
In-Reply-To: <1478022694-25308-3-git-send-email-jon.mason@broadcom.com>
Hi Jon
> @@ -56,6 +57,8 @@
> #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
> #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
> #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
> +#define PHY_BRCM_EXP_LANE_SWAP 0x00010000
> +
You define this, but don't use it...
Andrew
^ permalink raw reply
* RE: [PATCH v3 3/3] clocksource: Add clockevent support to NPS400 driver
From: Thomas Gleixner @ 2016-11-01 18:45 UTC (permalink / raw)
To: Noam Camus
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
daniel.lezcano@linaro.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Chris Metcalf
In-Reply-To: <DB6PR0501MB2518D05EF3EFC35031C16371AAA10@DB6PR0501MB2518.eurprd05.prod.outlook.com>
On Tue, 1 Nov 2016, Noam Camus wrote:
> >> +static int nps_clkevent_set_next_event(unsigned long delta,
> >> + struct clock_event_device *dev) {
> >> + struct irq_desc *desc = irq_to_desc(nps_timer0_irq);
> >> + struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data);
> >> +
> >> + nps_clkevent_add_thread(true);
> >> + chip->irq_unmask(&desc->irq_data);
>
> > Oh no. You are not supposed to fiddle in the guts of the interrupts
> > from a random driver. Can you please explain what you are trying to do
> > and why the existing interfaces are> > not sufficient?
> This function is assigned and used by several hooks at clock_event_device
> type. Main purpose is to support oneshot timer mode and in general
> support NOHZ_FULL and finally TASK_ISOLATION.
What has the fact that you fiddle in the irq desc to do with nohz full and
isolation?
> The idea for this is borrowed from arch/tile timer driver that just like
> us aiming to support the TASK_ISOLATION.
Which does not make it any better.
> Will it be better to replace these with
> irq_percpu_enable()/irq_percpu_disable() which seem to achieve quiet the
> same affect?
Correct. Not using existing functions is always a bad idea.
>
> >> +static int nps_clkevent_set_periodic(struct clock_event_device *dev)
> >> +{
> >> + nps_clkevent_add_thread(false);
> >> + if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0)
> >> + nps_clkevent_timer_event_setup(nps_timer0_freq / HZ);
>
> >So how is that enabling interrupts again?
> I guess that in our system we never switch back to periodic. Time
> infrastructure starts as periodic (I set CLOCK_EVT_FEAT_PERIODIC) and
> when timer is ready state is switched to oneshot mode and never goes back
> to periodic. I might be missing here, but couldn't find any place where
> CLOCK_EVT_STATE_PERIODIC is set but in tick_setup_periodic(). Should I
> call here to enable interrupts anyway?
Right. We never switch back to periodic when we are in one shot mode. So,
you can spare that call.
> >> + ret = cpuhp_setup_state(CPUHP_AP_NPS_TIMER_STARTING,
> >> + "AP_NPS_TIMER_STARTING",
> >
> >Please make this "clockevents/nps:starting"
> Sorry but I can't see any similar thing all around.
> Could you explain why you prefer this format for the string?
Because its way better to read. We messed that up when we started the
conversion and switched over to the more informative strings later. Still
need to fixup the existing state derived strings.
Thanks,
tglx
^ permalink raw reply
* Re: [PATCH V3 1/2] iio: adc: spmi-vadc: Update changes to support reporting of Raw adc code.
From: Jonathan Cameron @ 2016-11-01 18:30 UTC (permalink / raw)
To: Rama Krishna Phani A, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh-DgEjT+Ai2ygdnm+yROfE0A, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
smohanad-sgV2jX0FEOL9JmXXK+q4OQ, mgautam-sgV2jX0FEOL9JmXXK+q4OQ,
sivaa-sgV2jX0FEOL9JmXXK+q4OQ, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
Julia.Lawall-L2FTfq7BK8M
In-Reply-To: <0beb28aa-1726-3046-1652-96f0029fa5dc-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 31/10/16 08:48, Rama Krishna Phani A wrote:
> Hi Jonathan,
>
> On 30-Oct-16 11:05 PM, Jonathan Cameron wrote:
>> On 26/10/16 15:41, Rama Krishna Phani A wrote:
>>> Logic to convert adc code to voltage is generic across all channels.
>>> Different scaling can be done on the obtained voltage to report in physical
>>> units. Implement separate function for generic conversion logic.
>>> Scaling functionality can be changed per channel. Update changes to support
>>> reporting of Raw adc code.
>> Pleas rewrite this description. Perhaps give examples of the changes
>> it makes to what is read from the various attributes?
> There are several channels in the ADC of PMIC which can be used to
> measure voltage, temperature, current etc., Hardware provides
> readings for all channels in adc code. That adc code needs to be
> converted to voltage. The logic for conversion of adc code to voltage
> is common for all ADC channels(voltage, temperature and current
> .,etc). Once voltage is obtained ., scaling is done on that voltage.
>
> For Ex., Thermal SW wants to know the temperature of thermistor on
> PMIC and it expects the temperature to be reported in millidegC. ADC
> channel is used to read the adc code and convert it to voltage. Once
> the voltage is available based on the thermistor spec that voltage is
> mapped to a temperature and then that value is reported to Thermal
> SW.
>
> Mapping of voltage to temperature is called scaling for that channel
> and scaling function can be different per channel based on how the
> voltage is reported.
Is the thermistor always part of the device? (i.e. in the chip) in which
case this might be fine. If it's external then it needs to be described
by a separate device which acts as a consumer of the IIO channel and
in turn provides the scaled output to thermal.
The thermistor should really be separately described. This is already
done in drivers/hwmon/ntc_thermistor
Are any of these scalings characteristics of the chip supported by
this driver, or are they the result of external hardware?
>>
>> I haven't immediately followed what this change is actually doing.
>>
>> I 'think' the point here is to not apply the calibration to
>> the raw adc counts when a true raw read is requested?
>>
> When a true raw read is requested .,Scaling is not applied.
>> There are several unconnected looking changes in here...
>>>
>>> Signed-off-by: Rama Krishna Phani A <rphani-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>> ---
>>> drivers/iio/adc/qcom-spmi-vadc.c | 54 +++++++++++++++++++++-------------------
>>> 1 file changed, 28 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
>>> index c2babe5..ff4d549 100644
>>> --- a/drivers/iio/adc/qcom-spmi-vadc.c
>>> +++ b/drivers/iio/adc/qcom-spmi-vadc.c
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
>>> *
>>> * This program is free software; you can redistribute it and/or modify
>>> * it under the terms of the GNU General Public License version 2 and
>>> @@ -84,7 +84,7 @@
>>> #define VADC_MAX_ADC_CODE 0xa800
>>>
>>> #define VADC_ABSOLUTE_RANGE_UV 625000
>>> -#define VADC_RATIOMETRIC_RANGE_UV 1800000
>>> +#define VADC_RATIOMETRIC_RANGE 1800
>>>
>>> #define VADC_DEF_PRESCALING 0 /* 1:1 */
>>> #define VADC_DEF_DECIMATION 0 /* 512 */
>>> @@ -418,7 +418,7 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
>>> u16 read_1, read_2;
>>> int ret;
>>>
>>> - vadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE_UV;
>>> + vadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
>>> vadc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
>>>
>>> prop = vadc_get_channel(vadc, VADC_REF_1250MV);
>>> @@ -468,21 +468,30 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
>>> return ret;
>>> }
>>>
>>> -static s32 vadc_calibrate(struct vadc_priv *vadc,
>>> - const struct vadc_channel_prop *prop, u16 adc_code)
>>> +static void vadc_scale_calib(struct vadc_priv *vadc, u16 adc_code,
>>> + const struct vadc_channel_prop *prop,
>>> + s64 *scale_voltage)
>>> {
>>> - const struct vadc_prescale_ratio *prescale;
>>> - s64 voltage;
>>> + *scale_voltage = (adc_code -
>>> + vadc->graph[prop->calibration].gnd);
>>> + *scale_voltage *= vadc->graph[prop->calibration].dx;
>>> + *scale_voltage = div64_s64(*scale_voltage,
>>> + vadc->graph[prop->calibration].dy);
>>> + if (prop->calibration == VADC_CALIB_ABSOLUTE)
>>> + *scale_voltage +=
>>> + vadc->graph[prop->calibration].dx;
>>>
>>> - voltage = adc_code - vadc->graph[prop->calibration].gnd;
>>> - voltage *= vadc->graph[prop->calibration].dx;
>>> - voltage = div64_s64(voltage, vadc->graph[prop->calibration].dy);
>>> + if (*scale_voltage < 0)
>>> + *scale_voltage = 0;
>>> +}
>>>
>>> - if (prop->calibration == VADC_CALIB_ABSOLUTE)
>>> - voltage += vadc->graph[prop->calibration].dx;
>>> +static s64 vadc_scale_fn(struct vadc_priv *vadc,
>>> + const struct vadc_channel_prop *prop, u16 adc_code)
>>> +{
>>> + const struct vadc_prescale_ratio *prescale;
>>> + s64 voltage = 0;
>>>
>>> - if (voltage < 0)
>>> - voltage = 0;
>>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>>>
>>> prescale = &vadc_prescale_ratios[prop->prescale];
>>>
>>> @@ -552,11 +561,8 @@ static int vadc_read_raw(struct iio_dev *indio_dev,
>>> if (ret)
>>> break;
>>>
>>> - *val = vadc_calibrate(vadc, prop, adc_code);
>>> + *val = vadc_scale_fn(vadc, prop, adc_code);
>>>
>>> - /* 2mV/K, return milli Celsius */
>>> - *val /= 2;
>>> - *val -= KELVINMIL_CELSIUSMIL;
>>> return IIO_VAL_INT;
>>> case IIO_CHAN_INFO_RAW:
>>> prop = &vadc->chan_props[chan->address];
>>> @@ -564,12 +570,8 @@ static int vadc_read_raw(struct iio_dev *indio_dev,
>>> if (ret)
>>> break;
>>>
>>> - *val = vadc_calibrate(vadc, prop, adc_code);
>>> + *val = (int)adc_code;
>>> return IIO_VAL_INT;
>> So this is 'more raw'.
> Yes., its raw value.
>>> - case IIO_CHAN_INFO_SCALE:
>>> - *val = 0;
>>> - *val2 = 1000;
>>> - return IIO_VAL_INT_PLUS_MICRO;
>>> default:
>>> ret = -EINVAL;
>>> break;
>>> @@ -616,8 +618,8 @@ struct vadc_channels {
>>> VADC_CHAN(_dname, IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre) \
>>>
>>> #define VADC_CHAN_VOLT(_dname, _pre) \
>>> - VADC_CHAN(_dname, IIO_VOLTAGE, \
>>> - BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
>>> + VADC_CHAN(_dname, IIO_VOLTAGE, \
>>> + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED),\
>>> _pre) \
>> It very unusual to report both raw and processed values. Please explain
>> why that is needed here? It may be valid to maintain backwards compatibility
>> of ABI. Which would be fine. However if I read the above correctly you are
>> changing what comes out of reading the raw value so the ABI just changed...
>>
> With the help of IIO sysfs ., we can read the ADC channel readings
> either in RAW format or in processed format. There are two separate
> individual entries to read the ADC channel either in Raw format or in
> processed format. Most of the clients for ADC expect the readings in
> processed format.
If we are talking in kernel, that is worked out by the application of
scale. The IIO in kernel interfaces will do this automatically.
I we are talking in userspace, then the userspace needs to be
extended to support raw and scale reading.
>>
>>> /*
>>> @@ -850,9 +852,9 @@ static int vadc_get_dt_data(struct vadc_priv *vadc, struct device_node *node)
>>>
>>> iio_chan->channel = prop.channel;
>>> iio_chan->datasheet_name = vadc_chan->datasheet_name;
>>> + iio_chan->extend_name = child->name;
>> What's this change?
> We can choose how we want to display our adc channel entries in sysfs. Am using the child node name to be displayed as the sysfs entry rather than channel number for easy interpretation.
>
> For ex: for vcoin(coin battery voltage channel.,) with this change it appears like below in iio adc sysfs
>
> "in_voltage_vcoin_input"
No. This introduces a mass of undocumented (and uncontrolled) ABI.
If there are reasons to add such a label then it should not be done
in the file name.
>
>>> iio_chan->info_mask_separate = vadc_chan->info_mask;
>>> iio_chan->type = vadc_chan->type;
>>> - iio_chan->indexed = 1;
>> Or for that matter this one...
> reason explained above.
>>> iio_chan->address = index++;
>>>
>>> iio_chan++;
>>>
>>
>
> Thanks,
> Ramakrishna
>
> ---
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> https://www.avast.com/antivirus
>
> --
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^ permalink raw reply
* Re: [PATCH v3 0/6] add NS2 support to bgmac
From: Scott Branden @ 2016-11-01 18:01 UTC (permalink / raw)
To: Jon Mason, David Miller, Rob Herring, Mark Rutland,
Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
Hi Jon,
On 16-11-01 10:51 AM, Jon Mason wrote:
> Changes in v3:
> * Clean-up the bgmac DT binding doc (per Rob Herring)
> * Document the lane swap binding and make it generic (Per Andrew Lunn)
Where is the documentation of the lane swap binding?
>
>
> Changes in v2:
> * Remove the PHY power-on (per Andrew Lunn)
> * Misc PHY clean-ups regarding comments and #defines (per Andrew Lunn)
> This results on none of the original PHY code from Vikas being
> present. So, I'm removing him as an author and giving him
> "Inspired-by" credit.
> * Move PHY lane swapping to PHY driver (per Andrew Lunn and Florian
> Fainelli)
> * Remove bgmac sleep (per Florian Fainelli)
> * Re-add bgmac chip reset (per Florian Fainelli and Ray Jui)
> * Rebased on latest net-next
> * Added patch for bcm54xx_auxctl_read, which is used in the BCM54810
>
>
> Add support for the amac found in the Broadcom Northstar2 SoC to the
> bgmac driver. This necessitates adding support to connect to an
> externally defined phy (as described in the device tree) in the driver.
> These phy changes are in addition to the changes necessary to get NS2
> working.
>
>
> Jon Mason (6):
> net: phy: broadcom: add bcm54xx_auxctl_read
> net: phy: broadcom: Add BCM54810 PHY entry
> Documentation: devicetree: net: add NS2 bindings to amac
> net: ethernet: bgmac: device tree phy enablement
> net: ethernet: bgmac: add NS2 support
> arm64: dts: NS2: add AMAC ethernet support
>
> .../devicetree/bindings/net/brcm,amac.txt | 16 ++--
> arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 ++
> arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 +++
> drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++
> drivers/net/ethernet/broadcom/bgmac-platform.c | 100 ++++++++++++++++++++-
> drivers/net/ethernet/broadcom/bgmac.c | 55 ++----------
> drivers/net/ethernet/broadcom/bgmac.h | 8 ++
> drivers/net/phy/Kconfig | 2 +-
> drivers/net/phy/broadcom.c | 68 +++++++++++++-
> include/linux/brcmphy.h | 11 +++
> 10 files changed, 268 insertions(+), 57 deletions(-)
>
^ permalink raw reply
* [PATCH v3 6/6] arm64: dts: NS2: add AMAC ethernet support
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device
tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 +++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 2d7872a..2e4d90d 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -56,6 +56,10 @@
};
};
+&enet {
+ status = "ok";
+};
+
&pci_phy0 {
status = "ok";
};
@@ -172,6 +176,7 @@
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
+ enet-phy-lane-swap;
reg = <0x10>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc40..773ed59 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -191,6 +191,18 @@
#include "ns2-clock.dtsi"
+ enet: ethernet@61000000 {
+ compatible = "brcm,ns2-amac";
+ reg = <0x61000000 0x1000>,
+ <0x61090000 0x1000>,
+ <0x61030000 0x100>;
+ reg-names = "amac_base", "idm_base", "nicpm_base";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ phy-handle = <&gphy0>;
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v3 5/6] net: ethernet: bgmac: add NS2 support
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal-g1n6cQUeyibVItvQsEIGlw,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Add support for the variant of amac hardware present in the Broadcom
Northstar2 based SoCs. Northstar2 requires an additional register to be
configured with the port speed/duplexity (NICPM). This can be added to
the link callback to hide it from the instances that do not use this.
Also, clearing of the pending interrupts on init is required due to
observed issues on some platforms.
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
drivers/net/ethernet/broadcom/bgmac-platform.c | 56 +++++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 3 ++
drivers/net/ethernet/broadcom/bgmac.h | 1 +
3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index aed5dc5..f6d48c7 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -14,12 +14,21 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcma/bcma.h>
+#include <linux/brcmphy.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
+#define NICPM_IOMUX_CTRL 0x00000008
+
+#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
+#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
+#define NICPM_IOMUX_CTRL_SPD_10M 0
+#define NICPM_IOMUX_CTRL_SPD_100M 1
+#define NICPM_IOMUX_CTRL_SPD_1000M 2
+
static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
{
return readl(bgmac->plat.base + offset);
@@ -87,12 +96,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static void bgmac_nicpm_speed_set(struct net_device *net_dev)
+{
+ struct bgmac *bgmac = netdev_priv(net_dev);
+ u32 val;
+
+ if (!bgmac->plat.nicpm_base)
+ return;
+
+ val = NICPM_IOMUX_CTRL_INIT_VAL;
+ switch (bgmac->net_dev->phydev->speed) {
+ default:
+ pr_err("Unsupported speed. Defaulting to 1000Mb\n");
+ case SPEED_1000:
+ val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_100:
+ val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_10:
+ val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ }
+
+ writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
+
+ bgmac_adjust_link(bgmac->net_dev);
+}
+
static int platform_phy_connect(struct bgmac *bgmac)
{
struct phy_device *phy_dev;
- phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
- bgmac_adjust_link);
+ if (bgmac->plat.nicpm_base)
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_nicpm_speed_set);
+ else
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_adjust_link);
if (!phy_dev) {
dev_err(bgmac->dev, "Phy connect failed\n");
return -ENODEV;
@@ -182,6 +225,14 @@ static int bgmac_probe(struct platform_device *pdev)
if (IS_ERR(bgmac->plat.idm_base))
return PTR_ERR(bgmac->plat.idm_base);
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
+ if (regs) {
+ bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
+ regs);
+ if (IS_ERR(bgmac->plat.nicpm_base))
+ return PTR_ERR(bgmac->plat.nicpm_base);
+ }
+
bgmac->read = platform_bgmac_read;
bgmac->write = platform_bgmac_write;
bgmac->idm_read = platform_bgmac_idm_read;
@@ -213,6 +264,7 @@ static int bgmac_remove(struct platform_device *pdev)
static const struct of_device_id bgmac_of_enet_match[] = {
{.compatible = "brcm,amac",},
{.compatible = "brcm,nsp-amac",},
+ {.compatible = "brcm,ns2-amac",},
{},
};
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 4584958..a805cc8 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
static void bgmac_chip_init(struct bgmac *bgmac)
{
+ /* Clear any erroneously pending interrupts */
+ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
+
/* 1 interrupt per received frame */
bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index ea52ac3..b1820ea 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -463,6 +463,7 @@ struct bgmac {
struct {
void *base;
void *idm_base;
+ void *nicpm_base;
} plat;
struct {
struct bcma_device *core;
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 4/6] net: ethernet: bgmac: device tree phy enablement
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
Change the bgmac driver to allow for phy's defined by the device tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++++++++++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 48 +++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 52 ++------------------------
drivers/net/ethernet/broadcom/bgmac.h | 7 ++++
4 files changed, 105 insertions(+), 50 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-bcma.c b/drivers/net/ethernet/broadcom/bgmac-bcma.c
index c16ec3a..3e3efde 100644
--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
@@ -80,6 +80,50 @@ static void bcma_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, u32 mask,
bcma_maskset32(bgmac->bcma.cmn, offset, mask, set);
}
+static int bcma_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+ char bus_id[MII_BUS_ID_SIZE + 3];
+
+ /* Connect to the PHY */
+ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
+ bgmac->phyaddr);
+ phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "PHY connecton failed\n");
+ return PTR_ERR(phy_dev);
+ }
+
+ return 0;
+}
+
+static int bcma_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static const struct bcma_device_id bgmac_bcma_tbl[] = {
BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT,
BCMA_ANY_REV, BCMA_ANY_CLASS),
@@ -275,6 +319,10 @@ static int bgmac_probe(struct bcma_device *core)
bgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = bcma_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32;
+ if (bgmac->mii_bus)
+ bgmac->phy_connect = bcma_phy_connect;
+ else
+ bgmac->phy_connect = bcma_phy_direct_connect;
err = bgmac_enet_probe(bgmac);
if (err)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index be52f27..aed5dc5 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -16,6 +16,7 @@
#include <linux/bcma/bcma.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
+#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
@@ -86,6 +87,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static int platform_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
+ bgmac_adjust_link);
+ if (!phy_dev) {
+ dev_err(bgmac->dev, "Phy connect failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int platform_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static int bgmac_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -102,7 +143,6 @@ static int bgmac_probe(struct platform_device *pdev)
/* Set the features of the 4707 family */
bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
- bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4;
bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP;
bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP;
@@ -151,6 +191,12 @@ static int bgmac_probe(struct platform_device *pdev)
bgmac->cco_ctl_maskset = platform_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = platform_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = platform_bgmac_cmn_maskset32;
+ if (of_parse_phandle(np, "phy-handle", 0)) {
+ bgmac->phy_connect = platform_phy_connect;
+ } else {
+ bgmac->phy_connect = platform_phy_direct_connect;
+ bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
+ }
return bgmac_enet_probe(bgmac);
}
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 856379c..4584958 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1388,7 +1388,7 @@ static const struct ethtool_ops bgmac_ethtool_ops = {
* MII
**************************************************/
-static void bgmac_adjust_link(struct net_device *net_dev)
+void bgmac_adjust_link(struct net_device *net_dev)
{
struct bgmac *bgmac = netdev_priv(net_dev);
struct phy_device *phy_dev = net_dev->phydev;
@@ -1411,50 +1411,7 @@ static void bgmac_adjust_link(struct net_device *net_dev)
phy_print_status(phy_dev);
}
}
-
-static int bgmac_phy_connect_direct(struct bgmac *bgmac)
-{
- struct fixed_phy_status fphy_status = {
- .link = 1,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
- };
- struct phy_device *phy_dev;
- int err;
-
- phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
- if (!phy_dev || IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
- return -ENODEV;
- }
-
- err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (err) {
- dev_err(bgmac->dev, "Connecting PHY failed\n");
- return err;
- }
-
- return err;
-}
-
-static int bgmac_phy_connect(struct bgmac *bgmac)
-{
- struct phy_device *phy_dev;
- char bus_id[MII_BUS_ID_SIZE + 3];
-
- /* Connect to the PHY */
- snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
- bgmac->phyaddr);
- phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "PHY connecton failed\n");
- return PTR_ERR(phy_dev);
- }
-
- return 0;
-}
+EXPORT_SYMBOL_GPL(bgmac_adjust_link);
int bgmac_enet_probe(struct bgmac *info)
{
@@ -1507,10 +1464,7 @@ int bgmac_enet_probe(struct bgmac *info)
netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
- if (!bgmac->mii_bus)
- err = bgmac_phy_connect_direct(bgmac);
- else
- err = bgmac_phy_connect(bgmac);
+ err = bgmac_phy_connect(bgmac);
if (err) {
dev_err(bgmac->dev, "Cannot connect to phy\n");
goto err_dma_free;
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index 80836b4..ea52ac3 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -513,10 +513,12 @@ struct bgmac {
u32 (*get_bus_clock)(struct bgmac *bgmac);
void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
u32 set);
+ int (*phy_connect)(struct bgmac *bgmac);
};
int bgmac_enet_probe(struct bgmac *info);
void bgmac_enet_remove(struct bgmac *bgmac);
+void bgmac_adjust_link(struct net_device *net_dev);
struct mii_bus *bcma_mdio_mii_register(struct bcma_device *core, u8 phyaddr);
void bcma_mdio_mii_unregister(struct mii_bus *mii_bus);
@@ -583,4 +585,9 @@ static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
{
bgmac_maskset(bgmac, offset, ~0, set);
}
+
+static inline int bgmac_phy_connect(struct bgmac *bgmac)
+{
+ return bgmac->phy_connect(bgmac);
+}
#endif /* _BGMAC_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/6] Documentation: devicetree: net: add NS2 bindings to amac
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
Clean-up the documentation to the bgmac-amac driver, per suggestion by
Rob Herring, and add details for NS2 support.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
Documentation/devicetree/bindings/net/brcm,amac.txt | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt
index ba5ecc1..2fefa1a 100644
--- a/Documentation/devicetree/bindings/net/brcm,amac.txt
+++ b/Documentation/devicetree/bindings/net/brcm,amac.txt
@@ -2,11 +2,17 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings
-------------------------------------------------------------
Required properties:
- - compatible: "brcm,amac" or "brcm,nsp-amac"
- - reg: Address and length of the GMAC registers,
- Address and length of the GMAC IDM registers
- - reg-names: Names of the registers. Must have both "amac_base" and
- "idm_base"
+ - compatible: "brcm,amac"
+ "brcm,nsp-amac"
+ "brcm,ns2-amac"
+ - reg: Address and length of the register set for the device. It
+ contains the information of registers in the same order as
+ described by reg-names
+ - reg-names: Names of the registers.
+ "amac_base": Address and length of the GMAC registers
+ "idm_base": Address and length of the GMAC IDM registers
+ "nicpm_base": Address and length of the NIC Port Manager
+ registers (required for Northstar2)
- interrupts: Interrupt number
Optional properties:
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/6] net: phy: broadcom: Add BCM54810 PHY entry
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
The BCM54810 PHY requires some semi-unique configuration, which results
in some additional configuration in addition to the standard config.
Also, some users of the BCM54810 require the PHY lanes to be swapped.
Since there is no way to detect this, add a device tree query to see if
it is applicable.
Inspired-by: Vikas Soni <vsoni@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 58 +++++++++++++++++++++++++++++++++++++++++++++-
include/linux/brcmphy.h | 10 ++++++++
3 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 45f68ea..31967ca 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -217,7 +217,7 @@ config BROADCOM_PHY
select BCM_NET_PHYLIB
---help---
Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
- BCM5481 and BCM5482 PHYs.
+ BCM5481, BCM54810 and BCM5482 PHYs.
config CICADA_PHY
tristate "Cicada PHYs"
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 3a64b3d..b1e32e9 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -18,7 +18,7 @@
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/brcmphy.h>
-
+#include <linux/of.h>
#define BRCM_PHY_MODEL(phydev) \
((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
@@ -45,6 +45,34 @@ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
}
+static int bcm54810_config(struct phy_device *phydev)
+{
+ int rc, val;
+
+ val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
+ val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
+ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
+ val);
+ if (rc < 0)
+ return rc;
+
+ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
+ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
+ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+ val);
+ if (rc < 0)
+ return rc;
+
+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
static int bcm50610_a0_workaround(struct phy_device *phydev)
{
@@ -217,6 +245,12 @@ static int bcm54xx_config_init(struct phy_device *phydev)
(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev);
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
+ err = bcm54810_config(phydev);
+ if (err)
+ return err;
+ }
+
bcm54xx_phydsp_config(phydev);
return 0;
@@ -314,6 +348,7 @@ static int bcm5482_read_status(struct phy_device *phydev)
static int bcm5481_config_aneg(struct phy_device *phydev)
{
+ struct device_node *np = phydev->mdio.dev.of_node;
int ret;
/* Aneg firsly. */
@@ -344,6 +379,14 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
phy_write(phydev, 0x18, reg);
}
+ if (of_property_read_bool(np, "enet-phy-lane-swap")) {
+ /* Lane Swap - Undocumented register...magic! */
+ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
+ 0x11B);
+ if (ret < 0)
+ return ret;
+ }
+
return ret;
}
@@ -578,6 +621,18 @@ static struct phy_driver broadcom_drivers[] = {
.ack_interrupt = bcm_phy_ack_intr,
.config_intr = bcm_phy_config_intr,
}, {
+ .phy_id = PHY_ID_BCM54810,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Broadcom BCM54810",
+ .features = PHY_GBIT_FEATURES |
+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ .config_init = bcm54xx_config_init,
+ .config_aneg = bcm5481_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = bcm_phy_ack_intr,
+ .config_intr = bcm_phy_config_intr,
+}, {
.phy_id = PHY_ID_BCM5482,
.phy_id_mask = 0xfffffff0,
.name = "Broadcom BCM5482",
@@ -661,6 +716,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
{ PHY_ID_BCM54616S, 0xfffffff0 },
{ PHY_ID_BCM5464, 0xfffffff0 },
{ PHY_ID_BCM5481, 0xfffffff0 },
+ { PHY_ID_BCM54810, 0xfffffff0 },
{ PHY_ID_BCM5482, 0xfffffff0 },
{ PHY_ID_BCM50610, 0xfffffff0 },
{ PHY_ID_BCM50610M, 0xfffffff0 },
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 0ed6691..69c7a79 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -13,6 +13,7 @@
#define PHY_ID_BCM5241 0x0143bc30
#define PHY_ID_BCMAC131 0x0143bc70
#define PHY_ID_BCM5481 0x0143bca0
+#define PHY_ID_BCM54810 0x03625d00
#define PHY_ID_BCM5482 0x0143bcb0
#define PHY_ID_BCM5411 0x00206070
#define PHY_ID_BCM5421 0x002060e0
@@ -56,6 +57,8 @@
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
+#define PHY_BRCM_EXP_LANE_SWAP 0x00010000
+
/* Broadcom BCM7xxx specific workarounds */
#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
@@ -111,6 +114,7 @@
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
@@ -192,6 +196,12 @@
#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
+/* BCM54810 Registers */
+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
+#define BCM54810_SHD_CLK_CTL 0x3
+#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
+
/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/6] net: phy: broadcom: add bcm54xx_auxctl_read
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478022694-25308-1-git-send-email-jon.mason@broadcom.com>
Add a helper function to read the AUXCTL register for the BCM54xx. This
mirrors the bcm54xx_auxctl_write function already present in the code.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/phy/broadcom.c | 10 ++++++++++
include/linux/brcmphy.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 583ef8a..3a64b3d 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -30,6 +30,16 @@ MODULE_DESCRIPTION("Broadcom PHY driver");
MODULE_AUTHOR("Maciej W. Rozycki");
MODULE_LICENSE("GPL");
+static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
+{
+ /* The register must be written to both the Shadow Register Select and
+ * the Shadow Read Register Selector
+ */
+ phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
+ regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
+ return phy_read(phydev, MII_BCM54XX_AUX_CTL);
+}
+
static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
{
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 60def78..0ed6691 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -110,6 +110,7 @@
#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/6] add NS2 support to bgmac
From: Jon Mason @ 2016-11-01 17:51 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal-g1n6cQUeyibVItvQsEIGlw,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Changes in v3:
* Clean-up the bgmac DT binding doc (per Rob Herring)
* Document the lane swap binding and make it generic (Per Andrew Lunn)
Changes in v2:
* Remove the PHY power-on (per Andrew Lunn)
* Misc PHY clean-ups regarding comments and #defines (per Andrew Lunn)
This results on none of the original PHY code from Vikas being
present. So, I'm removing him as an author and giving him
"Inspired-by" credit.
* Move PHY lane swapping to PHY driver (per Andrew Lunn and Florian
Fainelli)
* Remove bgmac sleep (per Florian Fainelli)
* Re-add bgmac chip reset (per Florian Fainelli and Ray Jui)
* Rebased on latest net-next
* Added patch for bcm54xx_auxctl_read, which is used in the BCM54810
Add support for the amac found in the Broadcom Northstar2 SoC to the
bgmac driver. This necessitates adding support to connect to an
externally defined phy (as described in the device tree) in the driver.
These phy changes are in addition to the changes necessary to get NS2
working.
Jon Mason (6):
net: phy: broadcom: add bcm54xx_auxctl_read
net: phy: broadcom: Add BCM54810 PHY entry
Documentation: devicetree: net: add NS2 bindings to amac
net: ethernet: bgmac: device tree phy enablement
net: ethernet: bgmac: add NS2 support
arm64: dts: NS2: add AMAC ethernet support
.../devicetree/bindings/net/brcm,amac.txt | 16 ++--
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 ++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 +++
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 100 ++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 55 ++----------
drivers/net/ethernet/broadcom/bgmac.h | 8 ++
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 68 +++++++++++++-
include/linux/brcmphy.h | 11 +++
10 files changed, 268 insertions(+), 57 deletions(-)
--
2.7.4
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^ permalink raw reply
* Re: [PATCH] clk: cdce925: add support for CDCE913, CDCE937, and CDCE949
From: Stephen Boyd @ 2016-11-01 17:48 UTC (permalink / raw)
To: Akinobu Mita
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, open list:OPEN FIRMWARE AND...,
Mike Looijmans, Michael Turquette
In-Reply-To: <CAC5umyiVcV_KEL+g=mRL-mGQfJrCU5XrEVNzX=CFFXWNuTMBGQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 11/01, Akinobu Mita wrote:
> 2016-11-01 3:15 GMT+09:00 Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>:
> > On 10/31, Akinobu Mita wrote:
> >> @@ -728,13 +780,19 @@ static int cdce925_probe(struct i2c_client *client,
> >> }
> >>
> >> static const struct i2c_device_id cdce925_id[] = {
> >> - { "cdce925", 0 },
> >> + { "cdce913", CDCE913 },
> >> + { "cdce925", CDCE925 },
> >> + { "cdce937", CDCE937 },
> >> + { "cdce949", CDCE949 },
> >> { }
> >> };
> >> MODULE_DEVICE_TABLE(i2c, cdce925_id);
> >>
> >> static const struct of_device_id clk_cdce925_of_match[] = {
> >> + { .compatible = "ti,cdce913" },
> >> { .compatible = "ti,cdce925" },
> >> + { .compatible = "ti,cdce937" },
> >> + { .compatible = "ti,cdce949" },
> >
> > Doesn't this need to be updated to point to the correct enum
> > values?
>
> I think it isn't needed. Because the data field in struct of_device_id
> for this driver is not used even if the device is registered from
> device tree. But the driver_data in i2c_device_id is used instead.
Ok. Have you tested this driver with DT or platform data? Do you
prefix the compatible string with "ti," in the DT case?
--
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^ permalink raw reply
* [PATCH] dt-bindings: Add vendor prefix for Udoo
From: Fabio Estevam @ 2016-11-01 17:40 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
devicetree-u79uwXL29TY76Z2rM5mHXA, Fabio Estevam
Udoo (http://www.udoo.org/) manufactures development boards based on
i.MX and x86.
Signed-off-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c8ae586..a9af542 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -295,6 +295,7 @@ tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
tyan Tyan Computer Corporation
+udoo Udoo
uniwest United Western Technologies Corp (UniWest)
upisemi uPI Semiconductor Corp.
urt United Radiant Technology Corporation
--
2.7.4
--
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* [PATCH v2 5/5] ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161101171006.24594-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
Therefore aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index b0b3220..34887a1 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -229,7 +229,7 @@
};
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -238,7 +238,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -247,7 +247,7 @@
status = "okay";
};
- backlight_lvds1: backlight_lvds1 {
+ backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -282,7 +282,7 @@
};
};
- panel_lcd {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -293,7 +293,7 @@
};
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -304,7 +304,7 @@
};
};
- panel_lvds1 {
+ panel-lvds1 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds1>;
@@ -447,7 +447,7 @@
};
&iomuxc {
- imx6q-nitrogen6_max {
+ imx6q-nitrogen6-max {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
@@ -504,7 +504,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -720,7 +720,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
--
2.9.3
--
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* [PATCH v2 4/5] ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161101171006.24594-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
Therefore aligning the panel nodes name across all platforms.
Also removing the bt_rfkill node since the mainline rfkill-gpio driver
doesn't support device trees.
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 32 +++++---------------------------
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 880bd78..63acd54 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -97,15 +97,6 @@
};
};
- bt_rfkill {
- compatible = "rfkill-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt_rfkill>;
- gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
- name = "bt_rfkill";
- type = <2>;
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -160,7 +151,7 @@
};
};
- backlight_lcd {
+ backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -169,7 +160,7 @@
status = "okay";
};
- backlight_lvds0: backlight_lvds0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -178,7 +169,7 @@
status = "okay";
};
- panel_lvds0 {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@@ -328,19 +319,6 @@
>;
};
- pinctrl_bt_rfkill: bt_rfkillgrp {
- fsl,pins = <
- /* BT wake */
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- /* BT reset */
- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0
- /* BT reg en */
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
- /* BT host wake irq */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0
- >;
- };
-
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
@@ -374,7 +352,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Home Button: J14 pin 5 */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
@@ -457,7 +435,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
>;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 3/5] ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161101171006.24594-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
Also aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index db868bc..e476d01 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -167,7 +167,7 @@
mux-ext-port = <3>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -176,7 +176,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -211,7 +211,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -222,7 +222,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -413,7 +413,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -561,7 +561,7 @@
>;
};
- pinctrl_wlan_vmmc: wlan_vmmcgrp {
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 2/5] ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161101171006.24594-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
Also aligning the panel nodes name across all platforms.
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 81dd6cd..1f9076e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -153,7 +153,7 @@
mux-ext-port = <4>;
};
- backlight_lcd: backlight_lcd {
+ backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -162,7 +162,7 @@
status = "okay";
};
- backlight_lvds: backlight_lvds {
+ backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -197,7 +197,7 @@
};
};
- lcd_panel {
+ panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@@ -208,7 +208,7 @@
};
};
- panel {
+ panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@@ -378,7 +378,7 @@
>;
};
- pinctrl_gpio_keys: gpio_keysgrp {
+ pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 1/5] ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161101171006.24594-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
SoM based on i.MX6 Quad with 1GB of DDR3.
https://boundarydevices.com/product/nit6x-som-v2/
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 53 ++
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 770 ++++++++++++++++++++++++++
3 files changed, 824 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 224e2a5..0572d68 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -387,6 +387,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
+ imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
new file mode 100644
index 0000000..cf4feef
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-nitrogen6_som2.dtsi"
+
+/ {
+ model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board";
+ compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
new file mode 100644
index 0000000..d80f21a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -0,0 +1,770 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lcd: backlight-lcd {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ backlight_lvds1: backlight-lvds1 {
+ compatible = "gpio-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_lvds1>;
+ gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ default-on;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ menu {
+ label = "Menu";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ };
+
+ home {
+ label = "Home";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ back {
+ label = "Back";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_j15>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel-lcd {
+ compatible = "okaya,rs800480t-7x0gp";
+ backlight = <&backlight_lcd>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ panel-lvds0 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds0>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel-lvds1 {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds1>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_can_xcvr: regulator-can-xcvr {
+ compatible = "regulator-fixed";
+ regulator-name = "CAN XCVR";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_xcvr>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_wlan_vmmc: regulator-wlan-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan_vmmc>;
+ regulator-name = "reg_wlan_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-nitrogen6_som2-sgtl5000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <®_can_xcvr>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ compatible = "microchip,sst25vf016b";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ rtc@68 {
+ compatible = "st,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ touchscreen@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_backlight_lvds1: backlight-lvds1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0
+ >;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_can_xcvr: can-xcvrgrp {
+ fsl,pins = <
+ /* Flexcan XCVR enable */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ /* Power Button */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ /* Menu Button */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ /* Home Button */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ /* Back Button */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ /* Volume Up Button */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
+ /* Volume Down Button */
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ /* PCIe I2C enable */
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
+ >;
+ };
+
+ pinctrl_j15: j15grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ /* PCIe reset */
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1
+ >;
+ };
+
+ pinctrl_rv4162: rv4162grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+ /* power enable, high active */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wlan_vmmc: wlan-vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0
+ MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
+ >;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wlan_vmmc>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <®_1p8v>;
+ keep-power-in-suspend;
+ status = "okay";
+};
--
2.9.3
--
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* [PATCH v2 0/5] ARM: dts: imx: update Boundary Devices boards support
From: Gary Bisson @ 2016-11-01 17:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
fabio.estevam-KZfg59tc24xl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-lFZ/pmaqli7XmaaqVzeoHQ, Gary Bisson
In-Reply-To: <20161025211955.5345-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
Hi all,
This series includes several patches to update the support for our platforms.
Here are the main goals of this series:
1- Adding support for our latest SOM (SOM2)
2- Replace underscores in nodes name
3- Fix panel naming consistency across the boards
Changelog v1->v2:
- Drop the USB PHY reset changes, waiting for Peter's series [1] to get in.
- Replace underscores in nodes name
Let me know if you have any question.
Regards,
Gary
[1] https://www.spinics.net/lists/arm-kernel/msg536105.html
Gary Bisson (5):
ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support
ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name
ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name
ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name
ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 53 ++
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 32 +-
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 18 +-
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 770 ++++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 12 +-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 10 +-
7 files changed, 849 insertions(+), 47 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
--
2.9.3
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^ permalink raw reply
* Re: [PATCH/RESEND V4 2/3] ARM64 LPC: Add missing range exception for special ISA
From: Bjorn Helgaas @ 2016-11-01 16:59 UTC (permalink / raw)
To: zhichang.yuan
Cc: catalin.marinas, will.deacon, robh+dt, bhelgaas, mark.rutland,
arnd, linux-arm-kernel, lorenzo.pieralisi, linux-kernel, linuxarm,
devicetree, linux-pci, linux-serial, minyard, benh, liviu.dudau,
zourongrong, john.garry, gabriele.paoloni, zhichang.yuan02,
kantyzc, xuwei5
In-Reply-To: <1478006926-240933-3-git-send-email-yuanzhichang@hisilicon.com>
On Tue, Nov 01, 2016 at 09:28:45PM +0800, zhichang.yuan wrote:
> Currently if the range property is not specified of_translate_one
> returns an error. There are some special devices that work on a
> range of I/O ports where it's is not correct to specify a range
> property as the cpu addresses are used by special accessors.
> Here we add a new exception in of_translate_one to return
> the cpu address if the range property is not there. The exception
> checks if the parent bus is ISA and if the special accessors are
> defined.
Using "()" after function names helps distinguish them from text.
s/it's is/it's/
I haven't been paying attention, so I missed the context. But "as the
cpu addresses are used by special accessors" doesn't really make sense
to me. In general, *most* acccessors use CPU addresses, i.e.,
resource addresses. Accessors don't use bus addresses because we may
have multiple instances of a bus, and we may reuse bus address ranges
on the different instances.
In the patch, I see a check for "parent bus is ISA"
("of_bus_isa_match(parent)"), but I don't see the check for whether
the special accessors are defined, so I can't quite connect the dots.
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
> ---
> arch/arm64/include/asm/io.h | 7 +++++++
> arch/arm64/kernel/extio.c | 24 +++++++++++++++++++++++
> drivers/of/address.c | 47 +++++++++++++++++++++++++++++++++++++++++++--
> drivers/pci/pci.c | 6 +++---
> include/linux/of_address.h | 17 ++++++++++++++++
> 5 files changed, 96 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> index 136735d..e480199 100644
> --- a/arch/arm64/include/asm/io.h
> +++ b/arch/arm64/include/asm/io.h
> @@ -175,6 +175,13 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
> #define outsl outsl
>
> DECLARE_EXTIO(l, u32)
> +
> +
> +#define indirect_io_ison indirect_io_ison
> +extern int indirect_io_ison(void);
This makes it look like "ison" is some new word I'm not familiar with.
"indirect_io_is_on()" or even "indirect_io_enabled()" would be more
readable.
> +
> +#define chk_indirect_range chk_indirect_range
> +extern int chk_indirect_range(u64 taddr);
> #endif
>
>
> diff --git a/arch/arm64/kernel/extio.c b/arch/arm64/kernel/extio.c
> index 80cafd5..55df8dc 100644
> --- a/arch/arm64/kernel/extio.c
> +++ b/arch/arm64/kernel/extio.c
> @@ -19,6 +19,30 @@
>
> struct extio_ops *arm64_extio_ops;
>
> +/**
> + * indirect_io_ison - check whether indirectIO can work well. This function only call
> + * before the target I/O address was obtained.
> + *
> + * Returns 1 when indirectIO can work.
> + */
> +int indirect_io_ison()
> +{
> + return arm64_extio_ops ? 1 : 0;
> +}
> +
> +/**
> + * check_indirect_io - check whether the input taddr is for indirectIO.
Comment name ("check_indirect_io") doesn't match actual function name
("chk_indirect_range").
One of my pet peeves: "check" is completely worthless as part of a
function name because it doesn't help the reader figure out the sense
of the result. What does a "true" result mean? Name it something
like "address_is_indirect()" so it reads naturally when the caller
does something like "if (address_is_indirect())"
> + * @taddr: the io address to be checked.
> + *
> + * Returns 1 when taddr is in the range; otherwise return 0.
> + */
> +int chk_indirect_range(u64 taddr)
> +{
> + if (arm64_extio_ops->start > taddr || arm64_extio_ops->end < taddr)
> + return 0;
> +
> + return 1;
> +}
>
> BUILD_EXTIO(b, u8)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 02b2903..0bee822 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -479,6 +479,39 @@ static int of_empty_ranges_quirk(struct device_node *np)
> return false;
> }
>
> +
> +/*
> + * Check whether the current device being translating use indirectIO.
What does "the current device" mean? I assume you're talking about
"any device on 'bus'"? And apparently the caller is inquiring about a
particular address, too?
> + * return 1 if the check is past, or 0 represents fail checking.
This doesn't really make sense. I assume you mean something like
"return 1 if 'address' uses indirectIO; 0 otherwise"?
> + */
> +static int of_isa_indirect_io(struct device_node *parent,
> + struct of_bus *bus, __be32 *addr,
> + int na, u64 *presult)
> +{
> + unsigned int flags;
> + unsigned int rlen;
> +
> + /* whether support indirectIO */
> + if (!indirect_io_ison())
> + return 0;
> +
> + if (!of_bus_isa_match(parent))
> + return 0;
> +
> + flags = bus->get_flags(addr);
> + if (!(flags & IORESOURCE_IO))
> + return 0;
> +
> + /* there is ranges property, apply the normal translation directly. */
> + if (of_get_property(parent, "ranges", &rlen))
> + return 0;
> +
> + *presult = of_read_number(addr + 1, na - 1);
> +
> + return chk_indirect_range(*presult);
> +}
> +
> static int of_translate_one(struct device_node *parent, struct of_bus *bus,
> struct of_bus *pbus, __be32 *addr,
> int na, int ns, int pna, const char *rprop)
> @@ -532,7 +565,7 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
> }
> memcpy(addr, ranges + na, 4 * pna);
>
> - finish:
> +finish:
> of_dump_addr("parent translation for:", addr, pna);
> pr_debug("with offset: %llx\n", (unsigned long long)offset);
>
> @@ -595,6 +628,15 @@ static u64 __of_translate_address(struct device_node *dev,
> result = of_read_number(addr, na);
> break;
> }
> + /*
> + * For indirectIO device which has no ranges property, get
> + * the address from reg directly.
> + */
> + if (of_isa_indirect_io(dev, bus, addr, na, &result)) {
> + pr_info("isa indirectIO matched(%s)..addr = 0x%llx\n",
> + of_node_full_name(dev), result);
> + break;
> + }
>
> /* Get new parent bus and counts */
> pbus = of_match_bus(parent);
> @@ -688,8 +730,9 @@ static int __of_address_to_resource(struct device_node *dev,
> if (taddr == OF_BAD_ADDR)
> return -EINVAL;
> memset(r, 0, sizeof(struct resource));
> - if (flags & IORESOURCE_IO) {
> + if (flags & IORESOURCE_IO && taddr >= PCIBIOS_MIN_IO) {
> unsigned long port;
> +
> port = pci_address_to_pio(taddr);
> if (port == (unsigned long)-1)
> return -EINVAL;
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index ba34907..1a08511 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -3263,7 +3263,7 @@ int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
>
> #ifdef PCI_IOBASE
> struct io_range *range;
> - resource_size_t allocated_size = 0;
> + resource_size_t allocated_size = PCIBIOS_MIN_IO;
I don't understand what's going on here. PCIBIOS_MIN_IO is an
*address*, so you're setting a *size* to an address. Maybe this just
needs an explanation. The connection to the rest of this patch isn't
obvious. If it could be split to a separate patch, so much the
better; then you'd have a nice place to describe it.
> /* check if the range hasn't been previously recorded */
> spin_lock(&io_range_lock);
> @@ -3312,7 +3312,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
>
> #ifdef PCI_IOBASE
> struct io_range *range;
> - resource_size_t allocated_size = 0;
> + resource_size_t allocated_size = PCIBIOS_MIN_IO;
>
> if (pio > IO_SPACE_LIMIT)
> return address;
> @@ -3335,7 +3335,7 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address)
> {
> #ifdef PCI_IOBASE
> struct io_range *res;
> - resource_size_t offset = 0;
> + resource_size_t offset = PCIBIOS_MIN_IO;
> unsigned long addr = -1;
>
> spin_lock(&io_range_lock);
> diff --git a/include/linux/of_address.h b/include/linux/of_address.h
> index 3786473..0ba7e21 100644
> --- a/include/linux/of_address.h
> +++ b/include/linux/of_address.h
> @@ -24,6 +24,23 @@ struct of_pci_range {
> #define for_each_of_pci_range(parser, range) \
> for (; of_pci_range_parser_one(parser, range);)
>
> +
> +#ifndef indirect_io_ison
> +#define indirect_io_ison indirect_io_ison
> +static inline int indirect_io_ison(void)
> +{
> + return 0;
> +}
> +#endif
> +
> +#ifndef chk_indirect_range
> +#define chk_indirect_range chk_indirect_range
> +static inline int chk_indirect_range(u64 taddr)
> +{
> + return 0;
> +}
> +#endif
> +
> /* Translate a DMA address from device space to CPU space */
> extern u64 of_translate_dma_address(struct device_node *dev,
> const __be32 *in_addr);
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 2/6] net: phy: broadcom: Add BCM54810 PHY entry
From: Andrew Lunn @ 2016-11-01 16:48 UTC (permalink / raw)
To: Jon Mason
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
rafal-g1n6cQUeyibVItvQsEIGlw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161101164337.GA19654-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> I'll make the generic string be "enet-phy-lane-swap" (without the
> previous "brcm"), and add the flag to phy.txt to document it.
Great.
Please be quite verbose as to what it means.
Thanks
Andrew
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