* Re: [PATCH V4] pinctrl: qcom: Add msm8994 pinctrl driver
From: Stephen Boyd @ 2016-11-01 23:53 UTC (permalink / raw)
To: Michael Scott
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Linus Walleij, Rob Herring,
Mark Rutland, Andy Gross, David Brown, Bjorn Andersson,
Joonwoo Park, Jeremy McNicoll
In-Reply-To: <20161031160009.20472-1-michael.scott-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 10/31, Michael Scott wrote:
> +
> +static const struct msm_pingroup msm8994_groups[] = {
> + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA,
> + NA, NA),
I see an hdmi_rcv group here after blsp_uim1. Please add it for
this gpio.
> + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti_trig_out_b,
> + NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti_trig_in_b, NA,
The qdss_cti_* is in function 5 for both of these, not function
4.
> + NA, NA, NA, NA, NA, NA),
> + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA,
> + NA, NA, NA, NA, NA),
> + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA,
> + NA, NA, NA, NA, NA),
> + PINGROUP(10, mdp_vsync, blsp_spi3, blsp_uart3, blsp_i2c3,
> + blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
> + PINGROUP(11, mdp_vsync, blsp_spi3, blsp_uart3, blsp_i2c3,
> + blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
> + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(13, cam_mclk0, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(14, cam_mclk1, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(15, cam_mclk2, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(16, cam_mclk3, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(17, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA,
> + qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(18, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA,
> + qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(19, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA,
> + qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(20, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA,
> + NA, NA, NA, NA),
> + PINGROUP(21, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA,
> + qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(22, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA,
> + qdss_tracedata_b, NA, NA, NA, NA, NA),
> + PINGROUP(23, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA,
> + qdss_tracedata_b, NA, NA, NA, NA),
> + PINGROUP(24, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5,
> + blsp_i2c5, NA, NA, NA, NA, NA, NA),
> + PINGROUP(25, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6,
> + blsp_uim6, NA, NA, qdss_tracedata_b, NA, NA, NA),
> + PINGROUP(26, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, gp0_clk,
> + NA, qdss_tracedata_b, NA, NA, NA, NA),
> + PINGROUP(27, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk,
> + qdss_tracectl_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(28, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_a, NA,
> + NA, NA, NA, NA, NA, NA),
> + PINGROUP(29, gp_mn, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(35, uim3, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(36, uim3, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(37, uim3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(38, uim3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(41, blsp_spi7, blsp_uart7, blsp_uim7, qdss_cti_trig_out_c,
> + NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(42, blsp_spi7, blsp_uart7, blsp_uim7, qdss_cti_trig_in_c, NA,
> + NA, NA, NA, NA, NA, NA),
> + PINGROUP(43, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(44, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA,
> + NA, NA, NA, NA, NA),
> + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA,
> + NA, NA, NA, NA, NA),
> + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(53, uim4, pci_e0, blsp_spi10, blsp_uart10, blsp_uim10, NA,
> + NA, NA, NA, qdss_tracedata_a, NA),
qdss_tracedata_a is at function 8.
> + PINGROUP(54, uim4, pci_e0, blsp_spi10, blsp_uart10, blsp_uim10,
> + gp_pdm0, NA, NA, NA, NA, qdss_tracedata_a),
qdss_tracedata_a is at function 9.
> + PINGROUP(55, uim4, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA,
> + NA, NA, qdss_cti_trig_in_a, NA),
qdss_cti_trig_in_a is at function 8.
> + PINGROUP(56, uim4, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA,
> + NA, qdss_cti_trig_out_a, NA, NA),
qdss_cti_trig_out_a is at function 7.
> + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
qdss_tracedata_b is at function 5.
> + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, qdss_tracedata_b,
> + NA, NA, NA, NA),
qdss_tracedata_b is at function 5.
> + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA, NA,
> + qdss_tracedata_a, NA, NA),
> + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, NA,
> + NA, NA),
> + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, NA,
> + NA, NA),
qdss_tracedata_a is at function 5 for both of the above.
> + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA,
> + qdss_tracedata_a, NA, NA, NA),
> + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA,
> + qdss_tracedata_a, NA, NA, NA),
qdss_tracedata_a is at function 6 for both of the above.
> + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
Perahps *_mi2s should just be *_i2s here. I don't see any m except for
mclk, which means master and sometimes there are sck for slaves
here.
> + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA, qdss_tracedata_a,
These have mi2s though which is fine. Also qdss_tracedata_a is at
function 6.
> + NA, NA, NA),
> + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
> + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA,
> + NA, NA),
qdss_tracedata_a is at function 4 for the above 3 gpios.
> + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11,
> + gcc_gp_clk2, NA, NA, NA, NA, NA, NA),
> + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11,
> + gcc_gp_clk3, NA, NA, NA, NA, NA, NA),
I'd do gcc_gp3_clk and gcc_gp2_clk instead. The number is on the
GP instance. Also, we have _a and _b in the 8996 driver, which
should be copied into here?
> + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA,
> + qdss_tracedata_a, NA, NA, NA, NA, NA),
> + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA,
> + qdss_tracedata_a, NA, NA, NA, NA, NA),
> + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA,
> + qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
> + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA, NA,
> + NA, NA, NA),
> + PINGROUP(89, tsif1, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(90, tsif1, blsp_spi10_cs3, qdss_tracedata_a, NA, NA, NA, NA,
> + NA, NA, NA, NA),
> + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, qdss_traceclk_b, NA, NA, NA,
> + NA),
> + PINGROUP(92, tsif2, sdc4, NA, NA, qdss_tracedata_b, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, qdss_tracedata_b, NA, NA,
> + NA, NA),
> + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, qdss_tracectl_b, NA, NA, NA,
> + NA),
> + PINGROUP(95, tsif2, sdc4, gp_pdm0, NA, NA, NA, qdss_cti_trig_out_d,
> + NA, NA, NA, NA),
> + PINGROUP(96, tsif2, sdc4, qdss_cti_trig_in_d, NA, NA, NA, NA, NA, NA,
> + NA, NA),
> + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(110, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(111, tsif1, blsp11_uart_tx_b, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(112, blsp11_uart_rx_b, NA, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(113, blsp11_i2c_sda_b, NA, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(114, blsp11_i2c_scl_b, NA, NA, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(115, grfc, rffe6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(116, grfc, rffe6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(117, grfc, rffe7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(118, grfc, rffe7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(126, grfc, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(127, grfc, nav_tsync, nav_pps, NA, NA, NA, NA, NA, NA, NA,
> + NA),
> + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(129, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(130, gps_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(131, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(132, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(133, gsm_tx, grfc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(134, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(135, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(136, rffe1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(137, rffe1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(138, rffe2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(139, rffe2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(140, rffe3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(141, rffe3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(142, rffe4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(143, rffe4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(144, rffe5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> + PINGROUP(145, rffe5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
We've typically left out rffe*, and grfc from this driver. I'd
just leave them out here as well.
> + SDC_PINGROUP(sdc1_rclk, 0x2044, 15, 0),
> + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
> + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
> + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
> + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
> + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
> + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
> + SDC_PINGROUP(sdc3_clk, 0x206c, 14, 6),
> + SDC_PINGROUP(sdc3_cmd, 0x206c, 11, 3),
> + SDC_PINGROUP(sdc3_data, 0x206c, 9, 0),
> +};
> +
> +#define NUM_GPIO_PINGROUPS 146
> +
> +static const struct msm_pinctrl_soc_data msm8994_pinctrl = {
> + .pins = msm8994_pins,
> + .npins = ARRAY_SIZE(msm8994_pins),
> + .functions = msm8994_functions,
> + .nfunctions = ARRAY_SIZE(msm8994_functions),
> + .groups = msm8994_groups,
> + .ngroups = ARRAY_SIZE(msm8994_groups),
> + .ngpios = NUM_GPIO_PINGROUPS,
> +};
> +
> +static int msm8994_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &msm8994_pinctrl);
> +}
> +
> +static const struct of_device_id msm8994_pinctrl_of_match[] = {
> + { .compatible = "qcom,msm8992-pinctrl", },
> + { .compatible = "qcom,msm8994-pinctrl", },
> + { },
Nitpick: this comma can be removed because this list shouldn't
have any elements after this terminator.
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^ permalink raw reply
* [PATCH] ARM: dts: imx6: Add imx-weim parameters to dtsi's
From: Joshua Clayton @ 2016-11-01 23:51 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Mark Rutland,
Russell King,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: Joshua Clayton
imx-weim should always set address-cells to 2,
and size_cells to 1.
On imx6, fsl,weim-cs-gpr will always be &gpr
Set these common parameters in the dtsi file,
rather than in a downstream dts.
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
arch/arm/boot/dts/imx6q-evi.dts | 3 ---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 --
arch/arm/boot/dts/imx6qdl.dtsi | 3 +++
arch/arm/boot/dts/imx6sl.dtsi | 3 +++
arch/arm/boot/dts/imx6sx.dtsi | 3 +++
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index bd0b85c..a88cbd8 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -241,10 +241,7 @@
};
&weim {
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
- fsl,weim-cs-gpr = <&gpr>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 8006467..52390ba 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -613,8 +613,6 @@
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 1bbd36f..d7bed1f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1092,10 +1092,13 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 02378db..c2b28c0 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -893,8 +893,11 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 9526c38..78eb023 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -968,10 +968,13 @@
};
weim: weim@021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
From: Heiko Stübner @ 2016-11-01 23:30 UTC (permalink / raw)
To: Ziyuan Xu
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
zhengsq-TNX95d0MmH7DzftRWevZcw, zyw-TNX95d0MmH7DzftRWevZcw,
finley.xiao-TNX95d0MmH7DzftRWevZcw,
dianders-F7+t8E8rja9g9hUCZPvPmw
In-Reply-To: <20161030025725.32155-1-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Am Sonntag, 30. Oktober 2016, 10:57:25 schrieb Ziyuan Xu:
> There is a 'cpu-id' field in efuse, export it for other drivers
> reference.
>
> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 76b2864..71c3ce7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1023,6 +1023,9 @@
> clock-names = "pclk_efuse";
>
> /* Data cells */
> + cpu_id: cpu-id {
I've added the address, so this gets to be cpu_id: cpu-id@7 to make it
compliant and applied the result to my dts64 branch for 4.10
Thanks
Heiko
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^ permalink raw reply
* Re: [PATCH v8 1/3] ARM: dts: da850: Add cfgchip syscon node
From: David Lechner @ 2016-11-01 23:12 UTC (permalink / raw)
To: Sekhar Nori, Rob Herring, Mark Rutland, Kevin Hilman
Cc: Axel Haslam, Bartosz Golaszewski, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <b3617c00-1f1d-5ab8-23e9-a96307a53558@ti.com>
On 11/01/2016 04:53 AM, Sekhar Nori wrote:
> Hi David,
>
> On Tuesday 01 November 2016 02:17 AM, David Lechner wrote:
>> Add a syscon node for the SoC CFGCHIPn registers. It includes a child node
>> for the USB PHY that is part of this range of registers.
>>
>> Also have to add OF_DEV_AUXDATA() entry so that clock lookup will work for
>> the the USB PHY driver.
>>
>> Signed-off-by: David Lechner <david@lechnology.com>
>
> For future, please do not combine device-tree addition and other C code into a
> single patch. I have applied this patch while splitting it into two as
> attached.
>
Sorry. I should know that by now. :-/
Thank you for fixing it for me.
^ permalink raw reply
* Re: [PATCHv2] ARM: dts: socfpga: add specific compatible strings for boards
From: Olof Johansson @ 2016-11-01 22:23 UTC (permalink / raw)
To: Dinh Nguyen
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
vladimir_zapolskiy-nmGgyN9QBj3QT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161101205652.26384-1-dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Tue, Nov 01, 2016 at 03:56:52PM -0500, Dinh Nguyen wrote:
> Add a more specific board compatible entry for all of the SOCFPGA
> Cyclone 5 based boards.
>
> Signed-off-by: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> v2: remove extra space and add a comma between compatible entries
> ---
> arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> index afea364..5ecd2ef 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> @@ -18,7 +18,7 @@
>
> / {
> model = "Terasic DE-0(Atlas)";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
>
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> index 424523b..e5a98e5 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Aries/DENX MCV EVK";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
>
> aliases {
> ethernet0 = &gmac0;
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> index 15e43f4..b0577c1 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Altera SOCFPGA Cyclone V SoC Development Kit";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
This looks a little too generic, what if there's another dk with another
SoC down the road?
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> index 02e22f5..c5623a7 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Terasic SoCkit";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "terasic,sockit", "altr,socfpga-cyclone5", "altr,socfpga";
Same thing here, this seems a bit on the generic side.
-Olof
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^ permalink raw reply
* Re: [PATCH 0/2] mmc: dw_mmc: fix the wrong operation for reset controller
From: John Stultz @ 2016-11-01 21:56 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-mmc,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Ulf Hansson, Rob Herring, Mark Rutland, lkml, Guodong Xu, Leo Yan,
Vincent Guittot
In-Reply-To: <20161031024942.4415-1-jh80.chung@samsung.com>
On Sun, Oct 30, 2016 at 7:49 PM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> This patch adds the "reset-names" as reset controller for dwmmc controller.
> Linaro guys had reported the issue about booting stuck.
>
> Some SoCs are enabled the CONFIG_RESET_CONTROLLER.
> then dwmmc controller are waiting for getting reset controller.
> But if doesn't define "resets" property in device-tree, it should be stuck.
>
> If use the reset-names as reset controller for dwmmc controller,
> it's more stable than now.
> This commit is related with the below commit.
>
> Fixes: d6786fefe816 ("mmc: dw_mmc: add reset support to dwmmc host controller")
So I wasn't hit by the issue, as I don't tend to boot from SD on my
hikey, but I did run these patches and I'm not seeing any issues with
my Android environment.
So for what its worth:
Acked-by: John Stultz <john.stultz@linaro.org>
thanks
-john
^ permalink raw reply
* Re: [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding
From: Andrew Lunn @ 2016-11-01 21:09 UTC (permalink / raw)
To: Scott Branden
Cc: Mark Rutland, devicetree, Florian Fainelli, netdev, linux-kernel,
Jon Mason, Rob Herring, bcm-kernel-feedback-list, rafal,
David Miller, linux-arm-kernel
In-Reply-To: <f56145b6-adb6-186b-0b75-45a9f3a6c58e@broadcom.com>
> If set, indicates the PHY will swap the TX/RX lanes to compensate
> for the board being designed with the lanes swapped.
Thanks, much better.
Andrew
^ permalink raw reply
* Re: [PATCH v4 6/7] net: ethernet: bgmac: add NS2 support
From: Jon Mason @ 2016-11-01 21:05 UTC (permalink / raw)
To: Scott Branden
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli, rafal,
bcm-kernel-feedback-list, netdev, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <711f4964-e655-4007-9804-f45bd47fed73@broadcom.com>
On Tue, Nov 01, 2016 at 01:34:30PM -0700, Scott Branden wrote:
> One change in this patch
>
> On 16-11-01 01:04 PM, Jon Mason wrote:
> >Add support for the variant of amac hardware present in the Broadcom
> >Northstar2 based SoCs. Northstar2 requires an additional register to be
> >configured with the port speed/duplexity (NICPM). This can be added to
> >the link callback to hide it from the instances that do not use this.
> >Also, clearing of the pending interrupts on init is required due to
> >observed issues on some platforms.
> >
> >Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> >---
> > drivers/net/ethernet/broadcom/bgmac-platform.c | 56 +++++++++++++++++++++++++-
> > drivers/net/ethernet/broadcom/bgmac.c | 3 ++
> > drivers/net/ethernet/broadcom/bgmac.h | 1 +
> > 3 files changed, 58 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
> >index aed5dc5..f6d48c7 100644
> >--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
> >+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
> >@@ -14,12 +14,21 @@
> > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> >
> > #include <linux/bcma/bcma.h>
> >+#include <linux/brcmphy.h>
> > #include <linux/etherdevice.h>
> > #include <linux/of_address.h>
> > #include <linux/of_mdio.h>
> > #include <linux/of_net.h>
> > #include "bgmac.h"
> >
> >+#define NICPM_IOMUX_CTRL 0x00000008
> >+
> >+#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
> >+#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
> >+#define NICPM_IOMUX_CTRL_SPD_10M 0
> >+#define NICPM_IOMUX_CTRL_SPD_100M 1
> >+#define NICPM_IOMUX_CTRL_SPD_1000M 2
> >+
> > static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
> > {
> > return readl(bgmac->plat.base + offset);
> >@@ -87,12 +96,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
> > WARN_ON(1);
> > }
> >
> >+static void bgmac_nicpm_speed_set(struct net_device *net_dev)
> >+{
> >+ struct bgmac *bgmac = netdev_priv(net_dev);
> >+ u32 val;
> >+
> >+ if (!bgmac->plat.nicpm_base)
> >+ return;
> >+
> >+ val = NICPM_IOMUX_CTRL_INIT_VAL;
> >+ switch (bgmac->net_dev->phydev->speed) {
> >+ default:
> >+ pr_err("Unsupported speed. Defaulting to 1000Mb\n");
> This should be dev_err
It should probably be netdev_err (and there are a few instances below
that should probably be changed to netdev_err as well).
Thanks,
Jon
> >+ case SPEED_1000:
> >+ val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> >+ break;
> >+ case SPEED_100:
> >+ val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> >+ break;
> >+ case SPEED_10:
> >+ val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> >+ break;
> >+ }
> >+
> >+ writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
> >+
> >+ bgmac_adjust_link(bgmac->net_dev);
> >+}
> >+
> > static int platform_phy_connect(struct bgmac *bgmac)
> > {
> > struct phy_device *phy_dev;
> >
> >- phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
> >- bgmac_adjust_link);
> >+ if (bgmac->plat.nicpm_base)
> >+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> >+ bgmac->dev->of_node,
> >+ bgmac_nicpm_speed_set);
> >+ else
> >+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> >+ bgmac->dev->of_node,
> >+ bgmac_adjust_link);
> > if (!phy_dev) {
> > dev_err(bgmac->dev, "Phy connect failed\n");
> > return -ENODEV;
> >@@ -182,6 +225,14 @@ static int bgmac_probe(struct platform_device *pdev)
> > if (IS_ERR(bgmac->plat.idm_base))
> > return PTR_ERR(bgmac->plat.idm_base);
> >
> >+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
> >+ if (regs) {
> >+ bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
> >+ regs);
> >+ if (IS_ERR(bgmac->plat.nicpm_base))
> >+ return PTR_ERR(bgmac->plat.nicpm_base);
> >+ }
> >+
> > bgmac->read = platform_bgmac_read;
> > bgmac->write = platform_bgmac_write;
> > bgmac->idm_read = platform_bgmac_idm_read;
> >@@ -213,6 +264,7 @@ static int bgmac_remove(struct platform_device *pdev)
> > static const struct of_device_id bgmac_of_enet_match[] = {
> > {.compatible = "brcm,amac",},
> > {.compatible = "brcm,nsp-amac",},
> >+ {.compatible = "brcm,ns2-amac",},
> > {},
> > };
> >
> >diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
> >index 4584958..a805cc8 100644
> >--- a/drivers/net/ethernet/broadcom/bgmac.c
> >+++ b/drivers/net/ethernet/broadcom/bgmac.c
> >@@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
> > /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
> > static void bgmac_chip_init(struct bgmac *bgmac)
> > {
> >+ /* Clear any erroneously pending interrupts */
> >+ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
> >+
> > /* 1 interrupt per received frame */
> > bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
> >
> >diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
> >index ea52ac3..b1820ea 100644
> >--- a/drivers/net/ethernet/broadcom/bgmac.h
> >+++ b/drivers/net/ethernet/broadcom/bgmac.h
> >@@ -463,6 +463,7 @@ struct bgmac {
> > struct {
> > void *base;
> > void *idm_base;
> >+ void *nicpm_base;
> > } plat;
> > struct {
> > struct bcma_device *core;
> >
^ permalink raw reply
* Re: [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding
From: Scott Branden @ 2016-11-01 21:01 UTC (permalink / raw)
To: Jon Mason, Andrew Lunn
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree, netdev, linux-kernel, bcm-kernel-feedback-list, rafal,
linux-arm-kernel
In-Reply-To: <20161101205913.GA27191@broadcom.com>
On 16-11-01 01:59 PM, Jon Mason wrote:
> On Tue, Nov 01, 2016 at 09:48:26PM +0100, Andrew Lunn wrote:
>>> +- enet-phy-lane-swap: If set, indicates the PHY device requires swapping the
>>> + TX/RX lanes to function properly.
>>
>> Is 'requires' the right word here? The PHY performs the actual swap of
>> the Tx/Rx lanes.
>
> What I'm trying to say here is that without the lane swapping, the PHY
> will not function properly. Thus, those PHYs require this parameter
> to work. I am open to suggestions to reword the sentence to make it
> clearer.
If set, indicates the PHY will swap the TX/RX lanes to compensate for
the board being designed with the lanes swapped.
>
> Thanks,
> Jon
>
>>
>> Andrew
^ permalink raw reply
* Re: [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding
From: Jon Mason @ 2016-11-01 20:59 UTC (permalink / raw)
To: Andrew Lunn
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
rafal-g1n6cQUeyibVItvQsEIGlw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161101204826.GA21010-g2DYL2Zd6BY@public.gmane.org>
On Tue, Nov 01, 2016 at 09:48:26PM +0100, Andrew Lunn wrote:
> > +- enet-phy-lane-swap: If set, indicates the PHY device requires swapping the
> > + TX/RX lanes to function properly.
>
> Is 'requires' the right word here? The PHY performs the actual swap of
> the Tx/Rx lanes.
What I'm trying to say here is that without the lane swapping, the PHY
will not function properly. Thus, those PHYs require this parameter
to work. I am open to suggestions to reword the sentence to make it
clearer.
Thanks,
Jon
>
> Andrew
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^ permalink raw reply
* [PATCHv2] ARM: dts: socfpga: add specific compatible strings for boards
From: Dinh Nguyen @ 2016-11-01 20:56 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
olof-nZhT3qVonbNeoWH0uzbU5w,
vladimir_zapolskiy-nmGgyN9QBj3QT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Dinh Nguyen
Add a more specific board compatible entry for all of the SOCFPGA
Cyclone 5 based boards.
Signed-off-by: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
v2: remove extra space and add a comma between compatible entries
---
arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index afea364..5ecd2ef 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -18,7 +18,7 @@
/ {
model = "Terasic DE-0(Atlas)";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index 424523b..e5a98e5 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -19,7 +19,7 @@
/ {
model = "Aries/DENX MCV EVK";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
ethernet0 = &gmac0;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 15e43f4..b0577c1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -19,7 +19,7 @@
/ {
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index 02e22f5..c5623a7 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -19,7 +19,7 @@
/ {
model = "Terasic SoCkit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "terasic,sockit", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 9aaf413..5b7e3c2 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -21,7 +21,7 @@
/ {
model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index b844473..363ee62 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -51,7 +51,7 @@
/ {
model = "samtec VIN|ING FPGA";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
--
2.8.3
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^ permalink raw reply related
* Re: [PATCH v2 2/3] irqchip: mtk-cirq: Add mediatek mtk-cirq implement
From: Marc Zyngier @ 2016-11-01 20:49 UTC (permalink / raw)
To: Youlin Pei
Cc: Rob Herring, Matthias Brugger, Thomas Gleixner, Jason Cooper,
Mark Rutland, Russell King, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
hongkun.cao-NuS5LvNUpcJWk0Htik3J/w,
yong.wu-NuS5LvNUpcJWk0Htik3J/w, erin.lo-NuS5LvNUpcJWk0Htik3J/w,
chieh-jay.liu-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <1478001122-8664-3-git-send-email-youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Tue, Nov 01 2016 at 11:52:01 AM, Youlin Pei <youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> In Mediatek SOCs, the CIRQ is a low power interrupt controller
> designed to works outside MCUSYS which comprises with Cortex-Ax
> cores,CCI and GIC.
>
> The CIRQ controller is integrated in between MCUSYS( include
> Cortex-Ax, CCI and GIC ) and interrupt sources as the second
> level interrupt controller. The external interrupts which outside
> MCUSYS will feed through CIRQ then bypass to GIC. CIRQ can monitors
> all edge trigger interupts. When an edge interrupt is triggered,
> CIRQ can record the status and generate a pulse signal to GIC when
> flush command executed.
>
> When system enters sleep mode, MCUSYS will be turned off to improve
> power consumption, also GIC is power down. The edge trigger interrupts
> will be lost in this scenario without CIRQ.
>
> This commit provides the CIRQ irqchip implement.
>
> Signed-off-by: Youlin Pei <youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/irqchip/Makefile | 2 +-
> drivers/irqchip/irq-mtk-cirq.c | 262 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 263 insertions(+), 1 deletion(-)
> create mode 100644 drivers/irqchip/irq-mtk-cirq.c
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index e4dbfc8..8f33580 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -60,7 +60,7 @@ obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
> obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
> obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
> obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
> -obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
> +obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o irq-mtk-cirq.o
> obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o
> obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
> obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
> diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
> new file mode 100644
> index 0000000..fc43ef3
> --- /dev/null
> +++ b/drivers/irqchip/irq-mtk-cirq.c
> @@ -0,0 +1,262 @@
> +/*
> + * Copyright (c) 2016 MediaTek Inc.
> + * Author: Youlin.Pei <youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/syscore_ops.h>
> +
> +#define CIRQ_ACK 0x40
> +#define CIRQ_MASK_SET 0xc0
> +#define CIRQ_MASK_CLR 0x100
> +#define CIRQ_SENS_SET 0x180
> +#define CIRQ_SENS_CLR 0x1c0
> +#define CIRQ_POL_SET 0x240
> +#define CIRQ_POL_CLR 0x280
> +#define CIRQ_CONTROL 0x300
> +
> +#define CIRQ_EN 0x1
> +#define CIRQ_EDGE 0x2
> +#define CIRQ_FLUSH 0x4
> +
> +#define CIRQ_IRQ_NUM 0x200
> +
> +struct mtk_cirq_chip_data {
> + void __iomem *base;
> + unsigned int ext_irq_start;
> +};
> +
> +static struct mtk_cirq_chip_data *cirq_data;
Are you guaranteed that you'll only ever have a single CIRQ in any
system?
> +
> +static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
> +{
> + struct mtk_cirq_chip_data *chip_data = data->chip_data;
> + unsigned int cirq_num = data->hwirq;
> + u32 mask = 1 << (cirq_num % 32);
> +
> + writel(mask, chip_data->base + offset + (cirq_num / 32) * 4);
Why can't you use the relaxed accessors?
> +}
> +
> +static void mtk_cirq_mask(struct irq_data *data)
> +{
> + mtk_cirq_write_mask(data, CIRQ_MASK_SET);
> + irq_chip_mask_parent(data);
> +}
> +
> +static void mtk_cirq_unmask(struct irq_data *data)
> +{
> + mtk_cirq_write_mask(data, CIRQ_MASK_CLR);
> + irq_chip_unmask_parent(data);
> +}
> +
> +static void mtk_cirq_eoi(struct irq_data *data)
> +{
> + mtk_cirq_write_mask(data, CIRQ_ACK);
EOI and ACK have very different semantics. What is this write actually
doing? Also, you're now doing an additional MMIO write on each interrupt
EOI, doubling its cost. Do you really need to do actually signal the HW
that we've EOIed an interrupt? I would have hoped that you'd be able to
put it in "bypass" mode as long as you're not suspending...
> + irq_chip_eoi_parent(data);
> +}
> +
> +static int mtk_cirq_set_type(struct irq_data *data, unsigned int type)
> +{
> + int ret;
> +
> + switch (type & IRQ_TYPE_SENSE_MASK) {
> + case IRQ_TYPE_EDGE_FALLING:
> + mtk_cirq_write_mask(data, CIRQ_POL_CLR);
> + mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
> + break;
> + case IRQ_TYPE_EDGE_RISING:
> + mtk_cirq_write_mask(data, CIRQ_POL_SET);
> + mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
> + break;
> + case IRQ_TYPE_LEVEL_LOW:
> + mtk_cirq_write_mask(data, CIRQ_POL_CLR);
> + mtk_cirq_write_mask(data, CIRQ_SENS_SET);
> + break;
> + case IRQ_TYPE_LEVEL_HIGH:
> + mtk_cirq_write_mask(data, CIRQ_POL_SET);
> + mtk_cirq_write_mask(data, CIRQ_SENS_SET);
> + break;
> + default:
> + break;
> + }
> +
> + data = data->parent_data;
> + ret = data->chip->irq_set_type(data, type);
> + return ret;
> +}
> +
> +static struct irq_chip mtk_cirq_chip = {
> + .name = "MT_CIRQ",
> + .irq_mask = mtk_cirq_mask,
> + .irq_unmask = mtk_cirq_unmask,
> + .irq_eoi = mtk_cirq_eoi,
> + .irq_set_type = mtk_cirq_set_type,
> + .irq_retrigger = irq_chip_retrigger_hierarchy,
> +#ifdef CONFIG_SMP
> + .irq_set_affinity = irq_chip_set_affinity_parent,
> +#endif
> +};
> +
> +static int mtk_cirq_domain_translate(struct irq_domain *d,
> + struct irq_fwspec *fwspec,
> + unsigned long *hwirq,
> + unsigned int *type)
> +{
> + if (is_of_node(fwspec->fwnode)) {
> + if (fwspec->param_count != 3)
> + return -EINVAL;
> +
> + /* No PPI should point to this domain */
> + if (fwspec->param[0] != 0)
> + return -EINVAL;
> +
> + /* cirq support irq number check */
> + if (fwspec->param[1] < cirq_data->ext_irq_start)
> + return -EINVAL;
> +
> + *hwirq = fwspec->param[1] - cirq_data->ext_irq_start;
What if the result is > CIRQ_IRQ_NUM?
> + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int mtk_cirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *arg)
> +{
> + int i;
> + irq_hw_number_t hwirq;
> + struct irq_fwspec *fwspec = arg;
> + struct irq_fwspec parent_fwspec = *fwspec;
> +
> + if (fwspec->param_count != 3)
> + return -EINVAL;
> +
> + /* cirq doesn't support PPI */
> + if (fwspec->param[0])
> + return -EINVAL;
> +
> + if (fwspec->param[1] < cirq_data->ext_irq_start)
> + return -EINVAL;
> +
> + hwirq = fwspec->param[1] - cirq_data->ext_irq_start;
All this is a pure copy of mtk_cirq_domain_translate(). Please use it.
> + for (i = 0; i < nr_irqs; i++)
> + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
> + &mtk_cirq_chip,
> + domain->host_data);
This is a bit silly. This loop only exists for the benefit of MSI
support, which we're not dealing with here. So please stick a
if (WARN_ON(nr_irqs != 1))
return -EINVAL;
and drop the loop.
> +
> + parent_fwspec.fwnode = domain->parent->fwnode;
> + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
> + &parent_fwspec);
> +}
> +
> +static const struct irq_domain_ops cirq_domain_ops = {
> + .translate = mtk_cirq_domain_translate,
> + .alloc = mtk_cirq_domain_alloc,
> + .free = irq_domain_free_irqs_common,
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int mtk_cirq_suspend(void)
> +{
> + u32 value;
> +
> + /* set edge_only mode, record edge-triggerd interrupts */
> + /* enable cirq */
> + value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> + value |= (CIRQ_EDGE | CIRQ_EN);
> + writel(value, cirq_data->base + CIRQ_CONTROL);
You're mixing relaxed and non-relaxed accessors. Why?
> + return 0;
> +}
> +
> +static void mtk_cirq_resume(void)
> +{
> + u32 value;
> +
> + /* flush recored interrupts, will send signals to parent controller */
> + value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> + writel(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
Same remark.
> +
> + /* disable cirq */
> + value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> + value &= ~(CIRQ_EDGE | CIRQ_EN);
> + writel(value, cirq_data->base + CIRQ_CONTROL);
So from this, I infer that CIRQ is not enabled when the kernel is
running (not suspended). It really makes me wonder why you need to do
anything in the EOI callback.
> +}
> +
> +static struct syscore_ops mtk_cirq_syscore_ops = {
> + .suspend = mtk_cirq_suspend,
> + .resume = mtk_cirq_resume,
> +};
> +
> +static void mtk_cirq_syscore_init(void)
> +{
> + register_syscore_ops(&mtk_cirq_syscore_ops);
> +}
> +#else
> +static inline void mtk_cirq_syscore_init(void) {}
> +#endif
> +
> +static int __init mtk_cirq_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct irq_domain *domain, *domain_parent;
> + int ret;
> +
> + domain_parent = irq_find_host(parent);
> + if (!domain_parent) {
> + pr_err("mtk_cirq: interrupt-parent not found\n");
> + return -EINVAL;
> + }
> +
> + cirq_data = kzalloc(sizeof(*cirq_data), GFP_KERNEL);
> + if (!cirq_data)
> + return -ENOMEM;
> +
> + cirq_data->base = of_iomap(node, 0);
> + if (!cirq_data->base) {
> + pr_err("mtk_cirq: unable to map cirq register\n");
> + ret = -ENXIO;
> + goto out_free;
> + }
> +
> + ret = of_property_read_u32(node, "mediatek,ext-irq-start",
> + &cirq_data->ext_irq_start);
> + if (ret)
> + goto out_unmap;
> +
> + domain = irq_domain_add_hierarchy(domain_parent, 0, CIRQ_IRQ_NUM, node,
> + &cirq_domain_ops, cirq_data);
So you support at most 512 interrupts, and yet the GIC supports up to
987 SPIs. What happens for interrupt lines that out of the CIRQ range?
Maybe having an explicit range in DT would be a good thing. That also
brings back the question of having a single CIRQ in the system...
> + if (!domain) {
> + ret = -ENOMEM;
> + goto out_unmap;
> + }
> +
> + mtk_cirq_syscore_init();
> +
> + return 0;
> +
> +out_unmap:
> + iounmap(cirq_data->base);
> +out_free:
> + kfree(cirq_data);
> + return ret;
> +}
> +
> +IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);
Thanks,
M.
--
Jazz is not dead. It just smells funny.
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^ permalink raw reply
* Re: [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding
From: Andrew Lunn @ 2016-11-01 20:48 UTC (permalink / raw)
To: Jon Mason
Cc: David Miller, Rob Herring, Mark Rutland, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
rafal-g1n6cQUeyibVItvQsEIGlw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1478030682-27012-3-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> +- enet-phy-lane-swap: If set, indicates the PHY device requires swapping the
> + TX/RX lanes to function properly.
Is 'requires' the right word here? The PHY performs the actual swap of
the Tx/Rx lanes.
Andrew
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^ permalink raw reply
* Re: [PATCH v4 6/7] net: ethernet: bgmac: add NS2 support
From: Scott Branden @ 2016-11-01 20:34 UTC (permalink / raw)
To: Jon Mason, David Miller, Rob Herring, Mark Rutland,
Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478030682-27012-7-git-send-email-jon.mason@broadcom.com>
One change in this patch
On 16-11-01 01:04 PM, Jon Mason wrote:
> Add support for the variant of amac hardware present in the Broadcom
> Northstar2 based SoCs. Northstar2 requires an additional register to be
> configured with the port speed/duplexity (NICPM). This can be added to
> the link callback to hide it from the instances that do not use this.
> Also, clearing of the pending interrupts on init is required due to
> observed issues on some platforms.
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> ---
> drivers/net/ethernet/broadcom/bgmac-platform.c | 56 +++++++++++++++++++++++++-
> drivers/net/ethernet/broadcom/bgmac.c | 3 ++
> drivers/net/ethernet/broadcom/bgmac.h | 1 +
> 3 files changed, 58 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
> index aed5dc5..f6d48c7 100644
> --- a/drivers/net/ethernet/broadcom/bgmac-platform.c
> +++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
> @@ -14,12 +14,21 @@
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> #include <linux/bcma/bcma.h>
> +#include <linux/brcmphy.h>
> #include <linux/etherdevice.h>
> #include <linux/of_address.h>
> #include <linux/of_mdio.h>
> #include <linux/of_net.h>
> #include "bgmac.h"
>
> +#define NICPM_IOMUX_CTRL 0x00000008
> +
> +#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
> +#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
> +#define NICPM_IOMUX_CTRL_SPD_10M 0
> +#define NICPM_IOMUX_CTRL_SPD_100M 1
> +#define NICPM_IOMUX_CTRL_SPD_1000M 2
> +
> static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
> {
> return readl(bgmac->plat.base + offset);
> @@ -87,12 +96,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
> WARN_ON(1);
> }
>
> +static void bgmac_nicpm_speed_set(struct net_device *net_dev)
> +{
> + struct bgmac *bgmac = netdev_priv(net_dev);
> + u32 val;
> +
> + if (!bgmac->plat.nicpm_base)
> + return;
> +
> + val = NICPM_IOMUX_CTRL_INIT_VAL;
> + switch (bgmac->net_dev->phydev->speed) {
> + default:
> + pr_err("Unsupported speed. Defaulting to 1000Mb\n");
This should be dev_err
> + case SPEED_1000:
> + val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> + break;
> + case SPEED_100:
> + val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> + break;
> + case SPEED_10:
> + val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> + break;
> + }
> +
> + writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
> +
> + bgmac_adjust_link(bgmac->net_dev);
> +}
> +
> static int platform_phy_connect(struct bgmac *bgmac)
> {
> struct phy_device *phy_dev;
>
> - phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
> - bgmac_adjust_link);
> + if (bgmac->plat.nicpm_base)
> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> + bgmac->dev->of_node,
> + bgmac_nicpm_speed_set);
> + else
> + phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> + bgmac->dev->of_node,
> + bgmac_adjust_link);
> if (!phy_dev) {
> dev_err(bgmac->dev, "Phy connect failed\n");
> return -ENODEV;
> @@ -182,6 +225,14 @@ static int bgmac_probe(struct platform_device *pdev)
> if (IS_ERR(bgmac->plat.idm_base))
> return PTR_ERR(bgmac->plat.idm_base);
>
> + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
> + if (regs) {
> + bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
> + regs);
> + if (IS_ERR(bgmac->plat.nicpm_base))
> + return PTR_ERR(bgmac->plat.nicpm_base);
> + }
> +
> bgmac->read = platform_bgmac_read;
> bgmac->write = platform_bgmac_write;
> bgmac->idm_read = platform_bgmac_idm_read;
> @@ -213,6 +264,7 @@ static int bgmac_remove(struct platform_device *pdev)
> static const struct of_device_id bgmac_of_enet_match[] = {
> {.compatible = "brcm,amac",},
> {.compatible = "brcm,nsp-amac",},
> + {.compatible = "brcm,ns2-amac",},
> {},
> };
>
> diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
> index 4584958..a805cc8 100644
> --- a/drivers/net/ethernet/broadcom/bgmac.c
> +++ b/drivers/net/ethernet/broadcom/bgmac.c
> @@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
> /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
> static void bgmac_chip_init(struct bgmac *bgmac)
> {
> + /* Clear any erroneously pending interrupts */
> + bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
> +
> /* 1 interrupt per received frame */
> bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
>
> diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
> index ea52ac3..b1820ea 100644
> --- a/drivers/net/ethernet/broadcom/bgmac.h
> +++ b/drivers/net/ethernet/broadcom/bgmac.h
> @@ -463,6 +463,7 @@ struct bgmac {
> struct {
> void *base;
> void *idm_base;
> + void *nicpm_base;
> } plat;
> struct {
> struct bcma_device *core;
>
^ permalink raw reply
* Re: [PATCH] ARM: dts: socfpga: add specific compatible strings for boards
From: Dinh Nguyen @ 2016-11-01 20:13 UTC (permalink / raw)
To: Vladimir Zapolskiy, Dinh Nguyen,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
olof-nZhT3qVonbNeoWH0uzbU5w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <6ebcc3e9-37b7-7c27-a111-9fc663d07864-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Hi Vladimir,
On 11/01/2016 03:10 PM, Vladimir Zapolskiy wrote:
> Hi Dinh,
>
> On 11/01/2016 05:38 PM, Dinh Nguyen wrote:
>> Add a more specific board compatible entry for all of the SOCFPGA
>> Cyclone 5 based boards.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> ---
>> arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
>> arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
>> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +-
>> arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +-
>> arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
>> arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
>> 6 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
>> index afea364..5ecd2ef 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
>> @@ -18,7 +18,7 @@
>>
>> / {
>> model = "Terasic DE-0(Atlas)";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5",
>> "altr,socfpga";
>>
>> chosen {
>> bootargs = "earlyprintk";
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
>> index 424523b..668d77c 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
>> @@ -19,7 +19,7 @@
>>
>> / {
>> model = "Aries/DENX MCV EVK";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "denx, mcvevk", "altr,socfpga-cyclone5",
>> "altr,socfpga";
>
> Redundant space ^
OK
>
>>
>> aliases {
>> ethernet0 = &gmac0;
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
>> index 15e43f4..b0577c1 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
>> @@ -19,7 +19,7 @@
>>
>> / {
>> model = "Altera SOCFPGA Cyclone V SoC Development Kit";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
>>
>> chosen {
>> bootargs = "earlyprintk";
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
>> index 02e22f5..c5623a7 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
>> @@ -19,7 +19,7 @@
>>
>> / {
>> model = "Terasic SoCkit";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "terasic,sockit", "altr,socfpga-cyclone5",
>> "altr,socfpga";
>>
>> chosen {
>> bootargs = "earlyprintk";
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
>> index 9aaf413..992ae49 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
>> @@ -21,7 +21,7 @@
>>
>> / {
>> model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "macnica, sodia", "altr,socfpga-cyclone5",
>> "altr,socfpga";
>
> Redundant space ^
Ok,
>
> If it is not yet done, you may consider to add Macnica to
> Documentation/devicetree/bindings/vendor-prefixes.txt
>
Yes, I have sent separate patches to add the vendor prefixes.
>>
>> chosen {
>> bootargs = "earlyprintk";
>> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
>> b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
>> index b844473..78b187e 100644
>> --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
>> +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
>> @@ -51,7 +51,7 @@
>>
>> / {
>> model = "samtec VIN|ING FPGA";
>> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
>> + compatible = "samtec,vining". "altr,socfpga-cyclone5",
>> "altr,socfpga";
>
> Comma is expected here ^
Ok,
>
> Probably Terasic and Samtec are also not in the vendor-prefixes.txt list,
> usually checkpatch complains about it.
Yes, I have sent patches for the vendor prefixes. Thanks for reviewing.
Dinh
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^ permalink raw reply
* Re: [PATCH] ARM: dts: socfpga: add specific compatible strings for boards
From: Vladimir Zapolskiy @ 2016-11-01 20:10 UTC (permalink / raw)
To: Dinh Nguyen, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
olof-nZhT3qVonbNeoWH0uzbU5w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161101153817.6977-1-dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Hi Dinh,
On 11/01/2016 05:38 PM, Dinh Nguyen wrote:
> Add a more specific board compatible entry for all of the SOCFPGA
> Cyclone 5 based boards.
>
> Signed-off-by: Dinh Nguyen <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +-
> arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> index afea364..5ecd2ef 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
> @@ -18,7 +18,7 @@
>
> / {
> model = "Terasic DE-0(Atlas)";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
>
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> index 424523b..668d77c 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Aries/DENX MCV EVK";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "denx, mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
Redundant space ^
>
> aliases {
> ethernet0 = &gmac0;
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> index 15e43f4..b0577c1 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Altera SOCFPGA Cyclone V SoC Development Kit";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
>
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> index 02e22f5..c5623a7 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> @@ -19,7 +19,7 @@
>
> / {
> model = "Terasic SoCkit";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "terasic,sockit", "altr,socfpga-cyclone5", "altr,socfpga";
>
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
> index 9aaf413..992ae49 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
> @@ -21,7 +21,7 @@
>
> / {
> model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "macnica, sodia", "altr,socfpga-cyclone5", "altr,socfpga";
Redundant space ^
If it is not yet done, you may consider to add Macnica to
Documentation/devicetree/bindings/vendor-prefixes.txt
>
> chosen {
> bootargs = "earlyprintk";
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> index b844473..78b187e 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> @@ -51,7 +51,7 @@
>
> / {
> model = "samtec VIN|ING FPGA";
> - compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> + compatible = "samtec,vining". "altr,socfpga-cyclone5", "altr,socfpga";
Comma is expected here ^
Probably Terasic and Samtec are also not in the vendor-prefixes.txt list,
usually checkpatch complains about it.
>
> chosen {
> bootargs = "console=ttyS0,115200";
>
--
With best wishes,
Vladimir
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^ permalink raw reply
* [PATCH v4 7/7] arm64: dts: NS2: add AMAC ethernet support
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device
tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 +++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 2d7872a..2e4d90d 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -56,6 +56,10 @@
};
};
+&enet {
+ status = "ok";
+};
+
&pci_phy0 {
status = "ok";
};
@@ -172,6 +176,7 @@
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
+ enet-phy-lane-swap;
reg = <0x10>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc40..773ed59 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -191,6 +191,18 @@
#include "ns2-clock.dtsi"
+ enet: ethernet@61000000 {
+ compatible = "brcm,ns2-amac";
+ reg = <0x61000000 0x1000>,
+ <0x61090000 0x1000>,
+ <0x61030000 0x100>;
+ reg-names = "amac_base", "idm_base", "nicpm_base";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ phy-handle = <&gphy0>;
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v4 6/7] net: ethernet: bgmac: add NS2 support
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
Add support for the variant of amac hardware present in the Broadcom
Northstar2 based SoCs. Northstar2 requires an additional register to be
configured with the port speed/duplexity (NICPM). This can be added to
the link callback to hide it from the instances that do not use this.
Also, clearing of the pending interrupts on init is required due to
observed issues on some platforms.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/ethernet/broadcom/bgmac-platform.c | 56 +++++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 3 ++
drivers/net/ethernet/broadcom/bgmac.h | 1 +
3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index aed5dc5..f6d48c7 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -14,12 +14,21 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcma/bcma.h>
+#include <linux/brcmphy.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
+#define NICPM_IOMUX_CTRL 0x00000008
+
+#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
+#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
+#define NICPM_IOMUX_CTRL_SPD_10M 0
+#define NICPM_IOMUX_CTRL_SPD_100M 1
+#define NICPM_IOMUX_CTRL_SPD_1000M 2
+
static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
{
return readl(bgmac->plat.base + offset);
@@ -87,12 +96,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static void bgmac_nicpm_speed_set(struct net_device *net_dev)
+{
+ struct bgmac *bgmac = netdev_priv(net_dev);
+ u32 val;
+
+ if (!bgmac->plat.nicpm_base)
+ return;
+
+ val = NICPM_IOMUX_CTRL_INIT_VAL;
+ switch (bgmac->net_dev->phydev->speed) {
+ default:
+ pr_err("Unsupported speed. Defaulting to 1000Mb\n");
+ case SPEED_1000:
+ val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_100:
+ val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_10:
+ val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ }
+
+ writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
+
+ bgmac_adjust_link(bgmac->net_dev);
+}
+
static int platform_phy_connect(struct bgmac *bgmac)
{
struct phy_device *phy_dev;
- phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
- bgmac_adjust_link);
+ if (bgmac->plat.nicpm_base)
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_nicpm_speed_set);
+ else
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_adjust_link);
if (!phy_dev) {
dev_err(bgmac->dev, "Phy connect failed\n");
return -ENODEV;
@@ -182,6 +225,14 @@ static int bgmac_probe(struct platform_device *pdev)
if (IS_ERR(bgmac->plat.idm_base))
return PTR_ERR(bgmac->plat.idm_base);
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
+ if (regs) {
+ bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
+ regs);
+ if (IS_ERR(bgmac->plat.nicpm_base))
+ return PTR_ERR(bgmac->plat.nicpm_base);
+ }
+
bgmac->read = platform_bgmac_read;
bgmac->write = platform_bgmac_write;
bgmac->idm_read = platform_bgmac_idm_read;
@@ -213,6 +264,7 @@ static int bgmac_remove(struct platform_device *pdev)
static const struct of_device_id bgmac_of_enet_match[] = {
{.compatible = "brcm,amac",},
{.compatible = "brcm,nsp-amac",},
+ {.compatible = "brcm,ns2-amac",},
{},
};
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 4584958..a805cc8 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
static void bgmac_chip_init(struct bgmac *bgmac)
{
+ /* Clear any erroneously pending interrupts */
+ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
+
/* 1 interrupt per received frame */
bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index ea52ac3..b1820ea 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -463,6 +463,7 @@ struct bgmac {
struct {
void *base;
void *idm_base;
+ void *nicpm_base;
} plat;
struct {
struct bcma_device *core;
--
2.7.4
^ permalink raw reply related
* [PATCH v4 5/7] net: ethernet: bgmac: device tree phy enablement
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal-g1n6cQUeyibVItvQsEIGlw,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Change the bgmac driver to allow for phy's defined by the device tree
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++++++++++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 48 +++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 52 ++------------------------
drivers/net/ethernet/broadcom/bgmac.h | 7 ++++
4 files changed, 105 insertions(+), 50 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-bcma.c b/drivers/net/ethernet/broadcom/bgmac-bcma.c
index c16ec3a..3e3efde 100644
--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
@@ -80,6 +80,50 @@ static void bcma_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, u32 mask,
bcma_maskset32(bgmac->bcma.cmn, offset, mask, set);
}
+static int bcma_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+ char bus_id[MII_BUS_ID_SIZE + 3];
+
+ /* Connect to the PHY */
+ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
+ bgmac->phyaddr);
+ phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "PHY connecton failed\n");
+ return PTR_ERR(phy_dev);
+ }
+
+ return 0;
+}
+
+static int bcma_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static const struct bcma_device_id bgmac_bcma_tbl[] = {
BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT,
BCMA_ANY_REV, BCMA_ANY_CLASS),
@@ -275,6 +319,10 @@ static int bgmac_probe(struct bcma_device *core)
bgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = bcma_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32;
+ if (bgmac->mii_bus)
+ bgmac->phy_connect = bcma_phy_connect;
+ else
+ bgmac->phy_connect = bcma_phy_direct_connect;
err = bgmac_enet_probe(bgmac);
if (err)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index be52f27..aed5dc5 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -16,6 +16,7 @@
#include <linux/bcma/bcma.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
+#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
@@ -86,6 +87,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static int platform_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
+ bgmac_adjust_link);
+ if (!phy_dev) {
+ dev_err(bgmac->dev, "Phy connect failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int platform_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static int bgmac_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -102,7 +143,6 @@ static int bgmac_probe(struct platform_device *pdev)
/* Set the features of the 4707 family */
bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
- bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4;
bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP;
bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP;
@@ -151,6 +191,12 @@ static int bgmac_probe(struct platform_device *pdev)
bgmac->cco_ctl_maskset = platform_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = platform_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = platform_bgmac_cmn_maskset32;
+ if (of_parse_phandle(np, "phy-handle", 0)) {
+ bgmac->phy_connect = platform_phy_connect;
+ } else {
+ bgmac->phy_connect = platform_phy_direct_connect;
+ bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
+ }
return bgmac_enet_probe(bgmac);
}
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 856379c..4584958 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1388,7 +1388,7 @@ static const struct ethtool_ops bgmac_ethtool_ops = {
* MII
**************************************************/
-static void bgmac_adjust_link(struct net_device *net_dev)
+void bgmac_adjust_link(struct net_device *net_dev)
{
struct bgmac *bgmac = netdev_priv(net_dev);
struct phy_device *phy_dev = net_dev->phydev;
@@ -1411,50 +1411,7 @@ static void bgmac_adjust_link(struct net_device *net_dev)
phy_print_status(phy_dev);
}
}
-
-static int bgmac_phy_connect_direct(struct bgmac *bgmac)
-{
- struct fixed_phy_status fphy_status = {
- .link = 1,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
- };
- struct phy_device *phy_dev;
- int err;
-
- phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
- if (!phy_dev || IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
- return -ENODEV;
- }
-
- err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (err) {
- dev_err(bgmac->dev, "Connecting PHY failed\n");
- return err;
- }
-
- return err;
-}
-
-static int bgmac_phy_connect(struct bgmac *bgmac)
-{
- struct phy_device *phy_dev;
- char bus_id[MII_BUS_ID_SIZE + 3];
-
- /* Connect to the PHY */
- snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
- bgmac->phyaddr);
- phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "PHY connecton failed\n");
- return PTR_ERR(phy_dev);
- }
-
- return 0;
-}
+EXPORT_SYMBOL_GPL(bgmac_adjust_link);
int bgmac_enet_probe(struct bgmac *info)
{
@@ -1507,10 +1464,7 @@ int bgmac_enet_probe(struct bgmac *info)
netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
- if (!bgmac->mii_bus)
- err = bgmac_phy_connect_direct(bgmac);
- else
- err = bgmac_phy_connect(bgmac);
+ err = bgmac_phy_connect(bgmac);
if (err) {
dev_err(bgmac->dev, "Cannot connect to phy\n");
goto err_dma_free;
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index 80836b4..ea52ac3 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -513,10 +513,12 @@ struct bgmac {
u32 (*get_bus_clock)(struct bgmac *bgmac);
void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
u32 set);
+ int (*phy_connect)(struct bgmac *bgmac);
};
int bgmac_enet_probe(struct bgmac *info);
void bgmac_enet_remove(struct bgmac *bgmac);
+void bgmac_adjust_link(struct net_device *net_dev);
struct mii_bus *bcma_mdio_mii_register(struct bcma_device *core, u8 phyaddr);
void bcma_mdio_mii_unregister(struct mii_bus *mii_bus);
@@ -583,4 +585,9 @@ static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
{
bgmac_maskset(bgmac, offset, ~0, set);
}
+
+static inline int bgmac_phy_connect(struct bgmac *bgmac)
+{
+ return bgmac->phy_connect(bgmac);
+}
#endif /* _BGMAC_H */
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v4 4/7] Documentation: devicetree: net: add NS2 bindings to amac
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
Clean-up the documentation to the bgmac-amac driver, per suggestion by
Rob Herring, and add details for NS2 support.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
Documentation/devicetree/bindings/net/brcm,amac.txt | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt
index ba5ecc1..2fefa1a 100644
--- a/Documentation/devicetree/bindings/net/brcm,amac.txt
+++ b/Documentation/devicetree/bindings/net/brcm,amac.txt
@@ -2,11 +2,17 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings
-------------------------------------------------------------
Required properties:
- - compatible: "brcm,amac" or "brcm,nsp-amac"
- - reg: Address and length of the GMAC registers,
- Address and length of the GMAC IDM registers
- - reg-names: Names of the registers. Must have both "amac_base" and
- "idm_base"
+ - compatible: "brcm,amac"
+ "brcm,nsp-amac"
+ "brcm,ns2-amac"
+ - reg: Address and length of the register set for the device. It
+ contains the information of registers in the same order as
+ described by reg-names
+ - reg-names: Names of the registers.
+ "amac_base": Address and length of the GMAC registers
+ "idm_base": Address and length of the GMAC IDM registers
+ "nicpm_base": Address and length of the NIC Port Manager
+ registers (required for Northstar2)
- interrupts: Interrupt number
Optional properties:
--
2.7.4
^ permalink raw reply related
* [PATCH v4 3/7] net: phy: broadcom: Add BCM54810 PHY entry
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, netdev, linux-kernel, bcm-kernel-feedback-list, rafal,
linux-arm-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
The BCM54810 PHY requires some semi-unique configuration, which results
in some additional configuration in addition to the standard config.
Also, some users of the BCM54810 require the PHY lanes to be swapped.
Since there is no way to detect this, add a device tree query to see if
it is applicable.
Inspired-by: Vikas Soni <vsoni@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 58 +++++++++++++++++++++++++++++++++++++++++++++-
include/linux/brcmphy.h | 9 +++++++
3 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 45f68ea..31967ca 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -217,7 +217,7 @@ config BROADCOM_PHY
select BCM_NET_PHYLIB
---help---
Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
- BCM5481 and BCM5482 PHYs.
+ BCM5481, BCM54810 and BCM5482 PHYs.
config CICADA_PHY
tristate "Cicada PHYs"
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 3a64b3d..b1e32e9 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -18,7 +18,7 @@
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/brcmphy.h>
-
+#include <linux/of.h>
#define BRCM_PHY_MODEL(phydev) \
((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
@@ -45,6 +45,34 @@ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
}
+static int bcm54810_config(struct phy_device *phydev)
+{
+ int rc, val;
+
+ val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
+ val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
+ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
+ val);
+ if (rc < 0)
+ return rc;
+
+ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
+ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
+ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+ val);
+ if (rc < 0)
+ return rc;
+
+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
static int bcm50610_a0_workaround(struct phy_device *phydev)
{
@@ -217,6 +245,12 @@ static int bcm54xx_config_init(struct phy_device *phydev)
(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev);
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
+ err = bcm54810_config(phydev);
+ if (err)
+ return err;
+ }
+
bcm54xx_phydsp_config(phydev);
return 0;
@@ -314,6 +348,7 @@ static int bcm5482_read_status(struct phy_device *phydev)
static int bcm5481_config_aneg(struct phy_device *phydev)
{
+ struct device_node *np = phydev->mdio.dev.of_node;
int ret;
/* Aneg firsly. */
@@ -344,6 +379,14 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
phy_write(phydev, 0x18, reg);
}
+ if (of_property_read_bool(np, "enet-phy-lane-swap")) {
+ /* Lane Swap - Undocumented register...magic! */
+ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
+ 0x11B);
+ if (ret < 0)
+ return ret;
+ }
+
return ret;
}
@@ -578,6 +621,18 @@ static struct phy_driver broadcom_drivers[] = {
.ack_interrupt = bcm_phy_ack_intr,
.config_intr = bcm_phy_config_intr,
}, {
+ .phy_id = PHY_ID_BCM54810,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Broadcom BCM54810",
+ .features = PHY_GBIT_FEATURES |
+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ .config_init = bcm54xx_config_init,
+ .config_aneg = bcm5481_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = bcm_phy_ack_intr,
+ .config_intr = bcm_phy_config_intr,
+}, {
.phy_id = PHY_ID_BCM5482,
.phy_id_mask = 0xfffffff0,
.name = "Broadcom BCM5482",
@@ -661,6 +716,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
{ PHY_ID_BCM54616S, 0xfffffff0 },
{ PHY_ID_BCM5464, 0xfffffff0 },
{ PHY_ID_BCM5481, 0xfffffff0 },
+ { PHY_ID_BCM54810, 0xfffffff0 },
{ PHY_ID_BCM5482, 0xfffffff0 },
{ PHY_ID_BCM50610, 0xfffffff0 },
{ PHY_ID_BCM50610M, 0xfffffff0 },
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 0ed6691..848dc50 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -13,6 +13,7 @@
#define PHY_ID_BCM5241 0x0143bc30
#define PHY_ID_BCMAC131 0x0143bc70
#define PHY_ID_BCM5481 0x0143bca0
+#define PHY_ID_BCM54810 0x03625d00
#define PHY_ID_BCM5482 0x0143bcb0
#define PHY_ID_BCM5411 0x00206070
#define PHY_ID_BCM5421 0x002060e0
@@ -56,6 +57,7 @@
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
+
/* Broadcom BCM7xxx specific workarounds */
#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
@@ -111,6 +113,7 @@
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
@@ -192,6 +195,12 @@
#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
+/* BCM54810 Registers */
+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
+#define BCM54810_SHD_CLK_CTL 0x3
+#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
+
/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
Add the documentation for PHY lane swapping. This is a boolean entry to
notify the phy device drivers that the TX/RX lanes need to be swapped.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
Documentation/devicetree/bindings/net/phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index bc1c3c8..3dce607 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -35,6 +35,9 @@ Optional Properties:
- broken-turn-around: If set, indicates the PHY device does not correctly
release the turn around line low at the end of a MDIO transaction.
+- enet-phy-lane-swap: If set, indicates the PHY device requires swapping the
+ TX/RX lanes to function properly.
+
Example:
ethernet-phy@0 {
--
2.7.4
^ permalink raw reply related
* [PATCH v4 1/7] net: phy: broadcom: add bcm54xx_auxctl_read
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, netdev, linux-kernel, bcm-kernel-feedback-list, rafal,
linux-arm-kernel
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>
Add a helper function to read the AUXCTL register for the BCM54xx. This
mirrors the bcm54xx_auxctl_write function already present in the code.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/phy/broadcom.c | 10 ++++++++++
include/linux/brcmphy.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 583ef8a..3a64b3d 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -30,6 +30,16 @@ MODULE_DESCRIPTION("Broadcom PHY driver");
MODULE_AUTHOR("Maciej W. Rozycki");
MODULE_LICENSE("GPL");
+static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
+{
+ /* The register must be written to both the Shadow Register Select and
+ * the Shadow Read Register Selector
+ */
+ phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
+ regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
+ return phy_read(phydev, MII_BCM54XX_AUX_CTL);
+}
+
static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
{
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 60def78..0ed6691 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -110,6 +110,7 @@
#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
--
2.7.4
^ permalink raw reply related
* [PATCH v4 0/7] add NS2 support to bgmac
From: Jon Mason @ 2016-11-01 20:04 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
Changes in v4:
* Actually send out the lane swap binding doc patch (Per Scott Branden)
* Remove unused #define (Per Andrew Lunn)
Changes in v3:
* Clean-up the bgmac DT binding doc (per Rob Herring)
* Document the lane swap binding and make it generic (Per Andrew Lunn)
Changes in v2:
* Remove the PHY power-on (per Andrew Lunn)
* Misc PHY clean-ups regarding comments and #defines (per Andrew Lunn)
This results on none of the original PHY code from Vikas being
present. So, I'm removing him as an author and giving him
"Inspired-by" credit.
* Move PHY lane swapping to PHY driver (per Andrew Lunn and Florian
Fainelli)
* Remove bgmac sleep (per Florian Fainelli)
* Re-add bgmac chip reset (per Florian Fainelli and Ray Jui)
* Rebased on latest net-next
* Added patch for bcm54xx_auxctl_read, which is used in the BCM54810
Add support for the amac found in the Broadcom Northstar2 SoC to the
bgmac driver. This necessitates adding support to connect to an
externally defined phy (as described in the device tree) in the driver.
These phy changes are in addition to the changes necessary to get NS2
working.
Jon Mason (7):
net: phy: broadcom: add bcm54xx_auxctl_read
Documentation: devicetree: add PHY lane swap binding
net: phy: broadcom: Add BCM54810 PHY entry
Documentation: devicetree: net: add NS2 bindings to amac
net: ethernet: bgmac: device tree phy enablement
net: ethernet: bgmac: add NS2 support
arm64: dts: NS2: add AMAC ethernet support
.../devicetree/bindings/net/brcm,amac.txt | 16 ++--
Documentation/devicetree/bindings/net/phy.txt | 3 +
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 ++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 +++
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 100 ++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 55 ++----------
drivers/net/ethernet/broadcom/bgmac.h | 8 ++
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 68 +++++++++++++-
include/linux/brcmphy.h | 10 +++
11 files changed, 270 insertions(+), 57 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v2 3/3] clocksource: Add clockevent support to NPS400 driver
From: Daniel Lezcano @ 2016-11-01 20:01 UTC (permalink / raw)
To: Noam Camus
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Vineet Gupta
In-Reply-To: <DB6PR0501MB2518720A0F95ACBBBCB1CB27AAAE0-wTfl6qNNZ1PL+HUNrKNnF8DSnupUy6xnnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
On Mon, Oct 31, 2016 at 05:03:40PM +0000, Noam Camus wrote:
> >From: Daniel Lezcano [mailto:daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org]
> >Sent: Monday, October 31, 2016 12:53 PM
>
> >>
> >> The design idea is that for each core there is dedicated regirtser
>
> >s/regirtser/register/
>
> >Hey ! re-read yourself.
> Thanks, I do but sometimes reading over and over and still left with such typos
> Will Fix on next patch Set V4
>
> >> (TSI) serving all 16 HW threads.
> >> The register is a bitmask with one bit for each HW thread.
> >> When HW thread wants that next expiration of timer interrupt will hit
> >> it then the proper bit should be set in this dedicated register.
>
> >I'm not sure to understand this sentence. Do you mean each cpu/thread must
> >set a flag in the TSI register at BIT(phys_id) when they set a timer ?
> Correct, each thread needs to set its bit in TSI register, otherwise the he
> won't be interrupted by timer.
>
> >> When timer expires all HW threads within this core which their bit is
> >> set at the TSI register will be interrupted.
>
> >Does it mean some HW threads will be wake up for nothing ?
> See below after the example you gave
>
> >eg.
>
> >HWT1 sets the timer to expire within 2 seconds
> >HWT2 sets the timer to expire within 2 hours
>
> >When the first timer expires, that will wake up HWT1 *and* HWT2 ?
>
> You are correct, indeed not optimal but much simpler than managing book
> keeping of all 16 threads. Functionality wise one who registered this timer
> will notice that it expired too soon and will register a new one. This is how
> it works now in our machines.
Assuming cpu0 and cpu1 are sibling, does
taskset 0x1 time sleep 2 & taskset 0x2 time sleep 3
give a correct result without a dmesg log ?
Can you give the content of the /proc/timer_list ?
I'm not sure it is safe to have this kind of spurious interrupt for the time
framework.
> >The code is a bit confusing because of the very specific design of this timer.
>
> >Below more questions for clarification.
>
> ...
> >> diff --git a/drivers/clocksource/timer-nps.c
> >> b/drivers/clocksource/timer-nps.c index 6156e54..0757328 100644
> >> --- a/drivers/clocksource/timer-nps.c
> >> +++ b/drivers/clocksource/timer-nps.c
> >> @@ -46,7 +46,7 @@
> >> /* This array is per cluster of CPUs (Each NPS400 cluster got 256
> >> CPUs) */ static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM]
> >> __read_mostly;
> >>
> >> -static unsigned long nps_timer_rate;
> >> +static unsigned long nps_timer1_freq;
> >
> >Why declare a global static variable for a local use in nps_setup_clocksource ?
> Indeed no need. It will be fixed at V4
>
> ...
> >> +/* Timer related Aux registers */
> >> +#define AUX_REG_TIMER0_TSI 0xFFFFF850 /* timer 0 HW threads mask */
> >> +#define NPS_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
> >> +#define NPS_REG_TIMER0_CTRL 0x22 /* timer 0 control */
> >> +#define NPS_REG_TIMER0_CNT 0x21 /* timer 0 count */
> >> +
> >> +#define TIMER0_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
> >> +#define TIMER0_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
>
> >Please, use BIT(nr) macro.
> Will fix that on V4.
>
> >Can you elaborate "Count only when CPU NOT halted" ?
> The Idea here is:
> The Not Halted mode flag (NH) causes cycles to be counted only when the
> processor is running (not halted). When set to 0 the timer will count every
> clock cycle. When set to 1 the timer will only count when the processor is
> running. The NH flag is set to 0 when the processor is Reset.
When is the processor halted ? At idle time ?
There is an inconsistency here:
- If the power management of the CPU allows to power it down and the timer
belongs to the same power domain to the CPU, then it will be powered down
also. In this case, the C3STOP flag must be used and the CPU wakeup must be
delegated to a backup timer.
- If there is no power management on the CPU. The timer must continue to
count cycles in order to wake up the CPU if it is halted (assuming it
is clock gated).
In both cases, TIMER0_CTRL_NH is not needed.
Or is the CPU halted *only* when debugging it ?
> It may be used when working with JTAG (I never used it this way though).
>
> >> +static unsigned long nps_timer0_freq; static unsigned long
> >> +nps_timer0_irq;
> >> +
> >> +/*
> >> + * Arm the timer to interrupt after @cycles */ static void
> >> +nps_clkevent_timer_event_setup(unsigned int cycles) {
> >> + write_aux_reg(NPS_REG_TIMER0_LIMIT, cycles);
> >> + write_aux_reg(NPS_REG_TIMER0_CNT, 0); /* start from 0 */
> >> +
> >> + write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_IE | TIMER0_CTRL_NH);
> >> +}
> >> +
> >> +static void nps_clkevent_rm_thread(bool remove_thread) {
> >> + unsigned int cflags;
> >> + unsigned int enabled_threads;
> >> + unsigned long flags;
> >> + int thread;
> >> +
> >> + local_irq_save(flags);
> >> + hw_schd_save(&cflags);
> >
> >Can you explain why those two lines are needed ?
> The idea is that access to shared core registers (among threads) is not done
> in parallel to keep their consistency. For example Read Modified Write of TSI
> register is not atomic, so using two lines above avoid any interference during
> this code execution.
Mmmh, I'm not used to hardware scheduling. Why hw_schd_save() is needed ?
regmap provides the API to deal with read/write of shared register.
> >> +
> >> +static int nps_clkevent_set_next_event(unsigned long delta,
> >> + struct clock_event_device *dev) {
> >> + struct irq_desc *desc = irq_to_desc(nps_timer0_irq);
> >> + struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data);
> >> +
> >> + nps_clkevent_add_thread(true);
> >> + chip->irq_unmask(&desc->irq_data);
>
> >Can you explain why invoking low level IRQ callbacks is needed here ?
> I needed those callbacks functionality and didn't want to duplicate it here.
If you need these callbacks here, then there is probably an issue with the
driver design.
> >> +
> >> +static int nps_clkevent_set_periodic(struct clock_event_device *dev)
> >> +{
> >> + nps_clkevent_add_thread(false);
> >> + if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0)
> >> + nps_clkevent_timer_event_setup(nps_timer0_freq / HZ);
>
> >Please explain this. I read only CPU0 can set the periodic timer.
> When system works in periodic mode for clock events we just need to set for
> all HW threads within same core their respective bit at TSI register. We also
> need but only once to arm the shared timer control register. Since that for
> each core thread 0 is always available we choose HW thread 0 to do that. ...
I see. Please, add the explanation as a comment in the code.
> >> +static int __init nps_setup_clockevent(struct device_node *node) {
> >> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> >> + struct clk *clk;
>
> >clk = 0xDEADBEEF
> >> + int ret;
> >> +
> >> + nps_timer0_irq = irq_of_parse_and_map(node, 0);
> >> + if (nps_timer0_irq <= 0) {
> >> + pr_err("clockevent: missing irq");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + nps_get_timer_clk(node, &nps_timer0_freq, clk);
> >> +
> >> + /* Needs apriori irq_set_percpu_devid() done in intc map function */
> >> + ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
> >> + "Timer0 (per-cpu-tick)", evt);
> >> + if (ret) {
> >> + pr_err("Couldn't request irq\n");
> >> + clk_disable_unprepare(clk);
>
> >clk is on the stack, hence returning back from the function, clk is
> >undefined.
>
> >clk_disable_unprepare(0xDEADBEEF) ==> kernel panic
>
> >It does not make sense to add the nps_get_timer_clk() function.
>
> >Better to have a couple of duplicated lines and properly rollback from the
> >right place instead of rollbacking supposed actions taken from inside a
> >function.
> As I wrote above I will use **clk for the rollback, so nps_get_timer_clk()
> will make sense and avoid code duplication.
>
> >> + return ret;
> >> + }
> >> +
> >> + ret = cpuhp_setup_state(CPUHP_AP_NPS_TIMER_STARTING,
> >> + "AP_NPS_TIMER_STARTING",
> >> + nps_timer_starting_cpu,
> >> + nps_timer_dying_cpu);
> >> + if (ret) {
> >> + pr_err("Failed to setup hotplug state");
> >> + clk_disable_unprepare(clk);
> >> + return ret;
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clkevt, "ezchip,nps400-timer0",
> >> + nps_setup_clockevent);
> >> +#endif /* CONFIG_EZNPS_MTM_EXT */
> >> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> >> index 34bd805..9efc1a3 100644
> >> --- a/include/linux/cpuhotplug.h
> >> +++ b/include/linux/cpuhotplug.h
> >> @@ -60,6 +60,7 @@ enum cpuhp_state {
> >> CPUHP_AP_MARCO_TIMER_STARTING,
> >> CPUHP_AP_MIPS_GIC_TIMER_STARTING,
> >> CPUHP_AP_ARC_TIMER_STARTING,
> >> + CPUHP_AP_NPS_TIMER_STARTING,
>
> >Oops, wait. Here, arch/arc/kernel/time.c should be moved in
> >drivers/clocksource and consolidated with this driver.
>
> >Very likely, CPUHP_AP_ARC_TIMER_STARTING can be used for all ARC timers.
>
> Indeed the ARC timer driver served as my inspiration but due to HW threads
> handling they are not the same. Moving drivers from arch/arc to
> driver/clocksource is not my call (Vineet Gupta is the maintainer of ARC) And
> I think they quiet differ now so consolidation gain is not obvious.
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