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* Re: [PATCH 2/3] drm/bridge: Add ti-ftp410 HDMI transmitter driver
From: Laurent Pinchart @ 2016-11-03 17:46 UTC (permalink / raw)
  To: Jyri Sarha
  Cc: devicetree, bcousson, khilman, dri-devel, bgolaszewski,
	tomi.valkeinen
In-Reply-To: <9b6a6a4405de344cb9fbea735fea37adee1d726e.1478103726.git.jsarha@ti.com>

Hi Jyri,

Thank you for the patch.

On Wednesday 02 Nov 2016 18:32:16 Jyri Sarha wrote:
> Add very basic ti-ftp410 HDMI transmitter driver. The only feature
> separating this from a completely dummy bridge is the DDC i2c
> support. However, other HW specific features may be added later when
> needed. For instance there is a set of registers behind i2c if it is
> connected. The implementations is tested against my new tilcdc bridge
> support and works with BeagleBone DVI-D Cape Rev A3. A DT binding
> document is also added.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> ---
>  .../bindings/display/bridge/ti,tfp410.txt          |  30 ++++
>  drivers/gpu/drm/bridge/Kconfig                     |   7 +
>  drivers/gpu/drm/bridge/Makefile                    |   1 +
>  drivers/gpu/drm/bridge/ti-tfp410.c                 | 199 ++++++++++++++++++
>  4 files changed, 237 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt create mode
> 100644 drivers/gpu/drm/bridge/ti-tfp410.c
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
> b/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt new file
> mode 100644
> index 0000000..dc93713
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
> @@ -0,0 +1,30 @@
> +TFP410 HDMI/DVI bridge bindings

I'd name the document "TI TFP410 DVI Transmitter". DVI bridge doesn't tell 
whether the device is a receiver or transmitter.

> +Required properties:
> +	- compatible: "ti,tfp410"

The device is an I2C slave, it should have a reg property. Given that the chip 
can be used without being controlled through I2C, the reg property should be 
optional. You should document this clearly, and explain how the DT node can be 
instantiated as a child of an I2C controller when the I2C interface is used, 
or in other parts of the device tree otherwise.

> +Optional properties:
> +	- ddc-i2c: phandle of an I2C controller used for DDC EDID probing

The TFP410 doesn't handle DDC, this property should be part of the connector 
node.

> +Optional subnodes:
> +	- video input: this subnode can contain a video input port node
> +	  to connect the bridge to a display controller output (See this
> +	  documentation [1]).

You also need an output port for the DVI output. Those two ports should be 
required, not optional.

> +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +Example:
> +	hdmi-bridge {
> +		compatible = "ti,tfp410";
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +				bridge_in: endpoint {
> +					remote-endpoint = <&dc_out>;
> +				};
> +			};
> +		};
> +	};


> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index bd6acc8..a424e03 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -81,6 +81,13 @@ config DRM_TOSHIBA_TC358767
>  	---help---
>  	  Toshiba TC358767 eDP bridge chip driver.
> 
> +config DRM_TI_TFP410
> +	tristate "TI TFP410 DVI/HDMI bridge"
> +	depends on OF
> +	select DRM_KMS_HELPER
> +	---help---
> +	  Texas Instruments TFP410 DVI/HDMI Transmitter driver
> +
>  source "drivers/gpu/drm/bridge/analogix/Kconfig"
> 
>  source "drivers/gpu/drm/bridge/adv7511/Kconfig"
> diff --git a/drivers/gpu/drm/bridge/Makefile
> b/drivers/gpu/drm/bridge/Makefile index 97ed1a5..8b065d9 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o
>  obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
>  obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> +obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c
> b/drivers/gpu/drm/bridge/ti-tfp410.c new file mode 100644
> index 0000000..b0753d2
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ti-tfp410.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright (C) 2016 Texas Instruments
> + * Author: Jyri Sarha <jsarha@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> by + * the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_graph.h>
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +
> +struct tfp410 {
> +	struct drm_bridge	bridge;
> +	struct drm_connector	connector;
> +
> +	struct i2c_adapter	*ddc;
> +
> +	struct device *dev;
> +};
> +
> +static inline struct tfp410 *
> +drm_bridge_to_tfp410(struct drm_bridge *bridge)
> +{
> +	return container_of(bridge, struct tfp410, bridge);
> +}
> +
> +static inline struct tfp410 *
> +drm_connector_to_tfp410(struct drm_connector *connector)
> +{
> +	return container_of(connector, struct tfp410, connector);
> +}
> +
> +static int tfp410_get_modes(struct drm_connector *connector)
> +{
> +	struct tfp410 *hdmi = drm_connector_to_tfp410(connector);
> +	struct edid *edid;
> +	int ret;
> +
> +	if (!hdmi->ddc)
> +		goto fallback;
> +
> +	edid = drm_get_edid(connector, hdmi->ddc);
> +	if (!edid) {
> +		DRM_INFO("EDID read failed. Fallback to standard modes\n");
> +		goto fallback;
> +	}
> +
> +	drm_mode_connector_update_edid_property(connector, edid);
> +
> +	return drm_add_edid_modes(connector, edid);
> +fallback:
> +	/* No EDID, fallback on the XGA standard modes */
> +	ret = drm_add_modes_noedid(connector, 1920, 1200);
> +
> +	/* And prefer a mode pretty much anything can handle */
> +	drm_set_preferred_mode(connector, 1024, 768);
> +
> +	return ret;
> +}
> +
> +static const struct drm_connector_helper_funcs tfp410_con_helper_funcs = {
> +	.get_modes	= tfp410_get_modes,
> +};
> +
> +static enum drm_connector_status
> +tfp410_connector_detect(struct drm_connector *connector, bool force)
> +{
> +	struct tfp410 *hdmi = drm_connector_to_tfp410(connector);
> +
> +	if (hdmi->ddc) {
> +		if (drm_probe_ddc(hdmi->ddc))
> +			return connector_status_connected;
> +		else
> +			return connector_status_disconnected;
> +	}
> +
> +	return connector_status_unknown;
> +}
> +
> +static const struct drm_connector_funcs tfp410_con_funcs = {
> +	.dpms			= drm_atomic_helper_connector_dpms,
> +	.detect			= tfp410_connector_detect,
> +	.fill_modes		= drm_helper_probe_single_connector_modes,
> +	.destroy		= drm_connector_cleanup,
> +	.reset			= drm_atomic_helper_connector_reset,
> +	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
> +	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int tfp410_attach(struct drm_bridge *bridge)
> +{
> +	struct tfp410 *hdmi = drm_bridge_to_tfp410(bridge);
> +	int ret;
> +
> +	if (!bridge->encoder) {
> +		dev_err(hdmi->dev, "Missing encoder\n");
> +		return -ENODEV;
> +	}
> +
> +	drm_connector_helper_add(&hdmi->connector,
> +				 &tfp410_con_helper_funcs);
> +	ret = drm_connector_init(bridge->dev, &hdmi->connector,
> +				 &tfp410_con_funcs, DRM_MODE_CONNECTOR_HDMIA);
> +	if (ret) {
> +		dev_err(hdmi->dev, "drm_connector_init() failed: %d\n", ret);
> +		return ret;
> +	}
> +
> +	drm_mode_connector_attach_encoder(&hdmi->connector,
> +					  bridge->encoder);
> +
> +	return 0;
> +}
> +
> +static const struct drm_bridge_funcs tfp410_bridge_funcs = {
> +	.attach		= tfp410_attach,
> +};
> +
> +static int tfp410_probe(struct platform_device *pdev)
> +{
> +	struct device_node *ddc_phandle;
> +	struct tfp410 *hdmi;
> +	int ret;
> +
> +	if (!pdev->dev.of_node) {
> +		dev_err(&pdev->dev, "device-tree data is missing\n");
> +		return -ENXIO;
> +	}
> +
> +	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
> +	if (!hdmi)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, hdmi);
> +
> +	ddc_phandle = of_parse_phandle(pdev->dev.of_node, "ddc-i2c", 0);
> +	if (ddc_phandle) {
> +		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_phandle);
> +		of_node_put(ddc_phandle);
> +		if (!hdmi->ddc)
> +			return -EPROBE_DEFER;
> +	} else {
> +		dev_info(&pdev->dev,
> +			 "No ddc i2c bus, disabling EDID readout\n");
> +	}
> +
> +	hdmi->bridge.funcs = &tfp410_bridge_funcs;
> +	hdmi->bridge.of_node = pdev->dev.of_node;
> +	hdmi->dev = &pdev->dev;
> +
> +	ret = drm_bridge_add(&hdmi->bridge);
> +	if (ret) {
> +		dev_err(&pdev->dev, "drm_bridge_add() failed: %d\n", ret);
> +		goto fail;
> +	}
> +
> +	return 0;
> +fail:
> +	i2c_put_adapter(hdmi->ddc);
> +	return ret;
> +}
> +
> +static int tfp410_remove(struct platform_device *pdev)
> +{
> +	struct tfp410 *hdmi = platform_get_drvdata(pdev);
> +
> +	drm_bridge_remove(&hdmi->bridge);
> +
> +	if (hdmi->ddc)
> +		i2c_put_adapter(hdmi->ddc);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id tfp410_match[] = {
> +	{ .compatible = "ti,tfp410" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, tfp410_match);
> +
> +struct platform_driver tfp410_driver = {
> +	.probe	= tfp410_probe,
> +	.remove	= tfp410_remove,
> +	.driver	= {
> +		.name		= "tfp410-bridge",
> +		.of_match_table	= tfp410_match,
> +	},
> +};
> +module_platform_driver(tfp410_driver);
> +
> +MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
> +MODULE_DESCRIPTION("TI TFP410 HDMI bridge driver");
> +MODULE_LICENSE("GPL");

-- 
Regards,

Laurent Pinchart

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply

* Re: [PATCH 3/3] drm/tilcdc: Add drm bridge support for attaching drm bridge drivers
From: Laurent Pinchart @ 2016-11-03 17:50 UTC (permalink / raw)
  To: Jyri Sarha
  Cc: devicetree, bcousson, khilman, dri-devel, bgolaszewski,
	tomi.valkeinen
In-Reply-To: <463d18493ac508708ed764e71d11c2b89662544c.1478103726.git.jsarha@ti.com>

Hi Jyri,

Thank you for the patch.

On Wednesday 02 Nov 2016 18:32:17 Jyri Sarha wrote:
> Adds drm bride support for attaching drm bridge drivers to tilcdc. The
> decision whether a video port leads to an external encoder or bridge
> is made simply based on remote device's compatible string. The code
> has been tested with BeagleBone-Black with and without BeagleBone
> DVI-D Cape Rev A3 using ti-tfp410 driver.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> ---
>  .../devicetree/bindings/display/tilcdc/tilcdc.txt  |   7 +-
>  drivers/gpu/drm/tilcdc/tilcdc_drv.c                |   7 +-
>  drivers/gpu/drm/tilcdc/tilcdc_drv.h                |   2 +
>  drivers/gpu/drm/tilcdc/tilcdc_external.c           | 140 ++++++++++++++---
>  drivers/gpu/drm/tilcdc/tilcdc_external.h           |   1 +
>  5 files changed, 135 insertions(+), 22 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt index
> 6fddb4f..ae7a942 100644
> --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> @@ -34,9 +34,10 @@ Optional properties:
> 
>  Optional nodes:
> 
> - - port/ports: to describe a connection to an external encoder. The
> -   binding follows Documentation/devicetree/bindings/graph.txt and
> -   suppors a single port with a single endpoint.
> + - port/ports: to describe a connection to an external encoder or
> +   bridge. The binding follows

What's the difference between encoder and bridge here ? drm_bridge and 
drm_encoder are irrelevant to DT bindings, we should only care about the 
hardware view of the system here.

> +   Documentation/devicetree/bindings/graph.txt and suppors a single
> +   port with a single endpoint.
> 
>   - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
>     Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for
> connecting diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
> b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index dcc9621..ec22576 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
> @@ -384,9 +384,14 @@ static int tilcdc_init(struct drm_driver *ddrv, struct
> device *dev) ret = tilcdc_add_external_encoders(ddev);
>  		if (ret < 0)
>  			goto init_failed;
> +	} else {
> +		ret = tilcdc_attach_remote_device(ddev);
> +		if (ret)
> +			goto init_failed;
>  	}
> 
> -	if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
> +	if (!priv->remote_encoder &&
> +	    ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
>  		dev_err(dev, "no encoders/connectors found\n");
>  		ret = -ENXIO;
>  		goto init_failed;
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
> b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index d31fe5d..283ff28 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
> @@ -90,6 +90,8 @@ struct tilcdc_drm_private {
>  	struct drm_connector *connectors[8];
>  	const struct drm_connector_helper_funcs *connector_funcs[8];
> 
> +	struct drm_encoder *remote_encoder;
> +
>  	bool is_registered;
>  	bool is_componentized;
>  };
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c
> b/drivers/gpu/drm/tilcdc/tilcdc_external.c index 06a4c58..bcb1324 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_external.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.c
> @@ -28,6 +28,18 @@
>  		.raster_order           = 0,
>  };
> 
> +static const struct tilcdc_panel_info panel_info_default = {
> +		.ac_bias                = 255,
> +		.ac_bias_intrpt         = 0,
> +		.dma_burst_sz           = 16,
> +		.bpp                    = 16,
> +		.fdd                    = 0x80,
> +		.tft_alt_mode           = 0,
> +		.sync_edge              = 0,
> +		.sync_ctrl              = 1,
> +		.raster_order           = 0,
> +};
> +
>  static int tilcdc_external_mode_valid(struct drm_connector *connector,
>  				      struct drm_display_mode *mode)
>  {
> @@ -130,6 +142,101 @@ void tilcdc_remove_external_encoders(struct drm_device
> *dev) priv->connector_funcs[i]);
>  }
> 
> +static struct drm_encoder_funcs tilcdc_remote_encoder_funcs = {
> +	.destroy	= drm_encoder_cleanup,
> +};
> +
> +static
> +int tilcdc_attach_bridge(struct drm_device *ddev, struct drm_bridge
> *bridge) +{
> +	struct tilcdc_drm_private *priv = ddev->dev_private;
> +	int ret;
> +
> +	priv->remote_encoder->possible_crtcs = BIT(0);
> +	priv->remote_encoder->bridge = bridge;
> +	bridge->encoder = priv->remote_encoder;
> +
> +	ret = drm_bridge_attach(ddev, bridge);
> +	if (ret) {
> +		dev_err(ddev->dev, "drm_bridge_attach() failed %d\n", ret);
> +		return ret;
> +	}
> +
> +	tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_default);
> +
> +	return 0;
> +}
> +
> +static int tilcdc_node_has_port(struct device_node *dev_node)
> +{
> +	struct device_node *node;
> +
> +	node = of_get_child_by_name(dev_node, "ports");
> +	if (!node)
> +		node = of_get_child_by_name(dev_node, "port");
> +	if (!node)
> +		return 0;
> +	of_node_put(node);
> +
> +	return 1;
> +}
> +
> +static
> +struct device_node *tilcdc_get_remote_node(struct device_node *node)
> +{
> +	struct device_node *ep;
> +	struct device_node *parent;
> +
> +	if (!tilcdc_node_has_port(node))
> +		return NULL;
> +
> +	ep = of_graph_get_next_endpoint(node, NULL);
> +	if (!ep)
> +		return NULL;
> +
> +	parent = of_graph_get_remote_port_parent(ep);
> +	of_node_put(ep);
> +
> +	return parent;
> +}
> +
> +int tilcdc_attach_remote_device(struct drm_device *ddev)
> +{
> +	struct tilcdc_drm_private *priv = ddev->dev_private;
> +	struct device_node *remote_node;
> +	struct drm_bridge *bridge;
> +	int ret;
> +
> +	remote_node = tilcdc_get_remote_node(ddev->dev->of_node);
> +	if (!remote_node)
> +		return 0;
> +
> +	bridge = of_drm_find_bridge(remote_node);
> +	of_node_put(remote_node);
> +	if (!bridge)
> +		return -EPROBE_DEFER;
> +
> +	priv->remote_encoder = devm_kzalloc(ddev->dev,
> +					    sizeof(*priv->remote_encoder),
> +					    GFP_KERNEL);
> +	if (!priv->remote_encoder)
> +		return -ENOMEM;
> +
> +	ret = drm_encoder_init(ddev, priv->remote_encoder,
> +			       &tilcdc_remote_encoder_funcs,
> +			       DRM_MODE_ENCODER_NONE, NULL);
> +	if (ret) {
> +		dev_err(ddev->dev, "drm_encoder_init() failed %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = tilcdc_attach_bridge(ddev, bridge);
> +	if (ret)
> +		drm_encoder_cleanup(priv->remote_encoder);
> +
> +	return ret;
> +}
> +
>  static int dev_match_of(struct device *dev, void *data)
>  {
>  	return dev->of_node == data;
> @@ -141,16 +248,10 @@ int tilcdc_get_external_components(struct device *dev,
> struct device_node *node;
>  	struct device_node *ep = NULL;
>  	int count = 0;
> +	int ret = 0;
> 
> -	/* Avoid error print by of_graph_get_next_endpoint() if there
> -	 * is no ports present.
> -	 */
> -	node = of_get_child_by_name(dev->of_node, "ports");
> -	if (!node)
> -		node = of_get_child_by_name(dev->of_node, "port");
> -	if (!node)
> +	if (!tilcdc_node_has_port(dev->of_node))
>  		return 0;
> -	of_node_put(node);
> 
>  	while ((ep = of_graph_get_next_endpoint(dev->of_node, ep))) {
>  		node = of_graph_get_remote_port_parent(ep);
> @@ -160,17 +261,20 @@ int tilcdc_get_external_components(struct device *dev,
> }
> 
>  		dev_dbg(dev, "Subdevice node '%s' found\n", node->name);
> -		if (match)
> -			drm_of_component_match_add(dev, match, dev_match_of,
> -						   node);
> -		of_node_put(node);
> -		count++;
> -	}
> 
> -	if (count > 1) {
> -		dev_err(dev, "Only one external encoder is supported\n");
> -		return -EINVAL;
> +		if (of_device_is_compatible(node, "nxp,tda998x")) {
> +			if (match)
> +				drm_of_component_match_add(dev, match,
> +							   dev_match_of, 
node);
> +			ret = 1;
> +		}
> +
> +		of_node_put(node);
> +		if (count++ > 1) {
> +			dev_err(dev, "Only one port is supported\n");
> +			return -EINVAL;
> +		}
>  	}
> 
> -	return count;
> +	return ret;
>  }
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.h
> b/drivers/gpu/drm/tilcdc/tilcdc_external.h index c700e0c..a27c365 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_external.h
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.h
> @@ -22,4 +22,5 @@
>  void tilcdc_remove_external_encoders(struct drm_device *dev);
>  int tilcdc_get_external_components(struct device *dev,
>  				   struct component_match **match);
> +int tilcdc_attach_remote_device(struct drm_device *ddev);
>  #endif /* __TILCDC_SLAVE_H__ */

-- 
Regards,

Laurent Pinchart

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dri-devel mailing list
dri-devel@lists.freedesktop.org
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* Re: [PATCH v2 3/3] reset: Add the TI SCI reset driver
From: Andrew F. Davis @ 2016-11-03 17:50 UTC (permalink / raw)
  To: Philipp Zabel
  Cc: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring,
	Mark Rutland, Suman Anna,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477647364.3010.28.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

On 10/28/2016 04:36 AM, Philipp Zabel wrote:
> Hi Andrew,
> 
> is there (going to be) as stable branch I can base these on, or should I
> just wait until the prerequisite patches appear in arm-soc/for-next?
> 
> Am Donnerstag, den 27.10.2016, 16:49 -0500 schrieb Andrew F. Davis:
>> Some TI Keystone family of SoCs contain a system controller (like the
>> Power Management Micro Controller (PMMC) on K2G SoCs) that manage the
>> low-level device control (like clocks, resets etc) for the various
>> hardware modules present on the SoC. These device control operations
>> are provided to the host processor OS through a communication protocol
>> called the TI System Control Interface (TI SCI) protocol.
>>
>> This patch adds a reset driver that communicates to the system
>> controller over the TI SCI protocol for performing reset management
>> of various devices present on the SoC. Various reset functionalities
>> are achieved by the means of different TI SCI device operations
>> provided by the TI SCI framework.
>>
>> Signed-off-by: Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>
>> [s-anna-l0cyMroinI0@public.gmane.org: documentation changes, revised commit message]
>> Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
>> Signed-off-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
>> ---
>>  MAINTAINERS                  |   1 +
>>  drivers/reset/Kconfig        |   9 ++
>>  drivers/reset/Makefile       |   1 +
>>  drivers/reset/reset-ti-sci.c | 262 +++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 273 insertions(+)
>>  create mode 100644 drivers/reset/reset-ti-sci.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index accf991..b93d91a 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -11901,6 +11901,7 @@ F:	include/dt-bindings/clock/k2g.h
>>  F:	drivers/clk/keystone/sci-clk.c
>>  F:	Documentation/devicetree/bindings/reset/ti,sci-reset.txt
>>  F:	include/dt-bindings/reset/k2g.h
>> +F:	drivers/reset/reset-ti-sci.c
>>  
>>  THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
>>  M:	Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 06d9fa2..4c21c9d 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -66,6 +66,15 @@ config RESET_SUNXI
>>  	help
>>  	  This enables the reset driver for Allwinner SoCs.
>>  
>> +config RESET_TI_SCI
>> +	tristate "TI System Control Interface (TI-SCI) reset driver"
>> +	depends on RESET_CONTROLLER
>> +	depends on TI_SCI_PROTOCOL
>> +	help
>> +	  This enables the reset driver support over TI System Control Interface
>> +	  available on some new TI SoCs. If you wish to use reset resources
>> +	  managed by the TI System Controller, say Y here. Otherwise, say N.
>> +
>>  config TI_SYSCON_RESET
>>  	tristate "TI SYSCON Reset Driver"
>>  	depends on HAS_IOMEM
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index bbe7026..36321f2 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>>  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>>  obj-$(CONFIG_RESET_STM32) += reset-stm32.o
>>  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>> +obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
>>  obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
>>  obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>>  obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
>> diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c
>> new file mode 100644
>> index 0000000..42ccf12
>> --- /dev/null
>> +++ b/drivers/reset/reset-ti-sci.c
>> @@ -0,0 +1,262 @@
>> +/*
>> + * Texas Instrument's System Control Interface (TI-SCI) reset driver
>> + *
>> + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
>> + *	Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/idr.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/soc/ti/ti_sci_protocol.h>
>> +
>> +/**
>> + * struct ti_sci_reset_control - reset control structure
>> + * @dev_id: SoC-specific device identifier
>> + * @reset_mask: reset mask to use for toggling reset
>> + */
>> +struct ti_sci_reset_control {
>> +	u32 dev_id;
>> +	u32 reset_mask;
>> +};
>> +
>> +/**
>> + * struct ti_sci_reset_data - reset controller information structure
>> + * @rcdev: reset controller entity
>> + * @dev: reset controller device pointer
>> + * @sci: TI SCI handle used for communication with system controller
>> + * @idr: idr structure for mapping ids to reset control structures
>> + */
>> +struct ti_sci_reset_data {
>> +	struct reset_controller_dev rcdev;
>> +	struct device *dev;
>> +	const struct ti_sci_handle *sci;
>> +	struct idr idr;
>> +};
>> +
>> +#define to_ti_sci_reset_data(p)	\
>> +	container_of((p), struct ti_sci_reset_data, rcdev)
>> +
>> +/**
>> + * ti_sci_reset_set() - program a device's reset
>> + * @rcdev: reset controller entity
>> + * @id: ID of the reset to toggle
>> + * @assert: boolean flag to indicate assert or deassert
>> + *
>> + * This is a common internal function used to assert or deassert a device's
>> + * reset using the TI SCI protocol. The device's reset is asserted if the
>> + * @assert argument is true, or deasserted if @assert argument is false.
>> + * The mechanism itself is a read-modify-write procedure, the current device
>> + * reset register is read using a TI SCI device operation, the new value is
>> + * set or un-set using the reset's mask, and the new reset value written by
>> + * using another TI SCI device operation.
>> + *
>> + * Return: 0 for successful request, else a corresponding error value
>> + */
>> +static int ti_sci_reset_set(struct reset_controller_dev *rcdev,
>> +			    unsigned long id, bool assert)
>> +{
>> +	struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
>> +	const struct ti_sci_handle *sci = data->sci;
>> +	const struct ti_sci_dev_ops *dev_ops = &sci->ops.dev_ops;
>> +	struct ti_sci_reset_control *control;
>> +	u32 reset_state;
>> +	int ret;
>> +
>> +	control = idr_find(&data->idr, id);
>> +	if (!control)
>> +		return -EINVAL;
>> +
>> +	ret = dev_ops->get_device_resets(sci, control->dev_id,
>> +					 &reset_state);
>> +	if (ret)
>> +		return ret;
>> +
>> +	if (assert)
>> +		reset_state |= control->reset_mask;
>> +	else
>> +		reset_state &= ~control->reset_mask;
>> +
>> +	return dev_ops->set_device_resets(sci, control->dev_id,
>> +					  reset_state);
> 
> Without any locking? Maybe the read-modify-write could just be moved one
> level down with an update_bits type of callback in the ti_sci_dev_ops.
> 

That may be useful to add at some point, for now I want to work with the
existing framework, it can always be moved later. I'll add some
per-control locks for v3.

Thanks,
Andrew

>> +}
>> +
>> +/**
>> + * ti_sci_reset_assert() - assert device reset
>> + * @rcdev: reset controller entity
>> + * @id: ID of the reset to be asserted
>> + *
>> + * This function implements the reset driver op to assert a device's reset
>> + * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
>> + * with the corresponding parameters as passed in, but with the @assert
>> + * argument set to true for asserting the reset.
>> + *
>> + * Return: 0 for successful request, else a corresponding error value
>> + */
>> +static int ti_sci_reset_assert(struct reset_controller_dev *rcdev,
>> +			       unsigned long id)
>> +{
>> +	return ti_sci_reset_set(rcdev, id, true);
>> +}
>> +
>> +/**
>> + * ti_sci_reset_deassert() - deassert device reset
>> + * @rcdev: reset controller entity
>> + * @id: ID of the reset to be deasserted
>> + *
>> + * This function implements the reset driver op to deassert a device's reset
>> + * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
>> + * with the corresponding parameters as passed in, but with the @assert
>> + * argument set to false for deasserting the reset.
>> + *
>> + * Return: 0 for successful request, else a corresponding error value
>> + */
>> +static int ti_sci_reset_deassert(struct reset_controller_dev *rcdev,
>> +				 unsigned long id)
>> +{
>> +	return ti_sci_reset_set(rcdev, id, false);
>> +}
>> +
>> +/**
>> + * ti_sci_reset_status() - check device reset status
>> + * @rcdev: reset controller entity
>> + * @id: ID of reset to be checked
>> + *
>> + * This function implements the reset driver op to return the status of a
>> + * device's reset using the TI SCI protocol. The reset register value is read
>> + * by invoking the TI SCI device opertation .get_device_resets(), and the
>> + * status of the specific reset is extracted and returned using this reset's
>> + * reset mask.
>> + *
>> + * Return: 0 if reset is deasserted, or a non-zero value if reset is asserted
>> + */
>> +static int ti_sci_reset_status(struct reset_controller_dev *rcdev,
>> +			       unsigned long id)
>> +{
>> +	struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
>> +	const struct ti_sci_handle *sci = data->sci;
>> +	const struct ti_sci_dev_ops *dev_ops = &sci->ops.dev_ops;
>> +	struct ti_sci_reset_control *control;
>> +	u32 reset_state;
>> +	int ret;
>> +
>> +	control = idr_find(&data->idr, id);
>> +	if (!control)
>> +		return -EINVAL;
>> +
>> +	ret = dev_ops->get_device_resets(sci, control->dev_id,
>> +					 &reset_state);
>> +	if (ret)
>> +		return ret;
>> +
>> +	return reset_state & control->reset_mask;
>> +}
>> +
>> +static struct reset_control_ops ti_sci_reset_ops = {
>> +	.assert		= ti_sci_reset_assert,
>> +	.deassert	= ti_sci_reset_deassert,
>> +	.status		= ti_sci_reset_status,
>> +};
>> +
>> +/**
>> + * ti_sci_reset_of_xlate() - translate a set of OF arguments to a reset ID
>> + * @rcdev: reset controller entity
>> + * @reset_spec: OF reset argument specifier
>> + *
>> + * This function performs the translation of the reset argument specifier
>> + * values defined in a reset consumer device node. The function allocates a
>> + * reset control structure for that device reset, and will be used by the
>> + * driver for performing any reset functions on that reset. An idr structure
>> + * is allocated and used to map to the reset control structure. This idr
>> + * is used by the driver to do reset lookups.
>> + *
>> + * Return: 0 for successful request, else a corresponding error value
>> + */
>> +static int ti_sci_reset_of_xlate(struct reset_controller_dev *rcdev,
>> +				 const struct of_phandle_args *reset_spec)
>> +{
>> +	struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
>> +	struct ti_sci_reset_control *control;
>> +
>> +	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
>> +		return -EINVAL;
>> +
>> +	control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
>> +	if (!control)
>> +		return -ENOMEM;
>> +
>> +	control->dev_id = reset_spec->args[0];
>> +	control->reset_mask = reset_spec->args[1];
>> +
>> +	return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
>> +}
>> +
>> +static const struct of_device_id ti_sci_reset_of_match[] = {
>> +	{ .compatible = "ti,sci-reset", },
>> +	{ /* sentinel */ },
>> +};
>> +MODULE_DEVICE_TABLE(of, ti_sci_reset_of_match);
>> +
>> +static int ti_sci_reset_probe(struct platform_device *pdev)
>> +{
>> +	struct ti_sci_reset_data *data;
>> +
>> +	if (!pdev->dev.of_node)
>> +		return -ENODEV;
>> +
>> +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
>> +	if (!data)
>> +		return -ENOMEM;
>> +
>> +	data->sci = devm_ti_sci_get_handle(&pdev->dev);
>> +	if (IS_ERR(data->sci))
>> +		return PTR_ERR(data->sci);
>> +
>> +	data->rcdev.ops = &ti_sci_reset_ops;
>> +	data->rcdev.owner = THIS_MODULE;
>> +	data->rcdev.of_node = pdev->dev.of_node;
>> +	data->rcdev.of_reset_n_cells = 2;
>> +	data->rcdev.of_xlate = ti_sci_reset_of_xlate;
>> +	data->dev = &pdev->dev;
>> +	idr_init(&data->idr);
>> +
>> +	platform_set_drvdata(pdev, data);
>> +
>> +	return reset_controller_register(&data->rcdev);
>> +}
>> +
>> +static int ti_sci_reset_remove(struct platform_device *pdev)
>> +{
>> +	struct ti_sci_reset_data *data = platform_get_drvdata(pdev);
>> +
>> +	reset_controller_unregister(&data->rcdev);
>> +
>> +	idr_destroy(&data->idr);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver ti_sci_reset_driver = {
>> +	.probe = ti_sci_reset_probe,
>> +	.remove = ti_sci_reset_remove,
>> +	.driver = {
>> +		.name = "ti-sci-reset",
>> +		.of_match_table = ti_sci_reset_of_match,
>> +	},
>> +};
>> +module_platform_driver(ti_sci_reset_driver);
>> +
>> +MODULE_AUTHOR("Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>");
>> +MODULE_DESCRIPTION("TI System Control Interface (TI SCI) Reset driver");
>> +MODULE_LICENSE("GPL v2");
> 
> regards
> Philipp
> 
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* [PATCH 0/3] arm64: renesas: enable H3ULCB board peripherals
From: Vladimir Barinov @ 2016-11-03 18:04 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Vladimir Barinov

Hello,

This adds the folowing:
- Update DT bindings documentation
- add R8A7795 SoC based H3ULCB board peripherals

Vladimir Barinov (3):
[1/3] dt: arm: shmobile: update H3ULCB board Documentation
[2/3] arm64: dts: h3ulcb: update header
[3/3] arm64: dts: h3ulcb: enable SDHI2

---
This patchset is against the 'kernel/git/horms/renesas.git' repo.

 Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts     | 48 +++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 2 deletions(-)
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* [PATCH 1/3] dt: arm: shmobile: update H3ULCB board Documentation
From: Vladimir Barinov @ 2016-11-03 18:04 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Vladimir Barinov
In-Reply-To: <1478196242-939-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

This updates H3ULCB Device tree bindings Documentation with
official board name

Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 94f2c5f..a1e94da 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -51,7 +51,7 @@ Boards:
     compatible = "renesas,genmai", "renesas,r7s72100"
   - Gose (RTP0RC7793SEB00010S)
     compatible = "renesas,gose", "renesas,r8a7793"
-  - H3ULCB (RTP0RC7795SKB00010S)
+  - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
     compatible = "renesas,h3ulcb", "renesas,r8a7795";
   - Henninger
     compatible = "renesas,henninger", "renesas,r8a7791"
-- 
1.9.1

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* [PATCH 2/3] arm64: dts: h3ulcb: update header
From: Vladimir Barinov @ 2016-11-03 18:04 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Vladimir Barinov
In-Reply-To: <1478196242-939-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

This updates H3ULCB device tree header with official board name

Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index bcb11a8..f178fe1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the H3ULCB board
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
-- 
1.9.1

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* [PATCH 3/3] arm64: dts: h3ulcb: enable SDHI2
From: Vladimir Barinov @ 2016-11-03 18:05 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196242-939-1-git-send-email-vladimir.barinov@cogentembedded.com>

This supports SDHI2 for H3ULCB onboard eMMC

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index a244edb..e46687e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -55,6 +55,24 @@
 		clock-frequency = <24576000>;
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";
 
@@ -113,6 +131,18 @@
 		function = "sdhi0";
 		power-source = <1800>;
 	};
+
+	sdhi2_pins_3v3: sd2_3v3 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_1v8: sd2_1v8 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
 
 	sound_pins: sound {
 		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
@@ -128,6 +158,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins_3v3>;
+	pinctrl-1 = <&sdhi2_pins_1v8>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &ssi1 {
 	shared-pin;
 };
-- 
1.9.1

^ permalink raw reply related

* [PATCH 0/9] arm64: renesas: add M3ULCB board
From: Vladimir Barinov @ 2016-11-03 18:06 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov

Hello,

This adds the folowing:
- R8A7796 SoC based M3ULCB (R-Car Starter Kit Pro) device tree
- Document DT bindings

Vladimir Barinov (9):
[1/9] dt: arm: shmobile: add M3ULCB board DT bindings
[2/9] arm64: dts: m3ulcb: initial device tree
[3/9] arm64: dts: m3ulcb: enable SCIF clk and pins
[4/9] arm64: dts: m3ulcb: enable GPIO leds
[5/9] arm64: dts: m3ulcb: enable GPIO keys
[6/9] arm64: dts: m3ulcb: enable SDHI0
[7/9] arm64: dts: m3ulcb: enable EXTALR clk
[8/9] arm64: dts: m3ulcb: enable WDT
[9/9] arm64: dts: m3ulcb: enable SDHI2

---
This patchset is against the 'kernel/git/horms/renesas.git' repo.

 Documentation/devicetree/bindings/arm/shmobile.txt |   2 +
 arch/arm64/boot/dts/renesas/Makefile               |   2 +-
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts     | 189 +++++++++++++++++++++
 3 files changed, 192 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

^ permalink raw reply

* [PATCH 1/9] dt: arm: shmobile: add M3ULCB board DT bindings
From: Vladimir Barinov @ 2016-11-03 18:06 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

Add M3ULCB Device tree bindings Documentation, listing it as a supported
board.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 9a60cb3..94f2c5f 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -63,6 +63,8 @@ Boards:
     compatible = "renesas,kzm9g", "renesas,sh73a0"
   - Lager (RTP0RC7790SEB00010S)
     compatible = "renesas,lager", "renesas,r8a7790"
+  - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
+    compatible = "renesas,m3ulcb", "renesas,r8a7796";
   - Marzen (R0P7779A00010S)
     compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)
-- 
1.9.1

^ permalink raw reply related

* [PATCH 2/9] arm64: dts: m3ulcb: initial device tree
From: Vladimir Barinov @ 2016-11-03 18:07 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

Add the initial device tree for the R8A7796 SoC based M3ULCB low cost
board (R-Car Starter Kit Pro)

This commit supports the following peripherals:
- SCIF (console)

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/Makefile           |  2 +-
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 51 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index eb72830..1618e0a 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,5 +1,5 @@
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
-dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
+dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
 
 always		:= $(dtb-y)
 clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
new file mode 100644
index 0000000..ecb9e11
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -0,0 +1,51 @@
+/*
+ * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7796.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas M3ULCB board based on r8a7796";
+	compatible = "renesas,m3ulcb", "renesas,r8a7796";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&pfc {
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+};
+
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 3/9] arm64: dts: m3ulcb: enable SCIF clk and pins
From: Vladimir Barinov @ 2016-11-03 18:07 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index ecb9e11..67ce368 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -37,10 +37,18 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: scif2 {
 		groups = "scif2_data_a";
 		function = "scif2";
 	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_a";
+		function = "scif_clk";
+	};
 };
 
 &scif2 {
@@ -49,3 +57,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 4/9] arm64: dts: m3ulcb: enable GPIO leds
From: Vladimir Barinov @ 2016-11-03 18:07 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

This supports GPIO leds on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index fb694b8..3329f78 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -31,6 +31,17 @@
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led5 {
+			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+		};
+		led6 {
+			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
 };
 
 &extal_clk {
-- 
1.9.1

^ permalink raw reply related

* [PATCH 5/9] arm64: dts: m3ulcb: enable GPIO keys
From: Vladimir Barinov @ 2016-11-03 18:07 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

This supports GPIO keys on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 14 +++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index fb694b8..3329f78 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -12,6 +12,7 @@
 /dts-v1/;
 #include "r8a7796.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "Renesas M3ULCB board based on r8a7796";
@@ -31,6 +31,18 @@
 			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
+
+	keyboard {
+		compatible = "gpio-keys";
+
+		key-1 {
+			linux,code = <KEY_1>;
+			label = "SW3";
+			wakeup-source;
+			debounce-interval = <20>;
+			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+		};
+	};
 };
 
 &extal_clk {
-- 
1.9.1

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^ permalink raw reply related

* [PATCH 6/9] arm64: dts: m3ulcb: enable SDHI0
From: Vladimir Barinov @ 2016-11-03 18:07 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

This supports SDHI0 on M3ULCB board SD card slot

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 3329f78..5be0cf6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -44,6 +44,30 @@
 			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &extal_clk {
@@ -68,8 +92,33 @@
 		groups = "scif_clk_a";
 		function = "scif_clk";
 	};
+
+	sdhi0_pins_3v3: sd0_3v3 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_1v8: sd0_1v8 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
 };
 
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins_3v3>;
+	pinctrl-1 = <&sdhi0_pins_1v8>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	status = "okay";
+};
+
 &scif2 {
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

^ permalink raw reply related

* [PATCH 7/9] arm64: dts: m3ulcb: enable EXTALR clk
From: Vladimir Barinov @ 2016-11-03 18:08 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

This enables EXTALR clock that can be used for the watchdog.

Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 3682bcc..6936288 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -74,6 +74,10 @@
 	clock-frequency = <16666666>;
 };
 
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related

* [PATCH 8/9] arm64: dts: m3ulcb: enable WDT
From: Vladimir Barinov @ 2016-11-03 18:08 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

This supports watchdog timer for M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 6936288..bc3d8d5 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -146,3 +146,8 @@
 	clock-frequency = <14745600>;
 	status = "okay";
 };
+
+&wdt0 {
+	timeout-sec = <60>;
+	status = "okay";
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 9/9] arm64: dts: m3ulcb: enable SDHI2
From: Vladimir Barinov @ 2016-11-03 18:08 UTC (permalink / raw)
  To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
  Cc: devicetree, linux-renesas-soc, Vladimir Barinov
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov@cogentembedded.com>

This supports SDHI2 for M3ULCB onboard eMMC

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index a244edb..e46687e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -55,6 +55,24 @@
 		};
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";
 
@@ -113,6 +131,18 @@
 		function = "sdhi0";
 		power-source = <1800>;
 	};
+
+	sdhi2_pins_3v3: sd2_3v3 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_1v8: sd2_1v8 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
 };
 
 &sdhi0 {
@@ -128,6 +158,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins_3v3>;
+	pinctrl-1 = <&sdhi2_pins_1v8>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &scif2 {
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

^ permalink raw reply related

* Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
From: Krzysztof Kozlowski @ 2016-11-03 18:26 UTC (permalink / raw)
  To: Anurup M
  Cc: devicetree, linux-arm-kernel, linux-doc, mark.rutland,
	will.deacon, corbet, catalin.marinas, robh+dt, arnd, f.fainelli,
	rmk+kernel, krzk, anurup.m, zhangshaokun, tanxiaojun, xuwei5,
	sanil.kumar, john.garry, gabriele.paoloni, shiju.jose,
	wangkefeng.wang, guohanjun, shyju.pv, linuxarm
In-Reply-To: <1478151727-20250-6-git-send-email-anurup.m@huawei.com>

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> 	1) Device tree bindings for Hisilicon SoC PMU.
> 	2) Add example for Hisilicon L3 cache, MN and DDRC PMU.

Get rid of this weird indentation in all patches.


> 
> Signed-off-by: Anurup M <anurup.m@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
>  .../devicetree/bindings/arm/hisilicon/pmu.txt      | 127 +++++++++++++++++++++
>  1 file changed, 127 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> new file mode 100644
> index 0000000..e7b35e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> @@ -0,0 +1,127 @@
> +Hisilicon SoC hip05/06/07 ARMv8 PMU
> +===================================
> +
> +The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
> +system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
> +comtroller. These PMU devices are independent and have hardware logic to
> +gather statistics and performance information.
> +
> +HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
> +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
> +e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
> +
> +The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
> +the parent node will be the djtag node of the corresponding CPU die(SCCL).
> +
> +For uncore PMU devices there are some common required properties as detailed
> +below.
> +
> +Required properties:
> +	- compatible : This field contain two values. The first value is
> +		always "hisilicon" and second value is the Module type as shown
> +		in below examples:

Over-complicated sentence. Just:

	- compatible : One of:
		"hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
			device (Version 1)
		...
		...

BTW, No need of CC-ing me. I am not a maintainer of relevant subsystems.

Best regards,
Krzysztof

^ permalink raw reply

* Re: [RESEND/PATCH v6 3/3] clk: qcom: Add A53 clock driver
From: Bjorn Andersson @ 2016-11-03 18:28 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Georgi Djakov, mturquette-rdvid1DuHRBWk0Htik3J/w,
	linux-clk-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring
In-Reply-To: <20161102225520.GW16026-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

On Wed 02 Nov 15:55 PDT 2016, Stephen Boyd wrote:

> On 11/02, Bjorn Andersson wrote:
> > On Thu 27 Oct 18:54 PDT 2016, Stephen Boyd wrote:
> > 
> > > On 10/19, Georgi Djakov wrote:
> > > > Add a driver for the A53 Clock Controller. It is a hardware block that
> > > > implements a combined mux and half integer divider functionality. It can
> > > > choose between a fixed-rate clock or the dedicated A53 PLL. The source
> > > > and the divider can be set both at the same time.
> > > > 
> > > > This is required for enabling CPU frequency scaling on platforms like
> > > > MSM8916.
> > > > 
> > > 
> > > Please Cc DT reviewers.
> > > 
> > > > Signed-off-by: Georgi Djakov <georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > > > ---
> > > >  .../devicetree/bindings/clock/qcom,a53cc.txt       |  22 +++
> > > >  drivers/clk/qcom/Kconfig                           |   8 ++
> > > >  drivers/clk/qcom/Makefile                          |   1 +
> > > >  drivers/clk/qcom/a53cc.c                           | 155 +++++++++++++++++++++
> > > >  4 files changed, 186 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> > > >  create mode 100644 drivers/clk/qcom/a53cc.c
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> > > > new file mode 100644
> > > > index 000000000000..a025f062f177
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> > > > @@ -0,0 +1,22 @@
> > > > +Qualcomm A53 CPU Clock Controller Binding
> > > > +------------------------------------------------
> > > > +The A53 CPU Clock Controller is hardware, which provides a combined
> > > > +mux and divider functionality for the CPU clocks. It can choose between
> > > > +a fixed rate clock and the dedicated A53 PLL.
> > > > +
> > > > +Required properties :
> > > > +- compatible : shall contain:
> > > > +
> > > > +			"qcom,a53cc"
> > > > +
> > > > +- reg : shall contain base register location and length
> > > > +	of the APCS region
> > > > +- #clock-cells : shall contain 1
> > > > +
> > > > +Example:
> > > > +
> > > > +	apcs: syscon@b011000 {
> > > > +		compatible = "qcom,a53cc", "syscon";
> > > 
> > > Why is it a syscon? Is that part used?
> > > 
> > 
> > I use the register at offset 8 for interrupting the other subsystems, so
> > this must be available as something I can poke.
> > 
> > Which makes me think that this should be described as a "simple-mfd" and
> > "syscon" with the a53cc node as a child - grabbing the regmap of the
> > syscon parent, rather then ioremapping the same region again.
> > 
> 
> That's sort of a question for DT reviewers. The register space
> certainly seems like a free for all with a tilt toward power
> management of the CPU, similar to how this was done on Krait
> based designs.
> 

Right. But this kind of mashup blocks was the reason why simple-mfd was
put in place.

> I wonder why we didn't make up some provider/consumer binding for
> the "kicking" feature used by SMD/RPM code. Then this could be a
> clock provider and a "kick" provider (haha #kick-cells) and the
> usage of syscon/regmap wouldn't be mandatory.
> 

I did consider doing that, but had enough dependencies to put in place
as it was.

I'm in favour of us inventing a kicker API and it's found outside out
use cases as well (e.g. virtio/rpmsg).

Regards,
Bjorn
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^ permalink raw reply

* [PATCH 1/2] backlight: arcxcnn: add support for ArticSand devices
From: Olimpiu Dejeu @ 2016-11-03 18:29 UTC (permalink / raw)
  To: robh
  Cc: lee.jones, linux-kernel, linux-fbdev, devicetree, jg1.han,
	Olimpiu Dejeu

Resubmition of arcxcnn backliught driver addressing the naming convention
 concerns raised by Rob H. 

Signed-off-by: Olimpiu Dejeu <olimpiu@arcticsand.com>

---
 drivers/video/backlight/Kconfig      |   7 +
 drivers/video/backlight/Makefile     |   1 +
 drivers/video/backlight/arcxcnn_bl.c | 541 +++++++++++++++++++++++++++++++++++
 include/linux/i2c/arcxcnn.h          |  67 +++++
 4 files changed, 616 insertions(+)
 create mode 100644 drivers/video/backlight/arcxcnn_bl.c
 create mode 100644 include/linux/i2c/arcxcnn.h

diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 5ffa4b4..4e1d2ad 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -460,6 +460,13 @@ config BACKLIGHT_BD6107
 	help
 	  If you have a Rohm BD6107 say Y to enable the backlight driver.
 
+config BACKLIGHT_ARCXCNN
+	tristate "Backlight driver for the Arctic Sands ARCxCnnnn family"
+	depends on I2C
+	help
+	  If you have an ARCxCnnnn family backlight say Y to enable
+	  the backlight driver.
+
 endif # BACKLIGHT_CLASS_DEVICE
 
 endif # BACKLIGHT_LCD_SUPPORT
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 16ec534..8905129 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_BACKLIGHT_SKY81452)	+= sky81452-backlight.o
 obj-$(CONFIG_BACKLIGHT_TOSA)		+= tosa_bl.o
 obj-$(CONFIG_BACKLIGHT_TPS65217)	+= tps65217_bl.o
 obj-$(CONFIG_BACKLIGHT_WM831X)		+= wm831x_bl.o
+obj-$(CONFIG_BACKLIGHT_ARCXCNN) 	+= arcxcnn_bl.o
diff --git a/drivers/video/backlight/arcxcnn_bl.c b/drivers/video/backlight/arcxcnn_bl.c
new file mode 100644
index 0000000..1dad680
--- /dev/null
+++ b/drivers/video/backlight/arcxcnn_bl.c
@@ -0,0 +1,541 @@
+/*
+ * Backlight driver for ArcticSand ARC_X_C_0N_0N Devices
+ *
+ * Copyright 2016 ArcticSand, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/pwm.h>
+#include <linux/regulator/consumer.h>
+
+#include "linux/i2c/arcxcnn.h"
+
+#define ARCXCNN_CMD		(0x00)  /* Command Register */
+#define ARCXCNN_CMD_STDBY	(0x80)	/* I2C Standby */
+#define ARCXCNN_CMD_RESET	(0x40)	/* Reset */
+#define ARCXCNN_CMD_BOOST	(0x10)	/* Boost */
+#define ARCXCNN_CMD_OVP_MASK	(0x0C)	/* --- Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_XXV	(0x0C)	/* <rsvrd> Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_20V	(0x08)	/* 20v Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_24V	(0x04)	/* 24v Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_31V	(0x00)	/* 31.4v Over Voltage Threshold */
+#define ARCXCNN_CMD_EXT_COMP	(0x01)	/* part (0) or full (1) external comp */
+
+#define ARCXCNN_CONFIG	(0x01)  /* Configuration */
+#define ARCXCNN_STATUS1	(0x02)  /* Status 1 */
+#define ARCXCNN_STATUS2	(0x03)  /* Status 2 */
+#define ARCXCNN_FADECTRL	(0x04)  /* Fading Control */
+#define ARCXCNN_ILED_CONFIG	(0x05)  /* ILED Configuration */
+
+#define ARCXCNN_LEDEN		(0x06)  /* LED Enable Register */
+#define ARCXCNN_LEDEN_ISETEXT	(0x80)	/* Full-scale current set externally */
+#define ARCXCNN_LEDEN_MASK	(0x3F)	/* LED string enables */
+#define ARCXCNN_LEDEN_LED1	(0x01)
+#define ARCXCNN_LEDEN_LED2	(0x02)
+#define ARCXCNN_LEDEN_LED3	(0x04)
+#define ARCXCNN_LEDEN_LED4	(0x08)
+#define ARCXCNN_LEDEN_LED5	(0x10)
+#define ARCXCNN_LEDEN_LED6	(0x20)
+
+#define ARCXCNN_WLED_ISET_LSB	(0x07)  /* LED ISET LSB (in upper nibble) */
+#define ARCXCNN_WLED_ISET_MSB	(0x08)  /* LED ISET MSB (8 bits) */
+
+#define ARCXCNN_DIMFREQ		(0x09)
+#define ARCXCNN_COMP_CONFIG	(0x0A)
+#define ARCXCNN_FILT_CONFIG	(0x0B)
+#define ARCXCNN_IMAXTUNE	(0x0C)
+
+#define DEFAULT_BL_NAME		"arctic_bl"
+#define MAX_BRIGHTNESS		4095
+
+static int s_no_reset_on_remove;
+module_param_named(noreset, s_no_reset_on_remove, int, 0644);
+MODULE_PARM_DESC(noreset, "No reset on module removal");
+
+static int s_ibright = 60;
+module_param_named(ibright, s_ibright, int, 0644);
+MODULE_PARM_DESC(ibright, "Initial brightness (when no plat data)");
+
+static int s_iledstr = 0x3F;
+module_param_named(iledstr, s_iledstr, int, 0644);
+MODULE_PARM_DESC(iledstr, "Initial LED String (when no plat data)");
+
+static int s_retries = 2; /* 1 == only one try */
+module_param_named(retries, s_retries, int, 0644);
+MODULE_PARM_DESC(retries, "I2C retries attempted");
+
+enum arcxcnn_brightness_ctrl_mode {
+	PWM_BASED = 1,
+	REGISTER_BASED,
+};
+
+struct arcxcnn;
+
+struct arcxcnn {
+	char chipname[64];
+	enum arcxcnn_chip_id chip_id;
+	enum arcxcnn_brightness_ctrl_mode mode;
+	struct i2c_client *client;
+	struct backlight_device *bl;
+	struct device *dev;
+	struct arcxcnn_platform_data *pdata;
+	struct pwm_device *pwm;
+	struct regulator *supply;	/* regulator for VDD input */
+};
+
+static int arcxcnn_write_byte(struct arcxcnn *lp, u8 reg, u8 data)
+{
+	s32 ret = -1;
+	int att;
+
+	for (att = 0; att < s_retries; att++) {
+		ret = i2c_smbus_write_byte_data(lp->client, reg, data);
+		if (ret >= 0)
+			return 0;
+	}
+	return ret;
+}
+
+static u8 arcxcnn_read_byte(struct arcxcnn *lp, u8 reg)
+{
+	int val;
+	int att;
+
+	for (att = 0; att < s_retries; att++) {
+		val = i2c_smbus_read_byte_data(lp->client, reg);
+		if (val >= 0)
+			return (u8)val;
+	}
+	return 0;
+}
+
+static int arcxcnn_update_bit(struct arcxcnn *lp, u8 reg, u8 mask, u8 data)
+{
+	int ret, att;
+	u8 tmp;
+
+	for (att = 0, ret = -1; att < s_retries; att++) {
+		ret = i2c_smbus_read_byte_data(lp->client, reg);
+		if (ret >= 0)
+			break;
+	}
+	if (ret < 0) {
+		dev_err(lp->dev, "failed to read 0x%.2x\n", reg);
+		return ret;
+	}
+
+	tmp = (u8)ret;
+	tmp &= ~mask;
+	tmp |= data & mask;
+
+	return arcxcnn_write_byte(lp, reg, tmp);
+}
+
+static int arcxcnn_set_brightness(struct arcxcnn *lp, u32 brightness)
+{
+	int ret;
+	u8 val;
+
+	val = (brightness & 0xF) << 4;
+	ret = arcxcnn_write_byte(lp, ARCXCNN_WLED_ISET_LSB, val);
+	if (ret < 0)
+		return ret;
+	val = (brightness >> 4);
+	ret = arcxcnn_write_byte(lp, ARCXCNN_WLED_ISET_MSB, val);
+	return ret;
+}
+
+static int arcxcnn_bl_update_status(struct backlight_device *bl)
+{
+	struct arcxcnn *lp = bl_get_data(bl);
+	u32 brightness = bl->props.brightness;
+
+	if (bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
+		brightness = 0;
+
+	/* set brightness */
+	if (lp->mode == PWM_BASED)
+		; /* via pwm */
+	else if (lp->mode == REGISTER_BASED)
+		arcxcnn_set_brightness(lp, brightness);
+
+	/* set power-on/off/save modes */
+	if (bl->props.power == 0)
+		/* take out of standby */
+		arcxcnn_update_bit(lp, ARCXCNN_CMD, ARCXCNN_CMD_STDBY, 0);
+	else
+		/* 1-3 == power save, 4 = off
+		 * place in low-power standby mode
+		 */
+		arcxcnn_update_bit(lp, ARCXCNN_CMD,
+				ARCXCNN_CMD_STDBY, ARCXCNN_CMD_STDBY);
+	return 0;
+}
+
+static const struct backlight_ops arcxcnn_bl_ops = {
+	.options = BL_CORE_SUSPENDRESUME,
+	.update_status = arcxcnn_bl_update_status,
+};
+
+static int arcxcnn_backlight_register(struct arcxcnn *lp)
+{
+	struct backlight_device *bl;
+	struct backlight_properties props;
+	struct arcxcnn_platform_data *pdata = lp->pdata;
+	const char *name = pdata->name ? : DEFAULT_BL_NAME;
+
+	memset(&props, 0, sizeof(props));
+	props.type = BACKLIGHT_PLATFORM;
+	props.max_brightness = MAX_BRIGHTNESS;
+
+	if (pdata->initial_brightness > props.max_brightness)
+		pdata->initial_brightness = props.max_brightness;
+
+	props.brightness = pdata->initial_brightness;
+
+	bl = devm_backlight_device_register(lp->dev, name, lp->dev, lp,
+				       &arcxcnn_bl_ops, &props);
+	if (IS_ERR(bl))
+		return PTR_ERR(bl);
+
+	lp->bl = bl;
+
+	return 0;
+}
+
+static ssize_t arcxcnn_get_chip_id(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct arcxcnn *lp = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n", lp->chipname);
+}
+
+static ssize_t arcxcnn_get_led_str(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct arcxcnn *lp = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%02X\n", lp->pdata->led_str);
+}
+
+static ssize_t arcxcnn_set_led_str(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t len)
+{
+	struct arcxcnn *lp = dev_get_drvdata(dev);
+	unsigned long ledstr;
+
+	if (kstrtoul(buf, 0, &ledstr))
+		return 0;
+
+	if (ledstr != lp->pdata->led_str) {
+		/* don't allow 0 for ledstr, use power to turn all off */
+		if (ledstr == 0)
+			return 0;
+		lp->pdata->led_str = ledstr & 0x3F;
+		arcxcnn_update_bit(lp, ARCXCNN_LEDEN,
+			ARCXCNN_LEDEN_MASK, lp->pdata->led_str);
+	}
+	return len;
+}
+
+static ssize_t arcxcnn_get_bl_ctl_mode(struct device *dev,
+	     struct device_attribute *attr, char *buf)
+{
+	struct arcxcnn *lp = dev_get_drvdata(dev);
+	char *strmode = NULL;
+
+	if (lp->mode == PWM_BASED)
+		strmode = "pwm based";
+	else if (lp->mode == REGISTER_BASED)
+		strmode = "register based";
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n", strmode);
+}
+
+static DEVICE_ATTR(chip_id, 0444, arcxcnn_get_chip_id, NULL);
+static DEVICE_ATTR(led_str, 0664, arcxcnn_get_led_str, arcxcnn_set_led_str);
+static DEVICE_ATTR(bl_ctl_mode, 0444, arcxcnn_get_bl_ctl_mode, NULL);
+
+static struct attribute *arcxcnn_attributes[] = {
+	&dev_attr_chip_id.attr,
+	&dev_attr_led_str.attr,
+	&dev_attr_bl_ctl_mode.attr,
+	NULL,
+};
+
+static const struct attribute_group arcxcnn_attr_group = {
+	.attrs = arcxcnn_attributes,
+};
+
+#ifdef CONFIG_OF
+static int arcxcnn_parse_dt(struct arcxcnn *lp)
+{
+	struct device *dev = lp->dev;
+	struct device_node *node = dev->of_node;
+	u32 prog_val, num_entry, sources[6];
+	int ret;
+
+	if (!node) {
+		dev_err(dev, "no platform data.\n");
+		return -EINVAL;
+	}
+	lp->pdata->led_config_0_set = false;
+	lp->pdata->led_config_1_set = false;
+	lp->pdata->dim_freq_set = false;
+	lp->pdata->comp_config_set = false;
+	lp->pdata->filter_config_set = false;
+	lp->pdata->trim_config_set = false;
+
+	ret = of_property_read_string(node, "label", &lp->pdata->name);
+	if (ret < 0)
+		lp->pdata->name = NULL;
+
+	ret = of_property_read_u32(node, "default-brightness", &prog_val);
+	if (ret < 0)
+		prog_val = s_ibright;
+	lp->pdata->initial_brightness = prog_val;
+	if (lp->pdata->initial_brightness > MAX_BRIGHTNESS)
+		lp->pdata->initial_brightness = MAX_BRIGHTNESS;
+
+	ret = of_property_read_u32(node, "arc,led-config-0", &prog_val);
+	if (ret == 0) {
+		lp->pdata->led_config_0 = (u8)prog_val;
+		lp->pdata->led_config_0_set = true;
+	}
+	ret = of_property_read_u32(node, "arc,led-config-1", &prog_val);
+	if (ret == 0) {
+		lp->pdata->led_config_1 = (u8)prog_val;
+		lp->pdata->led_config_1_set = true;
+	}
+	ret = of_property_read_u32(node, "arc,dim-freq", &prog_val);
+	if (ret == 0) {
+		lp->pdata->dim_freq = (u8)prog_val;
+		lp->pdata->dim_freq_set = true;
+	}
+	ret = of_property_read_u32(node, "arc,comp-config", &prog_val);
+	if (ret == 0) {
+		lp->pdata->comp_config = (u8)prog_val;
+		lp->pdata->comp_config_set = true;
+	}
+	ret = of_property_read_u32(node, "arc,filter-config", &prog_val);
+	if (ret == 0) {
+		lp->pdata->filter_config = (u8)prog_val;
+		lp->pdata->filter_config_set = true;
+	}
+	ret = of_property_read_u32(node, "arc,trim-config", &prog_val);
+	if (ret == 0) {
+		lp->pdata->trim_config = (u8)prog_val;
+		lp->pdata->trim_config_set = true;
+	}
+	ret = of_property_count_u32_elems(node, "led-sources");
+	if (ret < 0)
+		lp->pdata->led_str = 0x3F;
+	else {
+		num_entry = ret;
+		if (num_entry > 6)
+			num_entry = 6;
+
+		ret = of_property_read_u32_array(node, "led-sources", sources,
+					num_entry);
+		if (ret < 0) {
+			dev_err(dev, "led-sources node is invalid.\n");
+			return -EINVAL;
+		}
+
+		lp->pdata->led_str = 0;
+		while (num_entry > 0)
+			lp->pdata->led_str |= (1 << sources[--num_entry]);
+	}
+	return 0;
+}
+#else
+static int arcxcnn_parse_dt(struct arcxcnn *lp)
+{
+	return -EINVAL;
+}
+#endif
+
+static int arcxcnn_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+{
+	struct arcxcnn *lp;
+	int ret;
+	u8 regval;
+	u16 chipid;
+
+	if (!i2c_check_functionality(cl->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	lp = devm_kzalloc(&cl->dev, sizeof(*lp), GFP_KERNEL);
+	if (!lp)
+		return -ENOMEM;
+
+	lp->client = cl;
+	lp->dev = &cl->dev;
+	lp->chip_id = id->driver_data;
+	lp->pdata = dev_get_platdata(&cl->dev);
+
+	if (!lp->pdata) {
+		lp->pdata = devm_kzalloc(lp->dev,
+				sizeof(*lp->pdata), GFP_KERNEL);
+		if (!lp->pdata)
+			return -ENOMEM;
+
+		/* no platform data, parse the device-tree for info.  if there
+		 * is no device tree entry, we are being told we exist because
+		 * user-land said so, so make up the info we need
+		 */
+		ret = arcxcnn_parse_dt(lp);
+		if (ret < 0) {
+			/* no device tree, use defaults based on module params
+			 */
+			lp->pdata->led_config_0_set = false;
+			lp->pdata->led_config_1_set = false;
+			lp->pdata->dim_freq_set = false;
+			lp->pdata->comp_config_set = false;
+			lp->pdata->filter_config_set = false;
+			lp->pdata->trim_config_set = false;
+
+			lp->pdata->name = NULL;
+			lp->pdata->initial_brightness = s_ibright;
+			lp->pdata->led_str = s_iledstr;
+		}
+	}
+
+	if (lp->pdata->dim_freq_set)
+		lp->mode = PWM_BASED;
+	else
+		lp->mode = REGISTER_BASED;
+
+	i2c_set_clientdata(cl, lp);
+
+	/* read device ID */
+	regval = arcxcnn_read_byte(lp, 0x1E);
+	chipid = regval;
+	chipid <<= 8;
+	regval = arcxcnn_read_byte(lp, 0x1F);
+	chipid |= regval;
+
+	/* make sure it belongs to this driver
+	 * TODO - handle specific ids
+	 */
+	if (chipid != 0x02A5) {
+		#if 1
+		dev_info(&cl->dev, "Chip Id is %04X\n", chipid);
+		#else
+		dev_err(&cl->dev, "%04X is not ARC2C\n", chipid);
+		return -ENODEV;
+		#endif
+	}
+	/* reset the device */
+	arcxcnn_write_byte(lp, ARCXCNN_CMD, ARCXCNN_CMD_RESET);
+
+	/* set initial brightness */
+	arcxcnn_set_brightness(lp, lp->pdata->initial_brightness);
+
+	/* if fadectrl set in DT, set the value directly, else leave default */
+	if (lp->pdata->led_config_0_set)
+		arcxcnn_write_byte(lp, ARCXCNN_FADECTRL,
+			lp->pdata->led_config_0);
+
+	/* if iled config set in DT, set the value, else internal mode */
+	if (lp->pdata->led_config_1_set)
+		arcxcnn_write_byte(lp, ARCXCNN_ILED_CONFIG,
+			lp->pdata->led_config_1);
+	else
+		arcxcnn_write_byte(lp, ARCXCNN_ILED_CONFIG, 0x57);
+
+	/* other misc DT settings */
+	if (lp->pdata->dim_freq_set)
+		arcxcnn_write_byte(lp, ARCXCNN_FADECTRL, lp->pdata->dim_freq);
+	if (lp->pdata->comp_config_set)
+		arcxcnn_write_byte(lp, ARCXCNN_COMP_CONFIG,
+			lp->pdata->comp_config);
+	if (lp->pdata->filter_config_set)
+		arcxcnn_write_byte(lp, ARCXCNN_FILT_CONFIG,
+			lp->pdata->filter_config);
+	if (lp->pdata->trim_config_set)
+		arcxcnn_write_byte(lp, ARCXCNN_IMAXTUNE,
+			lp->pdata->trim_config);
+
+	/* set initial LED Strings */
+	arcxcnn_update_bit(lp, ARCXCNN_LEDEN,
+		ARCXCNN_LEDEN_MASK, lp->pdata->led_str);
+
+	snprintf(lp->chipname, sizeof(lp->chipname),
+		"%s-%04X", id->name, chipid);
+
+	ret = arcxcnn_backlight_register(lp);
+	if (ret) {
+		dev_err(lp->dev,
+			"failed to register backlight. err: %d\n", ret);
+		return ret;
+	}
+
+	ret = sysfs_create_group(&lp->dev->kobj, &arcxcnn_attr_group);
+	if (ret) {
+		dev_err(lp->dev, "failed to register sysfs. err: %d\n", ret);
+		return ret;
+	}
+
+	backlight_update_status(lp->bl);
+	return 0;
+}
+
+static int arcxcnn_remove(struct i2c_client *cl)
+{
+	struct arcxcnn *lp = i2c_get_clientdata(cl);
+
+	if (!s_no_reset_on_remove) {
+		/* disable all strings */
+		arcxcnn_write_byte(lp, ARCXCNN_LEDEN, 0x00);
+		/* reset the device */
+		arcxcnn_write_byte(lp, ARCXCNN_CMD, ARCXCNN_CMD_RESET);
+	}
+	lp->bl->props.brightness = 0;
+	backlight_update_status(lp->bl);
+	if (lp->supply)
+		regulator_disable(lp->supply);
+	sysfs_remove_group(&lp->dev->kobj, &arcxcnn_attr_group);
+
+	return 0;
+}
+
+static const struct of_device_id arcxcnn_dt_ids[] = {
+	{ .compatible = "arc,arc2c0608" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, arcxcnn_dt_ids);
+
+/* Note that the device/chip ID is not fixed in silicon so
+ * auto-probing of these devices on the bus is most likely
+ * not possible, use device tree to set i2c bus address
+ */
+static const struct i2c_device_id arcxcnn_ids[] = {
+	{"arc2c0608", ARC2C0608},
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, arcxcnn_ids);
+
+static struct i2c_driver arcxcnn_driver = {
+	.driver = {
+		   .name = "arcxcnn_bl",
+		   .of_match_table = of_match_ptr(arcxcnn_dt_ids),
+		   },
+	.probe = arcxcnn_probe,
+	.remove = arcxcnn_remove,
+	.id_table = arcxcnn_ids,
+};
+
+module_i2c_driver(arcxcnn_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Brian Dodge <bdodge09@outlook.com>");
+MODULE_DESCRIPTION("ARCXCNN Backlight driver");
diff --git a/include/linux/i2c/arcxcnn.h b/include/linux/i2c/arcxcnn.h
new file mode 100644
index 0000000..1c681dd
--- /dev/null
+++ b/include/linux/i2c/arcxcnn.h
@@ -0,0 +1,67 @@
+/*
+ * Backlight driver for ArcticSand ARC2C0608 Backlight Devices
+ *
+ * Copyright 2016 ArcticSand, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _ARCXCNN_H
+#define _ARCXCNN_H
+
+enum arcxcnn_chip_id {
+	ARC2C0608
+};
+
+enum arcxcnn_brightness_source {
+	ARCXCNN_PWM_ONLY,
+	ARCXCNN_I2C_ONLY = 2,
+};
+
+#define ARCXCNN_MAX_PROGENTRIES	48	/* max a/v pairs for custom */
+
+/**
+ * struct arcxcnn_platform_data
+ * @name : Backlight driver name. If it is not defined, default name is set.
+ * @initial_brightness : initial value of backlight brightness
+ * @led_str	 : initial LED string enables, upper bit is global on/off
+ * @led_config_0 : fading speed (period between intensity steps)
+ * @led_config_1 : misc settings, see datasheet
+ * @dim_freq	 : pwm dimming frequency if in pwm mode
+ * @comp_config	 : misc config, see datasheet
+ * @filter_config: RC/PWM filter config, see datasheet
+ * @trim_config	 : full scale current trim, see datasheet
+ * @led_config_0_set	: the value in led_config_0 is valid
+ * @led_config_1_set	: the value in led_config_1 is valid
+ * @dim_freq_set	: the value in dim_freq is valid
+ * @comp_config_set	: the value in comp_config is valid
+ * @filter_config_set	: the value in filter_config is valid
+ * @trim_config_set	: the value in trim_config is valid
+ *
+ * the _set flags are used to indicate that the value was explicitly set
+ * in the device tree or platform data. settings not set are left as default
+ * power-on default values of the chip except for led_str and led_config_1
+ * which are set by the driver (led_str is specified indirectly in the
+ * device tree via "led-sources")
+ */
+struct arcxcnn_platform_data {
+	const char *name;
+	u16 initial_brightness;
+	u8	led_str;
+
+	u8	led_config_0;
+	u8	led_config_1;
+	u8	dim_freq;
+	u8	comp_config;
+	u8	filter_config;
+	u8	trim_config;
+
+	bool	led_config_0_set;
+	bool	led_config_1_set;
+	bool	dim_freq_set;
+	bool	comp_config_set;
+	bool	filter_config_set;
+	bool	trim_config_set;
+};
+
+#endif
-- 
2.7.4

^ permalink raw reply related

* [PATCH 2/2] backlight: arcxcnn: devicetree bindings for ArticSand devices
From: Olimpiu Dejeu @ 2016-11-03 18:29 UTC (permalink / raw)
  To: robh
  Cc: lee.jones, linux-kernel, linux-fbdev, devicetree, jg1.han,
	Olimpiu Dejeu

Resubmition of arcxcnn backliught driver addressing the naming convention
 concerns raised by Rob H. Note that all the device tree properties are
 determined by the board design or IC EPROM settings and are not intended
 to be user adjustable.

Signed-off-by: Olimpiu Dejeu <olimpiu@arcticsand.com>

---
 .../bindings/leds/backlight/arcxcnn_bl.txt         | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt

diff --git a/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt b/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt
new file mode 100644
index 0000000..a7b6ff2
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt
@@ -0,0 +1,33 @@
+Binding for ArcticSand arc2c0608 LED driver
+
+Required properties:
+- compatible: should be "arc,arc2c0608"
+- reg: slave address
+
+Optional properties:
+- default-brightness: brightness value on boot, value from: 0-4095
+- label: The name of the backlight device
+			See Documentation/devicetree/bindings/leds/common.txt
+- led-sources: List of enabled channels from 0 to 5.
+			See Documentation/devicetree/bindings/leds/common.txt
+
+- arc,led-config-0: setting for register ILED_CONFIG_0
+- arc,led-config-1: setting for register ILED_CONFIG_1
+- arc,dim-freq: PWM mode frequence setting (bits [3:0] used)
+- arc,comp-config: setting for register CONFIG_COMP
+- arc,filter-config: setting for register FILTER_CONFIG
+- arc,trim-config: setting for register IMAXTUNE
+
+Note: Optional properties not specified will default to values in IC EPROM
+
+Example:
+
+arc2c0608@30 {
+	compatible = "arc,arc2c0608";
+	reg = <0x30>;
+	default-brightness = <500>;
+	label = "lcd-backlight";
+	linux,default-trigger = "backlight";
+	led-sources = <0 1 2 5>;
+};
+
-- 
2.7.4

^ permalink raw reply related

* Re: [PATCH 10/13] ARM: dts: exynos: replace to "max-frequecy" instead of "clock-freq-min-max"
From: Krzysztof Kozlowski @ 2016-11-03 18:41 UTC (permalink / raw)
  To: Jaehoon Chung
  Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-rockchip, ulf.hansson, robh+dt, krzk,
	heiko, shawn.lin
In-Reply-To: <20161103062135.10697-11-jh80.chung@samsung.com>

On Thu, Nov 03, 2016 at 03:21:32PM +0900, Jaehoon Chung wrote:
> In drivers/mmc/core/host.c, there is "max-frequency" property.
> It should be same behavior. So Use the "max-frequency" instead of
> "clock-freq-min-max".
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
>  arch/arm/boot/dts/exynos3250-artik5-eval.dts | 2 +-
>  arch/arm/boot/dts/exynos3250-artik5.dtsi     | 2 +-
>  arch/arm/boot/dts/exynos3250-monk.dts        | 2 +-
>  arch/arm/boot/dts/exynos3250-rinato.dts      | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)

This looks totally independent to rest of patches so it can be applied
separately without any functional impact (except lack of minimum
frequency). Is that correct?

Best regards,
Krzysztof

^ permalink raw reply

* Re: [PATCH v3 1/5] pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank
From: Krzysztof Kozlowski @ 2016-11-03 19:12 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: krzk-DgEjT+Ai2ygdnm+yROfE0A, kgene-DgEjT+Ai2ygdnm+yROfE0A,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8,
	will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
	sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
	jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ,
	inki.dae-Sze3O3UU22JBDgjK7y7TUQ,
	jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ,
	beomho.seo-Sze3O3UU22JBDgjK7y7TUQ,
	jaewon02.kim-Sze3O3UU22JBDgjK7y7TUQ,
	human.hwang-Sze3O3UU22JBDgjK7y7TUQ,
	ideal.song-Sze3O3UU22JBDgjK7y7TUQ,
	ingi2.kim-Sze3O3UU22JBDgjK7y7TUQ,
	m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ,
	a.hajda-Sze3O3UU22JBDgjK7y7TUQ, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
	andi.shyti-Sze3O3UU22JBDgjK7y7TUQ, chanwoo-DgEjT+Ai2ygdnm+yROfE0A,
	Tomasz Figa, Linus Walleij, linux-gpio-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478155149-28527-2-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

On Thu, Nov 03, 2016 at 03:39:05PM +0900, Chanwoo Choi wrote:
> This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
> In the pre-existing Exynos series, the registers of the gpio bank are included
> in the one memory map. But, some gpio bank need to support the one more memory
> map (IORESOURCE_MEM) because the registers of gpio bank are separated into
> the different memory map.
> 
> For example,
> The both ALIVE and IMEM domain have the different memory base address.
> The GFP[1-5] of exynos5433 are composed as following:
> - ALIVE domain : WEINT_* registers
> - IMEM domain  : CON/DAT/PUD/DRV/CONPDN/PUDPDN register
> 
> Cc: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Cc: Kukjin Kim <kgene-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Suggested-by: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  .../bindings/pinctrl/samsung-pinctrl.txt           | 19 ++++++++++
>  drivers/pinctrl/samsung/pinctrl-exynos.c           | 39 +++++++++------------
>  drivers/pinctrl/samsung/pinctrl-exynos.h           | 11 ++++++
>  drivers/pinctrl/samsung/pinctrl-samsung.c          | 40 ++++++++++++++--------
>  drivers/pinctrl/samsung/pinctrl-samsung.h          | 10 ++++--
>  5 files changed, 80 insertions(+), 39 deletions(-)
> 

Hi,

Reviewed-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Best regards,
Krzysztof
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply

* Re: [PATCH v3 2/5] pinctrl: samsung: Add GPF support for Exynos5433
From: Krzysztof Kozlowski @ 2016-11-03 19:20 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: krzk, kgene, javier, robh+dt, mark.rutland, catalin.marinas,
	will.deacon, devicetree, linux-arm-kernel, linux-samsung-soc,
	linux-kernel, jh80.chung, sw0312.kim, jy0922.shim, inki.dae,
	jonghwa3.lee, beomho.seo, jaewon02.kim, human.hwang, ideal.song,
	ingi2.kim, m.szyprowski, a.hajda, s.nawrocki, andi.shyti, chanwoo,
	Tomasz Figa, Linus Walleij, linux-gpio
In-Reply-To: <1478155149-28527-3-git-send-email-cw00.choi@samsung.com>

On Thu, Nov 03, 2016 at 03:39:06PM +0900, Chanwoo Choi wrote:
> This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
> to support the multiple memory map because the registers of GPFx are located
> in the different domain.
> 
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

I think that, instead of in previous patch, the
"samsung,exynos5433-pinctrl" compatible should be documented here along
with information that it requires two addresses for mappings.

Best regards,
Krzysztof


> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index d657b52dfdb5..12f7d1eb65bc 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1339,6 +1339,11 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
>  	EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
>  	EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
>  	EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
> +	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
> +	EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
> +	EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
> +	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
> +	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
>  };
>  
>  /* pin banks of exynos5433 pin-controller - AUD */
> @@ -1420,6 +1425,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_wkup_init = exynos_eint_wkup_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.nr_ext_resources = 1,
>  	}, {
>  		/* pin-controller instance 1 data */
>  		.pin_banks	= exynos5433_pin_banks1,
> -- 
> 1.9.1
> 

^ permalink raw reply

* [PATCH v2] ARM: DTS: r8a7794: alt: Fix PFC names for DU
From: Jacopo Mondi @ 2016-11-03 19:34 UTC (permalink / raw)
  To: horms-/R6kz+dDXgpPR4JQBCEnsQ, magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	linux-I+IVW8TIWO2tmTQ+vhA3Yw
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jacopo Mondi
In-Reply-To: <1478180574-15464-1-git-send-email-jacopo-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>

Update the PFC pin groups and function names of DU interface for
r8a7794 ALT board.

The currently specified pin groups and function names prevented PFC and
DU interfaces from being correctly configured:

sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
rcar-du: probe of feb00000.display failed with error -22

Signed-off-by: Jacopo Mondi <jacopo-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---

v1->v2:
    - s/PCF/PFC/ in commit message according to Sergei Shtylyov's comment

Patch applied against Simon Horman's renesas/master branch.
The PCF pin groups and function renaming was introduced by commit 56ed4bb9 and
DTS for ALT board has never been update accordingly.
Tested displaying frames on VGA interface: the rcar-du driver loads correctly.

 arch/arm/boot/dts/r8a7794-alt.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35a..9d65fb3 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -165,8 +165,8 @@
 	pinctrl-names = "default";
 
 	du_pins: du {
-		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
-		function = "du";
+		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+		function = "du1";
 	};
 
 	scif2_pins: scif2 {
-- 
2.7.4

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