* Re: [PATCH v2 06/14] ASoC: sun4i-codec: Add support for A31 playback through headphone output
From: Maxime Ripard @ 2016-11-06 18:57 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai,
Rob Herring, Mark Rutland, Linux-ALSA, linux-arm-kernel,
linux-kernel, devicetree, linux-sunxi
In-Reply-To: <CAGb2v65CZJ+1LTWWk3+vABV8PDgsDta+nZ7o3H2Z--KFPe2kog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Fri, Nov 04, 2016 at 09:08:11AM +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 4, 2016 at 1:36 AM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > Hi,
> >
> > On Thu, Nov 03, 2016 at 03:55:48PM +0800, Chen-Yu Tsai wrote:
> >> +/* headphone controls */
> >> +static const char * const sun6i_codec_hp_src_enum_text[] = {
> >> + "DAC", "Mixer",
> >> +};
> >> +
> >> +static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
> >> + SUN6I_CODEC_OM_DACA_CTRL,
> >> + SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
> >> + SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
> >> + sun6i_codec_hp_src_enum_text);
> >> +
> >> +static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
> >> + SOC_DAPM_ENUM("Headphone Source Playback Route",
> >> + sun6i_codec_hp_src_enum),
> >> +};
> >
> > What is that route exactly? A muxer?
>
> Yup. The following is part of the widgets list later in the code:
>
> + /* Headphone output path */
> + SND_SOC_DAPM_MUX("Headphone Source Playback Route",
> + SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
Oh, right.
You can add my Acked-by on this one and the other patches too.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: add USB1-related nodes of Allwinner A64
From: Maxime Ripard @ 2016-11-06 18:56 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, Catalin Marinas, Will Deacon,
linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring,
Andre Przywara, linux-arm-kernel
In-Reply-To: <20161105143830.10099-1-icenowy@aosc.xyz>
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On Sat, Nov 05, 2016 at 10:38:29PM +0800, Icenowy Zheng wrote:
> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
> PHY device which have two ports. One of the port is wired to both a HCI
> USB controller and the OTG controller, which is currently not supported.
> The another one is only wired to a HCI controller, and the device node of
> OHCI/EHCI controller of the port can be added now.
>
> Also the A64 USB PHY device node is also added for the HCI controllers to
> work.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 50 +++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 3d70be3..c2b6dc8 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -259,5 +259,55 @@
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + usbphy: phy@01c19400 {
> + compatible = "allwinner,sun50i-a64-usb-phy";
> + reg = <0x01c19400 0x14>,
> + <0x01c1b800 0x4>;
> + reg-names = "phy_ctrl",
> + "pmu1";
> + clocks = <&ccu CLK_USB_PHY0>,
> + <&ccu CLK_USB_PHY1>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ohci1: usb@01c1a400 {
> + compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
> + reg = <0x01c1b400 0x100>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + /*
> + * According to the user manual, OHCI1 USB clock
> + * depends on OHCI0 clock.
> + */
This is something that should be dealt with in the clock framework,
not in your driver.
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI0>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@01c1a000 {
> + compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
> + reg = <0x01c1b000 0x100>;
And please order these nodes by base address.
Also, in both the ehci and ohci nodes, the unit-address and reg don't
match, which one is the right one?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: sunxi: enable EHCI1, OHCI1 and USB PHY nodes in Pine64
From: Maxime Ripard @ 2016-11-06 18:54 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, Catalin Marinas, Will Deacon,
linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring,
Andre Przywara, linux-arm-kernel
In-Reply-To: <20161105143830.10099-2-icenowy@aosc.xyz>
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Hi,
On Sat, Nov 05, 2016 at 10:38:30PM +0800, Icenowy Zheng wrote:
> Pine64 have two USB Type-A ports, which are wired to the two ports of
> A64 USB PHY, and the lower port is the EHCI/OHCI1 port.
>
> Enable the necessary nodes to enable the lower USB port to work.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> index 4709590..d836995 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> @@ -72,3 +72,15 @@
> &i2c1_pins {
> bias-pull-up;
> };
> +
> +&usbphy {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
Please order the nodes by alphebetical order.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v5 4/7] ASoC: sunxi: Add sun8i I2S driver
From: Jean-Francois Moine @ 2016-11-06 18:02 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Dave Airlie, Liam Girdwood, Mark Brown, Maxime Ripard,
Rob Herring, Linux-ALSA, devicetree, dri-devel, linux-arm-kernel,
linux-sunxi
In-Reply-To: <CAGb2v67gDd650TJk_-oHOehnzdH2qor=36HXdPt339Ji=ToAMg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Sun, 23 Oct 2016 09:33:16 +0800
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> On Fri, Oct 21, 2016 at 4:36 PM, Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org> wrote:
> > This patch adds I2S support to sun8i SoCs as the A83T and H3.
> >
> > Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> > ---
> > Note: This driver is closed to the sun4i-i2s except that:
> > - it handles the H3
>
> If it's close to sun4i-i2s, you should probably rework that one to support
> the newer SoCs.
I started to add the H3 into the sun4i-i2s, but I am blocked with
regmap.
Many H3 registers are common with the A10, but some of them have more
or less fields, the fields may be at different offsets. And, finally,
some registers are completely different.
This would not raise any problem, except with regmap which is really
painful.
As I may understood, regmap is used to simplify suspend/resume, but, is
it useful to save the I2S register on suspend?
Practically, I am streaming some tune on my device. I suspend it for
any reason. The next morning, I resume it. Are you sure I want to
continue to hear the end of the tune?
I better think that streaming should be simply stopped on suspend.
Then, there is no need to save the playing registers, and, here I am,
there is no need to use regmap.
May I go this way?
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
--
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* [PATCH v4 3/3] clocksource: Add clockevent support to NPS400 driver
From: Noam Camus @ 2016-11-06 17:44 UTC (permalink / raw)
To: robh+dt, mark.rutland, daniel.lezcano
Cc: tglx, devicetree, linux-kernel, Noam Camus
In-Reply-To: <1478454298-381-1-git-send-email-noamca@mellanox.com>
From: Noam Camus <noamca@mellanox.com>
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.
The design idea is that for each core there is dedicated regirtser
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.
Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent
Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 --
.../bindings/timer/ezchip,nps400-timer0.txt | 17 ++
.../bindings/timer/ezchip,nps400-timer1.txt | 15 ++
drivers/clocksource/timer-nps.c | 213 ++++++++++++++++++++
4 files changed, 245 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
deleted file mode 100644
index c8c03d7..0000000
--- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-NPS Network Processor
-
-Required properties:
-
-- compatible : should be "ezchip,nps400-timer"
-
-Clocks required for compatible = "ezchip,nps400-timer":
-- clocks : Must contain a single entry describing the clock input
-
-Example:
-
-timer {
- compatible = "ezchip,nps400-timer";
- clocks = <&sysclk>;
-};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
new file mode 100644
index 0000000..e3cfce8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
@@ -0,0 +1,17 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer0"
+
+Clocks required for compatible = "ezchip,nps400-timer0":
+- interrupts : The interrupt of the first timer
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer0";
+ interrupts = <3>;
+ clocks = <&sysclk>;
+};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
new file mode 100644
index 0000000..c0ab419
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer1"
+
+Clocks required for compatible = "ezchip,nps400-timer1":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer1";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 1533349..1097ad6 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -109,3 +109,216 @@ static int __init nps_setup_clocksource(struct device_node *node)
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
nps_setup_clocksource);
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
+ nps_setup_clocksource);
+
+#ifdef CONFIG_EZNPS_MTM_EXT
+#include <soc/nps/mtm.h>
+
+/* Timer related Aux registers */
+#define NPS_REG_TIMER0_TSI 0xFFFFF850
+#define NPS_REG_TIMER0_LIMIT 0x23
+#define NPS_REG_TIMER0_CTRL 0x22
+#define NPS_REG_TIMER0_CNT 0x21
+
+/*
+ * Interrupt Enabled (IE) - re-arm the timer
+ * Not Halted (NH) - is cleared when working with JTAG (for debug)
+ */
+#define TIMER0_CTRL_IE BIT(0)
+#define TIMER0_CTRL_NH BIT(1)
+
+static unsigned long nps_timer0_freq;
+static unsigned long nps_timer0_irq;
+
+/*
+ * Arm the timer to interrupt after @cycles
+ */
+static void nps_clkevent_timer_event_setup(unsigned int cycles)
+{
+ write_aux_reg(NPS_REG_TIMER0_LIMIT, cycles);
+ write_aux_reg(NPS_REG_TIMER0_CNT, 0);
+
+ write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+}
+
+/*
+ * Clear from TSI the bit for this thread (if not in periodic mode)
+ * If still there are pending HW treads set next timer event
+ */
+static void nps_clkevent_rm_thread(bool remove_thread)
+{
+ unsigned int cflags;
+ unsigned int enabled_threads = 0;
+ int thread;
+
+ hw_schd_save(&cflags);
+
+ enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
+
+ /* remove thread from TSI1 */
+ if (remove_thread) {
+ thread = read_aux_reg(CTOP_AUX_THREAD_ID);
+ enabled_threads &= ~(1 << thread);
+ write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
+ }
+
+ /* Re-arm the timer if needed */
+ if (!enabled_threads)
+ write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
+ else
+ write_aux_reg(NPS_REG_TIMER0_CTRL,
+ TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+
+ hw_schd_restore(cflags);
+}
+
+static void nps_clkevent_add_thread(bool set_event)
+{
+ int thread;
+ unsigned int cflags, enabled_threads;
+
+ hw_schd_save(&cflags);
+
+ /* add thread to TSI1 */
+ thread = read_aux_reg(CTOP_AUX_THREAD_ID);
+ enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
+ enabled_threads |= (1 << thread);
+ write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
+
+ /* set next timer event */
+ if (set_event)
+ write_aux_reg(NPS_REG_TIMER0_CTRL,
+ TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+
+ hw_schd_restore(cflags);
+}
+
+static int nps_clkevent_set_next_event(unsigned long delta,
+ struct clock_event_device *dev)
+{
+ nps_clkevent_add_thread(true);
+ enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
+
+ return 0;
+}
+
+/*
+ * Whenever anyone tries to change modes, we just mask interrupts
+ * and wait for the next event to get set.
+ */
+static int nps_clkevent_timer_shutdown(struct clock_event_device *dev)
+{
+ disable_percpu_irq(nps_timer0_irq);
+
+ return 0;
+}
+
+/*
+ * For each HW thread set its relevant bit at the TSI register
+ * To arm the timer only thread 0 is needed since it is shared
+ * by all HW threads within same core.
+ */
+static int nps_clkevent_set_periodic(struct clock_event_device *dev)
+{
+ nps_clkevent_add_thread(false);
+ if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0)
+ nps_clkevent_timer_event_setup(nps_timer0_freq / HZ);
+
+ return 0;
+}
+
+static int nps_clkevent_set_oneshot(struct clock_event_device *dev)
+{
+ nps_clkevent_rm_thread(true);
+ nps_clkevent_timer_shutdown(dev);
+
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
+ .name = "NPS Timer0",
+ .features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_PERIODIC,
+ .rating = 300,
+ .set_next_event = nps_clkevent_set_next_event,
+ .set_state_periodic = nps_clkevent_set_periodic,
+ .set_state_oneshot = nps_clkevent_set_oneshot,
+ .set_state_oneshot_stopped = nps_clkevent_timer_shutdown,
+ .set_state_shutdown = nps_clkevent_timer_shutdown,
+ .tick_resume = nps_clkevent_timer_shutdown,
+};
+
+static irqreturn_t timer_irq_handler(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+ int irq_reenable = clockevent_state_periodic(evt);
+
+ /* Remove HW thread from TSI only if NOT in periodic state */
+ nps_clkevent_rm_thread(!irq_reenable);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static int nps_timer_starting_cpu(unsigned int cpu)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+
+ evt->cpumask = cpumask_of(smp_processor_id());
+
+ clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
+ enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
+
+ return 0;
+}
+
+static int nps_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(nps_timer0_irq);
+ return 0;
+}
+
+static int __init nps_setup_clockevent(struct device_node *node)
+{
+ struct clk *clk;
+ int ret;
+
+ nps_timer0_irq = irq_of_parse_and_map(node, 0);
+ if (nps_timer0_irq <= 0) {
+ pr_err("clockevent: missing irq");
+ return -EINVAL;
+ }
+
+ ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
+ if (ret)
+ return ret;
+
+ /* Needs apriori irq_set_percpu_devid() done in intc map function */
+ ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
+ "Timer0 (per-cpu-tick)",
+ &nps_clockevent_device);
+ if (ret) {
+ pr_err("Couldn't request irq\n");
+ clk_disable_unprepare(clk);
+ return ret;
+ }
+
+ ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
+ "clockevents/nps:starting",
+ nps_timer_starting_cpu,
+ nps_timer_dying_cpu);
+ if (ret) {
+ pr_err("Failed to setup hotplug state");
+ clk_disable_unprepare(clk);
+ free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
+ return ret;
+ }
+
+ return 0;
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
+ nps_setup_clockevent);
+#endif /* CONFIG_EZNPS_MTM_EXT */
--
1.7.1
^ permalink raw reply related
* [PATCH v4 2/3] clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer
From: Noam Camus @ 2016-11-06 17:44 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Noam Camus
In-Reply-To: <1478454298-381-1-git-send-email-noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
nps_setup_clocksource() should take node as only argument i.e.:
replace
int __init nps_setup_clocksource(struct device_node *node, struct clk *clk)
with
int __init nps_setup_clocksource(struct device_node *node)
This is also serve as preperation for next patch which adds support
for clockevents to nps400.
Specifically we add new function nps_get_timer_clk() to serve clocksource
and later clockevent registration.
Signed-off-by: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
---
drivers/clocksource/timer-nps.c | 63 +++++++++++++++++++++++----------------
1 files changed, 37 insertions(+), 26 deletions(-)
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 70c149a..1533349 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -46,7 +46,33 @@
/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
-static unsigned long nps_timer_rate;
+static int nps_get_timer_clk(struct device_node *node,
+ unsigned long *timer_freq,
+ struct clk **clk)
+{
+ int ret;
+
+ *clk = of_clk_get(node, 0);
+ if (IS_ERR(*clk)) {
+ pr_err("timer missing clk");
+ return PTR_ERR(*clk);
+ }
+
+ ret = clk_prepare_enable(*clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clk\n");
+ return ret;
+ }
+
+ *timer_freq = clk_get_rate(*clk);
+ if (!(*timer_freq)) {
+ pr_err("Couldn't clk get rate\n");
+ clk_disable_unprepare(*clk);
+ return *timer_freq;
+ }
+
+ return 0;
+}
static cycle_t nps_clksrc_read(struct clocksource *clksrc)
{
@@ -55,26 +81,24 @@ static cycle_t nps_clksrc_read(struct clocksource *clksrc)
return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
}
-static int __init nps_setup_clocksource(struct device_node *node,
- struct clk *clk)
+static int __init nps_setup_clocksource(struct device_node *node)
{
int ret, cluster;
+ struct clk *clk;
+ unsigned long nps_timer1_freq;
+
for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
nps_msu_reg_low_addr[cluster] =
nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
- NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+ NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
- ret = clk_prepare_enable(clk);
- if (ret) {
- pr_err("Couldn't enable parent clock\n");
+ ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
+ if (ret)
return ret;
- }
- nps_timer_rate = clk_get_rate(clk);
-
- ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
- nps_timer_rate, 301, 32, nps_clksrc_read);
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
+ nps_timer1_freq, 301, 32, nps_clksrc_read);
if (ret) {
pr_err("Couldn't register clock source.\n");
clk_disable_unprepare(clk);
@@ -83,18 +107,5 @@ static int __init nps_setup_clocksource(struct device_node *node,
return ret;
}
-static int __init nps_timer_init(struct device_node *node)
-{
- struct clk *clk;
-
- clk = of_clk_get(node, 0);
- if (IS_ERR(clk)) {
- pr_err("Can't get timer clock.\n");
- return PTR_ERR(clk);
- }
-
- return nps_setup_clocksource(node, clk);
-}
-
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
- nps_timer_init);
+ nps_setup_clocksource);
--
1.7.1
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^ permalink raw reply related
* [PATCH v4 1/3] soc: Support for NPS HW scheduling
From: Noam Camus @ 2016-11-06 17:44 UTC (permalink / raw)
To: robh+dt, mark.rutland, daniel.lezcano
Cc: tglx, devicetree, linux-kernel, Noam Camus
In-Reply-To: <1478454298-381-1-git-send-email-noamca@mellanox.com>
From: Noam Camus <noamca@mellanox.com>
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
arch/arc/plat-eznps/include/plat/ctop.h | 2 -
include/soc/nps/mtm.h | 59 +++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+), 2 deletions(-)
create mode 100644 include/soc/nps/mtm.h
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index 9d6718c..ee2e32d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,9 +46,7 @@
#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
/* EZchip core instructions */
-#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
-#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
#define CTOP_INST_SCHD_RW 0x3E6F7004
#define CTOP_INST_SCHD_RD 0x3E6F7084
diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h
new file mode 100644
index 0000000..d2f5e7e
--- /dev/null
+++ b/include/soc/nps/mtm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_MTM_H
+#define SOC_NPS_MTM_H
+
+#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
+#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
+
+static inline void hw_schd_save(unsigned int *flags)
+{
+ __asm__ __volatile__(
+ " .word %1\n"
+ " st r3,[%0]\n"
+ :
+ : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
+ : "r3", "memory");
+}
+
+static inline void hw_schd_restore(unsigned int flags)
+{
+ __asm__ __volatile__(
+ " mov r3, %0\n"
+ " .word %1\n"
+ :
+ : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
+ : "r3");
+}
+
+#endif /* SOC_NPS_MTM_H */
--
1.7.1
^ permalink raw reply related
* [PATCH v4 0/3] Add clockevet for timer-nps driver to NPS400 SoC
From: Noam Camus @ 2016-11-06 17:44 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Noam Camus
From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Change log
---
V3 --> V4
Main changes are [Thanks for the review]:
Fix many typos at log [Daniel]
Add handling for bad return values [Daniel and Thomas]
Replace use of internal irqchip pointers with existing IRQ API [Thomas]
Provide interrupt handler (percpu) with dev_id equal to evt [Thomas]
Fix passing *clk by reference to nps_get_timer_clk() [Daniel]
V2 --> V3
Apply Rob Herring comment about backword compatibility
V1 --> V2
Apply Daniel Lezcano comments:
CLOCKSOURCE_OF_DECLARE return value
update hotplug callbacks usage
squash of 2 first commits.
In this version I created new commit to serve as preperation for adding clockevents.
This way the last patch is more readable with clockevent content.
---
In first version of this driver we supported clocksource for the NPS400.
The support for clockevent was taken from Synopsys ARC timer driver.
This was good for working with our simulator of NPS400.
However in NPS400 ASIC the timers behave differently than simulation.
The timers in ASIC are shared between all threads whithin a core
and hence need different driver to support this behaviour.
The idea of this design is that we got 16 HW threads per core
each represented at bimask in a shared register in this core.
So when thread wants that next clockevent expiration will produce
timer interrupt to itself the correspondance bit in this register
should be set.
So theoretically if all 16 bits are set then all HW threads will get
timer interrupt on next expiration of timer 0.
Note that we use Synopsys ARC design naming convention for the timers
where:
timer0 is used for clockevents
timer1 is used for clocksource.
Noam Camus (3):
soc: Support for NPS HW scheduling
clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer
clocksource: Add clockevent support to NPS400 driver
.../bindings/timer/ezchip,nps400-timer.txt | 15 --
.../bindings/timer/ezchip,nps400-timer0.txt | 17 ++
.../bindings/timer/ezchip,nps400-timer1.txt | 15 ++
arch/arc/plat-eznps/include/plat/ctop.h | 2 -
drivers/clocksource/timer-nps.c | 264 ++++++++++++++++++--
include/soc/nps/mtm.h | 59 +++++
6 files changed, 335 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
create mode 100644 include/soc/nps/mtm.h
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^ permalink raw reply
* Re: [RFC PATCH] ARM: dts: add panel and tcon nodes to Allwinner A33 Q8 tablet dts
From: Icenowy Zheng @ 2016-11-06 16:53 UTC (permalink / raw)
To: Hans de Goede, Maxime Ripard, Chen-Yu Tsai
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
In-Reply-To: <948897e3-12a2-b02c-ed26-929921ff04b2-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
06.11.2016, 22:27, "Hans de Goede" <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>:
> Hi,
>
> On 06-11-16 12:11, Icenowy Zheng wrote:
>> All A33 Q8 tablets features a LCD panel, with a resolution of either
>> 800x480 or 1024x600.
>>
>> Add "bone" device nodes to the device tree.
>
> Bone ?
>
>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>
> He, as discussed in the other thread since sun8i-a33-q8-tablet.dts
> is used for both 800x480 and 1024x600 versions we really need to
> introduce new sun8i-a33-q8-tablet-800x600.dts and
> sun8i-a33-q8-tablet-1024x600.dts files, which include
> sun8i-a33-q8-tablet.dts and then add just the panel bits; and patch
> newer u-boots to use those instead.
>
> This way people who stick with an old u-boot will just not get
> the drm driver, rather then all of a sudden getting a wrong
> resolution.
>
> Icenowy, can you please also submit a matching u-boot patch
> (both the new dts file, as well as updating the defconfig you
> use to the new dts file)?
Could you choose a compatible for 1024x600 variant?
(Since I have never such a Q8 tablet)
>
> Regards,
>
> Hans
>
>> ---
>>
>> Maybe it will be better to add them to sun8i-q8-reference-tablet.dtsi, as
>> these pin configurations are part of reference design of both A23 and A33,
>> not only restricted to Q8.
>>
>> The DTS file is tested by me, after cherry-picks this patch from Chen-Yu Tsai:
>> https://github.com/wens/linux/commit/2823b887a289fbee5f97f3c6b45ed6c74a6368c6
>>
>> And add these commands to my U-Boot boot command:
>>
>> fdt addr 0x43000000
>> fdt resize
>> fdt set /panel compatible "urt,umsh-8596md-t"
>> fdt set /panel status "okay"
>> fdt set /display-engine status "okay"
>> fdt set /soc@01c00000/lcd-controller@01c0c000 status "okay"
>>
>> arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 44 +++++++++++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>> index b0bc236..871a20c 100644
>> --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>> +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>> @@ -47,4 +47,48 @@
>> / {
>> model = "Q8 A33 Tablet";
>> compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
>> +
>> + panel: panel {
>> + /* compatible should be set according to the panel */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&lcd_en_q8>;
>> + backlight = <&backlight>;
>> + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
>> + power-supply = <®_dc1sw>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + panel_input: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&tcon0_out_lcd>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&tcon0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&lcd_rgb666_pins>;
>> +};
>> +
>> +&tcon0_out {
>> + tcon0_out_lcd: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&panel_input>;
>> + };
>> +};
>> +
>> +&pio {
>> + lcd_en_q8: lcd_en@0 {
>> + allwinner,pins = "PH7";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> };
--
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^ permalink raw reply
* Re: [RFC PATCH] ARM: dts: add panel and tcon nodes to Allwinner A33 Q8 tablet dts
From: Hans de Goede @ 2016-11-06 14:27 UTC (permalink / raw)
To: Icenowy Zheng, Maxime Ripard, Chen-Yu Tsai
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20161106111119.14927-1-icenowy-ymACFijhrKM@public.gmane.org>
Hi,
On 06-11-16 12:11, Icenowy Zheng wrote:
> All A33 Q8 tablets features a LCD panel, with a resolution of either
> 800x480 or 1024x600.
>
> Add "bone" device nodes to the device tree.
Bone ?
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
He, as discussed in the other thread since sun8i-a33-q8-tablet.dts
is used for both 800x480 and 1024x600 versions we really need to
introduce new sun8i-a33-q8-tablet-800x600.dts and
sun8i-a33-q8-tablet-1024x600.dts files, which include
sun8i-a33-q8-tablet.dts and then add just the panel bits; and patch
newer u-boots to use those instead.
This way people who stick with an old u-boot will just not get
the drm driver, rather then all of a sudden getting a wrong
resolution.
Icenowy, can you please also submit a matching u-boot patch
(both the new dts file, as well as updating the defconfig you
use to the new dts file)?
Regards,
Hans
> ---
>
> Maybe it will be better to add them to sun8i-q8-reference-tablet.dtsi, as
> these pin configurations are part of reference design of both A23 and A33,
> not only restricted to Q8.
>
> The DTS file is tested by me, after cherry-picks this patch from Chen-Yu Tsai:
> https://github.com/wens/linux/commit/2823b887a289fbee5f97f3c6b45ed6c74a6368c6
>
> And add these commands to my U-Boot boot command:
>
> fdt addr 0x43000000
> fdt resize
> fdt set /panel compatible "urt,umsh-8596md-t"
> fdt set /panel status "okay"
> fdt set /display-engine status "okay"
> fdt set /soc@01c00000/lcd-controller@01c0c000 status "okay"
>
> arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 44 +++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
> index b0bc236..871a20c 100644
> --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
> +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
> @@ -47,4 +47,48 @@
> / {
> model = "Q8 A33 Tablet";
> compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
> +
> + panel: panel {
> + /* compatible should be set according to the panel */
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_en_q8>;
> + backlight = <&backlight>;
> + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + power-supply = <®_dc1sw>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + panel_input: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_out_lcd>;
> + };
> + };
> + };
> +};
> +
> +&tcon0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_rgb666_pins>;
> +};
> +
> +&tcon0_out {
> + tcon0_out_lcd: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&panel_input>;
> + };
> +};
> +
> +&pio {
> + lcd_en_q8: lcd_en@0 {
> + allwinner,pins = "PH7";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> };
>
^ permalink raw reply
* Re: [PATCH 2/2] Documentation: DT: Add bmi160 imu binding
From: Jonathan Cameron @ 2016-11-06 12:41 UTC (permalink / raw)
To: Marcin Niestroj
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
Daniel Baluta, Gregor Boirie, Sanchayan Maity, Rob Herring,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161103112527.29623-2-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
On 03/11/16 11:25, Marcin Niestroj wrote:
> This adds documentation for Bosch BMI160 Inertial Measurement Unit
> device-tree bindings.
>
> Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
Unless I missed it in the previous patch we should also have of tables
added to the i2c and spi files (which is why the various tests haven't
been screaming at me that this device doesn't have documented bindings).
Otherwise, the use of interrupt names to indicate which pin on the chip
is a little unusual (if you cribbed this from somewhere I've forgotten
about then do say so!), so will want a devicetree bindings maintainer
input on this.
Thanks,
Jonathan
> ---
> .../devicetree/bindings/iio/imu/bmi160.txt | 34 ++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
> new file mode 100644
> index 0000000..b02ef3e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
> @@ -0,0 +1,34 @@
> +Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
> +and externally connectable Magnetometer
> +
> +https://www.bosch-sensortec.com/bst/products/all_products/bmi160
> +
> +Required properties:
> + - compatible : should be "bosch,bmi160"
> + - reg : the I2C address or SPI chip select number of the sensor
> + - spi-max-frequency : set maximum clock frequency (only for SPI)
> +
> +Optional properties:
> + - interrupt-parent : should be the phandle of the interrupt controller
> + - interrupts : interrupt mapping for GPIO IRQ, must be IRQ_TYPE_LEVEL_LOW
> + - interrupt-names : set to "INT2" if using INT2 pin
> +
> +Examples:
> +
> +bmi160@68 {
> + compatible = "bosch,bmi160";
> + reg = <0x68>;
> +
> + interrupt-parent = <&gpio4>;
> + interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> +};
> +
> +bmi160@0 {
> + compatible = "bosch,bmi160";
> + reg = <0>;
> + spi-max-frequency = <10000000>;
> +
> + interrupt-parent = <&gpio2>;
> + interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "INT2";
> +};
>
--
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^ permalink raw reply
* Re: [PATCH 1/2] iio: bmi160: Support hardware fifo
From: Jonathan Cameron @ 2016-11-06 12:35 UTC (permalink / raw)
To: Marcin Niestroj
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
Daniel Baluta, Gregor Boirie, Sanchayan Maity, Rob Herring,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161103112527.29623-1-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
On 03/11/16 11:25, Marcin Niestroj wrote:
> This patch was developed primarily based on bmc150_accel hardware fifo
> implementation.
>
> IRQ handler was added, which for now is responsible only for handling
> watermark interrupts. The BMI160 chip has two interrupt outputs. By
> default INT is considered to be connected. If INT2 is used instead, the
> interrupt-names device-tree property can be used to specify that.
>
> Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
I agree with Peter that there should have been a few precursor patches
to this one doing various cleanups and reworking bits that you have
in here. Would have made it easier to review (always a good thing :)
In general the resulting code looks good to me. A few little
additional comments inline from me. Mostly about small code ordering things
and function rename suggestions that would make the code more 'obviously'
correct.
Thanks,
Jonathan
> ---
> drivers/iio/imu/bmi160/bmi160.h | 3 +-
> drivers/iio/imu/bmi160/bmi160_core.c | 633 +++++++++++++++++++++++++++++++++--
> drivers/iio/imu/bmi160/bmi160_i2c.c | 7 +-
> drivers/iio/imu/bmi160/bmi160_spi.c | 3 +-
> 4 files changed, 618 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
> index d2ae6ed..4a7c10e 100644
> --- a/drivers/iio/imu/bmi160/bmi160.h
> +++ b/drivers/iio/imu/bmi160/bmi160.h
> @@ -4,7 +4,8 @@
> extern const struct regmap_config bmi160_regmap_config;
>
> int bmi160_core_probe(struct device *dev, struct regmap *regmap,
> - const char *name, bool use_spi);
> + const char *name, int irq,
> + bool use_spi, bool block_supported);
> void bmi160_core_remove(struct device *dev);
>
> #endif /* BMI160_H_ */
> diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
> index e0251b8..153734c 100644
> --- a/drivers/iio/imu/bmi160/bmi160_core.c
> +++ b/drivers/iio/imu/bmi160/bmi160_core.c
> @@ -2,6 +2,7 @@
> * BMI160 - Bosch IMU (accel, gyro plus external magnetometer)
> *
> * Copyright (c) 2016, Intel Corporation.
> + * Copyright (c) 2016, Grinn
> *
> * This file is subject to the terms and conditions of version 2 of
> * the GNU General Public License. See the file COPYING in the main
> @@ -9,7 +10,7 @@
> *
> * IIO core driver for BMI160, with support for I2C/SPI busses
> *
> - * TODO: magnetometer, interrupts, hardware FIFO
> + * TODO: magnetometer, interrupts
> */
> #include <linux/module.h>
> #include <linux/regmap.h>
> @@ -22,8 +23,12 @@
> #include <linux/iio/buffer.h>
> #include <linux/iio/sysfs.h>
>
> +#include <linux/of_irq.h>
> +
> #include "bmi160.h"
>
> +#define BMI160_IRQ_NAME "bmi160_event"
> +
> #define BMI160_REG_CHIP_ID 0x00
> #define BMI160_CHIP_ID_VAL 0xD1
>
> @@ -34,6 +39,21 @@
> #define BMI160_REG_DATA_GYRO_XOUT_L 0x0C
> #define BMI160_REG_DATA_ACCEL_XOUT_L 0x12
>
> +#define BMI160_REG_STATUS 0x1B
> +#define BMI160_STATUS_MAG_MAN_OP BIT(2)
> +
> +#define BMI160_REG_INT_STATUS0 0x1C
> +
> +#define BMI160_REG_INT_STATUS1 0x1D
> +#define BMI160_INT_STATUS_FWM BIT(6)
> +
> +#define BMI160_REG_INT_STATUS2 0x1E
> +
> +#define BMI160_REG_INT_STATUS3 0x1F
> +
> +#define BMI160_REG_FIFO_LENGTH 0x22
> +#define BMI160_REG_FIFO_DATA 0x24
> +
> #define BMI160_REG_ACCEL_CONFIG 0x40
> #define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0)
> #define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4)
> @@ -55,6 +75,36 @@
> #define BMI160_GYRO_RANGE_250DPS 0x03
> #define BMI160_GYRO_RANGE_125DPS 0x04
>
> +#define BMI160_REG_FIFO_CONFIG_0 0x46
> +
> +#define BMI160_REG_FIFO_CONFIG_1 0x47
> +#define BMI160_FIFO_GYRO_EN BIT(7)
> +#define BMI160_FIFO_ACCEL_EN BIT(6)
> +#define BMI160_FIFO_MAGN_EN BIT(5)
> +#define BMI160_FIFO_HEADER_EN BIT(4)
> +#define BMI160_FIFO_TAG_INT1_EN BIT(3)
> +#define BMI160_FIFO_TAG_INT2_EN BIT(2)
> +#define BMI160_FIFO_TIME_EN BIT(1)
> +
> +#define BMI160_REG_INT_EN_1 0x51
> +#define BMI160_INT_FWM_EN BIT(6)
> +#define BMI160_INT_FFULL_EN BIT(5)
> +#define BMI160_INT_DRDY_EN BIT(4)
> +
> +#define BMI160_REG_INT_OUT_CTRL 0x53
> +#define BMI160_INT2_OUTPUT_EN BIT(7)
> +#define BMI160_INT1_OUTPUT_EN BIT(3)
> +
> +#define BMI160_REG_INT_LATCH 0x54
> +
> +#define BMI160_REG_INT_MAP_1 0x56
> +#define BMI160_INT1_MAP_DRDY BIT(7)
> +#define BMI160_INT1_MAP_FWM BIT(6)
> +#define BMI160_INT1_MAP_FFULL BIT(5)
> +#define BMI160_INT2_MAP_DRDY BIT(3)
> +#define BMI160_INT2_MAP_FWM BIT(2)
> +#define BMI160_INT2_MAP_FFULL BIT(1)
> +
> #define BMI160_REG_CMD 0x7E
> #define BMI160_CMD_ACCEL_PM_SUSPEND 0x10
> #define BMI160_CMD_ACCEL_PM_NORMAL 0x11
> @@ -66,6 +116,8 @@
>
> #define BMI160_REG_DUMMY 0x7F
>
> +#define BMI160_FIFO_LENGTH 1024
> +
> #define BMI160_ACCEL_PMU_MIN_USLEEP 3200
> #define BMI160_ACCEL_PMU_MAX_USLEEP 3800
> #define BMI160_GYRO_PMU_MIN_USLEEP 55000
> @@ -110,8 +162,33 @@ enum bmi160_sensor_type {
> BMI160_NUM_SENSORS /* must be last */
> };
>
> +struct bmi160_irq_data {
> + unsigned int map_fwm;
> + unsigned int output_en;
> +};
> +
> +static const struct bmi160_irq_data bmi160_irq1_data = {
> + .map_fwm = BMI160_INT1_MAP_FWM,
> + .output_en = BMI160_INT1_OUTPUT_EN,
> +};
> +
> +static const struct bmi160_irq_data bmi160_irq2_data = {
> + .map_fwm = BMI160_INT2_MAP_FWM,
> + .output_en = BMI160_INT2_OUTPUT_EN,
> +};
> +
> struct bmi160_data {
> struct regmap *regmap;
> + struct mutex mutex;
> + const struct bmi160_irq_data *irq_data;
> + int irq;
> + int64_t timestamp;
> + int64_t fifo_sample_period;
> + bool fifo_enabled;
> + unsigned int fifo_config;
> + unsigned int fifo_sample_size;
> + u8 *fifo_buffer;
> + unsigned int watermark;
> };
>
> const struct regmap_config bmi160_regmap_config = {
> @@ -159,11 +236,11 @@ struct bmi160_pmu_time {
> static struct bmi160_pmu_time bmi160_pmu_time[] = {
> [BMI160_ACCEL] = {
> .min = BMI160_ACCEL_PMU_MIN_USLEEP,
> - .max = BMI160_ACCEL_PMU_MAX_USLEEP
> + .max = BMI160_ACCEL_PMU_MAX_USLEEP,
> },
> [BMI160_GYRO] = {
> .min = BMI160_GYRO_PMU_MIN_USLEEP,
> - .max = BMI160_GYRO_PMU_MIN_USLEEP,
Guessing this one is a bug!
> + .max = BMI160_GYRO_PMU_MAX_USLEEP,
> },
> };
>
> @@ -285,7 +362,9 @@ int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t,
> else
> cmd = bmi160_regs[t].pmu_cmd_suspend;
>
> + mutex_lock(&data->mutex);
> ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd);
> + mutex_unlock(&data->mutex);
> if (ret < 0)
> return ret;
>
> @@ -298,6 +377,7 @@ static
> int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
> int uscale)
> {
> + int ret;
> int i;
>
> for (i = 0; i < bmi160_scale_table[t].num; i++)
> @@ -307,8 +387,12 @@ int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
> if (i == bmi160_scale_table[t].num)
> return -EINVAL;
>
> - return regmap_write(data->regmap, bmi160_regs[t].range,
> - bmi160_scale_table[t].tbl[i].bits);
> + mutex_lock(&data->mutex);
> + ret = regmap_write(data->regmap, bmi160_regs[t].range,
> + bmi160_scale_table[t].tbl[i].bits);
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> }
>
> static
> @@ -317,7 +401,9 @@ int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
> {
> int i, ret, val;
>
> + mutex_lock(&data->mutex);
> ret = regmap_read(data->regmap, bmi160_regs[t].range, &val);
> + mutex_unlock(&data->mutex);
> if (ret < 0)
> return ret;
>
> @@ -340,7 +426,9 @@ static int bmi160_get_data(struct bmi160_data *data, int chan_type,
>
> reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(__le16);
>
> + mutex_lock(&data->mutex);
> ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(__le16));
> + mutex_unlock(&data->mutex);
> if (ret < 0)
> return ret;
>
> @@ -353,6 +441,7 @@ static
> int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
> int odr, int uodr)
> {
> + int ret;
> int i;
>
> for (i = 0; i < bmi160_odr_table[t].num; i++)
> @@ -363,20 +452,30 @@ int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
> if (i >= bmi160_odr_table[t].num)
> return -EINVAL;
>
> - return regmap_update_bits(data->regmap,
> - bmi160_regs[t].config,
> - bmi160_regs[t].config_odr_mask,
> - bmi160_odr_table[t].tbl[i].bits);
> + mutex_lock(&data->mutex);
> + ret = regmap_update_bits(data->regmap,
> + bmi160_regs[t].config,
> + bmi160_regs[t].config_odr_mask,
> + bmi160_odr_table[t].tbl[i].bits);
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> }
>
> -static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
> - int *odr, int *uodr)
> +static int64_t bmi160_frequency_to_period(int odr, int uodr)
> {
> - int i, val, ret;
> + uint64_t period = 1000000000000000;
> + int64_t frequency = (int64_t) odr * 1000000 + uodr;
>
> - ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
> - if (ret < 0)
> - return ret;
> + do_div(period, frequency);
> +
> + return period;
> +}
> +
> +static const struct bmi160_odr *bmi160_reg_to_odr(enum bmi160_sensor_type t,
> + unsigned int val)
> +{
> + int i;
>
> val &= bmi160_regs[t].config_odr_mask;
>
> @@ -385,10 +484,52 @@ static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
> break;
>
> if (i >= bmi160_odr_table[t].num)
> - return -EINVAL;
> + return ERR_PTR(-EINVAL);
> +
> + return &bmi160_odr_table[t].tbl[i];
> +}
> +
> +static int bmi160_get_sample_period(struct bmi160_data *data,
> + enum bmi160_sensor_type t,
> + int64_t *sample_period)
> +{
> + const struct bmi160_odr *odr_entry;
> + int ret;
> + unsigned int val;
> +
> + ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
> + if (ret < 0)
> + return ret;
>
> - *odr = bmi160_odr_table[t].tbl[i].odr;
> - *uodr = bmi160_odr_table[t].tbl[i].uodr;
> + odr_entry = bmi160_reg_to_odr(t, val);
> + if (IS_ERR(odr_entry))
> + return PTR_ERR(odr_entry);
> +
> + *sample_period = bmi160_frequency_to_period(odr_entry->odr,
> + odr_entry->uodr);
> +
> + return 0;
> +}
> +
> +static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
> + int *odr, int *uodr)
> +{
> + const struct bmi160_odr *odr_entry;
> + int ret;
> + unsigned int val;
> +
> + mutex_lock(&data->mutex);
> + ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
> + mutex_unlock(&data->mutex);
> + if (ret < 0)
> + return ret;
> +
> + odr_entry = bmi160_reg_to_odr(t, val);
> + if (IS_ERR(odr_entry))
> + return PTR_ERR(odr_entry);
> +
> + *odr = odr_entry->odr;
> + *uodr = odr_entry->uodr;
>
> return 0;
> }
> @@ -402,14 +543,18 @@ static irqreturn_t bmi160_trigger_handler(int irq, void *p)
> int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L;
> __le16 sample;
>
> + mutex_lock(&data->mutex);
> for_each_set_bit(i, indio_dev->active_scan_mask,
> indio_dev->masklength) {
> ret = regmap_bulk_read(data->regmap, base + i * sizeof(__le16),
> &sample, sizeof(__le16));
> - if (ret < 0)
> + if (ret < 0) {
> + mutex_unlock(&data->mutex);
> goto done;
> + }
> buf[j++] = sample;
> }
> + mutex_unlock(&data->mutex);
>
> iio_push_to_buffers_with_timestamp(indio_dev, buf,
> iio_get_time_ns(indio_dev));
> @@ -493,11 +638,364 @@ static const struct attribute_group bmi160_attrs_group = {
> .attrs = bmi160_attrs,
> };
>
Naming to my mind would imply we are causing the period to be updated
rather than reading the updated value that hte hardware is giving us.
I'd rename as simple _read_sample_period
> +static int bmi160_update_sample_period(struct bmi160_data *data,
> + enum bmi160_sensor_type sensor_type)
> +{
> + struct device *dev = regmap_get_device(data->regmap);
> + int64_t sample_period;
> + int ret;
> +
> + ret = bmi160_get_sample_period(data, sensor_type, &sample_period);
> + if (ret < 0)
> + return ret;
> +
> + if (data->fifo_sample_period) {
> + if (data->fifo_sample_period != sample_period) {
> + dev_warn(dev, "Enabled sensors have unequal ODR values\n");
> + return -EINVAL;
> + }
> + } else {
> + data->fifo_sample_period = sample_period;
> + }
> +
> + return 0;
> +}
> +
> +static int bmi160_fifo_enable(struct iio_dev *indio_dev,
> + struct bmi160_data *data)
> +{
> + struct regmap *regmap = data->regmap;
> + struct device *dev = regmap_get_device(regmap);
> + int ret;
> + int i;
> + unsigned int val;
> + unsigned int fifo_config = 0;
> +
> + /* Set fifo sample size and period */
> + for_each_set_bit(i, indio_dev->active_scan_mask,
> + indio_dev->masklength) {
> + if (i <= BMI160_SCAN_GYRO_Z)
> + fifo_config |= BMI160_FIFO_GYRO_EN;
> + else if (i <= BMI160_SCAN_ACCEL_Z)
> + fifo_config |= BMI160_FIFO_ACCEL_EN;
> + }
> +
> + data->fifo_sample_period = 0;
> + data->fifo_sample_size = 0;
> + if (fifo_config & BMI160_FIFO_GYRO_EN) {
> + data->fifo_sample_size += 6;
> + ret = bmi160_update_sample_period(data, BMI160_GYRO);
> + if (ret < 0)
> + return ret;
> + }
> + if (fifo_config & BMI160_FIFO_ACCEL_EN) {
> + data->fifo_sample_size += 6;
> + ret = bmi160_update_sample_period(data, BMI160_ACCEL);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /*
> + * Set watermark level and write real value back, as it will be used
> + * in timestamp calculation.
> + */
> + val = data->watermark * data->fifo_sample_size;
> + if (val > BMI160_FIFO_LENGTH - 1) {
> + val = BMI160_FIFO_LENGTH - 1;
> + data->watermark = val / data->fifo_sample_size;
> + }
> + val = data->watermark * data->fifo_sample_size / 4;
> +
> + ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_0, val);
> + if (ret < 0) {
> + dev_err(dev, "Failed to set watermark\n");
> + return ret;
> + }
> +
> + /* Enable FIFO channels */
> + ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_1,
> + fifo_config);
> + if (ret < 0) {
> + dev_err(dev, "Failed to write FIFO_CONFIG_1\n");
> + return ret;
> + }
> +
> + data->fifo_config = fifo_config;
> + data->fifo_enabled = true;
> +
> + return 0;
> +}
> +
> +static int bmi160_fifo_disable(struct bmi160_data *data)
> +{
> + struct regmap *regmap = data->regmap;
> + struct device *dev = regmap_get_device(regmap);
> + int ret;
> +
> + /* Disable all FIFO channels */
> + ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_1, 0);
> + if (ret < 0) {
> + dev_err(dev, "Failed to write FIFO_CONFIG_1\n");
> + return ret;
> + }
> +
> + data->fifo_enabled = false;
> +
> + return 0;
> +}
> +
> +static int bmi160_buffer_postenable(struct iio_dev *indio_dev)
> +{
> + struct bmi160_data *data = iio_priv(indio_dev);
> + int ret;
> +
> + if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
> + return iio_triggered_buffer_postenable(indio_dev);
> +
> + mutex_lock(&data->mutex);
> + ret = regmap_update_bits(data->regmap, BMI160_REG_INT_MAP_1,
> + data->irq_data->map_fwm, data->irq_data->map_fwm);
> + if (ret < 0)
> + goto unlock;
> +
> + ret = regmap_update_bits(data->regmap, BMI160_REG_INT_EN_1,
> + BMI160_INT_FWM_EN, BMI160_INT_FWM_EN);
> + if (ret < 0)
> + goto unlock;
> +
> + ret = bmi160_fifo_enable(indio_dev, data);
> +
> +unlock:
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> +}
> +
> +static int bmi160_buffer_predisable(struct iio_dev *indio_dev)
> +{
> + struct bmi160_data *data = iio_priv(indio_dev);
> + struct regmap *regmap = data->regmap;
> + int ret = 0;
> +
> + if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
> + return iio_triggered_buffer_predisable(indio_dev);
> +
> + mutex_lock(&data->mutex);
> +
I would rather expect this unwind to reverse the order of the setup above.
Either that is obviously correct, or there should be some comments in here
indicating why not.
> + ret = regmap_update_bits(regmap, BMI160_REG_INT_EN_1,
> + BMI160_INT_FWM_EN, 0);
> + if (ret < 0)
> + goto unlock;
> +
> + ret = bmi160_fifo_disable(data);
> +
> +unlock:
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> +}
> +
> +static const struct iio_buffer_setup_ops bmi160_buffer_ops = {
> + .postenable = bmi160_buffer_postenable,
> + .predisable = bmi160_buffer_predisable,
> +};
> +
> +static ssize_t bmi160_get_fifo_state(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct bmi160_data *data = iio_priv(indio_dev);
> + bool state;
> +
> + mutex_lock(&data->mutex);
> + state = data->fifo_enabled;
> + mutex_unlock(&data->mutex);
> +
> + return sprintf(buf, "%d\n", (int) state);
> +}
> +
> +static ssize_t bmi160_get_fifo_watermark(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct bmi160_data *data = iio_priv(indio_dev);
> + int wm;
> +
> + mutex_lock(&data->mutex);
> + wm = data->watermark;
> + mutex_unlock(&data->mutex);
> +
> + return sprintf(buf, "%d\n", wm);
> +}
> +
> +static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
> +static IIO_CONST_ATTR(hwfifo_watermark_max,
> + __stringify(BMI160_FIFO_LENGTH));
> +static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
> + bmi160_get_fifo_state, NULL, 0);
> +static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
> + bmi160_get_fifo_watermark, NULL, 0);
> +
> +static const struct attribute *bmi160_fifo_attributes[] = {
> + &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
> + &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
> + &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
> + &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
There are enough of these drivers now that sometimes soon we should
revisit the question of pulling these into the core. Can certainly
concieve of downstream consumer devices (in particular the iio_input
bridge when that finally resurfaces - my fault) wanting to be able to
manipulate or at least have visibilty of these.
> + NULL,
> +};
> +
> +static int bmi160_set_watermark(struct iio_dev *indio_dev, unsigned int val)
> +{
> + struct bmi160_data *data = iio_priv(indio_dev);
> +
> + if (val > BMI160_FIFO_LENGTH)
> + val = BMI160_FIFO_LENGTH;
> +
> + data->watermark = val;
> +
> + return 0;
> +}
> +
> +static int bmi160_fifo_transfer(struct bmi160_data *data,
> + char *buffer, int num_bytes)
> +{
> + struct regmap *regmap = data->regmap;
> + struct device *dev = regmap_get_device(regmap);
> + size_t step = regmap_get_raw_read_max(regmap);
> + int ret = 0;
> + int i;
> +
> + if (!step || step > num_bytes)
> + step = num_bytes;
> + else if (step < num_bytes)
> + step = data->fifo_sample_size;
> +
> + for (i = 0; i < num_bytes; i += step) {
> + ret = regmap_raw_read(regmap, BMI160_REG_FIFO_DATA,
> + &buffer[i], step);
> +
> + if (ret)
> + break;
> + }
> +
> + if (ret)
> + dev_err(dev,
> + "Error transferring data from fifo in single steps of %zu\n",
> + step);
> +
> + return ret;
> +}
> +
> +static int __bmi160_fifo_flush(struct iio_dev *indio_dev,
> + unsigned int samples, bool irq)
> +{
> + struct bmi160_data *data = iio_priv(indio_dev);
> + struct regmap *regmap = data->regmap;
> + struct device *dev = regmap_get_device(regmap);
> + int ret;
> + __le16 fifo_length;
> + unsigned int fifo_samples;
> + unsigned int fifo_bytes;
> + u8 *buffer = data->fifo_buffer;
> + u8 *buffer_iter;
> + int64_t last_timestamp, timestamp;
> + unsigned int last_samples;
> + unsigned int i;
> +
> + /* Get the current FIFO length */
> + ret = regmap_bulk_read(regmap, BMI160_REG_FIFO_LENGTH,
> + &fifo_length, sizeof(__le16));
> + if (ret < 0) {
> + dev_err(dev, "Error reading FIFO_LENGTH\n");
> + return ret;
> + }
> +
> + fifo_bytes = le16_to_cpu(fifo_length);
> + fifo_samples = fifo_bytes / data->fifo_sample_size;
> +
> + if (fifo_bytes % data->fifo_sample_size)
> + dev_warn(dev, "fifo_bytes %u is not dividable by %u\n",
> + fifo_bytes, data->fifo_sample_size);
> +
> + if (!fifo_samples)
> + return 0;
> +
> + if (samples && fifo_samples > samples) {
> + fifo_samples = samples;
> + fifo_bytes = fifo_samples * data->fifo_sample_size;
> + }
> +
> + /*
> + * If we are not called from IRQ, it means that we are flushing data
> + * on demand. In that case we do not have latest timestamp saved in
> + * data->timestamp. Get the time now instead.
> + *
> + * In case of IRQ flush, saved timestamp shows the time when number
> + * of samples configured by watermark were ready. Currently there might
> + * be more samples already.
> + * If we are not called from IRQ, than we are getting the current fifo
> + * length, as we are setting timestamp just after getting it.
> + */
It's a real pain that people almost always want timestamps with IMU data :(
Ah well, this is about the best that can be done...
> + if (!irq) {
> + last_timestamp = iio_get_time_ns(indio_dev);
> + last_samples = fifo_samples;
> + } else {
> + last_timestamp = data->timestamp;
> + last_samples = data->watermark;
> + }
> +
> + /* Get all measurements */
> + ret = bmi160_fifo_transfer(data, buffer, fifo_bytes);
> + if (ret)
> + return ret;
> +
> + /* Handle demux */
> + timestamp = last_timestamp - (last_samples * data->fifo_sample_period);
> + buffer_iter = buffer;
> + for (i = 0; i < fifo_samples; i++) {
> + u8 tmp_buf[indio_dev->scan_bytes];
> +
> + memcpy(tmp_buf, buffer_iter, data->fifo_sample_size);
> +
> + timestamp += data->fifo_sample_period;
> + iio_push_to_buffers_with_timestamp(indio_dev,
> + tmp_buf,
> + timestamp);
Not a comment on your code which is correct as it stands, but...
We should really get a useful utility functions in place:
iio_push_to_buffer_with_timestamp_safe(struct iio_dev *, void *data, void *working, timestamp);
Which would use the working space to do your little data shuffle as here - if
the timestamp is enabled, and skip it if not.
We've been meaning to add a multiple element push to buffer, so we'd need
a little helper to do the data shuffling for that as well (probably just
looping on the _safe version of the local push.)
> +
> + buffer_iter += data->fifo_sample_size;
> + }
> +
> + return fifo_samples;
> +}
> +
> +static int bmi160_fifo_flush(struct iio_dev *indio_dev, unsigned int samples)
> +{
> + struct bmi160_data *data = iio_priv(indio_dev);
> + int ret;
> +
> + mutex_lock(&data->mutex);
> + ret = __bmi160_fifo_flush(indio_dev, samples, false);
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> +}
> +
> static const struct iio_info bmi160_info = {
> - .driver_module = THIS_MODULE,
> - .read_raw = bmi160_read_raw,
> - .write_raw = bmi160_write_raw,
> - .attrs = &bmi160_attrs_group,
> + .driver_module = THIS_MODULE,
> + .read_raw = bmi160_read_raw,
> + .write_raw = bmi160_write_raw,
> + .attrs = &bmi160_attrs_group,
> +};
The realignment adds nothing but noise - so I wouldn't do it. These always
seem very nice and pretty but then we get another addition that requires
futher indenting and suddenly we have another pointless 15 lines of patch.
The only exception in my mind is things like filling in numerical arrays
where readability is really enhanced.
(I wouldn't have minded enough to comment if this hadn't been modifying
existing code but just introducing new indented code).
> +
> +static const struct iio_info bmi160_info_fifo = {
> + .driver_module = THIS_MODULE,
> + .read_raw = bmi160_read_raw,
> + .write_raw = bmi160_write_raw,
> + .attrs = &bmi160_attrs_group,
> + .hwfifo_set_watermark = bmi160_set_watermark,
> + .hwfifo_flush_to_buffer = bmi160_fifo_flush,
> };
>
> static const char *bmi160_match_acpi_device(struct device *dev)
> @@ -561,12 +1059,54 @@ static void bmi160_chip_uninit(struct bmi160_data *data)
> bmi160_set_mode(data, BMI160_ACCEL, false);
> }
>
> +static int bmi160_enable_irq(struct bmi160_data *data)
> +{
> + int ret;
> +
> + mutex_lock(&data->mutex);
> + ret = regmap_update_bits(data->regmap, BMI160_REG_INT_OUT_CTRL,
> + data->irq_data->output_en,
> + data->irq_data->output_en);
> + mutex_unlock(&data->mutex);
> +
> + return ret;
> +}
> +
> +static irqreturn_t bmi160_irq_thread_handler(int irq, void *p)
> +{
> + struct iio_dev *indio_dev = p;
> + struct bmi160_data *data = iio_priv(indio_dev);
> + struct device *dev = regmap_get_device(data->regmap);
> +
> + mutex_lock(&data->mutex);
> + if (data->fifo_enabled)
> + __bmi160_fifo_flush(indio_dev, BMI160_FIFO_LENGTH, true);
> + else
> + dev_warn(dev,
> + "IRQ has been triggered, but FIFO is not enabled.\n");
> + mutex_unlock(&data->mutex);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t bmi160_irq_handler(int irq, void *p)
> +{
> + struct iio_dev *indio_dev = p;
> + struct bmi160_data *data = iio_priv(indio_dev);
> +
> + data->timestamp = iio_get_time_ns(indio_dev);
> +
> + return IRQ_WAKE_THREAD;
> +}
> +
> int bmi160_core_probe(struct device *dev, struct regmap *regmap,
> - const char *name, bool use_spi)
> + const char *name, int irq,
> + bool use_spi, bool block_supported)
> {
> struct iio_dev *indio_dev;
> struct bmi160_data *data;
> int ret;
> + int irq2;
>
> indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
> if (!indio_dev)
> @@ -574,8 +1114,11 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
>
> data = iio_priv(indio_dev);
> dev_set_drvdata(dev, indio_dev);
> + data->irq = irq;
> data->regmap = regmap;
>
> + mutex_init(&data->mutex);
> +
> ret = bmi160_chip_init(data, use_spi);
> if (ret < 0)
> return ret;
> @@ -591,10 +1134,50 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
> indio_dev->info = &bmi160_info;
>
> ret = iio_triggered_buffer_setup(indio_dev, NULL,
> - bmi160_trigger_handler, NULL);
> + bmi160_trigger_handler,
> + &bmi160_buffer_ops);
> if (ret < 0)
> goto uninit;
>
> + if (data->irq > 0) {
> + /* Check which interrupt pin is connected to our board */
> + irq2 = of_irq_get_byname(dev->of_node, "INT2");
> + if (irq2 == data->irq) {
> + dev_dbg(dev, "Using interrupt line INT2\n");
> + data->irq_data = &bmi160_irq2_data;
> + } else {
> + dev_dbg(dev, "Using interrupt line INT1\n");
> + data->irq_data = &bmi160_irq1_data;
> + }
> +
> + ret = devm_request_threaded_irq(dev,
> + data->irq,
> + bmi160_irq_handler,
> + bmi160_irq_thread_handler,
> + IRQF_ONESHOT,
> + BMI160_IRQ_NAME,
> + indio_dev);
> + if (ret)
> + return ret;
> +
> + ret = bmi160_enable_irq(data);
> + if (ret < 0)
> + goto buffer_cleanup;
> +
> + if (block_supported) {
> + indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
> + indio_dev->info = &bmi160_info_fifo;
> + indio_dev->buffer->attrs = bmi160_fifo_attributes;
> + data->fifo_buffer = devm_kmalloc(dev,
> + BMI160_FIFO_LENGTH,
> + GFP_KERNEL);
> + if (!data->fifo_buffer) {
> + ret = -ENOMEM;
> + goto buffer_cleanup;
> + }
> + }
> + }
> +
> ret = iio_device_register(indio_dev);
> if (ret < 0)
> goto buffer_cleanup;
> diff --git a/drivers/iio/imu/bmi160/bmi160_i2c.c b/drivers/iio/imu/bmi160/bmi160_i2c.c
> index 07a179d..aa63f89 100644
> --- a/drivers/iio/imu/bmi160/bmi160_i2c.c
> +++ b/drivers/iio/imu/bmi160/bmi160_i2c.c
> @@ -23,6 +23,10 @@ static int bmi160_i2c_probe(struct i2c_client *client,
> {
> struct regmap *regmap;
> const char *name = NULL;
> + bool block_supported =
> + i2c_check_functionality(client->adapter, I2C_FUNC_I2C) ||
> + i2c_check_functionality(client->adapter,
> + I2C_FUNC_SMBUS_READ_I2C_BLOCK);
>
> regmap = devm_regmap_init_i2c(client, &bmi160_regmap_config);
> if (IS_ERR(regmap)) {
> @@ -34,7 +38,8 @@ static int bmi160_i2c_probe(struct i2c_client *client,
> if (id)
> name = id->name;
>
> - return bmi160_core_probe(&client->dev, regmap, name, false);
> + return bmi160_core_probe(&client->dev, regmap, name, client->irq,
> + false, block_supported);
> }
>
> static int bmi160_i2c_remove(struct i2c_client *client)
> diff --git a/drivers/iio/imu/bmi160/bmi160_spi.c b/drivers/iio/imu/bmi160/bmi160_spi.c
> index 1ec8b12..9b57fbe 100644
> --- a/drivers/iio/imu/bmi160/bmi160_spi.c
> +++ b/drivers/iio/imu/bmi160/bmi160_spi.c
> @@ -25,7 +25,8 @@ static int bmi160_spi_probe(struct spi_device *spi)
> (int)PTR_ERR(regmap));
> return PTR_ERR(regmap);
> }
> - return bmi160_core_probe(&spi->dev, regmap, id->name, true);
> + return bmi160_core_probe(&spi->dev, regmap, id->name, spi->irq,
> + true, true);
> }
>
> static int bmi160_spi_remove(struct spi_device *spi)
>
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^ permalink raw reply
* Re: [REGRESSION] "console: don't prefer first registered if DT specifies stdout-path" breaks console on video outputs of various ARM boards
From: Thorsten Leemhuis @ 2016-11-06 12:13 UTC (permalink / raw)
To: Hans de Goede, Linus Torvalds, Andrew Morton, Paul Burton,
Rob Herring, Frank Rowand
Cc: Greg Kroah-Hartman, Tejun Heo, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161104121135.4780-1-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
JFYI: I added below report to the list of regressions for Linux 4.9.
I'll watch this thread for further updates on this issue to document
progress in my weekly reports. Please let me know via
regressions-rCxcAJFjeRkk+I/owrrOrA@public.gmane.org in case the discussion moves to a different
place (bugzilla or another mail thread for example).
Current status (afaics): Revert discussed
tia! Ciao, Thorsten
P.S.: Thx for CCing me!
On 04.11.2016 13:11, Hans de Goede wrote:
> Hi All,
>
> While booting 4.9-rc# for the first time on an Allwinner A33 tablet,
> I noticed that after u-boot the LCD display stayed black. It turns out
> that there was an issue which caused X to never get up, and all kernel
> (and other startup) messages prior to that only went to ttyS0 which
> consists of 2 tiny testpads on the PCB with this tablet.
>
> The same issue will also happen on any ARM boards which have a HDMI or
> composite video output and which use a stdout-path pointing to their
> serial console. I think this will e.g. also impact the Raspberry Pi,
> I know for certain that this will impact the 99 different Allwinnner
> boards currently supported by mainline u-boot + the mainline kernel.
>
> This is a behavior changes from previous kernels and I consider this
> a regression. Thus I propose to revert the commit in question, for more
> info here is a partial copy of the commit message of the proposed revert:
>
> The reverted commit changes existing behavior on which many ARM boards
> rely. Many ARM small-board-computers, like e.g. the Raspberry Pi have
> both a video output and a serial console. Depending on whether the user
> is using the device as a more regular computer; or as a headless device
> we need to have the console on either one or the other.
>
> Many users rely on the kernel behavior of the console being present on
> both outputs, before the reverted commit the console setup with no
> console= kernel arguments on an ARM board which sets stdout-path in dt
> would look like this:
>
> [root@localhost ~]# cat /proc/consoles
> ttyS0 -W- (EC p a) 4:64
> tty0 -WU (E p ) 4:1
>
> Where as after the reverted commit, it looks like this:
>
> [root@localhost ~]# cat /proc/consoles
> ttyS0 -W- (EC p a) 4:64
>
> This commit reverts commit 05fd007e4629 ("console: don't prefer first
> registered if DT specifies stdout-path") restoring the original behavior.
>
> Regards,
>
> Hans
>
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^ permalink raw reply
* [RFC PATCH] ARM: dts: add panel and tcon nodes to Allwinner A33 Q8 tablet dts
From: Icenowy Zheng @ 2016-11-06 11:11 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Hans de Goede
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
All A33 Q8 tablets features a LCD panel, with a resolution of either
800x480 or 1024x600.
Add "bone" device nodes to the device tree.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Maybe it will be better to add them to sun8i-q8-reference-tablet.dtsi, as
these pin configurations are part of reference design of both A23 and A33,
not only restricted to Q8.
The DTS file is tested by me, after cherry-picks this patch from Chen-Yu Tsai:
https://github.com/wens/linux/commit/2823b887a289fbee5f97f3c6b45ed6c74a6368c6
And add these commands to my U-Boot boot command:
fdt addr 0x43000000
fdt resize
fdt set /panel compatible "urt,umsh-8596md-t"
fdt set /panel status "okay"
fdt set /display-engine status "okay"
fdt set /soc@01c00000/lcd-controller@01c0c000 status "okay"
arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 44 +++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
index b0bc236..871a20c 100644
--- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
@@ -47,4 +47,48 @@
/ {
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
+
+ panel: panel {
+ /* compatible should be set according to the panel */
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_en_q8>;
+ backlight = <&backlight>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_dc1sw>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+ };
+};
+
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
+&pio {
+ lcd_en_q8: lcd_en@0 {
+ allwinner,pins = "PH7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
--
2.10.1
^ permalink raw reply related
* Re: [REGRESSION] "console: don't prefer first registered if DT specifies stdout-path" breaks console on video outputs of various ARM boards
From: Hans de Goede @ 2016-11-06 10:54 UTC (permalink / raw)
To: Paul Burton
Cc: Linus Torvalds, Andrew Morton, Rob Herring, Frank Rowand,
Thorsten Leemhuis, Greg Kroah-Hartman, Tejun Heo, devicetree,
linux-kernel
In-Reply-To: <1573891.u0IFOelkNI@np-p-burton>
Hi,
On 05-11-16 11:40, Paul Burton wrote:
> On Friday, 4 November 2016 14:22:17 GMT Hans de Goede wrote:
>> Hi,
>>
>> On 04-11-16 13:30, Paul Burton wrote:
>>> Hi Hans,
>>>
>>> On Friday, 4 November 2016 13:11:34 GMT Hans de Goede wrote:
>>>> Hi All,
>>>>
>>>> While booting 4.9-rc# for the first time on an Allwinner A33 tablet,
>>>> I noticed that after u-boot the LCD display stayed black. It turns out
>>>> that there was an issue which caused X to never get up, and all kernel
>>>> (and other startup) messages prior to that only went to ttyS0 which
>>>> consists of 2 tiny testpads on the PCB with this tablet.
>>>>
>>>> The same issue will also happen on any ARM boards which have a HDMI or
>>>> composite video output and which use a stdout-path pointing to their
>>>> serial console. I think this will e.g. also impact the Raspberry Pi,
>>>> I know for certain that this will impact the 99 different Allwinnner
>>>> boards currently supported by mainline u-boot + the mainline kernel.
>>>>
>>>> This is a behavior changes from previous kernels and I consider this
>>>> a regression. Thus I propose to revert the commit in question, for more
>>>> info here is a partial copy of the commit message of the proposed revert:
>>>>
>>>> The reverted commit changes existing behavior on which many ARM boards
>>>> rely. Many ARM small-board-computers, like e.g. the Raspberry Pi have
>>>> both a video output and a serial console. Depending on whether the user
>>>> is using the device as a more regular computer; or as a headless device
>>>> we need to have the console on either one or the other.
>>>>
>>>> Many users rely on the kernel behavior of the console being present on
>>>> both outputs, before the reverted commit the console setup with no
>>>> console= kernel arguments on an ARM board which sets stdout-path in dt
>>>> would look like this:
>>>>
>>>> [root@localhost ~]# cat /proc/consoles
>>>> ttyS0 -W- (EC p a) 4:64
>>>> tty0 -WU (E p ) 4:1
>>>>
>>>> Where as after the reverted commit, it looks like this:
>>>>
>>>> [root@localhost ~]# cat /proc/consoles
>>>> ttyS0 -W- (EC p a) 4:64
>>>>
>>>> This commit reverts commit 05fd007e4629 ("console: don't prefer first
>>>> registered if DT specifies stdout-path") restoring the original behavior.
>>>>
>>>> Regards,
>>>>
>>>> Hans
>>>
>>> Ugh... so the devices you're talking about rely upon set stdout-path in
>>> their device tree but effectively rely upon us ignoring it?
>>
>> No they rely on the kernel using stdout-path as an extra console while
>> keeping tty0 as console, not ignoring it. This how stdout-path has always
>> worked (at least as long as the Allwinner boards have used it, which has
>> been 2 - 3 years now).
>>
>> If you want only the console specified by stdout-path you can get this by
>> specifying it with console=... on the kernel cmdline.
>>
>>> If that's the case then I guess reverting is probably the best option, but
>>> it does restore us to a position where we honor stdout-path for earlycon
>>> & then essentially ignore it for the proper kernel console. That seems
>>> pretty bust to me...
>>
>> We do not ignore it, we use both the tty pointed to by stdout-path and tty0.
>>
>> Regards,
>>
>> Hans
>
> Hi Hans,
>
> Could you walk me though how you're getting that behaviour from the current
> code? I don't see how that would happen besides perhaps if drivers are probed
> in a fortunate order. Is that what you're relying upon?
I guess so, I never looked carefully at this, it has just always worked
until your patch.
> What I see in my systems, and what 05fd007e4629 ("console: don't prefer first
> registered if DT specifies stdout-path") addressed, is that if there are for
> example 2 UARTs uart0 & uart1 that are probed in that order and stdout-path
> indicates that we should use uart1 we wind up essentially ignoring it because
> the ordering of the relevant calls goes:
>
> - of_console_check() for uart0
> - add_preferred_console() for uart0
> - register_console() for uart0
> - of_console_check() for uart1
> - add_preferred_console() for uart1
> - register_console() for uart1
>
> Since of_check_console() doesn't get called for uart1 until after uart0 has
> been probed, we don't add an entry for it to the console_cmdline array until
> after register_console() has already decided to enable uart0 because
> preferred_console == -1.
>
> I'm not the only one seeing this oddity either, for example see the discussion
> on this patch:
>
> https://patchwork.kernel.org/patch/9263753/
>
> By simply reverting my patch you restore us to a position where so far as I
> can see we simply do not honor stdout-path for the real kernel console.
As said before, we do still honor it, but in your probe example we also get
a (second) serial console on uart0, where as you only want one on uart1.
So I see a few possible solutions here:
1) Do a new version of your patch which changes the "&& !of_specified_console"
check to "&& (newcon == tty0 || !of_specified_console)", then we would still
always register tty0 (as long as it gets registered first, just like now) and
we would not register uart0 in your above example, note the "newcon == tty0"
check in my example is pseudo-code. I would be happy to try out such a patch
2) Add a new dt property to enable the new behavior you seek
I'm myself tending towards 1 as a better solution: treat tty0 special, because
some existing setups rely on it always being registered as a console even if
stdout-path is specified and otherwise always honor stdout-path.
Regards,
Hans
^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-06 10:19 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Jason Cooper, Gregory Clement, Sebastian Hesselbarth,
Martin Strba??ka, Tomas Hlavacek, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161105220848.k6rrjmvvhdaeduma-jgopVnDzZD+b0XQX99//ntPVjbGH4+40kFgPdswSElo@public.gmane.org>
> Will do for v2. arch/arm/boot/dts/keystone-* needs fixing in this
> regard, too.
There is a whitelist of compatible strings which are ignored, for
backwards compatibility. See of_mdiobus_child_is_phy(). It would be
nice to fix keystone, but it is not required.
Andrew
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* Re: Issue with dt_to_config with dts files that include headers from dt-bindings
From: Gaurav Minocha @ 2016-11-06 1:01 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CA+rpMbK=T+Z=-pML4RHLJpLziy-UuANpUcgKNbq06tMNrdAPKw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Sat, Nov 5, 2016 at 2:56 PM, Gaurav Minocha
<gaurav.minocha.os-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Nov 4, 2016 1:19 PM, "Peter Robinson" <pbrobinson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>
>> Hi Gaurav, Rob and Frank,
>>
>> I've just discovered the dt_to_config script (awesome thanks!) but it
>> errors out when a dts(i) includes a header file from dt-bindings. EG
>>
>> ./scripts/dtc/dt_to_config arch/arm/boot/dts/am335x-boneblack.dts
>> In file included from arch/arm/boot/dts/am335x-boneblack.dts:10:0:
>> arch/arm/boot/dts/am33xx.dtsi:11:35: error: no include path in which
>> to search for dt-bindings/gpio/gpio.h
>> #include <dt-bindings/gpio/gpio.h>
>> ^
>> arch/arm/boot/dts/am33xx.dtsi:12:40: error: no include path in which
>> to search for dt-bindings/pinctrl/am33xx.h
>> #include <dt-bindings/pinctrl/am33xx.h>
>> ^
>> arch/arm/boot/dts/am335x-boneblack.dts:12:41: error: no include path
>> in which to search for dt-bindings/display/tda998x.h
>> #include <dt-bindings/display/tda998x.h>
>> ^
>> Error: arch/arm/boot/dts/am335x-bone-common.dtsi:33.23-24 syntax error
>> FATAL ERROR: Unable to parse input tree
>>
>
> In bash do, export ARCH=arm
>
> Works for me!
>
>>
>> Regards,
>> Peter
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* [PATCH] usb: dwc2: add amcc,dwc-otg device tree definition
From: Christian Lamparter @ 2016-11-06 0:56 UTC (permalink / raw)
To: linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: John Youn, Mark Rutland, Rob Herring, Greg Kroah-Hartman
This patch adds support for the "amcc,usb-otg" device
which is found in the PowerPC Canyonlands' dts.
The device definition was added by:
commit c89b3458d8cc ("powerpc/44x: Add USB DWC DTS entry to Canyonlands board")'.
AMCC produced a standalone driver that was sent to the
linuxppc-dev at the time. However, it was never integrated.
Signed-off-by: Christian Lamparter <chunkeey-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
For anyone interested: the driver was sent to the ML multiple times back
in 2012 [0], [1].
[0] <https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-May/097847.html>
[1] <https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-May/097938.html>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
drivers/usb/dwc2/platform.c | 33 ++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 2c30a54..73c4dc5 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -12,6 +12,7 @@ Required properties:
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,usb-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index dde08d5..8230037 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -214,6 +214,38 @@ static const struct dwc2_core_params params_amlogic = {
.hibernation = -1,
};
+static const struct dwc2_core_params params_amcc_dwc_otg = {
+ .otg_cap = DWC2_CAP_PARAM_HNP_SRP_CAPABLE,
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = -1,
+ .host_nperio_tx_fifo_size = -1,
+ .host_perio_tx_fifo_size = -1,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ /* Avoid system hang during concurrently using USB and SATA */
+ .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ GAHBCFG_HBSTLEN_SHIFT,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
/*
* Check the dr_mode against the module configuration and hardware
* capabilities.
@@ -521,6 +553,7 @@ static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
+ { .compatible = "amcc,dwc-otg", .data = ¶ms_amcc_dwc_otg },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.10.2
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^ permalink raw reply related
* [PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7745 support
From: Sergei Shtylyov @ 2016-11-05 22:34 UTC (permalink / raw)
To: mturquette, linux-clk, sboyd, robh+dt, mark.rutland, devicetree
Cc: linux-renesas-soc, horms+renesas
In-Reply-To: <3539878.XFtRJDB9iq@wasted.cogentembedded.com>
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
<geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- removed the FDP1-1 module clock;
- added Geert's tag.
Changes in version 2:
- changed the Z2 clock's divisor to 3.
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5
drivers/clk/renesas/Kconfig | 1
drivers/clk/renesas/Makefile | 1
drivers/clk/renesas/r8a7745-cpg-mssr.c | 260 +++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6
drivers/clk/renesas/renesas-cpg-mssr.h | 1
6 files changed, 272 insertions(+), 2 deletions(-)
Index: linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- linux.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -14,6 +14,7 @@ They provide the following functionaliti
Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
+ - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
@@ -23,8 +24,8 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7795, r8a7796)
- - "usb_extal" (r8a7743)
+ - "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
+ - "usb_extal" (r8a7743, r8a7745)
- "extalr" (r8a7795, r8a7796)
- #clock-cells: Must be 2
Index: linux/drivers/clk/renesas/Kconfig
===================================================================
--- linux.orig/drivers/clk/renesas/Kconfig
+++ linux/drivers/clk/renesas/Kconfig
@@ -1,6 +1,7 @@
config CLK_RENESAS_CPG_MSSR
bool
default y if ARCH_R8A7743
+ default y if ARCH_R8A7745
default y if ARCH_R8A7795
default y if ARCH_R8A7796
Index: linux/drivers/clk/renesas/Makefile
===================================================================
--- linux.orig/drivers/clk/renesas/Makefile
+++ linux/drivers/clk/renesas/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7743) += r8a7743-cpg-mssr.o rcar-gen2-cpg.o
+obj-$(CONFIG_ARCH_R8A7745) += r8a7745-cpg-mssr.o rcar-gen2-cpg.o
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
Index: linux/drivers/clk/renesas/r8a7745-cpg-mssr.c
===================================================================
--- /dev/null
+++ linux/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -0,0 +1,260 @@
+/*
+ * r8a7745 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7745_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("lb", R8A7745_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 3, 1),
+ DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
+ DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7745_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7745_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7745_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7745_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7745_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("acp", R8A7745_CLK_ACP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7745_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7745_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7745_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7745_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7745_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+};
+
+static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7745_CLK_MP),
+ DEF_MOD("vcp0", 101, R8A7745_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7745_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7745_CLK_P),
+ DEF_MOD("3dg", 112, R8A7745_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7745_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7745_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7745_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7745_CLK_CP),
+ DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7745_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7745_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7745_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7745_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7745_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7745_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7745_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7745_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7745_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7745_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7745_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7745_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7745_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7745_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7745_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7745_CLK_HP),
+ DEF_MOD("iic1", 323, R8A7745_CLK_HP),
+ DEF_MOD("cmt1", 329, R8A7745_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7745_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS),
+ DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7745_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7745_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7745_CLK_HP),
+ DEF_MOD("hscif2", 713, R8A7745_CLK_ZS),
+ DEF_MOD("scif5", 714, R8A7745_CLK_P),
+ DEF_MOD("scif4", 715, R8A7745_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7745_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7745_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7745_CLK_P),
+ DEF_MOD("scif2", 719, R8A7745_CLK_P),
+ DEF_MOD("scif1", 720, R8A7745_CLK_P),
+ DEF_MOD("scif0", 721, R8A7745_CLK_P),
+ DEF_MOD("du0", 724, R8A7745_CLK_ZX),
+ DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX),
+ DEF_MOD("vin1", 810, R8A7745_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7745_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7745_CLK_HP),
+ DEF_MOD("ether", 813, R8A7745_CLK_P),
+ DEF_MOD("gpio6", 905, R8A7745_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7745_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7745_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7745_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7745_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7745_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7745_CLK_CP),
+ DEF_MOD("can1", 915, R8A7745_CLK_P),
+ DEF_MOD("can0", 916, R8A7745_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7745_CLK_QSPI),
+ DEF_MOD("i2c5", 925, R8A7745_CLK_HP),
+ DEF_MOD("i2c4", 927, R8A7745_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7745_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7745_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7745_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7745_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7745_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7745_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
+};
+
+static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+ * 0 0 0 15 x200/3 x208/2 x106
+ * 0 0 1 15 x200/3 x208/2 x88
+ * 0 1 0 20 x150/3 x156/2 x80
+ * 0 1 1 20 x150/3 x156/2 x66
+ * 1 0 0 26 / 2 x230/3 x240/2 x122
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+ * 1 1 0 30 / 2 x200/3 x208/2 x106
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
+ { 1, 208, 106, 200 },
+ { 1, 208, 88, 200 },
+ { 1, 156, 80, 150 },
+ { 1, 156, 66, 150 },
+ { 2, 240, 122, 230 },
+ { 2, 240, 102, 230 },
+ { 2, 208, 106, 200 },
+ { 2, 208, 88, 200 },
+};
+
+static int __init r8a7745_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen2_cpg_init(cpg_pll_config);
+}
+
+const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7745_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7745_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7745_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7745_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7745_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7745_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7745_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ linux/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -509,6 +509,12 @@ static const struct of_device_id cpg_mss
.data = &r8a7743_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_ARCH_R8A7745
+ {
+ .compatible = "renesas,r8a7745-cpg-mssr",
+ .data = &r8a7745_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_ARCH_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ linux/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -131,6 +131,7 @@ struct cpg_mssr_info {
};
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
#endif
^ permalink raw reply
* [PATCH v3 1/2] ARM: shmobile: r8a7745: add CPG clock index macros
From: Sergei Shtylyov @ 2016-11-05 22:31 UTC (permalink / raw)
To: robh+dt, mark.rutland
Cc: mturquette, linux-clk, sboyd, devicetree, linux-renesas-soc,
horms+renesas
In-Reply-To: <3539878.XFtRJDB9iq@wasted.cogentembedded.com>
Add macros usable by the device tree sources to reference the R8A7745 CPG
clocks by index. The data comes from the table 7.2c in the revision 0.50
of the RZ/G Series User's Manual.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/clock/r8a7745-cpg-mssr.h | 44 +++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
Index: linux/include/dt-bindings/clock/r8a7745-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a7745-cpg-mssr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7745 CPG Core Clocks */
+#define R8A7745_CLK_Z2 0
+#define R8A7745_CLK_ZG 1
+#define R8A7745_CLK_ZTR 2
+#define R8A7745_CLK_ZTRD2 3
+#define R8A7745_CLK_ZT 4
+#define R8A7745_CLK_ZX 5
+#define R8A7745_CLK_ZS 6
+#define R8A7745_CLK_HP 7
+#define R8A7745_CLK_B 9
+#define R8A7745_CLK_LB 10
+#define R8A7745_CLK_P 11
+#define R8A7745_CLK_CL 12
+#define R8A7745_CLK_CP 13
+#define R8A7745_CLK_M2 14
+#define R8A7745_CLK_ZB3 16
+#define R8A7745_CLK_ZB3D2 17
+#define R8A7745_CLK_DDR 18
+#define R8A7745_CLK_SDH 19
+#define R8A7745_CLK_SD0 20
+#define R8A7745_CLK_SD2 21
+#define R8A7745_CLK_SD3 22
+#define R8A7745_CLK_MMC0 23
+#define R8A7745_CLK_MP 24
+#define R8A7745_CLK_QSPI 25
+#define R8A7745_CLK_ACP 26
+#define R8A7745_CLK_RCAN 27
+#define R8A7745_CLK_R 28
+#define R8A7745_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */
^ permalink raw reply
* [PATCH v3 0/2] Renesas R8A7745 CPG/MSSR clock support
From: Sergei Shtylyov @ 2016-11-05 22:28 UTC (permalink / raw)
To: mturquette, linux-clk, sboyd, robh+dt, mark.rutland, devicetree
Cc: linux-renesas-soc, horms+renesas
Hello.
Here's the set of 2 patches against the 'clk-next' branch of CLK group's
'linux.git' repo plus the R8A7743 CPG/MSSR patches just re-posted. They also
depend on the common R-Car Gen2 support patch. As the DT patches in the
R8A7745/SK-RZG1E board support series depend on the patch #1 of this series,
it might make sense to merge this patch to the 'renesas.git' repo as well...
[1/2] ARM: shmobile: r8a7745: add CPG clock index macros
[2/2] clk: renesas: cpg-mssr: add R8A7745 support
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 7/8] ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes
From: Kevin Hilman @ 2016-11-05 22:10 UTC (permalink / raw)
To: Neil Armstrong
Cc: carlo-KA+7E9HrN00dnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477932286-27482-8-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:
> Add SD/SDIO/MMC nodes and PWM 32768Hz clock configuration to provide
> storage and WiFi functionality on the p23x boards.
Just curious... what storage functionality are you referring to here?
Kevin
> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> .../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 112 +++++++++++++++++++++
> 1 file changed, 112 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
> index 666fe2b..7830809 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
> @@ -56,6 +56,46 @@
> device_type = "memory";
> reg = <0x0 0x0 0x0 0x80000000>;
> };
> +
> + vddio_boot: regulator-vddio_boot {
> + compatible = "regulator-fixed";
> + regulator-name = "VDDIO_BOOT";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vddao_3v3: regulator-vddao_3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDDAO_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vcc_3v3: regulator-vcc_3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + emmc_pwrseq: emmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> + };
> +
> + wifi32k: wifi32k {
> + compatible = "pwm-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
> + clocks = <&wifi32k>;
> + clock-names = "ext_clock";
> + };
> };
>
> /* This UART is brought out to the DB9 connector */
> @@ -64,3 +104,75 @@
> pinctrl-0 = <&uart_ao_a_pins>;
> pinctrl-names = "default";
> };
> +
> +/* Wireless SDIO Module */
> +&sd_emmc_a {
> + status = "okay";
> + pinctrl-0 = <&sdio_pins>;
> + pinctrl-names = "default";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + max-frequency = <100000000>;
> +
> + non-removable;
> + disable-wp;
> +
> + mmc-pwrseq = <&sdio_pwrseq>;
> +
> + vmmc-supply = <&vddao_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +
> + brcmf: bcrmf@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +/* SD card */
> +&sd_emmc_b {
> + status = "okay";
> + pinctrl-0 = <&sdcard_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + max-frequency = <100000000>;
> + disable-wp;
> +
> + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> +
> + vmmc-supply = <&vddao_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +};
> +
> +/* eMMC */
> +&sd_emmc_c {
> + status = "okay";
> + pinctrl-0 = <&emmc_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <8>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + max-frequency = <200000000>;
> + non-removable;
> + disable-wp;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> +
> + mmc-pwrseq = <&emmc_pwrseq>;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +};
> +
> +&pwm_ef {
> + status = "okay";
> + pinctrl-0 = <&pwm_e_pins>;
> + pinctrl-names = "default";
> + clocks = <&clkc CLKID_FCLK_DIV4>;
> + clock-names = "clkin0";
> +};
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^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Uwe Kleine-König @ 2016-11-05 22:08 UTC (permalink / raw)
To: Andrew Lunn
Cc: Jason Cooper, Gregory Clement, Sebastian Hesselbarth,
Martin Strba??ka, Tomas Hlavacek, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161105210441.GB1216-g2DYL2Zd6BY@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1346 bytes --]
On Sat, Nov 05, 2016 at 10:04:41PM +0100, Andrew Lunn wrote:
> > +&mdio {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mdio_pins>;
> > + status = "okay";
> > +
> > + phy1: phy@1 {
> > + status = "okay";
> > + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + };
>
> phy.txt says:
>
> - compatible: Compatible list, may contain
> "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
> PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
> specifications. If neither of these are specified, the default is to
> assume clause 22.
>
> If the phy's identifier is known then the list may contain an entry
> of the form: "ethernet-phy-idAAAA.BBBB" where
> AAAA - The value of the 16 bit Phy Identifier 1 register as
> 4 hex digits. This is the chip vendor OUI bits 3:18
> BBBB - The value of the 16 bit Phy Identifier 2 register as
> 4 hex digits. This is the chip vendor OUI bits 19:24,
> followed by 10 bits of a vendor specific ID.
>
> The compatible list should not contain other values than those
> listed here.
>
> Please don't list the "marvell,*" names.
Will do for v2. arch/arm/boot/dts/keystone-* needs fixing in this
regard, too.
Best regards
Uwe
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^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-05 21:37 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Mark Rutland, Martin Strba??ka, Jason Cooper,
devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek, Rob Herring,
Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
In-Reply-To: <20161105212748.vtdprlxxismy5xmk-jgopVnDzZD+b0XQX99//ntPVjbGH4+40kFgPdswSElo@public.gmane.org>
On Sat, Nov 05, 2016 at 10:27:49PM +0100, Uwe Kleine-König wrote:
> Hello Andrew,
>
> On Sat, Nov 05, 2016 at 10:23:26PM +0100, Andrew Lunn wrote:
> > > Still missing is support for the switch.
> >
> > Is it a Marvell Switch? armada-370-rd.dts would be a good start for
> > the old binding? vf610-zii-dev-rev-b.dts uses the new binding.
>
> Yeah, a 88E6176. I already try to understand vf610-zii-dev-rev-b.dts. Do
> you know if this driver works for the 88E6176?
Yes it does.
The vf610-zii-dev-rev-b is a bit complex because it has three
switches, and an mdio mux. You should be able to transplant the
switch0: switch0@0 part into the mdio node.
Andrew
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^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Uwe Kleine-König @ 2016-11-05 21:27 UTC (permalink / raw)
To: Andrew Lunn
Cc: Jason Cooper, Gregory Clement, Sebastian Hesselbarth,
Martin Strba??ka, Tomas Hlavacek, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161105212326.GC1216-g2DYL2Zd6BY@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 756 bytes --]
Hello Andrew,
On Sat, Nov 05, 2016 at 10:23:26PM +0100, Andrew Lunn wrote:
> > Still missing is support for the switch.
>
> Is it a Marvell Switch? armada-370-rd.dts would be a good start for
> the old binding? vf610-zii-dev-rev-b.dts uses the new binding.
Yeah, a 88E6176. I already try to understand vf610-zii-dev-rev-b.dts. Do
you know if this driver works for the 88E6176?
> > SFP is untested as is UART1.
>
> UART would be unusual. They are normally i2c.
I wanted to say: SFP is untested, and UART1 is untested too. Yes, SFP is
connected via i2c.
> > Do I need to "register" turris in vendor-prefixes.txt for that?
>
> Yes please.
OK, will wait for Martin to comment what we want there. cznic or turris.
Thanks
Uwe
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