* [PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- added address-cells, size-cells and ranges properties
Changes in v3:
- no changes
Changes in v4:
- no changes
arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5030065..bbb1c00 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -439,6 +439,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra30-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x48000000 0x7ffffff>;
+ clocks = <&tegra_car TEGRA30_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.1.4
^ permalink raw reply related
* [PATCH V4 3/6] dt/bindings: Add bindings for Tegra GMI controller
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
- Updated examples and some information based on comments from Jon Hunter.
Changes in v3:
- Updates ranges description based on comments from Rob Herring
Changes in v4:
- renamed snor-*-inv to snor-*-active-high
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
new file mode 100644
index 0000000..83b0e54
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
@@ -0,0 +1,132 @@
+Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
+
+The Generic Memory Interface bus enables memory transfers between internal and
+external memory. Can be used to attach various high speed devices such as
+synchronous/asynchronous NOR, FPGA, UARTS and more.
+
+The actual devices are instantiated from the child nodes of a GMI node.
+
+Required properties:
+ - compatible : Should contain one of the following:
+ For Tegra20 must contain "nvidia,tegra20-gmi".
+ For Tegra30 must contain "nvidia,tegra30-gmi".
+ - reg: Should contain GMI controller registers location and length.
+ - clocks: Must contain an entry for each entry in clock-names.
+ - clock-names: Must include the following entries: "gmi"
+ - resets : Must contain an entry for each entry in reset-names.
+ - reset-names : Must include the following entries: "gmi"
+ - #address-cells: The number of cells used to represent physical base
+ addresses in the GMI address space. Should be 2.
+ - #size-cells: The number of cells used to represent the size of an address
+ range in the GMI address space. Should be 1.
+ - ranges: Must be set up to reflect the memory layout with three integer values
+ for each chip-select line in use (only one entry is supported, see below
+ comments):
+ <cs-number> <offset> <physical address of mapping> <size>
+
+Note that the GMI controller does not have any internal chip-select address
+decoding, because of that chip-selects either need to be managed via software
+or by employing external chip-select decoding logic.
+
+If external chip-select logic is used to support multiple devices it is assumed
+that the devices use the same timing and so are probably the same type. It also
+assumes that they can fit in the 256MB address range. In this case only one
+child device is supported which represents the active chip-select line, see
+examples for more insight.
+
+The chip-select number is decoded from the child nodes second address cell of
+'ranges' property, if 'ranges' property is not present or empty chip-select will
+then be decoded from the first cell of the 'reg' property.
+
+Optional child cs node properties:
+
+ - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
+ - nvidia,snor-mux-mode: Enable address/data MUX mode.
+ - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
+ If omitted it will be asserted with data.
+ - nvidia,snor-rdy-active-high: RDY signal is active high
+ - nvidia,snor-adv-active-high: ADV signal is active high
+ - nvidia,snor-oe-active-high: WE/OE signal is active high
+ - nvidia,snor-cs-active-high: CS signal is active high
+
+ Note that there is some special handling for the timing values.
+ From Tegra TRM:
+ Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
+
+ - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
+ bus. Valid values are 0-15, default is 1
+ - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
+ de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
+ (in case of MASTER Request). Valid values are 0-15, default is 1
+ - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
+ Valid values are 0-15, default is 1.
+ - nvidia,snor-ce-width: Number of cycles before CE is asserted.
+ Valid values are 0-15, default is 4
+ - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
+ Valid values are 0-15, default is 1
+ - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
+ Valid values are 0-255, default is 1
+ - nvidia,snor-wait-width: Number of cycles before READY is asserted.
+ Valid values are 0-255, default is 3
+
+Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
+controllers with a simple-bus node since they are all connected to the same
+chip-select (CS4), in this example external address decoding is provided:
+
+gmi@70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ bus@4,0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 4 0 0x40100>;
+
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+
+ can@0 {
+ reg = <0 0x100>;
+ ...
+ };
+
+ can@40000 {
+ reg = <0x40000 0x100>;
+ ...
+ };
+ };
+};
+
+Example with one SJA1000 CAN controller connected to the GMI bus
+on CS4:
+
+gmi@70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ can@4,0 {
+ reg = <4 0 0x100>;
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+ ...
+ };
+};
--
2.1.4
^ permalink raw reply related
* [PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: mark.rutland, gnurou, pgaikwad, linux-clk, devicetree,
pdeschrijver, Mirza Krak, sboyd, linux, linux-kernel, robh+dt,
linux-tegra, mturquette, linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
The maximum rate value of 127 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..67f1677 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
is max rate.
The maximum rate value of 92 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+ { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 0/6] Add support for Tegra GMI bus controller
From: Mirza Krak @ 2016-11-07 8:29 UTC (permalink / raw)
To: swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Mirza Krak
From: Mirza Krak <mirza.krak-3xdUHytR7SMQwY+2splSUA@public.gmane.org>
Hi.
This patch series adds support for the Tegra GMI bus controller.
I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom
carrier board which has multiple CAN controllers (SJA1000) connected to the
GMI bus.
I have re-based on top of latest tegra/for-next in V4. Also see individual
patches for changes in V4.
Hopefully this will be the last round.
See below links for previous discussions.
Comments on RFC:
https://marc.info/?l=linux-clk&m=146893557629903&w=2
https://marc.info/?l=linux-tegra&m=146893541829801&w=2
https://marc.info/?l=linux-tegra&m=146893542429814&w=2
Comments on V1:
https://marc.info/?l=linux-arm-kernel&m=147051551821122&w=2
https://marc.info/?l=linux-arm-kernel&m=147051553121150&w=2
https://marc.info/?l=linux-arm-kernel&m=147194856600627&w=2
https://marc.info/?l=linux-arm-kernel&m=147072742432211&w=2
Comments on V2:
https://marc.info/?l=devicetree&m=147522253920226&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=devicetree&m=147256931318922&w=2
Comments on V3:
https://marc.info/?l=linux-tegra&m=147789181607782&w=2
https://marc.info/?l=linux-tegra&m=147816818203104&w=2
https://marc.info/?l=linux-tegra&m=147816897003332&w=2
https://marc.info/?l=linux-tegra&m=147818119107204&w=2
Mirza Krak (6):
clk: tegra: add TEGRA20_CLK_NOR to init table
clk: tegra: add TEGRA30_CLK_NOR to init table
dt/bindings: Add bindings for Tegra GMI controller
ARM: tegra: Add Tegra30 GMI support
ARM: tegra: Add Tegra20 GMI support
bus: Add support for Tegra Generic Memory Interface
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 ++++++++++
arch/arm/boot/dts/tegra20.dtsi | 13 +
arch/arm/boot/dts/tegra30.dtsi | 13 +
drivers/bus/Kconfig | 7 +
drivers/bus/Makefile | 1 +
drivers/bus/tegra-gmi.c | 275 +++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 1 +
drivers/clk/tegra/clk-tegra30.c | 1 +
8 files changed, 443 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
create mode 100644 drivers/bus/tegra-gmi.c
--
2.1.4
^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Martin Strbačka @ 2016-11-07 7:41 UTC (permalink / raw)
To: Uwe Kleine-König, Andrew Lunn
Cc: Mark Rutland, devicetree, Jason Cooper, Tomas Hlavacek,
Rob Herring, Gregory Clement, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20161105212748.vtdprlxxismy5xmk@perseus.defre.kleine-koenig.org>
[-- Attachment #1.1.1: Type: text/plain, Size: 388 bytes --]
On 5.11.2016 22:27, Uwe Kleine-König wrote:
>>> Do I need to "register" turris in vendor-prefixes.txt for that?
>> >
>> > Yes please.
> OK, will wait for Martin to comment what we want there. cznic or turris.
Hello,
please use CZ.NIC in this case. Turris Omnia is a model name.
Thanks for your work!
Martin
--
Martin Strbacka CZ.NIC, z.s.p.o. tel. +420 604 217 854
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-07 5:41 UTC (permalink / raw)
To: Linus Walleij
Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Stephen Warren, Rob Herring, Mark Rutland, Jon Hunter,
Masahiro Yamada,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CACRpkdb4DQLzQWHxuZi=TDaeigNzVJV8TN1jsQfOHKF7yPLrUg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Saturday 05 November 2016 03:54 AM, Linus Walleij wrote:
> On Wed, Nov 2, 2016 at 10:09 AM, Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>
>> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
>> low power state of some of its IO pads. The IO pads can work in
>> the voltage of the 1.8V and 3.3V of IO power rail sources. When IO
>> interface are not used then IO pads can be configure in low power
>> state to reduce the power from that IO pads.
>>
>> On Tegra124, the IO power rail source is auto detected by SoC and hence
>> it is only require to configure in low power mode if IO pads are not
>> used.
>>
>> On T210 onwards, the auto-detection is removed from SoC and hence SW
>> must configure the PMC register explicitly to set proper voltage in
>> IO pads based on IO rail power source voltage.
>>
>> This driver adds the IO pad driver to configure the power state and
>> IO pad voltage based on the usage and power tree via pincontrol
>> framework. The configuration can be static and dynamic.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Looking for an ACK from Stephen &| Thierry.
This driver depends on some new APIs from tegra pmc driver. The new APIs
are integrated in Thierry's branch and he wanted to push the changes to
linux-next/main path if there is any client driver for this.
This series is the client driver for tegra PMC.
So if you are fine, then you can ACK and Thierry can take this in his
branch.
Or I will leave to you/Thierry to propose if some other idea for
discussion/acceptance.
>
>> ---
>> On top of the branch from Thierry's T186 work
>> https://github.com/thierryreding/linux/tree/tegra186
> But it's an orthogonal patch right?
>
> The build robot seems to have problems with it so pls fix these.
The driver built in pinctrl branch and so this is expected. The APIs are
in the above branch.
>
>> +static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
>> + {
>> + .property = "nvidia,power-source-voltage",
>> + .param = TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE,
>> + },
>> +};
> Why can you not use the standard power-source binding
> from Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> instead of inventing this nvidia,* variant?
Per binding doc,
power-source - select between different power supplies
So actually it selects the different source of power supply.
In my case, I will have same supply but voltage of that supply get changed.
So here property is for the power-supply-voltage.
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^ permalink raw reply
* [PATCH 3/3] ARM: dts: imx: Add ocotp node for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
In-Reply-To: <1478497281-5477-1-git-send-email-ping.bai@nxp.com>
Add ocotp node for i.MX6UL SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index c5c05fd..c6f6613 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -849,6 +849,12 @@
reg = <0x021b0000 0x4000>;
};
+ ocotp: ocotp-ctrl@021bc000 {
+ compatible = "fsl,imx6ul-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6UL_CLK_OCOTP>;
+ };
+
lcdif: lcdif@021c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
reg = <0x021c8000 0x4000>;
--
2.8.2
^ permalink raw reply related
* [PATCH 2/3] devicetree: bindings: nvmem: Add compatible string for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
In-Reply-To: <1478497281-5477-1-git-send-email-ping.bai@nxp.com>
Add new compatible string for i.MX6UL SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 383d588..a7ff65d 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,14 @@
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
Required properties:
- compatible: should be one of
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
- "fsl,imx6sl-ocotp" (i.MX6SL), or
- "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+ "fsl,imx6sl-ocotp" (i.MX6SL),
+ "fsl,imx6sx-ocotp" (i.MX6SX), or
+ "fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
--
2.8.2
^ permalink raw reply related
* [PATCH 1/3] driver: nvmem: Add ocotp driver support for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
i.MX6UL is an new SOC of i.MX6 family. Enable ocotp
driver support for this SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
drivers/nvmem/imx-ocotp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index ac27b9b..108e4bc 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -73,6 +73,7 @@ static const struct of_device_id imx_ocotp_dt_ids[] = {
{ .compatible = "fsl,imx6q-ocotp", (void *)128 },
{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
+ { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
{ },
};
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
--
2.8.2
^ permalink raw reply related
* Re: [PATCH 0/3] ARM: dts: am33xx: Add clock info to rtc nodes
From: Keerthy @ 2016-11-07 4:25 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
t-kristo-l0cyMroinI0
In-Reply-To: <1477547288-5041-1-git-send-email-j-keerthy-l0cyMroinI0@public.gmane.org>
On Thursday 27 October 2016 11:18 AM, Keerthy wrote:
> The series adds the clock info to rtc node.
>
> Boot tested and checked for rtc ticking on am335x-boneblack, am335x-bone
> am437x-gp-evm.
Tony,
The relevant driver changes are already pulled by Alexandre Belloni.
https://patchwork.kernel.org/patch/9398903/.
Hope you call pull this set.
Regards,
Keerthy
>
> Keerthy (3):
> ARM: dts: AM335X-bone-common: Add the internal and external clock
> nodes for rtc
> ARM: dts: AM335X-evm: Add the internal and external clock nodes for
> rtc
> ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for
> rtc
>
> arch/arm/boot/dts/am335x-bone-common.dtsi | 5 +++++
> arch/arm/boot/dts/am335x-evm.dts | 5 +++++
> arch/arm/boot/dts/am335x-evmsk.dts | 5 +++++
> arch/arm/boot/dts/am33xx.dtsi | 2 ++
> 4 files changed, 17 insertions(+)
>
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^ permalink raw reply
* Re: [PATCH 2/5] drivers: gpio: Add support for multiple IPs
From: Keerthy @ 2016-11-07 3:59 UTC (permalink / raw)
To: Linus Walleij, Grygorii Strashko
Cc: Roger Quadros, Alexandre Courbot, Lokesh Vutla, Rob Herring,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-OMAP
In-Reply-To: <CACRpkdac_UgM=xeXkSZ+rOvZvutt40USjCoEt5-SoFkqspuExw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Saturday 05 November 2016 01:53 PM, Linus Walleij wrote:
> On Fri, Nov 4, 2016 at 8:59 PM, Grygorii Strashko
> <grygorii.strashko-l0cyMroinI0@public.gmane.org> wrote:
>> On 11/04/2016 09:28 AM, Linus Walleij wrote:
>
>>> The DT model sort of mandates how the interrupts should be mapped
>>> at this point, and as far as I can tell from the binding the example looks
>>> like so:
>>>
>>> gpio: gpio@1e26000 {
>>> compatible = "ti,dm6441-gpio";
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> reg = <0x226000 0x1000>;
>>> interrupt-parent = <&intc>;
>>> interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
>>> 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH
>>> 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH
>>> 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH
>>> 50 IRQ_TYPE_EDGE_BOTH>;
>>> ti,ngpio = <144>;
>>> ti,davinci-gpio-unbanked = <0>;
>>> interrupt-controller;
>>> #interrupt-cells = <2>;
>>> };
>>
>> Above, DT bindings models Davinci GPIO IP as monolithic GPIO controller
>> with N gpio pins, but internally separate GPIO chips are created for each
>> banksX&Y register set (32 pins, 2 banked irq -or- 32 direct irqs).
>
> Hm it would be good to get away from that and just have one big gpio
> chip.
>
>> Translation from linear GPIO numbering to the proper internal GPIO chip is done
>> using chip.of_xlate().
>
> Yeah :/ this could be made simpler with a single chip just spanning all
> the banks and the common registers I think.
Okay Linus. Thanks for the direction.
>
> Yours,
> Linus Walleij
>
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^ permalink raw reply
* Re: [PATCH v2 0/9] ARM: DRA7: Add support for DRA718-evm
From: Lokesh Vutla @ 2016-11-07 3:49 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Tero Kristo, Sekhar Nori, Nishanth Menon,
Device Tree Mailing List, Rob Herring, Linux ARM Mailing List
In-Reply-To: <20161021103841.8044-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Hi Tony,
On Friday 21 October 2016 04:08 PM, Lokesh Vutla wrote:
> This series does minor dts cleanup for dra72-evm and adds support for
> DRA718-evm.
Do you have any comments on this series?
Thanks and regards,
Lokesh
>
> Changes since v1:
> - Updated xxx-supply to xxx-in-supply in Documentation.
>
> Lokesh Vutla (7):
> ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869
> ARM: dra72-evm: Fix modelling of regulators
> ARM: dts: dra72: Add separate dtsi for tps65917
> regulator: lp873x: Add support for populating input supply
> ARM: OMAP2+: board-generic: add support for DRA71x family
> ARM: omap2plus_defconfig: Enable REGULATOR_GPIO
> ARM: omap2plus_defconfig: Enable LP873X support
>
> Nishanth Menon (2):
> ARM: DRA7: hwmod: Do not register RTC on DRA71
> ARM: dts: Add support for dra718-evm
>
> .../devicetree/bindings/arm/omap/omap.txt | 6 +
> Documentation/devicetree/bindings/mfd/lp873x.txt | 8 +
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/dra71-evm.dts | 230 ++++++++++++++
> arch/arm/boot/dts/dra72-evm-common.dtsi | 348 +++------------------
> arch/arm/boot/dts/dra72-evm-revc.dts | 21 +-
> arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 134 ++++++++
> arch/arm/boot/dts/dra72-evm.dts | 14 +-
> arch/arm/configs/omap2plus_defconfig | 3 +
> arch/arm/mach-omap2/board-generic.c | 1 +
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 +-
> drivers/regulator/lp873x-regulator.c | 1 +
> 12 files changed, 453 insertions(+), 326 deletions(-)
> create mode 100644 arch/arm/boot/dts/dra71-evm.dts
> create mode 100644 arch/arm/boot/dts/dra72-evm-tps65917.dtsi
>
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^ permalink raw reply
* Re: [PATCH 14/17] ASoC: add simple-graph-card document
From: Kuninori Morimoto @ 2016-11-07 3:34 UTC (permalink / raw)
To: Mark Brown
Cc: Rob Herring, Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi,
Grant Likely, Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <20161104203342.aizjufjokuqrlyhh@sirena.org.uk>
Hi Mark
> This document really needs quite a bit of fleshing out but I'm not sure
> that should be a blocker for the series as a whole especially given that
> English is not your native language - we can build out later. I think
I'm sorry about my English...
> One thing I'm not 100% clear on here is why it has to be a CPU DAI (I'm
> guessing just one of them though the above says ports as an option?)
> that creates the card? Is there a concrete reason for that or is it
> just being defined as good pracctice?
This explain was not understandable, indeed.
This means, CPU side's port on DT need to have compatible,
and CPU side driver need to call asoc_simple_card_try_to_probe_graph_card()
(= [PATCH 12/17]). asoc_simple_card_try_to_probe_graph_card()
will check this compatible, and probe card driver.
I will fixup and repost v3 after of-graph people's review
compatible = "asoc-simple-graph-card";
^ permalink raw reply
* [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs
From: Joel Holdsworth @ 2016-11-07 2:49 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w,
geert-Td1EMuHUCqxL1ZNQvxDV9g, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA, marex-ynQEQJNshbs,
clifford-cPpHkPqGOEfk7+2FdBfRIA
Cc: Joel Holdsworth
In-Reply-To: <1478486962-26794-1-git-send-email-joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
and very regular structure, designed for low-cost, high-volume consumer
and system applications.
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.
The iCE40 family is notable because it is the first FPGA family to have
complete reverse engineered bit-stream documentation for the iCE40LP and
iCE40HX devices. Furthermore, there is now a Free Software Verilog
synthesis tool-chain: the "IceStorm" tool-chain.
This project is the work of Clifford Wolf, who is the maintainer of
Yosys Verilog RTL synthesis framework, and Mathias Lasser, with notable
contributions from "Cotton Seed", the main author of "arachne-pnr"; a
place-and-route tool for iCE40 FPGAs.
Having a Free Software synthesis tool-chain offers interesting
opportunities for embedded devices that are able reconfigure themselves
with open firmware that is generated on the device itself. For example
a mobile device might have an application processor with an iCE40 FPGA
attached, which implements slave devices, or through which the processor
communicates with other devices through the FPGA fabric.
A kernel driver for the iCE40 is useful, because in some cases, the FPGA
may need to be configured before other devices can be accessed.
An example of such a device is the icoBoard; a RaspberryPI HAT which
features an iCE40HX8K with a 1 or 8 MBit SRAM and ports for
Digilent-compatible PMOD modules. A PMOD module may contain a device
with which the kernel communicates, via the FPGA.
Signed-off-by: Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
---
drivers/fpga/Kconfig | 6 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ice40-spi.c | 217 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 224 insertions(+)
create mode 100644 drivers/fpga/ice40-spi.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d614102..5b0f137 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -13,6 +13,12 @@ config FPGA
if FPGA
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on OF && SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
config FPGA_MGR_SOCFPGA
tristate "Altera SOCFPGA FPGA Manager"
depends on ARCH_SOCFPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8d83fc6..adb5811 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c
new file mode 100644
index 0000000..7d7595b
--- /dev/null
+++ b/drivers/fpga/ice40-spi.c
@@ -0,0 +1,217 @@
+/*
+ * FPGA Manager Driver for Lattice iCE40.
+ *
+ * Copyright (c) 2016 Joel Holdsworth
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This driver adds support to the FPGA manager for configuring the SRAM of
+ * Lattice iCE40 FPGAs through slave SPI.
+ */
+
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/spi/spi.h>
+
+#define ICE40_SPI_FPGAMGR_RESET_DELAY 1 /* us (>200ns) */
+#define ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY 1200 /* us */
+
+#define ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
+
+struct ice40_fpga_priv {
+ struct spi_device *dev;
+ struct gpio_desc *reset;
+ struct gpio_desc *cdone;
+};
+
+static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
+ FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ struct spi_message message;
+ struct spi_transfer assert_cs_then_reset_delay = {.cs_change = 1,
+ .delay_usecs = ICE40_SPI_FPGAMGR_RESET_DELAY};
+ struct spi_transfer housekeeping_delay_then_release_cs = {
+ .delay_usecs = ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY};
+ int ret;
+
+ if ((flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+ dev_err(&dev->dev,
+ "Partial reconfiguration is not supported\n");
+ return -ENOTSUPP;
+ }
+
+ /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
+ spi_bus_lock(dev->master);
+
+ gpiod_set_value(priv->reset, 1);
+
+ spi_message_init(&message);
+ spi_message_add_tail(&assert_cs_then_reset_delay, &message);
+ ret = spi_sync_locked(dev, &message);
+
+ /* Come out of reset */
+ gpiod_set_value(priv->reset, 0);
+
+ /* Abort if the chip-select failed */
+ if (ret)
+ goto fail;
+
+ /* Check CDONE is de-asserted i.e. the FPGA is reset */
+ if (gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
+ ret = -EIO;
+ goto fail;
+ }
+
+ /* Wait for the housekeeping to complete, and release SS_B */
+ spi_message_init(&message);
+ spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
+ ret = spi_sync_locked(dev, &message);
+
+fail:
+ spi_bus_unlock(dev->master);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ return spi_write(priv->dev, buf, count);
+}
+
+static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ const u8 padding[ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BYTES] = {0,};
+
+ /* Check CDONE is asserted */
+ if (!gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev,
+ "CDONE was not asserted after firmware transfer\n");
+ return -EIO;
+ }
+
+ /* Send of zero-padding to activate the firmware */
+ return spi_write(dev, padding, sizeof(padding));
+}
+
+static void ice40_fpga_ops_fpga_remove(struct fpga_manager *mgr)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ /* Enter reset */
+ gpiod_set_value(priv->reset, 1);
+}
+
+static const struct fpga_manager_ops ice40_fpga_ops = {
+ .state = ice40_fpga_ops_state,
+ .write_init = ice40_fpga_ops_write_init,
+ .write = ice40_fpga_ops_write,
+ .write_complete = ice40_fpga_ops_write_complete,
+ .fpga_remove = ice40_fpga_ops_fpga_remove
+};
+
+static int ice40_fpga_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct device_node *np = spi->dev.of_node;
+ struct ice40_fpga_priv *priv;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "No Device Tree entry\n");
+ return -EINVAL;
+ }
+
+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = spi;
+
+ /* Check board setup data. */
+ if (spi->max_speed_hz > 25000000) {
+ dev_err(dev, "Speed is too high\n");
+ return -EINVAL;
+ }
+
+ if (spi->max_speed_hz < 1000000) {
+ dev_err(dev, "Speed is too low\n");
+ return -EINVAL;
+ }
+
+ if (spi->mode & SPI_CPHA) {
+ dev_err(dev, "Bad mode\n");
+ return -EINVAL;
+ }
+
+ /* Set up the GPIOs */
+ priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
+ if (IS_ERR(priv->cdone)) {
+ dev_err(dev, "Failed to get CDONE GPIO: %ld\n",
+ PTR_ERR(priv->cdone));
+ return -EINVAL;
+ }
+
+ priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(priv->reset)) {
+ dev_err(dev, "Failed to get CRESET_B GPIO: %ld\n",
+ PTR_ERR(priv->reset));
+ return -EINVAL;
+ }
+
+ /* Register with the FPGA manager */
+ ret = fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
+ &ice40_fpga_ops, priv);
+ if (ret) {
+ dev_err(dev, "Unable to register FPGA manager");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ice40_fpga_remove(struct spi_device *spi)
+{
+ fpga_mgr_unregister(&spi->dev);
+ return 0;
+}
+
+static const struct of_device_id ice40_fpga_of_match[] = {
+ { .compatible = "lattice,ice40-fpga-mgr", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
+
+static struct spi_driver ice40_fpga_driver = {
+ .probe = ice40_fpga_probe,
+ .remove = ice40_fpga_remove,
+ .driver = {
+ .name = "ice40spi",
+ .of_match_table = of_match_ptr(ice40_fpga_of_match),
+ },
+};
+
+module_spi_driver(ice40_fpga_driver);
+
+MODULE_AUTHOR("Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>");
+MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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^ permalink raw reply related
* [PATCH v8 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager
From: Joel Holdsworth @ 2016-11-07 2:49 UTC (permalink / raw)
To: atull, moritz.fischer, geert, robh, devicetree, linux-kernel,
linux-spi, marex, clifford
Cc: Joel Holdsworth
In-Reply-To: <1478486962-26794-1-git-send-email-joel@airwebreathe.org.uk>
This adds documentation of the device tree bindings of the Lattice iCE40
FPGA driver for the FPGA manager framework.
Signed-off-by: Joel Holdsworth <joel@airwebreathe.org.uk>
---
.../bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
new file mode 100644
index 0000000..7e7a78b
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
@@ -0,0 +1,21 @@
+Lattice iCE40 FPGA Manager
+
+Required properties:
+- compatible: Should contain "lattice,ice40-fpga-mgr"
+- reg: SPI chip select
+- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
+- cdone-gpios: GPIO input connected to CDONE pin
+- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
+ that unless the GPIO is held low during startup, the
+ FPGA will enter Master SPI mode and drive SCK with a
+ clock signal potentially jamming other devices on the
+ bus until the firmware is loaded.
+
+Example:
+ ice40: ice40@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v8 1/3] of: Add vendor prefix for Lattice Semiconductor
From: Joel Holdsworth @ 2016-11-07 2:49 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w,
geert-Td1EMuHUCqxL1ZNQvxDV9g, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA, marex-ynQEQJNshbs,
clifford-cPpHkPqGOEfk7+2FdBfRIA
Cc: Joel Holdsworth
Lattice Semiconductor Corporation is a manufacturer of integrated
circuits and IP products, including low-power FPGAs, video connectivity
devices and millimeter wave wireless products.
Website: http://latticesemi.com
Signed-off-by: Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa9..d64a835 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -146,6 +146,7 @@ kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
lantiq Lantiq Semiconductor
+lattice Lattice Semiconductor
lenovo Lenovo Group Ltd.
lg LG Corporation
linux Linux-specific binding
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 1/2] ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY
From: Shawn Guo @ 2016-11-07 2:06 UTC (permalink / raw)
To: Peter Chen
Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <VI1PR04MB14556348390F18AF8D5A261D8BA70-mr6QIVyDiCG7FDLoODJFCc9NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
On Mon, Nov 07, 2016 at 01:32:29AM +0000, Peter Chen wrote:
>
> >On Mon, Oct 31, 2016 at 10:58:28AM +0800, Peter Chen wrote:
> >> We need to change trimming value (as a percentage) of the 17.78mA TX
> >> reference current for better signal quality. With this change, we can
> >> patch the eye-diagram test on this board.
> >
> >s/patch/pass? I just want to confirm this is a typo, and can fix it up when applying.
> >
>
> Thanks, Shawn. It is a typo. Help me to change both of patches please.
Applied both, thanks.
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^ permalink raw reply
* Re: [PATCH v5 02/23] of: device: Export of_device_{get_modalias, uvent_modalias} to modules
From: Chen-Yu Tsai @ 2016-11-07 1:56 UTC (permalink / raw)
To: Peter Chen
Cc: Stephen Boyd, Greg KH, Arnd Bergmann, Neil Armstrong,
linux-arm-msm, linux-usb, linux-kernel, Bjorn Andersson,
Chen-Yu Tsai, Peter Chen, linux-arm-kernel, Andy Gross,
devicetree, Felipe Balbi
In-Reply-To: <20161107012920.GA10559@b29397-desktop>
On Mon, Nov 7, 2016 at 9:29 AM, Peter Chen <hzpeterchen@gmail.com> wrote:
> On Fri, Nov 04, 2016 at 01:51:34PM -0700, Stephen Boyd wrote:
>> Quoting Peter Chen (2016-10-24 18:16:32)
>> > On Mon, Oct 24, 2016 at 12:48:24PM -0700, Stephen Boyd wrote:
>> > > Quoting Chen-Yu Tsai (2016-10-24 05:19:05)
>> > > > Hi,
>> > > >
>> > > > On Tue, Oct 18, 2016 at 9:56 AM, Stephen Boyd <stephen.boyd@linaro.org> wrote:
>> > > > > The ULPI bus can be built as a module, and it will soon be
>> > > > > calling these functions when it supports probing devices from DT.
>> > > > > Export them so they can be used by the ULPI module.
>> > > > >
>> > > > > Acked-by: Rob Herring <robh@kernel.org>
>> > > > > Cc: <devicetree@vger.kernel.org>
>> > > > > Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
>> > > > > ---
>> > > > > drivers/of/device.c | 2 ++
>> > > > > 1 file changed, 2 insertions(+)
>> > > > >
>> > > > > diff --git a/drivers/of/device.c b/drivers/of/device.c
>> > > > > index 8a22a253a830..6719ab35b62e 100644
>> > > > > --- a/drivers/of/device.c
>> > > > > +++ b/drivers/of/device.c
>> > > > > @@ -225,6 +225,7 @@ ssize_t of_device_get_modalias(struct device *dev, char *str, ssize_t len)
>> > > > >
>> > > > > return tsize;
>> > > > > }
>> > > > > +EXPORT_SYMBOL_GPL(of_device_get_modalias);
>> > > > >
>> > > > > int of_device_request_module(struct device *dev)
>> > > > > {
>> > > > > @@ -290,6 +291,7 @@ void of_device_uevent(struct device *dev, struct kobj_uevent_env *env)
>> > > > > }
>> > > > > mutex_unlock(&of_mutex);
>> > > > > }
>> > > > > +EXPORT_SYMBOL_GPL(of_device_uevent_modalias);
>> > > >
>> > > > This is trailing the wrong function.
>> > > >
>> > >
>> > > Good catch. Must have been some bad rebase.
>> > >
>> > > Peter, can you fix it while applying or should I resend this patch?
>> > >
>> >
>> > But, this is device tree patch. I can only get chipidea part and other
>> > USB patches if Greg agrees.
>> >
>>
>> Were you expecting Rob to take the drivers/of/* patches? Sorry I thought
>> Rob acked them so they could go through usb with the other changes.
>
> I am just worried about possible merge error when linus pulls both OF
> and USB tree. Greg, is it ok the OF patches through USB tree with OF
> maintainer's ack?
May I suggest putting the OF patches on an immutable branch so other
subsystems can pull them in without pulling in the USB patches? At
least I want to use them in the I2C subsystem, and in the sunxi-rsb
driver.
Regards
ChenYu
^ permalink raw reply
* Re: [PATCH v2 06/14] ASoC: sun4i-codec: Add support for A31 playback through headphone output
From: Chen-Yu Tsai @ 2016-11-07 1:51 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Liam Girdwood, Mark Brown, Jaroslav Kysela,
Takashi Iwai, Rob Herring, Mark Rutland, Linux-ALSA,
linux-arm-kernel, linux-kernel, devicetree, linux-sunxi
In-Reply-To: <20161106185715.tlvcakzqay2lamd5@lukather>
On Mon, Nov 7, 2016 at 2:57 AM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> On Fri, Nov 04, 2016 at 09:08:11AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Nov 4, 2016 at 1:36 AM, Maxime Ripard
>> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>> > Hi,
>> >
>> > On Thu, Nov 03, 2016 at 03:55:48PM +0800, Chen-Yu Tsai wrote:
>> >> +/* headphone controls */
>> >> +static const char * const sun6i_codec_hp_src_enum_text[] = {
>> >> + "DAC", "Mixer",
>> >> +};
>> >> +
>> >> +static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
>> >> + SUN6I_CODEC_OM_DACA_CTRL,
>> >> + SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
>> >> + SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
>> >> + sun6i_codec_hp_src_enum_text);
>> >> +
>> >> +static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
>> >> + SOC_DAPM_ENUM("Headphone Source Playback Route",
>> >> + sun6i_codec_hp_src_enum),
>> >> +};
>> >
>> > What is that route exactly? A muxer?
>>
>> Yup. The following is part of the widgets list later in the code:
>>
>> + /* Headphone output path */
>> + SND_SOC_DAPM_MUX("Headphone Source Playback Route",
>> + SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
>
> Oh, right.
>
> You can add my Acked-by on this one and the other patches too.
Thanks. Mark already merged all the driver patches though.
ChenYu
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^ permalink raw reply
* RE: [PATCH 1/2] ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY
From: Peter Chen @ 2016-11-07 1:32 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
pawel.moll@arm.com, robh+dt@kernel.org, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20161105083145.GF5597@dragon>
>On Mon, Oct 31, 2016 at 10:58:28AM +0800, Peter Chen wrote:
>> We need to change trimming value (as a percentage) of the 17.78mA TX
>> reference current for better signal quality. With this change, we can
>> patch the eye-diagram test on this board.
>
>s/patch/pass? I just want to confirm this is a typo, and can fix it up when applying.
>
Thanks, Shawn. It is a typo. Help me to change both of patches please.
Peter
^ permalink raw reply
* Re: [PATCH v5 02/23] of: device: Export of_device_{get_modalias, uvent_modalias} to modules
From: Peter Chen @ 2016-11-07 1:29 UTC (permalink / raw)
To: Stephen Boyd, Greg KH
Cc: robh-DgEjT+Ai2ygdnm+yROfE0A, Chen-Yu Tsai, Felipe Balbi,
Arnd Bergmann, Neil Armstrong,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, linux-usb, linux-kernel,
Bjorn Andersson, devicetree, Peter Chen, Andy Gross,
linux-arm-kernel
In-Reply-To: <147829269430.21688.2345895151880009021@sboyd-linaro>
On Fri, Nov 04, 2016 at 01:51:34PM -0700, Stephen Boyd wrote:
> Quoting Peter Chen (2016-10-24 18:16:32)
> > On Mon, Oct 24, 2016 at 12:48:24PM -0700, Stephen Boyd wrote:
> > > Quoting Chen-Yu Tsai (2016-10-24 05:19:05)
> > > > Hi,
> > > >
> > > > On Tue, Oct 18, 2016 at 9:56 AM, Stephen Boyd <stephen.boyd-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > > > > The ULPI bus can be built as a module, and it will soon be
> > > > > calling these functions when it supports probing devices from DT.
> > > > > Export them so they can be used by the ULPI module.
> > > > >
> > > > > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > > > > Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> > > > > Signed-off-by: Stephen Boyd <stephen.boyd-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > > > > ---
> > > > > drivers/of/device.c | 2 ++
> > > > > 1 file changed, 2 insertions(+)
> > > > >
> > > > > diff --git a/drivers/of/device.c b/drivers/of/device.c
> > > > > index 8a22a253a830..6719ab35b62e 100644
> > > > > --- a/drivers/of/device.c
> > > > > +++ b/drivers/of/device.c
> > > > > @@ -225,6 +225,7 @@ ssize_t of_device_get_modalias(struct device *dev, char *str, ssize_t len)
> > > > >
> > > > > return tsize;
> > > > > }
> > > > > +EXPORT_SYMBOL_GPL(of_device_get_modalias);
> > > > >
> > > > > int of_device_request_module(struct device *dev)
> > > > > {
> > > > > @@ -290,6 +291,7 @@ void of_device_uevent(struct device *dev, struct kobj_uevent_env *env)
> > > > > }
> > > > > mutex_unlock(&of_mutex);
> > > > > }
> > > > > +EXPORT_SYMBOL_GPL(of_device_uevent_modalias);
> > > >
> > > > This is trailing the wrong function.
> > > >
> > >
> > > Good catch. Must have been some bad rebase.
> > >
> > > Peter, can you fix it while applying or should I resend this patch?
> > >
> >
> > But, this is device tree patch. I can only get chipidea part and other
> > USB patches if Greg agrees.
> >
>
> Were you expecting Rob to take the drivers/of/* patches? Sorry I thought
> Rob acked them so they could go through usb with the other changes.
I am just worried about possible merge error when linus pulls both OF
and USB tree. Greg, is it ok the OF patches through USB tree with OF
maintainer's ack?
--
Best Regards,
Peter Chen
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^ permalink raw reply
* Re: [PATCH v7 3/3] fpga: Add support for Lattice iCE40 FPGAs
From: Joel Holdsworth @ 2016-11-07 0:46 UTC (permalink / raw)
To: atull
Cc: moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w,
geert-Td1EMuHUCqxL1ZNQvxDV9g, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <alpine.DEB.2.10.1611040945100.2940@atull-VirtualBox>
>> +#include <linux/fpga/fpga-mgr.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/spi/spi.h>
>
> Hi Joel,
>
> The build breaks without this:
>
> #include <linux/module.h>
>
> Alan
>
Go it! - thanks!
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^ permalink raw reply
* Re: [PATCH 10/13] ARM: dts: exynos: replace to "max-frequecy" instead of "clock-freq-min-max"
From: Jaehoon Chung @ 2016-11-07 0:38 UTC (permalink / raw)
To: Krzysztof Kozlowski, Heiko Stuebner
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc, linux-rockchip, ulf.hansson, robh+dt,
shawn.lin
In-Reply-To: <20161104150447.GA4829@kozik-lap>
On 11/05/2016 12:04 AM, Krzysztof Kozlowski wrote:
> On Fri, Nov 04, 2016 at 12:19:49PM +0100, Heiko Stuebner wrote:
>> Hi Jaehoon,
>>
>> Am Freitag, 4. November 2016, 19:21:30 CET schrieb Jaehoon Chung:
>>> On 11/04/2016 03:41 AM, Krzysztof Kozlowski wrote:
>>>> On Thu, Nov 03, 2016 at 03:21:32PM +0900, Jaehoon Chung wrote:
>>>>> In drivers/mmc/core/host.c, there is "max-frequency" property.
>>>>> It should be same behavior. So Use the "max-frequency" instead of
>>>>> "clock-freq-min-max".
>>>>>
>>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>>> ---
>>>>>
>>>>> arch/arm/boot/dts/exynos3250-artik5-eval.dts | 2 +-
>>>>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +-
>>>>> arch/arm/boot/dts/exynos3250-monk.dts | 2 +-
>>>>> arch/arm/boot/dts/exynos3250-rinato.dts | 2 +-
>>>>> 4 files changed, 4 insertions(+), 4 deletions(-)
>>>>
>>>> This looks totally independent to rest of patches so it can be applied
>>>> separately without any functional impact (except lack of minimum
>>>> frequency). Is that correct?
>>>
>>> You're right. I will split the patches. And will resend.
>>> Thanks!
>>
>> I think what Krzysztof was asking was just if he can simply pick up this patch
>> alone, as it does not require any of the previous changes.
>>
>> Same is true for the Rockchip patches I guess, so we could just take them
>> individually into samsung/rockchip dts branches.
>
> Yes, I wanted to get exactly this information. I couldn't find it in
> cover letter.
In drivers/mmc/core/host.c, there already is "max-frequency" property.
It's same functionality with "clock-freq-min-max".
Minimum clock value can be fixed to 100K. because MMC core will check clock value from 400K to 100K.
But max-frequency can be difference.
If we can use "max-frequency" property, we don't need to use "clock-freq-min-max" property anymore.
I will resend the deprecated property instead of removing "clock-freq-min-max".
If you want to pick this, it's possible to pick. Then i will resend the patches without dt patches.
Best Regards,
Jaehoon Chung
>
> Best regards,
> Krzysztof
> --
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply
* Re: [PATCH v8] mtd: nand: add tango NAND flash controller support
From: Boris Brezillon @ 2016-11-06 22:58 UTC (permalink / raw)
To: Marc Gonzalez
Cc: linux-mtd, Richard Weinberger, DT, Rob Herring, Mark Rutland,
Mason, Sebastian Frias
In-Reply-To: <580F8407.5070706-y1yR0Z3OICC7zZZRDBGcUA@public.gmane.org>
On Tue, 25 Oct 2016 18:10:47 +0200
Marc Gonzalez <marc_gonzalez-y1yR0Z3OICC7zZZRDBGcUA@public.gmane.org> wrote:
> This driver supports the NAND Flash controller embedded in recent
> Tango chips, such as SMP8758 and SMP8759.
>
> Signed-off-by: Marc Gonzalez <marc_gonzalez-y1yR0Z3OICC7zZZRDBGcUA@public.gmane.org>
Applied after fixing a few coding style issues to make checkpatch happy.
Thanks,
Boris
> ---
> drivers/mtd/nand/Kconfig | 7 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/tango_nand.c | 654 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 662 insertions(+)
> create mode 100644 drivers/mtd/nand/tango_nand.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 7b7a887b4709..84ce3fe6e5e2 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -205,6 +205,13 @@ config MTD_NAND_S3C2410_CLKSTOP
> when the is NAND chip selected or released, but will save
> approximately 5mA of power when there is nothing happening.
>
> +config MTD_NAND_TANGO
> + tristate "NAND Flash support for Tango chips"
> + depends on ARCH_TANGO || COMPILE_TEST
> + depends on HAS_DMA
> + help
> + Enables the NAND Flash controller on Tango chips.
> +
> config MTD_NAND_DISKONCHIP
> tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation)"
> depends on HAS_IOMEM
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index cafde6f3d957..4904ad3614fb 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
> obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
> obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
> obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
> +obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o
> obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
> obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
> obj-$(CONFIG_MTD_NAND_DOCG4) += docg4.o
> diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
> new file mode 100644
> index 000000000000..74e39a92771c
> --- /dev/null
> +++ b/drivers/mtd/nand/tango_nand.c
> @@ -0,0 +1,654 @@
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/platform_device.h>
> +
> +/* Offsets relative to chip->base */
> +#define PBUS_CMD 0
> +#define PBUS_ADDR 4
> +#define PBUS_DATA 8
> +
> +/* Offsets relative to reg_base */
> +#define NFC_STATUS 0x00
> +#define NFC_FLASH_CMD 0x04
> +#define NFC_DEVICE_CFG 0x08
> +#define NFC_TIMING1 0x0c
> +#define NFC_TIMING2 0x10
> +#define NFC_XFER_CFG 0x14
> +#define NFC_PKT_0_CFG 0x18
> +#define NFC_PKT_N_CFG 0x1c
> +#define NFC_BB_CFG 0x20
> +#define NFC_ADDR_PAGE 0x24
> +#define NFC_ADDR_OFFSET 0x28
> +#define NFC_XFER_STATUS 0x2c
> +
> +/* NFC_STATUS values */
> +#define CMD_READY BIT(31)
> +
> +/* NFC_FLASH_CMD values */
> +#define NFC_READ 1
> +#define NFC_WRITE 2
> +
> +/* NFC_XFER_STATUS values */
> +#define PAGE_IS_EMPTY BIT(16)
> +
> +/* Offsets relative to mem_base */
> +#define METADATA 0x000
> +#define ERROR_REPORT 0x1c0
> +
> +/*
> + * Error reports are split in two bytes:
> + * byte 0 for the first packet in the page (PKT_0)
> + * byte 1 for other packets in the page (PKT_N, for N > 0)
> + * ERR_COUNT_PKT_N is the max error count over all but the first packet.
> + */
> +#define DECODE_OK_PKT_0(v) (v & BIT(7))
> +#define DECODE_OK_PKT_N(v) (v & BIT(15))
> +#define ERR_COUNT_PKT_0(v) ((v >> 0) & 0x3f)
> +#define ERR_COUNT_PKT_N(v) ((v >> 8) & 0x3f)
> +
> +/* Offsets relative to pbus_base */
> +#define PBUS_CS_CTRL 0x83c
> +#define PBUS_PAD_MODE 0x8f0
> +
> +/* PBUS_CS_CTRL values */
> +#define PBUS_IORDY BIT(31)
> +
> +/*
> + * PBUS_PAD_MODE values
> + * In raw mode, the driver communicates directly with the NAND chips.
> + * In NFC mode, the NAND Flash controller manages the communication.
> + * We use NFC mode for read and write; raw mode for everything else.
> + */
> +#define MODE_RAW 0
> +#define MODE_NFC BIT(31)
> +
> +#define METADATA_SIZE 4
> +#define BBM_SIZE 6
> +#define FIELD_ORDER 15
> +
> +#define MAX_CS 4
> +
> +struct tango_nfc {
> + struct nand_hw_control hw;
> + void __iomem *reg_base;
> + void __iomem *mem_base;
> + void __iomem *pbus_base;
> + struct tango_chip *chips[MAX_CS];
> + struct dma_chan *chan;
> + int freq_kHz;
> +};
> +
> +#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw)
> +
> +struct tango_chip {
> + struct nand_chip nand_chip;
> + void __iomem *base;
> + u32 timing1;
> + u32 timing2;
> + u32 xfer_cfg;
> + u32 pkt_0_cfg;
> + u32 pkt_n_cfg;
> + u32 bb_cfg;
> +};
> +
> +#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip)
> +
> +#define XFER_CFG(cs, page_count, steps, metadata_size) \
> + ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size))
> +
> +#define PKT_CFG(size, strength) ((size) << 16 | (strength))
> +
> +#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size))
> +
> +#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
> +
> +static void tango_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
> +{
> + struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
> +
> + if (ctrl & NAND_CLE)
> + writeb_relaxed(dat, tchip->base + PBUS_CMD);
> +
> + if (ctrl & NAND_ALE)
> + writeb_relaxed(dat, tchip->base + PBUS_ADDR);
> +}
> +
> +static int tango_dev_ready(struct mtd_info *mtd)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct tango_nfc *nfc = to_tango_nfc(chip->controller);
> +
> + return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY;
> +}
> +
> +static uint8_t tango_read_byte(struct mtd_info *mtd)
> +{
> + struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
> +
> + return readb_relaxed(tchip->base + PBUS_DATA);
> +}
> +
> +static void tango_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
> +
> + ioread8_rep(tchip->base + PBUS_DATA, buf, len);
> +}
> +
> +static void tango_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
> +{
> + struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
> +
> + iowrite8_rep(tchip->base + PBUS_DATA, buf, len);
> +}
> +
> +static void tango_select_chip(struct mtd_info *mtd, int idx)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct tango_nfc *nfc = to_tango_nfc(chip->controller);
> + struct tango_chip *tchip = to_tango_chip(chip);
> +
> + if (idx < 0)
> + return; /* No "chip unselect" function */
> +
> + writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
> + writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
> + writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
> + writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
> + writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
> + writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
> +}
> +
> +/*
> + * The controller does not check for bitflips in erased pages,
> + * therefore software must check instead.
> + */
> +static int check_erased_page(struct nand_chip *chip, u8 *buf)
> +{
> + u8 *meta = chip->oob_poi + BBM_SIZE;
> + u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
> + const int ecc_size = chip->ecc.bytes;
> + const int pkt_size = chip->ecc.size;
> + int i, res, meta_len, bitflips = 0;
> +
> + for (i = 0; i < chip->ecc.steps; ++i) {
> + meta_len = i ? 0 : METADATA_SIZE;
> + res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
> + meta, meta_len, chip->ecc.strength);
> + if (res < 0)
> + chip->mtd.ecc_stats.failed++;
> +
> + bitflips = max(res, bitflips);
> + buf += pkt_size;
> + ecc += ecc_size;
> + }
> +
> + return bitflips;
> +}
> +
> +static int decode_error_report(struct tango_nfc *nfc)
> +{
> + u32 status, res;
> +
> + status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
> + if (status & PAGE_IS_EMPTY)
> + return 0;
> +
> + res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
> +
> + if (DECODE_OK_PKT_0(res) && DECODE_OK_PKT_N(res))
> + return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
> +
> + return -EBADMSG;
> +}
> +
> +static void tango_dma_callback(void *arg)
> +{
> + complete(arg);
> +}
> +
> +static int do_dma(struct tango_nfc *nfc, int dir, int cmd,
> + const void *buf, int len, int page)
> +{
> + void __iomem *addr = nfc->reg_base + NFC_STATUS;
> + struct dma_chan *chan = nfc->chan;
> + struct dma_async_tx_descriptor *desc;
> + struct scatterlist sg;
> + struct completion tx_done;
> + int err = -EIO;
> + u32 res, val;
> +
> + sg_init_one(&sg, buf, len);
> + if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1)
> + return -EIO;
> +
> + desc = dmaengine_prep_slave_sg(chan, &sg, 1, dir, DMA_PREP_INTERRUPT);
> + if (!desc)
> + goto dma_unmap;
> +
> + desc->callback = tango_dma_callback;
> + desc->callback_param = &tx_done;
> + init_completion(&tx_done);
> +
> + writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE);
> +
> + writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE);
> + writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET);
> + writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD);
> +
> + dmaengine_submit(desc);
> + dma_async_issue_pending(chan);
> +
> + res = wait_for_completion_timeout(&tx_done, HZ);
> + if (res > 0)
> + err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000);
> +
> + writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
> +
> +dma_unmap:
> + dma_unmap_sg(chan->device->dev, &sg, 1, dir);
> +
> + return err;
> +}
> +
> +static int tango_read_page(struct mtd_info *mtd, struct nand_chip *chip,
> + uint8_t *buf, int oob_required, int page)
> +{
> + struct tango_nfc *nfc = to_tango_nfc(chip->controller);
> + int err, res, len = mtd->writesize;
> +
> + if (oob_required)
> + chip->ecc.read_oob(mtd, chip, page);
> +
> + err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page);
> + if (err)
> + return err;
> +
> + res = decode_error_report(nfc);
> + if (res < 0) {
> + chip->ecc.read_oob_raw(mtd, chip, page);
> + res = check_erased_page(chip, buf);
> + }
> +
> + return res;
> +}
> +
> +static int tango_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> + const uint8_t *buf, int oob_required, int page)
> +{
> + struct tango_nfc *nfc = to_tango_nfc(chip->controller);
> + int err, len = mtd->writesize;
> +
> + /* Calling tango_write_oob() would send PAGEPROG twice */
> + if (oob_required)
> + return -ENOTSUPP;
> +
> + writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
> + err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
> +{
> + *pos += len;
> +
> + if (*buf == NULL) {
> + /* skip over "len" bytes */
> + chip->cmdfunc(&chip->mtd, NAND_CMD_RNDOUT, *pos, -1);
> + } else {
> + tango_read_buf(&chip->mtd, *buf, len);
> + *buf += len;
> + }
> +}
> +
> +static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
> +{
> + *pos += len;
> +
> + if (*buf == NULL) {
> + /* skip over "len" bytes */
> + chip->cmdfunc(&chip->mtd, NAND_CMD_SEQIN, *pos, -1);
> + } else {
> + tango_write_buf(&chip->mtd, *buf, len);
> + *buf += len;
> + }
> +}
> +
> +/*
> + * Physical page layout (not drawn to scale)
> + *
> + * NB: Bad Block Marker area splits PKT_N in two (N1, N2).
> + *
> + * +---+-----------------+-------+-----+-----------+-----+----+-------+
> + * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N |
> + * +---+-----------------+-------+-----+-----------+-----+----+-------+
> + *
> + * Logical page layout:
> + *
> + * +-----+---+-------+-----+-------+
> + * oob = | BBM | M | ECC_0 | ... | ECC_N |
> + * +-----+---+-------+-----+-------+
> + *
> + * +-----------------+-----+-----------------+
> + * buf = | PKT_0 | ... | PKT_N |
> + * +-----------------+-----+-----------------+
> + */
> +static int raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
> +{
> + u8 *oob_orig = oob;
> + const int page_size = chip->mtd.writesize;
> + const int ecc_size = chip->ecc.bytes;
> + const int pkt_size = chip->ecc.size;
> + int pos = 0; /* position within physical page */
> + int rem = page_size; /* bytes remaining until BBM area */
> +
> + if (oob != NULL)
> + oob += BBM_SIZE;
> +
> + aux_read(chip, &oob, METADATA_SIZE, &pos);
> +
> + while (rem > pkt_size) {
> + aux_read(chip, &buf, pkt_size, &pos);
> + aux_read(chip, &oob, ecc_size, &pos);
> + rem = page_size - pos;
> + }
> +
> + aux_read(chip, &buf, rem, &pos);
> + aux_read(chip, &oob_orig, BBM_SIZE, &pos);
> + aux_read(chip, &buf, pkt_size - rem, &pos);
> + aux_read(chip, &oob, ecc_size, &pos);
> +
> + return 0;
> +}
> +
> +static int raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
> +{
> + const u8 *oob_orig = oob;
> + const int page_size = chip->mtd.writesize;
> + const int ecc_size = chip->ecc.bytes;
> + const int pkt_size = chip->ecc.size;
> + int pos = 0; /* position within physical page */
> + int rem = page_size; /* bytes remaining until BBM area */
> +
> + if (oob != NULL)
> + oob += BBM_SIZE;
> +
> + aux_write(chip, &oob, METADATA_SIZE, &pos);
> +
> + while (rem > pkt_size) {
> + aux_write(chip, &buf, pkt_size, &pos);
> + aux_write(chip, &oob, ecc_size, &pos);
> + rem = page_size - pos;
> + }
> +
> + aux_write(chip, &buf, rem, &pos);
> + aux_write(chip, &oob_orig, BBM_SIZE, &pos);
> + aux_write(chip, &buf, pkt_size - rem, &pos);
> + aux_write(chip, &oob, ecc_size, &pos);
> +
> + return 0;
> +}
> +
> +static int tango_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
> + uint8_t *buf, int oob_required, int page)
> +{
> + return raw_read(chip, buf, chip->oob_poi);
> +}
> +
> +static int tango_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
> + const uint8_t *buf, int oob_required, int page)
> +{
> + return raw_write(chip, buf, chip->oob_poi);
> +}
> +
> +static int tango_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
> +{
> + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
> + return raw_read(chip, NULL, chip->oob_poi);
> +}
> +
> +static int tango_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
> +{
> + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page);
> + raw_write(chip, NULL, chip->oob_poi);
> + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> + chip->waitfunc(mtd, chip);
> + return 0;
> +}
> +
> +static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
> +{
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> +
> + if (idx >= ecc->steps)
> + return -ERANGE;
> +
> + res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx;
> + res->length = ecc->bytes;
> +
> + return 0;
> +}
> +
> +static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
> +{
> + return -ERANGE; /* no free space in spare area */
> +}
> +
> +static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = {
> + .ecc = oob_ecc,
> + .free = oob_free,
> +};
> +
> +static u32 to_ticks(int kHz, int ps)
> +{
> + return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
> +}
> +
> +static int tango_set_timings(struct mtd_info *mtd,
> + const struct nand_data_interface *conf, bool check_only)
> +{
> + const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
> + struct nand_chip *chip = mtd_to_nand(mtd);
> + struct tango_nfc *nfc = to_tango_nfc(chip->controller);
> + struct tango_chip *tchip = to_tango_chip(chip);
> + u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr;
> + int kHz = nfc->freq_kHz;
> +
> + if (IS_ERR(sdr))
> + return PTR_ERR(sdr);
> +
> + if (check_only)
> + return 0;
> +
> + Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
> + Textw = to_ticks(kHz, sdr->tWB_max);
> + Twc = to_ticks(kHz, sdr->tWC_min);
> + Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min);
> +
> + Tacc = to_ticks(kHz, sdr->tREA_max);
> + Thold = to_ticks(kHz, sdr->tREH_min);
> + Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min);
> + Textr = to_ticks(kHz, sdr->tRHZ_max);
> +
> + tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
> + tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
> +
> + return 0;
> +}
> +
> +static int chip_init(struct device *dev, struct device_node *np)
> +{
> + u32 cs;
> + int err, res;
> + struct mtd_info *mtd;
> + struct nand_chip *chip;
> + struct tango_chip *tchip;
> + struct nand_ecc_ctrl *ecc;
> + struct tango_nfc *nfc = dev_get_drvdata(dev);
> +
> + tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
> + if (!tchip)
> + return -ENOMEM;
> +
> + res = of_property_count_u32_elems(np, "reg");
> + if (res < 0)
> + return res;
> +
> + if (res != 1)
> + return -ENOTSUPP; /* Multi-CS chips are not supported */
> +
> + err = of_property_read_u32_index(np, "reg", 0, &cs);
> + if (err)
> + return err;
> +
> + if (cs >= MAX_CS)
> + return -EINVAL;
> +
> + chip = &tchip->nand_chip;
> + ecc = &chip->ecc;
> + mtd = &chip->mtd;
> +
> + chip->read_byte = tango_read_byte;
> + chip->write_buf = tango_write_buf;
> + chip->read_buf = tango_read_buf;
> + chip->select_chip = tango_select_chip;
> + chip->cmd_ctrl = tango_cmd_ctrl;
> + chip->dev_ready = tango_dev_ready;
> + chip->setup_data_interface = tango_set_timings;
> + chip->options = NAND_USE_BOUNCE_BUFFER
> + | NAND_NO_SUBPAGE_WRITE
> + | NAND_WAIT_TCCS;
> + chip->controller = &nfc->hw;
> + tchip->base = nfc->pbus_base + (cs * 256);
> +
> + nand_set_flash_node(chip, np);
> + mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
> + mtd->dev.parent = dev;
> +
> + err = nand_scan_ident(mtd, 1, NULL);
> + if (err)
> + return err;
> +
> + ecc->mode = NAND_ECC_HW;
> + ecc->algo = NAND_ECC_BCH;
> + ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
> +
> + ecc->read_page_raw = tango_read_page_raw;
> + ecc->write_page_raw = tango_write_page_raw;
> + ecc->read_page = tango_read_page;
> + ecc->write_page = tango_write_page;
> + ecc->read_oob = tango_read_oob;
> + ecc->write_oob = tango_write_oob;
> +
> + err = nand_scan_tail(mtd);
> + if (err)
> + return err;
> +
> + tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
> + tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
> + tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
> + tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
> +
> + err = mtd_device_register(mtd, NULL, 0);
> + if (err)
> + return err;
> +
> + nfc->chips[cs] = tchip;
> +
> + return 0;
> +}
> +
> +static int tango_nand_remove(struct platform_device *pdev)
> +{
> + int cs;
> + struct tango_nfc *nfc = platform_get_drvdata(pdev);
> +
> + dma_release_channel(nfc->chan);
> +
> + for (cs = 0; cs < MAX_CS; ++cs) {
> + if (nfc->chips[cs] != NULL)
> + nand_release(&nfc->chips[cs]->nand_chip.mtd);
> + }
> +
> + return 0;
> +}
> +
> +static int tango_nand_probe(struct platform_device *pdev)
> +{
> + int err;
> + struct clk *clk;
> + struct resource *res;
> + struct tango_nfc *nfc;
> + struct device_node *np;
> +
> + nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
> + if (!nfc)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + nfc->reg_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(nfc->reg_base))
> + return PTR_ERR(nfc->reg_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + nfc->mem_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(nfc->mem_base))
> + return PTR_ERR(nfc->mem_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(nfc->pbus_base))
> + return PTR_ERR(nfc->pbus_base);
> +
> + clk = clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + nfc->chan = dma_request_chan(&pdev->dev, "nfc_sbox");
> + if (IS_ERR(nfc->chan))
> + return PTR_ERR(nfc->chan);
> +
> + platform_set_drvdata(pdev, nfc);
> + nand_hw_control_init(&nfc->hw);
> + nfc->freq_kHz = clk_get_rate(clk) / 1000;
> +
> + for_each_child_of_node(pdev->dev.of_node, np) {
> + err = chip_init(&pdev->dev, np);
> + if (err) {
> + tango_nand_remove(pdev);
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id tango_nand_ids[] = {
> + { .compatible = "sigma,smp8758-nand" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver tango_nand_driver = {
> + .probe = tango_nand_probe,
> + .remove = tango_nand_remove,
> + .driver = {
> + .name = "tango-nand",
> + .of_match_table = tango_nand_ids,
> + },
> +};
> +
> +module_platform_driver(tango_nand_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Sigma Designs");
> +MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");
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