* Re: [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]
From: Linus Walleij @ 2016-11-07 9:34 UTC (permalink / raw)
To: Joel Stanley
Cc: Mark Rutland, devicetree@vger.kernel.org, Andrew Jeffery,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
Rob Herring, Lee Jones, linux-arm-kernel@lists.infradead.org
In-Reply-To: <CACPK8Xcbv5VjE9deETV6zC4cPSfeBSgP96QYqV_ebAgtB9Jwtw@mail.gmail.com>
On Thu, Nov 3, 2016 at 11:59 PM, Joel Stanley <joel@jms.id.au> wrote:
> In the future I think we should send fixes separately from the rest of
> the series, so it's clear to Linus where we expect patches to end up.
>
> Perhaps Linus can share his preference with us?
Just make it clear to me where the patch is headed, if it is
a fix or a new feature.
Also mixing stuff in big series is of course problematic because
all the CC:in on MFD patches and whatnot that I don't apply
makes the picture blurry, but sometimes it is anyways needed
for context so it is a soft requirement.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]
From: Linus Walleij @ 2016-11-07 9:32 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
Rob Herring, Joel Stanley, Lee Jones,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1478097481-14895-2-git-send-email-andrew@aj.id.au>
On Wed, Nov 2, 2016 at 3:37 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
> will succeed but changes to the GPIO's value will not be accepted by the
> hardware. This is because the pinmux driver has misconfigured the SCU by
> writing 1 to the reserved bit.
>
> The description of SCU90[6] from the datasheet is 'Reserved, must keep
> at value ”0”'. The fix is to switch pinmux from the bit-flipping macro
> to explicitly configuring the .enable and .disable values to zero.
>
> The patch has been tested on an AST2500 EVB.
>
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Reported-by: Uma Yadlapati <yadlapat@us.ibm.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>
> This patch should be applied for 4.9.
Patch applied for fixes, adding Joel's review tag.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Geert Uytterhoeven @ 2016-11-07 9:30 UTC (permalink / raw)
To: Stephen Boyd
Cc: devicetree@vger.kernel.org, Arnd Bergmann, Kevin Hilman,
Michael Turquette, Magnus Damm, linux-kernel@vger.kernel.org,
Linux-Renesas, Simon Horman, Philipp Zabel, Olof Johansson,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20161104194914.GB16026@codeaurora.org>
Hi Stephen,
On Fri, Nov 4, 2016 at 8:49 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 11/02, Geert Uytterhoeven wrote:
>> On Tue, Nov 1, 2016 at 12:25 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >
>> > Would the pull requests for clk also have dts changes at the base
>> > of the tree? Perhaps clk side can just ack the clk patches and
>>
>> Yes they would: this is moving functionality from platform code to DT.
>> Without the DT updates, it will break bisection (except for R-Car Gen2,
>> where we have fallback code to handle old DTBs).
>>
>> > then have it all routed through arm-soc? The only worry I have is
>> > if we need to make some sort of change in clk side that conflicts
>> > with these changes. I don't usually like taking dts changes
>> > through clk tree, so I'd like to avoid that if possible.
>>
>> Everything could go through arm-soc only with your Acked-by.
>> However, there are new clock drivers pending on this series.
>> Either they have to go through arm-soc, too, or this series would
>> be pulled into the clk tree with these new clock drivers.
>>
>> > Part E could happen anytime after everything else happens, so
>> > that doesn't seem like a concern.
>>
>> Part E can indeed by postponed.
>> But if parts A-D are applied together, there's no reason to postpone part E.
>>
>> > Part C could also be made to
>> > only call into the new reset drivers if the reset dts nodes are
>> > present? If that's done then we could merge clk patches anytime
>> > and remove the dead code and the node search at some later time
>> > when everything has settled?
>>
>> That would require adding more backwards compatibility code for
>> old DTBs, even for platform where we're not interested in maintaining
>> that. In addition, Part C depends on the header file for the reset driver
>> to compile the clock driver, even if you would add some DT detection,
>> and on the reset driver to link. So I'm afraid this is not feasible.
>
> TL;DR: Sounds fine, I'll be on the lookout for the PR.
Thank you very much!
> Longer version: Let me step back a bit and actually think about
> this longer than 2 minutes. From what I see
> rcar_rst_read_mode_pins() already returns -ENODEV if the nodes
> aren't present. Great.
>
> So clk tree could be given a pull for the clk patches, part C, on
> top of part A, the reset driver. If the rcar_rst_read_mode_pins()
> returns failure because the node is missing, we fall back to the
> old style of doing things. Some drivers already do that anyway,
For R-Car Gen2, we want to keep backwards compatibility for a while.
But not for the others, and I didn't want to add more code that was going
to be removed again soon.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v7 1/2] mtd: nand: add tango NFC dt bindings doc
From: Marc Gonzalez @ 2016-11-07 9:26 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, Boris Brezillon, DT, Richard Weinberger, Mason,
Rob Herring, linux-mtd, Sebastian Frias
In-Reply-To: <1978954.SRtJpfOGp1@wuerfel>
On 07/11/2016 10:18, Arnd Bergmann wrote:
> On Tuesday, October 25, 2016 3:15:50 PM CET Marc Gonzalez wrote:
>> Add the tango NAND Flash Controller dt bindings documentation.
>>
>> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
>> ---
>> Documentation/devicetree/bindings/mtd/tango-nand.txt | 38 ++++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt
>> new file mode 100644
>> index 000000000000..3cbf95d6595a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt
>> @@ -0,0 +1,38 @@
>> +Sigma Designs Tango4 NAND Flash Controller (NFC)
>> +
>> +Required properties:
>> +
>> +- compatible: "sigma,smp8758-nand"
>> +- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
>> +- dmas: reference to the DMA channel used by the controller
>> +- dma-names: "nfc_sbox"
>
> Drop the "nfc_" prefix here, it seems redundant.
I don't think it's redundant; there are switch boxes for several
different HW blocks; nfc_sbox is the first one to be exposed.
>> +- clocks: reference to the system clock
>> +- #address-cells: <1>
>> +- #size-cells: <0>
>> +
>> +Children nodes represent the available NAND chips.
>> +See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
>> +
>> +Example:
>> +
>> + nand: nand@2c000 {
>> + compatible = "sigma,smp8758-nand";
>> + reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;
>
> It would be nicer to write this as
>
> reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
>
> which is identical in binary format.
I didn't know that, thanks for pointing it out.
Unfortunately, Boris already accepted the patch yesterday :-(
Boris, do you fixup patches in your tree?
Regards.
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply
* Re: Re: [RFC PATCH] ARM: dts: add panel and tcon nodes to Allwinner A33 Q8 tablet dts
From: Hans de Goede @ 2016-11-07 9:26 UTC (permalink / raw)
To: icenowy-ymACFijhrKM, Maxime Ripard, Chen-Yu Tsai
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
In-Reply-To: <2578261478451207-qhNp/iSrOUlxpj1cXAZ9Bg@public.gmane.org>
Hi,
On 06-11-16 17:53, Icenowy Zheng wrote:
>
>
> 06.11.2016, 22:27, "Hans de Goede" <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>:
>> Hi,
>>
>> On 06-11-16 12:11, Icenowy Zheng wrote:
>>> All A33 Q8 tablets features a LCD panel, with a resolution of either
>>> 800x480 or 1024x600.
>>>
>>> Add "bone" device nodes to the device tree.
>>
>> Bone ?
>>
>>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>
>> He, as discussed in the other thread since sun8i-a33-q8-tablet.dts
>> is used for both 800x480 and 1024x600 versions we really need to
>> introduce new sun8i-a33-q8-tablet-800x600.dts and
>> sun8i-a33-q8-tablet-1024x600.dts files, which include
>> sun8i-a33-q8-tablet.dts and then add just the panel bits; and patch
>> newer u-boots to use those instead.
>>
>> This way people who stick with an old u-boot will just not get
>> the drm driver, rather then all of a sudden getting a wrong
>> resolution.
>>
>> Icenowy, can you please also submit a matching u-boot patch
>> (both the new dts file, as well as updating the defconfig you
>> use to the new dts file)?
>
> Could you choose a compatible for 1024x600 variant?
Lets just add a sun8i-a33-q8-tablet-800x600.dts now and then
I will add a sun8i-a33-q8-tablet-1024x600.dts file later.
Regards,
Hans
>
> (Since I have never such a Q8 tablet)
>
>>
>> Regards,
>>
>> Hans
>>
>>> ---
>>>
>>> Maybe it will be better to add them to sun8i-q8-reference-tablet.dtsi, as
>>> these pin configurations are part of reference design of both A23 and A33,
>>> not only restricted to Q8.
>>>
>>> The DTS file is tested by me, after cherry-picks this patch from Chen-Yu Tsai:
>>> https://github.com/wens/linux/commit/2823b887a289fbee5f97f3c6b45ed6c74a6368c6
>>>
>>> And add these commands to my U-Boot boot command:
>>>
>>> fdt addr 0x43000000
>>> fdt resize
>>> fdt set /panel compatible "urt,umsh-8596md-t"
>>> fdt set /panel status "okay"
>>> fdt set /display-engine status "okay"
>>> fdt set /soc@01c00000/lcd-controller@01c0c000 status "okay"
>>>
>>> arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 44 +++++++++++++++++++++++++++++++
>>> 1 file changed, 44 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> index b0bc236..871a20c 100644
>>> --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
>>> @@ -47,4 +47,48 @@
>>> / {
>>> model = "Q8 A33 Tablet";
>>> compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
>>> +
>>> + panel: panel {
>>> + /* compatible should be set according to the panel */
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&lcd_en_q8>;
>>> + backlight = <&backlight>;
>>> + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
>>> + power-supply = <®_dc1sw>;
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + port@0 {
>>> + reg = <0>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + panel_input: endpoint@0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&tcon0_out_lcd>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&tcon0 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&lcd_rgb666_pins>;
>>> +};
>>> +
>>> +&tcon0_out {
>>> + tcon0_out_lcd: endpoint@0 {
>>> + reg = <0>;
>>> + remote-endpoint = <&panel_input>;
>>> + };
>>> +};
>>> +
>>> +&pio {
>>> + lcd_en_q8: lcd_en@0 {
>>> + allwinner,pins = "PH7";
>>> + allwinner,function = "gpio_out";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> };
>
^ permalink raw reply
* Re: [PATCH v7 1/2] mtd: nand: add tango NFC dt bindings doc
From: Arnd Bergmann @ 2016-11-07 9:18 UTC (permalink / raw)
To: Marc Gonzalez
Cc: linux-mtd, Boris Brezillon, Richard Weinberger, DT, Rob Herring,
Mark Rutland, Mason, Sebastian Frias
In-Reply-To: <580F5B06.6030608-y1yR0Z3OICC7zZZRDBGcUA@public.gmane.org>
On Tuesday, October 25, 2016 3:15:50 PM CET Marc Gonzalez wrote:
> Add the tango NAND Flash Controller dt bindings documentation.
>
> Signed-off-by: Marc Gonzalez <marc_gonzalez-y1yR0Z3OICC7zZZRDBGcUA@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mtd/tango-nand.txt | 38 ++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt
> new file mode 100644
> index 000000000000..3cbf95d6595a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt
> @@ -0,0 +1,38 @@
> +Sigma Designs Tango4 NAND Flash Controller (NFC)
> +
> +Required properties:
> +
> +- compatible: "sigma,smp8758-nand"
> +- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
> +- dmas: reference to the DMA channel used by the controller
> +- dma-names: "nfc_sbox"
Drop the "nfc_" prefix here, it seems redundant.
> +- clocks: reference to the system clock
> +- #address-cells: <1>
> +- #size-cells: <0>
> +
> +Children nodes represent the available NAND chips.
> +See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
> +
> +Example:
> +
> + nand: nand@2c000 {
> + compatible = "sigma,smp8758-nand";
> + reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;
It would be nicer to write this as
reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
which is identical in binary format.
Arnd
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^ permalink raw reply
* Re: [PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7745 support
From: Geert Uytterhoeven @ 2016-11-07 8:41 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Michael Turquette, linux-clk, Stephen Boyd, Rob Herring,
Mark Rutland, devicetree@vger.kernel.org, Linux-Renesas,
Simon Horman
In-Reply-To: <4419870.yM1Fh9cWBP@wasted.cogentembedded.com>
Hi Sergei,
On Sat, Nov 5, 2016 at 11:34 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
> <geert+renesas@glider.be>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 3:
> - removed the FDP1-1 module clock;
> - added Geert's tag.
>
> Changes in version 2:
> - changed the Z2 clock's divisor to 3.
> --- /dev/null
> +++ linux/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -0,0 +1,260 @@
> +static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
> + /* Core Clock Outputs */
> + DEF_FIXED("acp", R8A7745_CLK_ACP, CLK_EXTAL, 2, 1),
This clock is called CPEX instead of ACP in rev. 1.00 of the RZ/G Series User's
Manual: Hardware.
> +};
> +
> +static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
> + DEF_MOD("thermal", 522, CLK_EXTAL),
RZ/G1E does not have the thermal sensor (confirmed by rev. 1.00).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3 1/2] ARM: shmobile: r8a7745: add CPG clock index macros
From: Geert Uytterhoeven @ 2016-11-07 8:34 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Mark Rutland, Michael Turquette, linux-clk,
Stephen Boyd, devicetree@vger.kernel.org, Linux-Renesas,
Simon Horman
In-Reply-To: <6619847.B5XdH7v7xE@wasted.cogentembedded.com>
Hi Sergei,
On Sat, Nov 5, 2016 at 11:31 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add macros usable by the device tree sources to reference the R8A7745 CPG
> clocks by index. The data comes from the table 7.2c in the revision 0.50
> of the RZ/G Series User's Manual.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 2:
> - added Geert's tag.
>
> include/dt-bindings/clock/r8a7745-cpg-mssr.h | 44 +++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> Index: linux/include/dt-bindings/clock/r8a7745-cpg-mssr.h
> ===================================================================
> --- /dev/null
> +++ linux/include/dt-bindings/clock/r8a7745-cpg-mssr.h
> +#define R8A7745_CLK_ACP 26
This clock is called CPEX instead of ACP in rev. 1.00 of the RZ/G Series User's
Manual: Hardware.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH V4 6/6] bus: Add support for Tegra Generic Memory Interface
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...
Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
---
Changes in v2:
- Fixed some checkpatch errors
- Re-ordered probe to get rid of local variables
- Moved of_platform_default_populate call to the end of probe
- Use the timing and configuration properties from the child device
- Added warning if more then 1 child device exist
Changes in v3:
- added helper function to disable the controller which is used in remove and
on error.
- Added logic to parse CS# from "ranges" property with fallback to "reg"
property
Changes in v4:
- added sanity check of chip-select property (fail if invalid)
- adjusted for device tree binding property name changes
- fail probe if there are no child nodes
- removed superfluous error message
- removed superfluous newline in Kconfig
drivers/bus/Kconfig | 7 ++
drivers/bus/Makefile | 1 +
drivers/bus/tegra-gmi.c | 275 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 283 insertions(+)
create mode 100644 drivers/bus/tegra-gmi.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 4ed7d26..a9ebc4c 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -141,6 +141,13 @@ config TEGRA_ACONNECT
Driver for the Tegra ACONNECT bus which is used to interface with
the devices inside the Audio Processing Engine (APE) for Tegra210.
+config TEGRA_GMI
+ tristate "Tegra Generic Memory Interface bus driver"
+ depends on ARCH_TEGRA
+ help
+ Driver for the Tegra Generic Memory Interface bus which can be used
+ to attach devices such as NOR, UART, FPGA and more.
+
config UNIPHIER_SYSTEM_BUS
tristate "UniPhier System Bus driver"
depends on ARCH_UNIPHIER && OF
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index ac84cc4..34e2bab 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
+obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
new file mode 100644
index 0000000..687e212
--- /dev/null
+++ b/drivers/bus/tegra-gmi.c
@@ -0,0 +1,275 @@
+/*
+ * Driver for NVIDIA Generic Memory Interface
+ *
+ * Copyright (C) 2016 Host Mobility AB. All rights reserved.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/reset.h>
+
+#define TEGRA_GMI_CONFIG 0x00
+#define TEGRA_GMI_CONFIG_GO BIT(31)
+#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
+#define TEGRA_GMI_MUX_MODE BIT(28)
+#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
+#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
+#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
+#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
+#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
+#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
+
+#define TEGRA_GMI_TIMING0 0x10
+#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
+#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
+#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
+#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
+
+#define TEGRA_GMI_TIMING1 0x14
+#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
+#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
+#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
+
+#define TEGRA_GMI_MAX_CHIP_SELECT 8
+
+struct tegra_gmi_priv {
+ void __iomem *base;
+ struct reset_control *rst;
+ struct clk *clk;
+
+ u32 snor_config;
+ u32 snor_timing0;
+ u32 snor_timing1;
+};
+
+static void tegra_gmi_disable(struct tegra_gmi_priv *priv)
+{
+ u32 config;
+
+ /* stop GMI operation */
+ config = readl(priv->base + TEGRA_GMI_CONFIG);
+ config &= ~TEGRA_GMI_CONFIG_GO;
+ writel(config, priv->base + TEGRA_GMI_CONFIG);
+
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+}
+
+static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv *priv)
+{
+ writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0);
+ writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1);
+
+ priv->snor_config |= TEGRA_GMI_CONFIG_GO;
+ writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG);
+}
+
+static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv *priv)
+{
+ struct device_node *child = of_get_next_available_child(dev->of_node,
+ NULL);
+ u32 property, ranges[4];
+ int ret;
+
+ if (!child) {
+ dev_err(dev, "no child nodes found\n");
+ return -ENODEV;
+ }
+
+ /*
+ * We currently only support one child device due to lack of
+ * chip-select address decoding. Which means that we only have one
+ * chip-select line from the GMI controller.
+ */
+ if (of_get_child_count(dev->of_node) > 1)
+ dev_warn(dev, "only one child device is supported.");
+
+ if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
+ priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
+
+ if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
+ priv->snor_config |= TEGRA_GMI_MUX_MODE;
+
+ if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
+ priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
+
+ if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
+ priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
+ priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
+ priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
+ priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
+
+ /* Decode the CS# */
+ ret = of_property_read_u32_array(child, "ranges", ranges, 4);
+ if (ret < 0) {
+ /* Invalid binding */
+ if (ret == -EOVERFLOW) {
+ dev_err(dev,
+ "failed to decode CS: invalid ranges length\n");
+ goto error_cs;
+ }
+
+ /*
+ * If we reach here it means that the child node has an empty
+ * ranges or it does not exist at all. Attempt to decode the
+ * CS# from the reg property instead.
+ */
+ ret = of_property_read_u32(child, "reg", &property);
+ if (ret < 0) {
+ dev_err(dev,
+ "failed to decode CS: no reg property found\n");
+ goto error_cs;
+ }
+ } else {
+ property = ranges[1];
+ }
+
+ /* Valid chip selects are CS0-CS7 */
+ if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
+ dev_err(dev, "invalid chip select: %d", property);
+ ret = -EINVAL;
+ goto error_cs;
+ }
+
+ priv->snor_config |= TEGRA_GMI_CS_SELECT(property);
+
+ /* The default values that are provided below are reset values */
+ if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
+
+ if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
+
+error_cs:
+ of_node_put(child);
+ return ret;
+}
+
+static int tegra_gmi_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct tegra_gmi_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->clk = devm_clk_get(dev, "gmi");
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "can not get clock\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->rst = devm_reset_control_get(dev, "gmi");
+ if (IS_ERR(priv->rst)) {
+ dev_err(dev, "can not get reset\n");
+ return PTR_ERR(priv->rst);
+ }
+
+ ret = tegra_gmi_parse_dt(dev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "fail to enable clock.\n");
+ return ret;
+ }
+
+ reset_control_assert(priv->rst);
+ udelay(2);
+ reset_control_deassert(priv->rst);
+
+ tegra_gmi_init(dev, priv);
+
+ ret = of_platform_default_populate(dev->of_node, NULL, dev);
+ if (ret < 0) {
+ dev_err(dev, "fail to create devices.\n");
+ tegra_gmi_disable(priv);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ return 0;
+}
+
+static int tegra_gmi_remove(struct platform_device *pdev)
+{
+ struct tegra_gmi_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ of_platform_depopulate(&pdev->dev);
+
+ tegra_gmi_disable(priv);
+
+ return 0;
+}
+
+static const struct of_device_id tegra_gmi_id_table[] = {
+ { .compatible = "nvidia,tegra20-gmi", },
+ { .compatible = "nvidia,tegra30-gmi", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
+
+static struct platform_driver tegra_gmi_driver = {
+ .probe = tegra_gmi_probe,
+ .remove = tegra_gmi_remove,
+ .driver = {
+ .name = "tegra-gmi",
+ .of_match_table = tegra_gmi_id_table,
+ },
+};
+module_platform_driver(tegra_gmi_driver);
+
+MODULE_AUTHOR("Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org");
+MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related
* [PATCH V4 5/6] ARM: tegra: Add Tegra20 GMI support
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add a device node for the GMI controller found on Tegra20.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- added address-cells, size-cells and ranges properties
Changes in v3:
- fixed range address which is not the same as Tegra30.
Changes in v4:
- removed extra newline and a initial space in resets property.
arch/arm/boot/dts/tegra20.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 2207c08..e880750 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -376,6 +376,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd0000000 0xfffffff>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.1.4
^ permalink raw reply related
* [PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- added address-cells, size-cells and ranges properties
Changes in v3:
- no changes
Changes in v4:
- no changes
arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5030065..bbb1c00 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -439,6 +439,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra30-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x48000000 0x7ffffff>;
+ clocks = <&tegra_car TEGRA30_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.1.4
^ permalink raw reply related
* [PATCH V4 3/6] dt/bindings: Add bindings for Tegra GMI controller
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
- Updated examples and some information based on comments from Jon Hunter.
Changes in v3:
- Updates ranges description based on comments from Rob Herring
Changes in v4:
- renamed snor-*-inv to snor-*-active-high
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
new file mode 100644
index 0000000..83b0e54
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
@@ -0,0 +1,132 @@
+Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
+
+The Generic Memory Interface bus enables memory transfers between internal and
+external memory. Can be used to attach various high speed devices such as
+synchronous/asynchronous NOR, FPGA, UARTS and more.
+
+The actual devices are instantiated from the child nodes of a GMI node.
+
+Required properties:
+ - compatible : Should contain one of the following:
+ For Tegra20 must contain "nvidia,tegra20-gmi".
+ For Tegra30 must contain "nvidia,tegra30-gmi".
+ - reg: Should contain GMI controller registers location and length.
+ - clocks: Must contain an entry for each entry in clock-names.
+ - clock-names: Must include the following entries: "gmi"
+ - resets : Must contain an entry for each entry in reset-names.
+ - reset-names : Must include the following entries: "gmi"
+ - #address-cells: The number of cells used to represent physical base
+ addresses in the GMI address space. Should be 2.
+ - #size-cells: The number of cells used to represent the size of an address
+ range in the GMI address space. Should be 1.
+ - ranges: Must be set up to reflect the memory layout with three integer values
+ for each chip-select line in use (only one entry is supported, see below
+ comments):
+ <cs-number> <offset> <physical address of mapping> <size>
+
+Note that the GMI controller does not have any internal chip-select address
+decoding, because of that chip-selects either need to be managed via software
+or by employing external chip-select decoding logic.
+
+If external chip-select logic is used to support multiple devices it is assumed
+that the devices use the same timing and so are probably the same type. It also
+assumes that they can fit in the 256MB address range. In this case only one
+child device is supported which represents the active chip-select line, see
+examples for more insight.
+
+The chip-select number is decoded from the child nodes second address cell of
+'ranges' property, if 'ranges' property is not present or empty chip-select will
+then be decoded from the first cell of the 'reg' property.
+
+Optional child cs node properties:
+
+ - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
+ - nvidia,snor-mux-mode: Enable address/data MUX mode.
+ - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
+ If omitted it will be asserted with data.
+ - nvidia,snor-rdy-active-high: RDY signal is active high
+ - nvidia,snor-adv-active-high: ADV signal is active high
+ - nvidia,snor-oe-active-high: WE/OE signal is active high
+ - nvidia,snor-cs-active-high: CS signal is active high
+
+ Note that there is some special handling for the timing values.
+ From Tegra TRM:
+ Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
+
+ - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
+ bus. Valid values are 0-15, default is 1
+ - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
+ de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
+ (in case of MASTER Request). Valid values are 0-15, default is 1
+ - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
+ Valid values are 0-15, default is 1.
+ - nvidia,snor-ce-width: Number of cycles before CE is asserted.
+ Valid values are 0-15, default is 4
+ - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
+ Valid values are 0-15, default is 1
+ - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
+ Valid values are 0-255, default is 1
+ - nvidia,snor-wait-width: Number of cycles before READY is asserted.
+ Valid values are 0-255, default is 3
+
+Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
+controllers with a simple-bus node since they are all connected to the same
+chip-select (CS4), in this example external address decoding is provided:
+
+gmi@70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ bus@4,0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 4 0 0x40100>;
+
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+
+ can@0 {
+ reg = <0 0x100>;
+ ...
+ };
+
+ can@40000 {
+ reg = <0x40000 0x100>;
+ ...
+ };
+ };
+};
+
+Example with one SJA1000 CAN controller connected to the GMI bus
+on CS4:
+
+gmi@70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ can@4,0 {
+ reg = <4 0 0x100>;
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+ ...
+ };
+};
--
2.1.4
^ permalink raw reply related
* [PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: mark.rutland, gnurou, pgaikwad, linux-clk, devicetree,
pdeschrijver, Mirza Krak, sboyd, linux, linux-kernel, robh+dt,
linux-tegra, mturquette, linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
The maximum rate value of 127 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..67f1677 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
is max rate.
The maximum rate value of 92 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+ { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 0/6] Add support for Tegra GMI bus controller
From: Mirza Krak @ 2016-11-07 8:29 UTC (permalink / raw)
To: swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Mirza Krak
From: Mirza Krak <mirza.krak-3xdUHytR7SMQwY+2splSUA@public.gmane.org>
Hi.
This patch series adds support for the Tegra GMI bus controller.
I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom
carrier board which has multiple CAN controllers (SJA1000) connected to the
GMI bus.
I have re-based on top of latest tegra/for-next in V4. Also see individual
patches for changes in V4.
Hopefully this will be the last round.
See below links for previous discussions.
Comments on RFC:
https://marc.info/?l=linux-clk&m=146893557629903&w=2
https://marc.info/?l=linux-tegra&m=146893541829801&w=2
https://marc.info/?l=linux-tegra&m=146893542429814&w=2
Comments on V1:
https://marc.info/?l=linux-arm-kernel&m=147051551821122&w=2
https://marc.info/?l=linux-arm-kernel&m=147051553121150&w=2
https://marc.info/?l=linux-arm-kernel&m=147194856600627&w=2
https://marc.info/?l=linux-arm-kernel&m=147072742432211&w=2
Comments on V2:
https://marc.info/?l=devicetree&m=147522253920226&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=devicetree&m=147256931318922&w=2
Comments on V3:
https://marc.info/?l=linux-tegra&m=147789181607782&w=2
https://marc.info/?l=linux-tegra&m=147816818203104&w=2
https://marc.info/?l=linux-tegra&m=147816897003332&w=2
https://marc.info/?l=linux-tegra&m=147818119107204&w=2
Mirza Krak (6):
clk: tegra: add TEGRA20_CLK_NOR to init table
clk: tegra: add TEGRA30_CLK_NOR to init table
dt/bindings: Add bindings for Tegra GMI controller
ARM: tegra: Add Tegra30 GMI support
ARM: tegra: Add Tegra20 GMI support
bus: Add support for Tegra Generic Memory Interface
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 ++++++++++
arch/arm/boot/dts/tegra20.dtsi | 13 +
arch/arm/boot/dts/tegra30.dtsi | 13 +
drivers/bus/Kconfig | 7 +
drivers/bus/Makefile | 1 +
drivers/bus/tegra-gmi.c | 275 +++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 1 +
drivers/clk/tegra/clk-tegra30.c | 1 +
8 files changed, 443 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
create mode 100644 drivers/bus/tegra-gmi.c
--
2.1.4
^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Martin Strbačka @ 2016-11-07 7:41 UTC (permalink / raw)
To: Uwe Kleine-König, Andrew Lunn
Cc: Mark Rutland, devicetree, Jason Cooper, Tomas Hlavacek,
Rob Herring, Gregory Clement, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20161105212748.vtdprlxxismy5xmk@perseus.defre.kleine-koenig.org>
[-- Attachment #1.1.1: Type: text/plain, Size: 388 bytes --]
On 5.11.2016 22:27, Uwe Kleine-König wrote:
>>> Do I need to "register" turris in vendor-prefixes.txt for that?
>> >
>> > Yes please.
> OK, will wait for Martin to comment what we want there. cznic or turris.
Hello,
please use CZ.NIC in this case. Turris Omnia is a model name.
Thanks for your work!
Martin
--
Martin Strbacka CZ.NIC, z.s.p.o. tel. +420 604 217 854
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-07 5:41 UTC (permalink / raw)
To: Linus Walleij
Cc: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Stephen Warren, Rob Herring, Mark Rutland, Jon Hunter,
Masahiro Yamada,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CACRpkdb4DQLzQWHxuZi=TDaeigNzVJV8TN1jsQfOHKF7yPLrUg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Saturday 05 November 2016 03:54 AM, Linus Walleij wrote:
> On Wed, Nov 2, 2016 at 10:09 AM, Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>
>> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
>> low power state of some of its IO pads. The IO pads can work in
>> the voltage of the 1.8V and 3.3V of IO power rail sources. When IO
>> interface are not used then IO pads can be configure in low power
>> state to reduce the power from that IO pads.
>>
>> On Tegra124, the IO power rail source is auto detected by SoC and hence
>> it is only require to configure in low power mode if IO pads are not
>> used.
>>
>> On T210 onwards, the auto-detection is removed from SoC and hence SW
>> must configure the PMC register explicitly to set proper voltage in
>> IO pads based on IO rail power source voltage.
>>
>> This driver adds the IO pad driver to configure the power state and
>> IO pad voltage based on the usage and power tree via pincontrol
>> framework. The configuration can be static and dynamic.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Looking for an ACK from Stephen &| Thierry.
This driver depends on some new APIs from tegra pmc driver. The new APIs
are integrated in Thierry's branch and he wanted to push the changes to
linux-next/main path if there is any client driver for this.
This series is the client driver for tegra PMC.
So if you are fine, then you can ACK and Thierry can take this in his
branch.
Or I will leave to you/Thierry to propose if some other idea for
discussion/acceptance.
>
>> ---
>> On top of the branch from Thierry's T186 work
>> https://github.com/thierryreding/linux/tree/tegra186
> But it's an orthogonal patch right?
>
> The build robot seems to have problems with it so pls fix these.
The driver built in pinctrl branch and so this is expected. The APIs are
in the above branch.
>
>> +static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
>> + {
>> + .property = "nvidia,power-source-voltage",
>> + .param = TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE,
>> + },
>> +};
> Why can you not use the standard power-source binding
> from Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> instead of inventing this nvidia,* variant?
Per binding doc,
power-source - select between different power supplies
So actually it selects the different source of power supply.
In my case, I will have same supply but voltage of that supply get changed.
So here property is for the power-supply-voltage.
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^ permalink raw reply
* [PATCH 3/3] ARM: dts: imx: Add ocotp node for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
In-Reply-To: <1478497281-5477-1-git-send-email-ping.bai@nxp.com>
Add ocotp node for i.MX6UL SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index c5c05fd..c6f6613 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -849,6 +849,12 @@
reg = <0x021b0000 0x4000>;
};
+ ocotp: ocotp-ctrl@021bc000 {
+ compatible = "fsl,imx6ul-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6UL_CLK_OCOTP>;
+ };
+
lcdif: lcdif@021c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
reg = <0x021c8000 0x4000>;
--
2.8.2
^ permalink raw reply related
* [PATCH 2/3] devicetree: bindings: nvmem: Add compatible string for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
In-Reply-To: <1478497281-5477-1-git-send-email-ping.bai@nxp.com>
Add new compatible string for i.MX6UL SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 383d588..a7ff65d 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,14 @@
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
Required properties:
- compatible: should be one of
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
- "fsl,imx6sl-ocotp" (i.MX6SL), or
- "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+ "fsl,imx6sl-ocotp" (i.MX6SL),
+ "fsl,imx6sx-ocotp" (i.MX6SX), or
+ "fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
--
2.8.2
^ permalink raw reply related
* [PATCH 1/3] driver: nvmem: Add ocotp driver support for imx6ul
From: Bai Ping @ 2016-11-07 5:41 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel
Cc: fabio.estevam, devicetree, ping.bai, linux-arm-kernel
i.MX6UL is an new SOC of i.MX6 family. Enable ocotp
driver support for this SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
drivers/nvmem/imx-ocotp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index ac27b9b..108e4bc 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -73,6 +73,7 @@ static const struct of_device_id imx_ocotp_dt_ids[] = {
{ .compatible = "fsl,imx6q-ocotp", (void *)128 },
{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
+ { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
{ },
};
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
--
2.8.2
^ permalink raw reply related
* Re: [PATCH 0/3] ARM: dts: am33xx: Add clock info to rtc nodes
From: Keerthy @ 2016-11-07 4:25 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
t-kristo-l0cyMroinI0
In-Reply-To: <1477547288-5041-1-git-send-email-j-keerthy-l0cyMroinI0@public.gmane.org>
On Thursday 27 October 2016 11:18 AM, Keerthy wrote:
> The series adds the clock info to rtc node.
>
> Boot tested and checked for rtc ticking on am335x-boneblack, am335x-bone
> am437x-gp-evm.
Tony,
The relevant driver changes are already pulled by Alexandre Belloni.
https://patchwork.kernel.org/patch/9398903/.
Hope you call pull this set.
Regards,
Keerthy
>
> Keerthy (3):
> ARM: dts: AM335X-bone-common: Add the internal and external clock
> nodes for rtc
> ARM: dts: AM335X-evm: Add the internal and external clock nodes for
> rtc
> ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for
> rtc
>
> arch/arm/boot/dts/am335x-bone-common.dtsi | 5 +++++
> arch/arm/boot/dts/am335x-evm.dts | 5 +++++
> arch/arm/boot/dts/am335x-evmsk.dts | 5 +++++
> arch/arm/boot/dts/am33xx.dtsi | 2 ++
> 4 files changed, 17 insertions(+)
>
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^ permalink raw reply
* Re: [PATCH 2/5] drivers: gpio: Add support for multiple IPs
From: Keerthy @ 2016-11-07 3:59 UTC (permalink / raw)
To: Linus Walleij, Grygorii Strashko
Cc: Roger Quadros, Alexandre Courbot, Lokesh Vutla, Rob Herring,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-OMAP
In-Reply-To: <CACRpkdac_UgM=xeXkSZ+rOvZvutt40USjCoEt5-SoFkqspuExw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Saturday 05 November 2016 01:53 PM, Linus Walleij wrote:
> On Fri, Nov 4, 2016 at 8:59 PM, Grygorii Strashko
> <grygorii.strashko-l0cyMroinI0@public.gmane.org> wrote:
>> On 11/04/2016 09:28 AM, Linus Walleij wrote:
>
>>> The DT model sort of mandates how the interrupts should be mapped
>>> at this point, and as far as I can tell from the binding the example looks
>>> like so:
>>>
>>> gpio: gpio@1e26000 {
>>> compatible = "ti,dm6441-gpio";
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> reg = <0x226000 0x1000>;
>>> interrupt-parent = <&intc>;
>>> interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
>>> 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH
>>> 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH
>>> 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH
>>> 50 IRQ_TYPE_EDGE_BOTH>;
>>> ti,ngpio = <144>;
>>> ti,davinci-gpio-unbanked = <0>;
>>> interrupt-controller;
>>> #interrupt-cells = <2>;
>>> };
>>
>> Above, DT bindings models Davinci GPIO IP as monolithic GPIO controller
>> with N gpio pins, but internally separate GPIO chips are created for each
>> banksX&Y register set (32 pins, 2 banked irq -or- 32 direct irqs).
>
> Hm it would be good to get away from that and just have one big gpio
> chip.
>
>> Translation from linear GPIO numbering to the proper internal GPIO chip is done
>> using chip.of_xlate().
>
> Yeah :/ this could be made simpler with a single chip just spanning all
> the banks and the common registers I think.
Okay Linus. Thanks for the direction.
>
> Yours,
> Linus Walleij
>
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^ permalink raw reply
* Re: [PATCH v2 0/9] ARM: DRA7: Add support for DRA718-evm
From: Lokesh Vutla @ 2016-11-07 3:49 UTC (permalink / raw)
To: Tony Lindgren, Linux OMAP Mailing List
Cc: Tero Kristo, Sekhar Nori, Nishanth Menon,
Device Tree Mailing List, Rob Herring, Linux ARM Mailing List
In-Reply-To: <20161021103841.8044-1-lokeshvutla-l0cyMroinI0@public.gmane.org>
Hi Tony,
On Friday 21 October 2016 04:08 PM, Lokesh Vutla wrote:
> This series does minor dts cleanup for dra72-evm and adds support for
> DRA718-evm.
Do you have any comments on this series?
Thanks and regards,
Lokesh
>
> Changes since v1:
> - Updated xxx-supply to xxx-in-supply in Documentation.
>
> Lokesh Vutla (7):
> ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869
> ARM: dra72-evm: Fix modelling of regulators
> ARM: dts: dra72: Add separate dtsi for tps65917
> regulator: lp873x: Add support for populating input supply
> ARM: OMAP2+: board-generic: add support for DRA71x family
> ARM: omap2plus_defconfig: Enable REGULATOR_GPIO
> ARM: omap2plus_defconfig: Enable LP873X support
>
> Nishanth Menon (2):
> ARM: DRA7: hwmod: Do not register RTC on DRA71
> ARM: dts: Add support for dra718-evm
>
> .../devicetree/bindings/arm/omap/omap.txt | 6 +
> Documentation/devicetree/bindings/mfd/lp873x.txt | 8 +
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/dra71-evm.dts | 230 ++++++++++++++
> arch/arm/boot/dts/dra72-evm-common.dtsi | 348 +++------------------
> arch/arm/boot/dts/dra72-evm-revc.dts | 21 +-
> arch/arm/boot/dts/dra72-evm-tps65917.dtsi | 134 ++++++++
> arch/arm/boot/dts/dra72-evm.dts | 14 +-
> arch/arm/configs/omap2plus_defconfig | 3 +
> arch/arm/mach-omap2/board-generic.c | 1 +
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 +-
> drivers/regulator/lp873x-regulator.c | 1 +
> 12 files changed, 453 insertions(+), 326 deletions(-)
> create mode 100644 arch/arm/boot/dts/dra71-evm.dts
> create mode 100644 arch/arm/boot/dts/dra72-evm-tps65917.dtsi
>
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* Re: [PATCH 14/17] ASoC: add simple-graph-card document
From: Kuninori Morimoto @ 2016-11-07 3:34 UTC (permalink / raw)
To: Mark Brown
Cc: Rob Herring, Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi,
Grant Likely, Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <20161104203342.aizjufjokuqrlyhh@sirena.org.uk>
Hi Mark
> This document really needs quite a bit of fleshing out but I'm not sure
> that should be a blocker for the series as a whole especially given that
> English is not your native language - we can build out later. I think
I'm sorry about my English...
> One thing I'm not 100% clear on here is why it has to be a CPU DAI (I'm
> guessing just one of them though the above says ports as an option?)
> that creates the card? Is there a concrete reason for that or is it
> just being defined as good pracctice?
This explain was not understandable, indeed.
This means, CPU side's port on DT need to have compatible,
and CPU side driver need to call asoc_simple_card_try_to_probe_graph_card()
(= [PATCH 12/17]). asoc_simple_card_try_to_probe_graph_card()
will check this compatible, and probe card driver.
I will fixup and repost v3 after of-graph people's review
compatible = "asoc-simple-graph-card";
^ permalink raw reply
* [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs
From: Joel Holdsworth @ 2016-11-07 2:49 UTC (permalink / raw)
To: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w,
geert-Td1EMuHUCqxL1ZNQvxDV9g, robh-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA, marex-ynQEQJNshbs,
clifford-cPpHkPqGOEfk7+2FdBfRIA
Cc: Joel Holdsworth
In-Reply-To: <1478486962-26794-1-git-send-email-joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
and very regular structure, designed for low-cost, high-volume consumer
and system applications.
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.
The iCE40 family is notable because it is the first FPGA family to have
complete reverse engineered bit-stream documentation for the iCE40LP and
iCE40HX devices. Furthermore, there is now a Free Software Verilog
synthesis tool-chain: the "IceStorm" tool-chain.
This project is the work of Clifford Wolf, who is the maintainer of
Yosys Verilog RTL synthesis framework, and Mathias Lasser, with notable
contributions from "Cotton Seed", the main author of "arachne-pnr"; a
place-and-route tool for iCE40 FPGAs.
Having a Free Software synthesis tool-chain offers interesting
opportunities for embedded devices that are able reconfigure themselves
with open firmware that is generated on the device itself. For example
a mobile device might have an application processor with an iCE40 FPGA
attached, which implements slave devices, or through which the processor
communicates with other devices through the FPGA fabric.
A kernel driver for the iCE40 is useful, because in some cases, the FPGA
may need to be configured before other devices can be accessed.
An example of such a device is the icoBoard; a RaspberryPI HAT which
features an iCE40HX8K with a 1 or 8 MBit SRAM and ports for
Digilent-compatible PMOD modules. A PMOD module may contain a device
with which the kernel communicates, via the FPGA.
Signed-off-by: Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
---
drivers/fpga/Kconfig | 6 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ice40-spi.c | 217 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 224 insertions(+)
create mode 100644 drivers/fpga/ice40-spi.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d614102..5b0f137 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -13,6 +13,12 @@ config FPGA
if FPGA
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on OF && SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
config FPGA_MGR_SOCFPGA
tristate "Altera SOCFPGA FPGA Manager"
depends on ARCH_SOCFPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8d83fc6..adb5811 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c
new file mode 100644
index 0000000..7d7595b
--- /dev/null
+++ b/drivers/fpga/ice40-spi.c
@@ -0,0 +1,217 @@
+/*
+ * FPGA Manager Driver for Lattice iCE40.
+ *
+ * Copyright (c) 2016 Joel Holdsworth
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This driver adds support to the FPGA manager for configuring the SRAM of
+ * Lattice iCE40 FPGAs through slave SPI.
+ */
+
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/spi/spi.h>
+
+#define ICE40_SPI_FPGAMGR_RESET_DELAY 1 /* us (>200ns) */
+#define ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY 1200 /* us */
+
+#define ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
+
+struct ice40_fpga_priv {
+ struct spi_device *dev;
+ struct gpio_desc *reset;
+ struct gpio_desc *cdone;
+};
+
+static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
+ FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ struct spi_message message;
+ struct spi_transfer assert_cs_then_reset_delay = {.cs_change = 1,
+ .delay_usecs = ICE40_SPI_FPGAMGR_RESET_DELAY};
+ struct spi_transfer housekeeping_delay_then_release_cs = {
+ .delay_usecs = ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY};
+ int ret;
+
+ if ((flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+ dev_err(&dev->dev,
+ "Partial reconfiguration is not supported\n");
+ return -ENOTSUPP;
+ }
+
+ /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
+ spi_bus_lock(dev->master);
+
+ gpiod_set_value(priv->reset, 1);
+
+ spi_message_init(&message);
+ spi_message_add_tail(&assert_cs_then_reset_delay, &message);
+ ret = spi_sync_locked(dev, &message);
+
+ /* Come out of reset */
+ gpiod_set_value(priv->reset, 0);
+
+ /* Abort if the chip-select failed */
+ if (ret)
+ goto fail;
+
+ /* Check CDONE is de-asserted i.e. the FPGA is reset */
+ if (gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
+ ret = -EIO;
+ goto fail;
+ }
+
+ /* Wait for the housekeeping to complete, and release SS_B */
+ spi_message_init(&message);
+ spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
+ ret = spi_sync_locked(dev, &message);
+
+fail:
+ spi_bus_unlock(dev->master);
+
+ return ret;
+}
+
+static int ice40_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ return spi_write(priv->dev, buf, count);
+}
+
+static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+ struct spi_device *dev = priv->dev;
+ const u8 padding[ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BYTES] = {0,};
+
+ /* Check CDONE is asserted */
+ if (!gpiod_get_value(priv->cdone)) {
+ dev_err(&dev->dev,
+ "CDONE was not asserted after firmware transfer\n");
+ return -EIO;
+ }
+
+ /* Send of zero-padding to activate the firmware */
+ return spi_write(dev, padding, sizeof(padding));
+}
+
+static void ice40_fpga_ops_fpga_remove(struct fpga_manager *mgr)
+{
+ struct ice40_fpga_priv *priv = mgr->priv;
+
+ /* Enter reset */
+ gpiod_set_value(priv->reset, 1);
+}
+
+static const struct fpga_manager_ops ice40_fpga_ops = {
+ .state = ice40_fpga_ops_state,
+ .write_init = ice40_fpga_ops_write_init,
+ .write = ice40_fpga_ops_write,
+ .write_complete = ice40_fpga_ops_write_complete,
+ .fpga_remove = ice40_fpga_ops_fpga_remove
+};
+
+static int ice40_fpga_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct device_node *np = spi->dev.of_node;
+ struct ice40_fpga_priv *priv;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "No Device Tree entry\n");
+ return -EINVAL;
+ }
+
+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = spi;
+
+ /* Check board setup data. */
+ if (spi->max_speed_hz > 25000000) {
+ dev_err(dev, "Speed is too high\n");
+ return -EINVAL;
+ }
+
+ if (spi->max_speed_hz < 1000000) {
+ dev_err(dev, "Speed is too low\n");
+ return -EINVAL;
+ }
+
+ if (spi->mode & SPI_CPHA) {
+ dev_err(dev, "Bad mode\n");
+ return -EINVAL;
+ }
+
+ /* Set up the GPIOs */
+ priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
+ if (IS_ERR(priv->cdone)) {
+ dev_err(dev, "Failed to get CDONE GPIO: %ld\n",
+ PTR_ERR(priv->cdone));
+ return -EINVAL;
+ }
+
+ priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(priv->reset)) {
+ dev_err(dev, "Failed to get CRESET_B GPIO: %ld\n",
+ PTR_ERR(priv->reset));
+ return -EINVAL;
+ }
+
+ /* Register with the FPGA manager */
+ ret = fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
+ &ice40_fpga_ops, priv);
+ if (ret) {
+ dev_err(dev, "Unable to register FPGA manager");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ice40_fpga_remove(struct spi_device *spi)
+{
+ fpga_mgr_unregister(&spi->dev);
+ return 0;
+}
+
+static const struct of_device_id ice40_fpga_of_match[] = {
+ { .compatible = "lattice,ice40-fpga-mgr", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
+
+static struct spi_driver ice40_fpga_driver = {
+ .probe = ice40_fpga_probe,
+ .remove = ice40_fpga_remove,
+ .driver = {
+ .name = "ice40spi",
+ .of_match_table = of_match_ptr(ice40_fpga_of_match),
+ },
+};
+
+module_spi_driver(ice40_fpga_driver);
+
+MODULE_AUTHOR("Joel Holdsworth <joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>");
+MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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