* Re: [PATCH v4 0/3] ASoC/ARM: tegra: apalis t30/tk1/colibri t30: sgtl5000 audio
From: Thierry Reding @ 2016-11-07 13:42 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, devicetree@vger.kernel.org,
linux@armlinux.org.uk, gnurou@gmail.com, broonie@kernel.org,
mark.rutland@arm.com, prarit@redhat.com,
akpm@linux-foundation.org, tiwai@suse.com, lgirdwood@gmail.com,
ttynkkynen@nvidia.com, linux-arm-kernel@lists.infradead.org,
perex@perex.cz, alsa-devel
In-Reply-To: <1471355726.4197.6.camel@toradex.com>
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On Tue, Aug 16, 2016 at 01:55:28PM +0000, Marcel Ziswiler wrote:
> On Sun, 2016-06-19 at 02:59 +0200, Marcel Ziswiler wrote:
> > This series adds/integrates Freescale SGTL5000 analogue audio codec
> > support.
> >
> > Changes in v4:
> > - simple-audio-card does still not allow for more advanced use cases
> > like Tegra SoCs
> > - further platform drivers have been accepted since my last attempt
> > (e.g. rt5677 one)
> > - relevance for one further board the new Toradex Apalis TK1
> > - drop unused sound/jack.h include
> > - in tegra_sgtl5000_driver_remove() pass return value of
> > snd_soc_unregister_card() on to caller
> > - no longer set owner property in platform_driver to THIS_MODULE
> > - re-based/resend
> >
> > Changes in v3:
> > - revert to not using simple-audio-card being incompatible with tegra
> > - rebased to for-next
> >
> > Changes in v2:
> > - using simple-audio-card as suggested by Fabio
> >
> > Marcel Ziswiler (3):
> > ASoC: tegra: add tegra sgtl5000 machine driver
> > ARM: tegra: apalis/colibri t30: integrate audio
> > ARM: tegra: enable sgtl5000 audio
> >
> > .../bindings/sound/nvidia,tegra-audio-sgtl5000.txt | 42 ++++
> > arch/arm/boot/dts/tegra30-apalis.dtsi | 49 +++++
> > arch/arm/boot/dts/tegra30-colibri.dtsi | 49 +++++
> > arch/arm/configs/tegra_defconfig | 1 +
> > sound/soc/tegra/Kconfig | 11 ++
> > sound/soc/tegra/Makefile | 2 +
> > sound/soc/tegra/tegra_sgtl5000.c | 212
> > +++++++++++++++++++++
> > 7 files changed, 366 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/sound/nvidia,tegra-audio-
> > sgtl5000.txt
> > create mode 100644 sound/soc/tegra/tegra_sgtl5000.c
>
> With Mark finally having pulled the first patch of this series (https:/
> /lkml.org/lkml/2016/8/15/297) I'm wondering whether the second and
> third patch are now being pulled via tegra tree? Or should I rather re-
> submit those as a new v5 patch set?
Both patches applied now, thanks.
Thierry
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* Re: [PATCH 0/9] arm64: renesas: add M3ULCB board
From: Simon Horman @ 2016-11-07 13:35 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478196375-1131-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Thu, Nov 03, 2016 at 09:06:15PM +0300, Vladimir Barinov wrote:
> Hello,
>
> This adds the folowing:
> - R8A7796 SoC based M3ULCB (R-Car Starter Kit Pro) device tree
> - Document DT bindings
>
> Vladimir Barinov (9):
> [1/9] dt: arm: shmobile: add M3ULCB board DT bindings
I took the liberty of changing the subject of the above patch to:
arm64: dts: m3ulcb: add M3ULCB board DT bindings
> [2/9] arm64: dts: m3ulcb: initial device tree
> [3/9] arm64: dts: m3ulcb: enable SCIF clk and pins
> [4/9] arm64: dts: m3ulcb: enable GPIO leds
> [5/9] arm64: dts: m3ulcb: enable GPIO keys
> [6/9] arm64: dts: m3ulcb: enable SDHI0
> [7/9] arm64: dts: m3ulcb: enable EXTALR clk
> [8/9] arm64: dts: m3ulcb: enable WDT
> [9/9] arm64: dts: m3ulcb: enable SDHI2
I have queued up patches 1-5,7,8.
Please repost the SDHI patches when you are ready.
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^ permalink raw reply
* Re: [PATCH] ARM: tegra: nyan: Enable GPU node and related supply
From: Thierry Reding @ 2016-11-07 13:29 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Alexandre Courbot,
Stephen Warren
In-Reply-To: <20160918141311.17140-1-contact-W9ppeneeCTY@public.gmane.org>
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On Sun, Sep 18, 2016 at 04:13:11PM +0200, Paul Kocialkowski wrote:
> This enables the GPU node for tegra124 nyan boards, which is required to
> get graphics acceleration with nouveau on these devices.
>
> Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
> ---
> arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Applied, thanks.
Thierry
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* Re: [PATCH] ARM: tegra: nyan: Mark all USB ports as host
From: Thierry Reding @ 2016-11-07 13:28 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: linux-kernel, linux-tegra, linux-arm-kernel, devicetree,
Alexandre Courbot, Stephen Warren
In-Reply-To: <20160918102852.6593-1-contact@paulk.fr>
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On Sun, Sep 18, 2016 at 12:28:52PM +0200, Paul Kocialkowski wrote:
> Nyan boards only have host USB ports (2 external, 1 internal), there is
> no OTG-enabled connector.
>
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
> arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Where is this information coming from? I don't have one of the Nyans
myself, but one of the Tegra132 devices I have, which I think was
derived from one of the Nyans uses one of the external host ports as
forced recovery port, for which it would need OTG.
I suspect that the way to get U-Boot onto the Nyans is via tegrarcm?
In that case I think one of the ports must be OTG.
Thierry
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* Re: [PATCH 2/3] arm64: dts: h3ulcb: update header
From: Simon Horman @ 2016-11-07 13:27 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478196294-1021-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Thu, Nov 03, 2016 at 09:04:54PM +0300, Vladimir Barinov wrote:
> This updates H3ULCB device tree header with official board name
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Thanks, I have queued this up.
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* Re: [PATCH 1/3] dt: arm: shmobile: update H3ULCB board Documentation
From: Simon Horman @ 2016-11-07 13:26 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland, devicetree,
linux-renesas-soc
In-Reply-To: <1478196284-982-1-git-send-email-vladimir.barinov@cogentembedded.com>
On Thu, Nov 03, 2016 at 09:04:44PM +0300, Vladimir Barinov wrote:
> This updates H3ULCB Device tree bindings Documentation with
> official board name
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Thanks, I have queued this up after updating the subject to:
arm64: dts: h3ulcb: update documentation with official board name
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: h3ulcb: enable SDHI2
From: Simon Horman @ 2016-11-07 13:23 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478196302-1060-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Thu, Nov 03, 2016 at 09:05:02PM +0300, Vladimir Barinov wrote:
> This supports SDHI2 for H3ULCB onboard eMMC
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> ---
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 ++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> index a244edb..e46687e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
> @@ -55,6 +55,24 @@
> clock-frequency = <24576000>;
> };
>
> + reg_1p8v: regulator0 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator1 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> vcc_sdhi0: regulator-vcc-sdhi0 {
> compatible = "regulator-fixed";
>
> @@ -113,6 +131,18 @@
> function = "sdhi0";
> power-source = <1800>;
> };
> +
> + sdhi2_pins_3v3: sd2_3v3 {
> + groups = "sdhi2_data8", "sdhi2_ctrl";
> + function = "sdhi2";
> + power-source = <3300>;
> + };
> +
> + sdhi2_pins_1v8: sd2_1v8 {
> + groups = "sdhi2_data8", "sdhi2_ctrl";
> + function = "sdhi2";
> + power-source = <1800>;
> + };
I'd prefer if the pin nodes where named as follows:
sdhi2_pins_3v3 -> sdhi2_pins
sdhi2_pins_1v8 -> sdhi2_pins_uhs
And that a patch was provided to rename the SDHI0 nodes to match that scheme.
>
> sound_pins: sound {
> groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
> @@ -128,6 +158,19 @@
> status = "okay";
> };
>
> +&sdhi2 {
> + /* used for on-board 8bit eMMC */
> + pinctrl-0 = <&sdhi2_pins_3v3>;
> + pinctrl-1 = <&sdhi2_pins_1v8>;
> + pinctrl-names = "default", "state_uhs";
> +
> + vmmc-supply = <®_3p3v>;
> + vqmmc-supply = <®_1p8v>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> &ssi1 {
> shared-pin;
> };
> --
> 1.9.1
>
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* [PATCH 6/6] arm: dts: stm32f4: Add external I2S clock
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, amelie.delaunay, kernel, olivier.bideau, linux-kernel,
linux-clk, ludovic.barre, gabriel.fernandez, linux-arm-kernel
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch adds an external I2S clock in the DT.
The I2S clock could be derived from an external I2S clock or by I2S pll.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 2700449..14da6ce 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -68,6 +68,12 @@
compatible = "fixed-clock";
clock-frequency = <32000>;
};
+
+ clk_i2s_ckin: i2s-ckin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
};
soc {
@@ -356,7 +362,7 @@
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
- clocks = <&clk_hse>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 5/6] clk: stm32f4: Add SAI clocks
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, amelie.delaunay, kernel, olivier.bideau, linux-kernel,
linux-clk, ludovic.barre, gabriel.fernandez, linux-arm-kernel
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch introduces SAI clocks for stm32f4 socs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index b7cb359..c305659 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -217,6 +217,7 @@ enum {
PLL_VCO_I2S, PLL_VCO_SAI,
CLK_LCD,
CLK_I2S,
+ CLK_SAI1, CLK_SAI2,
END_PRIMARY_CLK
};
@@ -970,6 +971,9 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
static const char *i2s_parents[2] = { "plli2s-r", NULL };
+static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
+ "no-clock" };
+
struct stm32f4_clk_data {
const struct stm32f4_gate_data *gates_data;
const u64 *gates_map;
@@ -1063,6 +1067,19 @@ static void __init stm32f4_rcc_init(struct device_node *np)
i2s_parents, ARRAY_SIZE(i2s_parents), 0,
base + STM32F4_RCC_CFGR, 23, 1, 0, NULL,
&stm32f4_clk_lock);
+
+ sai_parents[2] = i2s_in_clk;
+
+ clks[CLK_SAI1] = clk_hw_register_mux_table(NULL, "sai1-clk",
+ sai_parents, ARRAY_SIZE(sai_parents), 0,
+ base + STM32F4_RCC_DCKCFGR, 20, 1, 0, NULL,
+ &stm32f4_clk_lock);
+
+ clks[CLK_SAI2] = clk_hw_register_mux_table(NULL, "sai2-clk",
+ sai_parents, ARRAY_SIZE(sai_parents), 0,
+ base + STM32F4_RCC_DCKCFGR, 22, 1, 0, NULL,
+ &stm32f4_clk_lock);
+
sys_parents[1] = hse_clk;
clk_register_mux_table(
NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
--
1.9.1
^ permalink raw reply related
* [PATCH 4/6] clk: stm32f4: Add I2S clock
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, amelie.delaunay, kernel, olivier.bideau, linux-kernel,
linux-clk, ludovic.barre, gabriel.fernandez, linux-arm-kernel
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch introduces I2S clock for stm32f4 soc.
The I2S clock could be derived from an external clock or from pll-i2s
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 5fa5d51..b7cb359 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -216,6 +216,7 @@ enum {
SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC,
PLL_VCO_I2S, PLL_VCO_SAI,
CLK_LCD,
+ CLK_I2S,
END_PRIMARY_CLK
};
@@ -967,6 +968,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
static const char *sdmux_parents[2] = { "pll48", "sys" };
+static const char *i2s_parents[2] = { "plli2s-r", NULL };
+
struct stm32f4_clk_data {
const struct stm32f4_gate_data *gates_data;
const u64 *gates_map;
@@ -1005,7 +1008,7 @@ struct stm32f4_clk_data {
static void __init stm32f4_rcc_init(struct device_node *np)
{
- const char *hse_clk;
+ const char *hse_clk, *i2s_in_clk;
int n;
const struct of_device_id *match;
const struct stm32f4_clk_data *data;
@@ -1038,6 +1041,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
stm32f4_gate_map = data->gates_map;
hse_clk = of_clk_get_parent_name(np, 0);
+ i2s_in_clk = of_clk_get_parent_name(np, 1);
clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
16000000, 160000);
@@ -1053,6 +1057,12 @@ static void __init stm32f4_rcc_init(struct device_node *np)
clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll(pllsrc,
&data->pll_data[2], &stm32f4_clk_lock);
+ i2s_parents[1] = i2s_in_clk;
+
+ clks[CLK_I2S] = clk_hw_register_mux_table(NULL, "i2s",
+ i2s_parents, ARRAY_SIZE(i2s_parents), 0,
+ base + STM32F4_RCC_CFGR, 23, 1, 0, NULL,
+ &stm32f4_clk_lock);
sys_parents[1] = hse_clk;
clk_register_mux_table(
NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
--
1.9.1
^ permalink raw reply related
* [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, kernel,
gabriel.fernandez, ludovic.barre, olivier.bideau, amelie.delaunay
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch adds post dividers of I2S & SAI PLLs.
These dividers are managed by a dedicated register (RCC_DCKCFGR).
The PLL should be off before a set rate.
This patch also introduces the lcd-tft clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index dda15bc..5fa5d51 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -215,6 +215,7 @@ struct stm32f4_gate_data {
enum {
SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC,
PLL_VCO_I2S, PLL_VCO_SAI,
+ CLK_LCD,
END_PRIMARY_CLK
};
@@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char *name,
static const struct clk_div_table pll_divp_table[] = {
{ 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 },
};
+static const struct clk_div_table pll_lcd_div_table[] = {
+ { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 },
+};
/*
* Decode current PLL state and (statically) model the state we inherit from
@@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
clk_register_pll_div(data->p_name, data->vco_name, 0, reg,
16, 2, 0, pll_divp_table, pll_hw, lock);
- if (data->q_name)
+ if (data->q_name) {
clk_register_pll_div(data->q_name, data->vco_name, 0, reg,
24, 4, CLK_DIVIDER_ONE_BASED, NULL,
pll_hw, lock);
- if (data->r_name)
+ if (data->pll_num == PLL_I2S)
+ clk_register_pll_div("plli2s-q-div", data->q_name,
+ 0, base + STM32F4_RCC_DCKCFGR,
+ 0, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
+
+ if (data->pll_num == PLL_SAI)
+ clk_register_pll_div("pllsai-q-div", data->q_name,
+ 0, base + STM32F4_RCC_DCKCFGR,
+ 8, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
+ }
+
+ if (data->r_name) {
clk_register_pll_div(data->r_name, data->vco_name, 0, reg,
28, 3, CLK_DIVIDER_ONE_BASED, NULL, pll_hw,
lock);
+ if (data->pll_num == PLL_SAI)
+ clks[CLK_LCD] = clk_register_pll_div("lcd-tft",
+ data->r_name, CLK_SET_RATE_PARENT,
+ base + STM32F4_RCC_DCKCFGR, 16, 2, 0,
+ pll_lcd_div_table, pll_hw,
+ &stm32f4_clk_lock);
+ }
+
return pll_hw;
}
--
1.9.1
^ permalink raw reply related
* [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, kernel,
gabriel.fernandez, ludovic.barre, olivier.bideau, amelie.delaunay
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com>
From: Gabriel Fernandez <gabriel.fernandez@st.com>
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.
The SDIO clock could be also derived from 48Mhz or from sys clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
drivers/clk/clk-stm32f4.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 7641acd..dda15bc 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -199,7 +199,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
- { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
+ { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
{ STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
@@ -940,6 +940,10 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
"no-clock", "lse", "lsi", "hse-rtc"
};
+static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
+
+static const char *sdmux_parents[2] = { "pll48", "sys" };
+
struct stm32f4_clk_data {
const struct stm32f4_gate_data *gates_data;
const u64 *gates_map;
@@ -1109,6 +1113,18 @@ static void __init stm32f4_rcc_init(struct device_node *np)
goto fail;
}
+ if (of_device_is_compatible(np, "st,stm32f469-rcc")) {
+ clk_hw_register_mux_table(NULL, "pll48",
+ pll48_parents, ARRAY_SIZE(pll48_parents), 0,
+ base + STM32F4_RCC_DCKCFGR, 27, 1, 0, NULL,
+ &stm32f4_clk_lock);
+
+ clk_hw_register_mux_table(NULL, "sdmux",
+ sdmux_parents, ARRAY_SIZE(sdmux_parents), 0,
+ base + STM32F4_RCC_DCKCFGR, 28, 1, 0, NULL,
+ &stm32f4_clk_lock);
+ }
+
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
--
1.9.1
^ permalink raw reply related
* [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
From: gabriel.fernandez-qxv4g6HH51o @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson-QSEj5FYQhm4dnm+yROfE0A,
andrea.merello-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
gabriel.fernandez-qxv4g6HH51o, ludovic.barre-qxv4g6HH51o,
olivier.bideau-qxv4g6HH51o, amelie.delaunay-qxv4g6HH51o
In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez-qxv4g6HH51o@public.gmane.org>
From: Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>
This patch introduces PLL_I2S and PLL_SAI.
Vco clock of these PLLs can be modify by DT (only n multiplicator,
m divider is still fixed by the boot-loader).
Each PLL has 3 dividers. PLL should be off when we modify the rate.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>
---
drivers/clk/clk-stm32f4.c | 371 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 359 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index c2661e2..7641acd 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -28,6 +28,7 @@
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
+#define STM32F4_RCC_CR 0x00
#define STM32F4_RCC_PLLCFGR 0x04
#define STM32F4_RCC_CFGR 0x08
#define STM32F4_RCC_AHB1ENR 0x30
@@ -37,6 +38,9 @@
#define STM32F4_RCC_APB2ENR 0x44
#define STM32F4_RCC_BDCR 0x70
#define STM32F4_RCC_CSR 0x74
+#define STM32F4_RCC_PLLI2SCFGR 0x84
+#define STM32F4_RCC_PLLSAICFGR 0x88
+#define STM32F4_RCC_DCKCFGR 0x8c
struct stm32f4_gate_data {
u8 offset;
@@ -208,7 +212,11 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
};
-enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, END_PRIMARY_CLK };
+enum {
+ SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC,
+ PLL_VCO_I2S, PLL_VCO_SAI,
+ END_PRIMARY_CLK
+};
/*
* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
@@ -324,23 +332,344 @@ static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
return clk;
}
+enum {
+ PLL,
+ PLL_I2S,
+ PLL_SAI,
+};
+
+struct stm32f4_pll {
+ spinlock_t *lock;
+ struct clk_hw hw;
+ u8 offset;
+ u8 bit_idx;
+ u8 bit_rdy_idx;
+ u8 status;
+ u8 n_start;
+};
+
+struct stm32f4_pll_data {
+ u8 pll_num;
+ u8 n_start;
+ const char *vco_name;
+ const char *p_name;
+ const char *q_name;
+ const char *r_name;
+};
+
+static const struct stm32f4_pll_data stm32f429_pll[] = {
+ { PLL, 192, "vco", "pll", "pll48", NULL, },
+ { PLL_I2S, 192, "vco-i2s", NULL, "plli2s-q", "plli2s-r", },
+ { PLL_SAI, 49, "vco-sai", NULL, "pllsai-q", "pllsai-r", },
+};
+
+static const struct stm32f4_pll_data stm32f469_pll[] = {
+ { PLL, 50, "vco", "pll", "pll-q", NULL, },
+ { PLL_I2S, 50, "vco-i2s", NULL, "plli2s-q", "plli2s-r", },
+ { PLL_SAI, 50, "vco-sai", "pllsai-p", "pllsai-q", "pllsai-r", },
+};
+
+#define to_stm32f4_pll(_hw) container_of(_hw, struct stm32f4_pll, hw)
+
+static int stm32f4_pll_is_enabled(struct clk_hw *hw)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+
+ return pll->status;
+}
+
+static int __stm32f4_pll_enable(struct clk_hw *hw)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long reg;
+ int ret = 0;
+
+ if (stm32f4_pll_is_enabled(hw))
+ return 0;
+
+ reg = readl(base + STM32F4_RCC_CR) | (1 << pll->bit_idx);
+ writel(reg, base + STM32F4_RCC_CR);
+
+ ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
+ reg & (1 << pll->bit_rdy_idx), 0, 10000);
+
+ pll->status = 1;
+
+ return ret;
+}
+
+static int stm32f4_pll_enable(struct clk_hw *hw)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ int ret = 0;
+ unsigned long flags = 0;
+
+ if (pll->lock)
+ spin_lock_irqsave(pll->lock, flags);
+
+ ret = __stm32f4_pll_enable(hw);
+
+ if (pll->lock)
+ spin_unlock_irqrestore(pll->lock, flags);
+
+ return ret;
+}
+
+static void __stm32f4_pll_disable(struct clk_hw *hw)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long reg;
+
+ reg = readl(base + STM32F4_RCC_CR) & ~(1 << pll->bit_idx);
+
+ writel(reg, base + STM32F4_RCC_CR);
+
+ pll->status = 0;
+}
+
+static void stm32f4_pll_disable(struct clk_hw *hw)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long flags = 0;
+
+ if (pll->lock)
+ spin_lock_irqsave(pll->lock, flags);
+
+ __stm32f4_pll_disable(hw);
+
+ if (pll->lock)
+ spin_unlock_irqrestore(pll->lock, flags);
+}
+
+static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
+ unsigned long pllm = pllcfgr & 0x3f;
+ unsigned long plln = (readl(base + pll->offset) >> 6) & 0x1ff;
+
+ return (parent_rate / pllm) * plln;
+}
+
+static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
+ unsigned long m = pllcfgr & 0x3f;
+ unsigned long n;
+
+ n = (rate * m) / *prate;
+
+ if (n < pll->n_start)
+ n = pll->n_start;
+ else if (n > 432)
+ n = 432;
+
+ return (*prate / m) * n;
+}
+
+static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct stm32f4_pll *pll = to_stm32f4_pll(hw);
+ unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
+ unsigned long m = pllcfgr & 0x3f;
+ unsigned long n;
+ unsigned long val;
+ int pll_state;
+
+ pll_state = stm32f4_pll_is_enabled(hw);
+
+ if (pll_state)
+ stm32f4_pll_disable(hw);
+
+ n = (rate * m) / parent_rate;
+
+ val = readl(base + pll->offset) & ~(0x1ff << 6);
+
+ writel(val | ((n & 0x1ff) << 6), base + pll->offset);
+
+ if (pll_state)
+ stm32f4_pll_enable(hw);
+
+ return 0;
+}
+
+static const struct clk_ops stm32f4_pll_gate_ops = {
+ .enable = stm32f4_pll_enable,
+ .disable = stm32f4_pll_disable,
+ .is_enabled = stm32f4_pll_is_enabled,
+ .recalc_rate = stm32f4_pll_recalc,
+ .round_rate = stm32f4_pll_round_rate,
+ .set_rate = stm32f4_pll_set_rate,
+};
+
+struct stm32f4_pll_div {
+ struct clk_divider div;
+ struct clk_hw *hw_pll;
+};
+
+#define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
+
+static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return clk_divider_ops.round_rate(hw, rate, prate);
+}
+
+static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int pll_state, ret;
+
+ struct clk_divider *div = to_clk_divider(hw);
+ struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
+
+ pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
+
+ if (pll_state)
+ stm32f4_pll_disable(pll_div->hw_pll);
+
+ ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+ if (pll_state)
+ stm32f4_pll_enable(pll_div->hw_pll);
+
+ return ret;
+}
+
+const struct clk_ops stm32f4_pll_div_ops = {
+ .recalc_rate = stm32f4_pll_div_recalc_rate,
+ .round_rate = stm32f4_pll_div_round_rate,
+ .set_rate = stm32f4_pll_div_set_rate,
+};
+
+static struct clk_hw *clk_register_pll_div(const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags, const struct clk_div_table *table,
+ struct clk_hw *pll_hw, spinlock_t *lock)
+{
+ struct stm32f4_pll_div *pll_div;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ /* allocate the divider */
+ pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
+ if (!pll_div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &stm32f4_pll_div_ops;
+ init.flags = flags;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_divider assignments */
+ pll_div->div.reg = reg;
+ pll_div->div.shift = shift;
+ pll_div->div.width = width;
+ pll_div->div.flags = clk_divider_flags;
+ pll_div->div.lock = lock;
+ pll_div->div.table = table;
+ pll_div->div.hw.init = &init;
+
+ pll_div->hw_pll = pll_hw;
+
+ /* register the clock */
+ hw = &pll_div->div.hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(pll_div);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
+static const struct clk_div_table pll_divp_table[] = {
+ { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 },
+};
+
/*
* Decode current PLL state and (statically) model the state we inherit from
* the bootloader.
*/
-static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
+
+static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
+ const struct stm32f4_pll_data *data, spinlock_t *lock)
{
- unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
+ struct stm32f4_pll *pll;
+ struct clk_init_data init = { NULL };
+ void __iomem *reg;
+ struct clk_hw *pll_hw;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = data->vco_name;
+ init.ops = &stm32f4_pll_gate_ops;
+ init.flags = CLK_IGNORE_UNUSED;
+ init.parent_names = &pllsrc;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+
+ switch (data->pll_num) {
+ case PLL:
+ pll->offset = STM32F4_RCC_PLLCFGR;
+ pll->bit_idx = 24;
+ pll->bit_rdy_idx = 25;
+ break;
+ case PLL_I2S:
+ pll->offset = STM32F4_RCC_PLLI2SCFGR;
+ pll->bit_idx = 26;
+ pll->bit_rdy_idx = 27;
+ break;
+ case PLL_SAI:
+ pll->offset = STM32F4_RCC_PLLSAICFGR;
+ pll->bit_idx = 28;
+ pll->bit_rdy_idx = 29;
+ break;
+ };
+
+ pll->n_start = data->n_start;
+ pll->status = (readl(base + STM32F4_RCC_CR) >> pll->bit_idx) & 0x1;
+ reg = base + pll->offset;
+
+ pll_hw = &pll->hw;
+ ret = clk_hw_register(NULL, pll_hw);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ if (data->p_name)
+ clk_register_pll_div(data->p_name, data->vco_name, 0, reg,
+ 16, 2, 0, pll_divp_table, pll_hw, lock);
+
+ if (data->q_name)
+ clk_register_pll_div(data->q_name, data->vco_name, 0, reg,
+ 24, 4, CLK_DIVIDER_ONE_BASED, NULL,
+ pll_hw, lock);
- unsigned long pllm = pllcfgr & 0x3f;
- unsigned long plln = (pllcfgr >> 6) & 0x1ff;
- unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1);
- const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk;
- unsigned long pllq = (pllcfgr >> 24) & 0xf;
+ if (data->r_name)
+ clk_register_pll_div(data->r_name, data->vco_name, 0, reg,
+ 28, 3, CLK_DIVIDER_ONE_BASED, NULL, pll_hw,
+ lock);
- clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm);
- clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp);
- clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq);
+ return pll_hw;
}
/*
@@ -615,18 +944,24 @@ struct stm32f4_clk_data {
const struct stm32f4_gate_data *gates_data;
const u64 *gates_map;
int gates_num;
+ const struct stm32f4_pll_data *pll_data;
+ int pll_num;
};
static const struct stm32f4_clk_data stm32f429_clk_data = {
.gates_data = stm32f429_gates,
.gates_map = stm32f42xx_gate_map,
.gates_num = ARRAY_SIZE(stm32f429_gates),
+ .pll_data = stm32f429_pll,
+ .pll_num = ARRAY_SIZE(stm32f429_pll),
};
static const struct stm32f4_clk_data stm32f469_clk_data = {
.gates_data = stm32f469_gates,
.gates_map = stm32f46xx_gate_map,
.gates_num = ARRAY_SIZE(stm32f469_gates),
+ .pll_data = stm32f469_pll,
+ .pll_num = ARRAY_SIZE(stm32f469_pll),
};
static const struct of_device_id stm32f4_of_match[] = {
@@ -647,6 +982,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
int n;
const struct of_device_id *match;
const struct stm32f4_clk_data *data;
+ unsigned long pllcfgr;
+ const char *pllsrc;
base = of_iomap(np, 0);
if (!base) {
@@ -677,7 +1014,17 @@ static void __init stm32f4_rcc_init(struct device_node *np)
clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
16000000, 160000);
- stm32f4_rcc_register_pll(hse_clk, "hsi");
+ pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
+ pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
+
+ stm32f4_rcc_register_pll(pllsrc, &data->pll_data[0],
+ &stm32f4_clk_lock);
+
+ clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll(pllsrc,
+ &data->pll_data[1], &stm32f4_clk_lock);
+
+ clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll(pllsrc,
+ &data->pll_data[2], &stm32f4_clk_lock);
sys_parents[1] = hse_clk;
clk_register_mux_table(
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 0/6] Add STM32F4 missing clocks
From: gabriel.fernandez @ 2016-11-07 13:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, daniel.thompson, andrea.merello
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, kernel,
gabriel.fernandez, ludovic.barre, olivier.bideau, amelie.delaunay
From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch-set adds:
- I2S & SAI PLLs
- SDIO & 48 Mhz clocks
- LCD-TFT clock
- I2S & SAI clocks
Gabriel Fernandez (6):
clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board
clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft
clock
clk: stm32f4: Add I2S clock
clk: stm32f4: Add SAI clocks
arm: dts: stm32f4: Add external I2S clock
arch/arm/boot/dts/stm32f429.dtsi | 8 +-
drivers/clk/clk-stm32f4.c | 441 +++++++++++++++++++++++++++++++++++++--
2 files changed, 434 insertions(+), 15 deletions(-)
--
1.9.1
^ permalink raw reply
* Re: [PATCH 6/9] arm64: dts: m3ulcb: enable SDHI0
From: Vladimir Barinov @ 2016-11-07 13:05 UTC (permalink / raw)
To: Simon Horman
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161107130054.GG12319-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Hi Simon,
On 07.11.2016 16:00, Simon Horman wrote:
> On Thu, Nov 03, 2016 at 09:07:51PM +0300, Vladimir Barinov wrote:
>> This supports SDHI0 on M3ULCB board SD card slot
> Is SDHI3 also exposed on the M3ULCB?
No, SDHI3 is not exposed on M3ULCB.
Only SDHI0 exposed to SD slot and SDHI2 as eMMC.
> If so could you consider sending patches to enable it?
>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 48 ++++++++++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> index 3329f78..5be0cf6 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> @@ -44,6 +44,30 @@
>> gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
>> };
>> };
>> +
>> + vcc_sdhi0: regulator-vcc-sdhi0 {
>> + compatible = "regulator-fixed";
>> +
>> + regulator-name = "SDHI0 Vcc";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + vccq_sdhi0: regulator-vccq-sdhi0 {
>> + compatible = "regulator-gpio";
>> +
>> + regulator-name = "SDHI0 VccQ";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
>> + gpios-states = <1>;
>> + states = <3300000 1
>> + 1800000 0>;
>> + };
>> };
>>
>> &extal_clk {
>> @@ -68,8 +92,33 @@
>> groups = "scif_clk_a";
>> function = "scif_clk";
>> };
>> +
>> + sdhi0_pins_3v3: sd0_3v3 {
>> + groups = "sdhi0_data4", "sdhi0_ctrl";
>> + function = "sdhi0";
>> + power-source = <3300>;
>> + };
>> +
>> + sdhi0_pins_1v8: sd0_1v8 {
>> + groups = "sdhi0_data4", "sdhi0_ctrl";
>> + function = "sdhi0";
>> + power-source = <1800>;
>> + };
> I would prefer the pin nodes to be named as follows:
>
> sdhi0_pins_3v3 -> sdhi0_pins_3v3
> sdhi0_pins_1v8 -> sdhi0_pins_uhs
>
> Likewise for SDHI2.
Okay, I will resend these changes in the next try.
Regards,
Vladimir
>
>> };
>>
>> +&sdhi0 {
>> + pinctrl-0 = <&sdhi0_pins_3v3>;
>> + pinctrl-1 = <&sdhi0_pins_1v8>;
>> + pinctrl-names = "default", "state_uhs";
>> +
>> + vmmc-supply = <&vcc_sdhi0>;
>> + vqmmc-supply = <&vccq_sdhi0>;
>> + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
>> + bus-width = <4>;
>> + sd-uhs-sdr50;
>> + status = "okay";
>> +};
>> +
>> &scif2 {
>> pinctrl-0 = <&scif2_pins>;
>> pinctrl-names = "default";
>> --
>> 1.9.1
>>
--
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^ permalink raw reply
* Re: [PATCH 4/9] arm64: dts: m3ulcb: enable GPIO leds
From: Vladimir Barinov @ 2016-11-07 13:02 UTC (permalink / raw)
To: Simon Horman
Cc: Magnus Damm, Rob Herring, Mark Rutland, devicetree,
linux-renesas-soc
In-Reply-To: <20161107125737.GF12319@verge.net.au>
Hi Simon,
On 07.11.2016 15:57, Simon Horman wrote:
> On Thu, Nov 03, 2016 at 09:07:31PM +0300, Vladimir Barinov wrote:
>> This supports GPIO leds on M3ULCB board
> Are GPIO leds and keys also present on the H3ULCB.
Yes.
> If so could you consider sending patches to enable them?
H3ULCB already includes GPIO leds and keys support in upstream kernel.
Regards,
Vladimir
>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> ---
>> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> index fb694b8..3329f78 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
>> @@ -31,6 +31,17 @@
>> /* first 128MB is reserved for secure area. */
>> reg = <0x0 0x48000000 0x0 0x38000000>;
>> };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> +
>> + led5 {
>> + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
>> + };
>> + led6 {
>> + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
>> + };
>> + };
>> };
>>
>> &extal_clk {
>> --
>> 1.9.1
>>
^ permalink raw reply
* Re: [PATCH 1/3] ipmi/bt-bmc: change compatible node to 'aspeed, ast2400-ibt-bmc'
From: Arnd Bergmann @ 2016-11-07 13:02 UTC (permalink / raw)
To: Cédric Le Goater
Cc: devicetree, Corey Minyard, Benjamin Herrenschmidt, Rob Herring,
Joel Stanley, openipmi-developer, linux-arm-kernel
In-Reply-To: <ebeba60f-429f-fb84-b9da-c27d11d23094@kaod.org>
On Wednesday, November 2, 2016 3:28:01 PM CET Cédric Le Goater wrote:
> On 11/02/2016 02:56 PM, Joel Stanley wrote:
> > On Wed, Nov 2, 2016 at 11:45 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> >> On Wednesday 02 November 2016, Cédric Le Goater wrote:
> >>> The Aspeed SoCs have two BT interfaces : one is IPMI compliant and the
> >>> other is H8S/2168 compliant.
> >>>
> >>> The current ipmi/bt-bmc driver implements the IPMI version and we
> >>> should reflect its nature in the compatible node name using
> >>> 'aspeed,ast2400-ibt-bmc' instead of 'aspeed,ast2400-bt-bmc'. The
> >>> latter should be used for a H8S interface driver if it is implemented
> >>> one day.
> >>>
> >>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >>
> >> We generally try to avoid changing the compatible strings after the
> >> fact, but it's probably ok in this case.
>
> As the device tree changes are not merged yet, we thought we had some
> more time to fine tune the naming.
Ok, I see. No problem then.
> >> I don't understand who decides which of the two interfaces is used:
> >> is it the same register set that can be driven by either one or the
> >> other driver, or do you expect to have two drivers that can both
> >> be active in the same system and talk to different hardware once
> >> you get there?
> >
> > It's the second case. The H8S BT has a different register layout so it
> > would require a different driver.
>
> yes.
>
> > We don't yet have a driver for the other BT device, but there was
> > recent talk of using it as an alternate (non-ipmi channel) between the
> > BMC and the host. Before that discussion I wasn't aware that the H8S
> > BT existed. I suggested we fix this up before it hits a final release.
> >
> > Cédric, do you think ast2400-ibt-bmc or ast2400-ipmi-bt-bmc does a
> > better job of describing the hardware here?
>
> The specs refer to the two interfaces as BT (non IPMI) and iBT (IPMI).
> I think we can keep the same naming.
Ok
> > While we're modifying the binding, should we add a compat string for
> > the ast2500?
>
> Well, if the change in this patch is fine for all, may be we can add
> the ast2500 compat string in a followup patch ?
Sounds good to me.
Arnd
------------------------------------------------------------------------------
Developer Access Program for Intel Xeon Phi Processors
Access to Intel Xeon Phi processor-based developer platforms.
With one year of Intel Parallel Studio XE.
Training and support from Colfax.
Order your platform today. http://sdm.link/xeonphi
^ permalink raw reply
* Re: [PATCH] serial: tegra20-hsuart: fix typo in dmas DT binding description
From: Thierry Reding @ 2016-11-07 13:01 UTC (permalink / raw)
To: Mirza Krak
Cc: swarren-3lzwWm7+Weoh9ZMKESR00Q, gnurou-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1468787481-27753-1-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 505 bytes --]
On Sun, Jul 17, 2016 at 10:31:21PM +0200, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> The description for dmas references a second property, which should be
> "dma-names" instead of "clock-names".
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: William Wu @ 2016-11-07 13:00 UTC (permalink / raw)
To: kishon-l0cyMroinI0, heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: huangtao-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA, groeck-hpIqsD4AKlfQT0dZR+AlfA,
frank.wang-TNX95d0MmH7DzftRWevZcw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dianders-hpIqsD4AKlfQT0dZR+AlfA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, wulf-TNX95d0MmH7DzftRWevZcw,
briannorris-hpIqsD4AKlfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a critical value for 480MHz
output clock stable time, so we try to change the delay time
to 1.2 millisecond to avoid this issue.
Signed-off-by: William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index ecfd7d1..8f2d2b6 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -267,7 +267,7 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
return ret;
/* waitting for the clk become stable */
- mdelay(1);
+ udelay(1200);
}
return 0;
--
2.0.0
^ permalink raw reply related
* Re: [PATCH 6/9] arm64: dts: m3ulcb: enable SDHI0
From: Simon Horman @ 2016-11-07 13:00 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland, devicetree,
linux-renesas-soc
In-Reply-To: <1478196471-1381-1-git-send-email-vladimir.barinov@cogentembedded.com>
On Thu, Nov 03, 2016 at 09:07:51PM +0300, Vladimir Barinov wrote:
> This supports SDHI0 on M3ULCB board SD card slot
Is SDHI3 also exposed on the M3ULCB?
If so could you consider sending patches to enable it?
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> ---
> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 48 ++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> index 3329f78..5be0cf6 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> @@ -44,6 +44,30 @@
> gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
> };
> };
> +
> + vcc_sdhi0: regulator-vcc-sdhi0 {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "SDHI0 Vcc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + vccq_sdhi0: regulator-vccq-sdhi0 {
> + compatible = "regulator-gpio";
> +
> + regulator-name = "SDHI0 VccQ";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
> + gpios-states = <1>;
> + states = <3300000 1
> + 1800000 0>;
> + };
> };
>
> &extal_clk {
> @@ -68,8 +92,33 @@
> groups = "scif_clk_a";
> function = "scif_clk";
> };
> +
> + sdhi0_pins_3v3: sd0_3v3 {
> + groups = "sdhi0_data4", "sdhi0_ctrl";
> + function = "sdhi0";
> + power-source = <3300>;
> + };
> +
> + sdhi0_pins_1v8: sd0_1v8 {
> + groups = "sdhi0_data4", "sdhi0_ctrl";
> + function = "sdhi0";
> + power-source = <1800>;
> + };
I would prefer the pin nodes to be named as follows:
sdhi0_pins_3v3 -> sdhi0_pins_3v3
sdhi0_pins_1v8 -> sdhi0_pins_uhs
Likewise for SDHI2.
> };
>
> +&sdhi0 {
> + pinctrl-0 = <&sdhi0_pins_3v3>;
> + pinctrl-1 = <&sdhi0_pins_1v8>;
> + pinctrl-names = "default", "state_uhs";
> +
> + vmmc-supply = <&vcc_sdhi0>;
> + vqmmc-supply = <&vccq_sdhi0>;
> + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + sd-uhs-sdr50;
> + status = "okay";
> +};
> +
> &scif2 {
> pinctrl-0 = <&scif2_pins>;
> pinctrl-names = "default";
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH] ARM: tegra: nyan: Enable GPU node and related supply
From: Jon Hunter @ 2016-11-07 13:00 UTC (permalink / raw)
To: Alexandre Courbot, Thierry Reding
Cc: Paul Kocialkowski, Linux Kernel Mailing List,
linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, Stephen Warren
In-Reply-To: <CAAVeFuLb5gU70B0jP0YNPB58NcuR_D0e--6zn3dG7VOmZafLRA@mail.gmail.com>
Thierry,
On 07/11/16 12:51, Alexandre Courbot wrote:
> On Wed, Sep 21, 2016 at 4:57 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>
>> On 20/09/16 19:17, Paul Kocialkowski wrote:
>>> * PGP Signed by an unknown key
>>>
>>> Le mardi 20 septembre 2016 à 13:24 +0100, Jon Hunter a écrit :
>>>> On 18/09/16 15:13, Paul Kocialkowski wrote:
>>>>>
>>>>> This enables the GPU node for tegra124 nyan boards, which is required to
>>>>> get graphics acceleration with nouveau on these devices.
>>>>>
>>>>> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
>>>>> ---
>>>>> arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +++++++-
>>>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>>> b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>>> index dab9509..225ca77 100644
>>>>> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>>> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>>> @@ -42,6 +42,12 @@
>>>>> };
>>>>> };
>>>>>
>>>>> + gpu@0,57000000 {
>>>>> + status = "okay";
>>>>> +
>>>>> + vdd-supply = <&vdd_gpu>;
>>>>> + };
>>>>> +
>>>>> serial@70006000 {
>>>>> /* Debug connector on the bottom of the board near SD card.
>>>>> */
>>>>> status = "okay";
>>>>> @@ -214,7 +220,7 @@
>>>>> regulator-always-on;
>>>>> };
>>>>>
>>>>> - sd6 {
>>>>> + vdd_gpu: sd6 {
>>>>> regulator-name = "+VDD_GPU_AP";
>>>>> regulator-min-microvolt = <650000>;
>>>>> regulator-max-microvolt =
>>>>> <1200000>;
>>>>>
>>>>
>>>> Looks good to me. I see the following error when booting but looking at the
>>>> code appears to be benign. Thierry, Alex, is this normal/okay?
>>>
>>> I have the same messages and asked Alexandre about them the other day. He told
>>> me that it looks normal.
>>
>> Ok great. Hopefully, Alex can ACK then.
>
> Apologies for the (very) delayed reply.
>
> Yes, the messages you are seeing are part of the normal probe sequence
> on Tegra. So this looks good to me.
>
> Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Can you pick this one up for v4.10 as well?
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 4/9] arm64: dts: m3ulcb: enable GPIO leds
From: Simon Horman @ 2016-11-07 12:57 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478196451-1298-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Thu, Nov 03, 2016 at 09:07:31PM +0300, Vladimir Barinov wrote:
> This supports GPIO leds on M3ULCB board
Are GPIO leds and keys also present on the H3ULCB.
If so could you consider sending patches to enable them?
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> ---
> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> index fb694b8..3329f78 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
> @@ -31,6 +31,17 @@
> /* first 128MB is reserved for secure area. */
> reg = <0x0 0x48000000 0x0 0x38000000>;
> };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led5 {
> + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
> + };
> + led6 {
> + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
> + };
> + };
> };
>
> &extal_clk {
> --
> 1.9.1
>
--
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^ permalink raw reply
* Re: [PATCH V4 5/6] ARM: tegra: Add Tegra20 GMI support
From: Thierry Reding @ 2016-11-07 12:56 UTC (permalink / raw)
To: Mirza Krak
Cc: swarren-3lzwWm7+Weoh9ZMKESR00Q, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478507405-13204-6-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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On Mon, Nov 07, 2016 at 09:30:04AM +0100, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add a device node for the GMI controller found on Tegra20.
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>
> Changes in v2:
> - added address-cells, size-cells and ranges properties
>
> Changes in v3:
> - fixed range address which is not the same as Tegra30.
>
> Changes in v4:
> - removed extra newline and a initial space in resets property.
>
> arch/arm/boot/dts/tegra20.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Applied, thanks.
Thierry
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^ permalink raw reply
* Re: [PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support
From: Thierry Reding @ 2016-11-07 12:56 UTC (permalink / raw)
To: Mirza Krak
Cc: swarren-3lzwWm7+Weoh9ZMKESR00Q, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478507405-13204-5-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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On Mon, Nov 07, 2016 at 09:30:03AM +0100, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add a device node for the GMI controller found on Tegra30.
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>
> Changes in v2:
> - added address-cells, size-cells and ranges properties
>
> Changes in v3:
> - no changes
>
> Changes in v4:
> - no changes
>
> arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Applied, thanks.
Thierry
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^ permalink raw reply
* Re: [PATCH] ARM: tegra: nyan: Enable GPU node and related supply
From: Alexandre Courbot @ 2016-11-07 12:51 UTC (permalink / raw)
To: Jon Hunter
Cc: Paul Kocialkowski, Linux Kernel Mailing List, Thierry Reding,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Stephen Warren
In-Reply-To: <e95335ae-ad19-b8cd-634b-63c6a0b88e01-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Wed, Sep 21, 2016 at 4:57 PM, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>
> On 20/09/16 19:17, Paul Kocialkowski wrote:
>> * PGP Signed by an unknown key
>>
>> Le mardi 20 septembre 2016 à 13:24 +0100, Jon Hunter a écrit :
>>> On 18/09/16 15:13, Paul Kocialkowski wrote:
>>>>
>>>> This enables the GPU node for tegra124 nyan boards, which is required to
>>>> get graphics acceleration with nouveau on these devices.
>>>>
>>>> Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
>>>> ---
>>>> arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +++++++-
>>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>> b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>> index dab9509..225ca77 100644
>>>> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>>> @@ -42,6 +42,12 @@
>>>> };
>>>> };
>>>>
>>>> + gpu@0,57000000 {
>>>> + status = "okay";
>>>> +
>>>> + vdd-supply = <&vdd_gpu>;
>>>> + };
>>>> +
>>>> serial@70006000 {
>>>> /* Debug connector on the bottom of the board near SD card.
>>>> */
>>>> status = "okay";
>>>> @@ -214,7 +220,7 @@
>>>> regulator-always-on;
>>>> };
>>>>
>>>> - sd6 {
>>>> + vdd_gpu: sd6 {
>>>> regulator-name = "+VDD_GPU_AP";
>>>> regulator-min-microvolt = <650000>;
>>>> regulator-max-microvolt =
>>>> <1200000>;
>>>>
>>>
>>> Looks good to me. I see the following error when booting but looking at the
>>> code appears to be benign. Thierry, Alex, is this normal/okay?
>>
>> I have the same messages and asked Alexandre about them the other day. He told
>> me that it looks normal.
>
> Ok great. Hopefully, Alex can ACK then.
Apologies for the (very) delayed reply.
Yes, the messages you are seeing are part of the normal probe sequence
on Tegra. So this looks good to me.
Acked-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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