* [v16, 7/7] mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0
From: Yangbo Lu @ 2016-11-09 3:14 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Scott Wood, Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, Xiaobo Xie, Minghuan Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Qiang Zhao, Russell King,
Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Yangbo Lu,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1478661252-42439-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version.
Acturally the right version numbers should be VVN=0x13 and SVN = 0x1.
This patch adds the GUTS driver support for eSDHC driver to match SoC.
And fix host version to avoid that incorrect version numbers break down
the ADMA data transfer.
Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Acked-by: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
Changes for v2:
- Got SVR through iomap instead of dts
Changes for v3:
- Managed GUTS through syscon instead of iomap in eSDHC driver
Changes for v4:
- Got SVR by GUTS driver instead of SYSCON
Changes for v5:
- Changed to get SVR through API fsl_guts_get_svr()
- Combined patch 4, patch 5 and patch 6 into one
Changes for v6:
- Added 'Acked-by: Ulf Hansson'
Changes for v7:
- None
Changes for v8:
- Added 'Acked-by: Scott Wood'
Changes for v9:
- None
Changes for v10:
- None
Changes for v11:
- Changed to use soc_device_match
Changes for v12:
- Matched soc through .family field instead of .soc_id
Changes for v13:
- None
Changes for v14:
- None
Changes for v15:
- None
Changes for v16:
- Added 'Acked-by: Arnd'
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-of-esdhc.c | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5cf7eba..4128a3c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -144,6 +144,7 @@ config MMC_SDHCI_OF_ESDHC
depends on MMC_SDHCI_PLTFM
depends on PPC || ARCH_MXC || ARCH_LAYERSCAPE
select MMC_SDHCI_IO_ACCESSORS
+ select FSL_GUTS
help
This selects the Freescale eSDHC controller support.
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index fb71c86..57bdb9e 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/module.h>
+#include <linux/sys_soc.h>
#include <linux/mmc/host.h>
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"
@@ -28,6 +29,7 @@
struct sdhci_esdhc {
u8 vendor_ver;
u8 spec_ver;
+ bool quirk_incorrect_hostver;
};
/**
@@ -73,6 +75,8 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host,
static u16 esdhc_readw_fixup(struct sdhci_host *host,
int spec_reg, u32 value)
{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
u16 ret;
int shift = (spec_reg & 0x2) * 8;
@@ -80,6 +84,12 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host,
ret = value & 0xffff;
else
ret = (value >> shift) & 0xffff;
+ /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
+ * vendor version and spec version information.
+ */
+ if ((spec_reg == SDHCI_HOST_VERSION) &&
+ (esdhc->quirk_incorrect_hostver))
+ ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
return ret;
}
@@ -558,6 +568,12 @@ static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
.ops = &sdhci_esdhc_le_ops,
};
+static struct soc_device_attribute soc_incorrect_hostver[] = {
+ { .family = "QorIQ T4240", .revision = "1.0", },
+ { .family = "QorIQ T4240", .revision = "2.0", },
+ { },
+};
+
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host;
@@ -571,6 +587,10 @@ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT;
esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
+ if (soc_device_match(soc_incorrect_hostver))
+ esdhc->quirk_incorrect_hostver = true;
+ else
+ esdhc->quirk_incorrect_hostver = false;
}
static int sdhci_esdhc_probe(struct platform_device *pdev)
--
2.1.0.27.g96db324
^ permalink raw reply related
* RE: [PATCH 1/2] gpio: xilinx: dt-binding: Add clock node
From: Shubhrajyoti Datta @ 2016-11-09 4:25 UTC (permalink / raw)
To: Soren Brinkmann
Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
michal.simek@xilinx.com
In-Reply-To: <20161108144846.GQ14444@xsjsorenbubuntu>
Hi Soren,
> -----Original Message-----
> From: Sören Brinkmann [mailto:soren.brinkmann@xilinx.com]
> Sent: Tuesday, November 08, 2016 8:19 PM
<snip>
> > +- clock-names: Input clock name
>
> Clock names are driver specific and must be documented here.
Will do thanks.
>
> >
> >
> > Example:
> > gpio: gpio@40000000 {
> > #gpio-cells = <2>;
> > compatible = "xlnx,xps-gpio-1.00.a";
> > + clocks = <&clkc 15>;
>
> Where are the clock-names?
Will add.
>
> Sören
^ permalink raw reply
* [PATCHv2 1/2] gpio: xilinx: dt-binding: Add clock node
From: Shubhrajyoti Datta @ 2016-11-09 5:09 UTC (permalink / raw)
To: linux-gpio, devicetree
Cc: soren.brinkmann, michal.simek, shubhrajyoti.datta,
Shubhrajyoti Datta
Add the clock node to the dt binding.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v2:
Make clocks optional
Add clock name
.../devicetree/bindings/gpio/gpio-xilinx.txt | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
index 63bf4be..1372007 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
@@ -25,12 +25,16 @@ Optional properties:
- xlnx,dout-default-2 : as above but the second channel
- xlnx,gpio2-width : as above but for the second channel
- xlnx,tri-default-2 : as above but for the second channel
+- clocks: Input clock specifier. Refer to common clock bindings.
+- clock-names: Input clock name, should be s_axi_aclk.
Example:
gpio: gpio@40000000 {
#gpio-cells = <2>;
compatible = "xlnx,xps-gpio-1.00.a";
+ clocks = <&clkc 15>;
+ clock-names = "s_axi_aclk";
gpio-controller ;
interrupt-parent = <µblaze_0_intc>;
interrupts = < 6 2 >;
--
1.7.1
^ permalink raw reply related
* [PATCHv2 2/2] gpio: xilinx: Add clock support
From: Shubhrajyoti Datta @ 2016-11-09 5:09 UTC (permalink / raw)
To: linux-gpio, devicetree
Cc: soren.brinkmann, michal.simek, shubhrajyoti.datta,
Shubhrajyoti Datta
In-Reply-To: <1478668191-26322-1-git-send-email-shubhrajyoti.datta@xilinx.com>
Add basic clock support for xilinx gpio.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v2 :
no change
drivers/gpio/gpio-xilinx.c | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 14b2a62..923cab8 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -13,6 +13,7 @@
*/
#include <linux/bitops.h>
+#include <linux/clk.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/module.h>
@@ -45,6 +46,7 @@
* @gpio_state: GPIO state shadow register
* @gpio_dir: GPIO direction shadow register
* @gpio_lock: Lock used for synchronization
+ * @clk: Clock resource for this controller
*/
struct xgpio_instance {
struct of_mm_gpio_chip mmchip;
@@ -52,6 +54,7 @@ struct xgpio_instance {
u32 gpio_state[2];
u32 gpio_dir[2];
spinlock_t gpio_lock[2];
+ struct clk *clk;
};
static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
@@ -282,6 +285,7 @@ static int xgpio_remove(struct platform_device *pdev)
struct xgpio_instance *chip = platform_get_drvdata(pdev);
of_mm_gpiochip_remove(&chip->mmchip);
+ clk_disable_unprepare(chip->clk);
return 0;
}
@@ -307,6 +311,23 @@ static int xgpio_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, chip);
+ /* Retrieve GPIO clock */
+ chip->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(chip->clk)) {
+ if (PTR_ERR(chip->clk) == -ENOENT) {
+ dev_info(&pdev->dev, "No clocks found for clk\n");
+ chip->clk = NULL;
+ } else {
+ dev_err(&pdev->dev, "axi clock error\n");
+ return PTR_ERR(chip->clk);
+ }
+ }
+ status = clk_prepare_enable(chip->clk);
+ if (status) {
+ dev_err(&pdev->dev, "Unable to enable clock.\n");
+ return status;
+ }
+
/* Update GPIO state shadow register with default value */
of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
@@ -362,6 +383,7 @@ static int xgpio_probe(struct platform_device *pdev)
if (status) {
pr_err("%s: error in probe function with status %d\n",
np->full_name, status);
+ clk_disable_unprepare(chip->clk);
return status;
}
--
1.7.1
^ permalink raw reply related
* Re: [PATCHv2 2/2] gpio: xilinx: Add clock support
From: Sören Brinkmann @ 2016-11-09 6:27 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA,
shubhrajyoti.datta-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1478668191-26322-2-git-send-email-shubhrajyoti.datta-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
On Wed, 2016-11-09 at 10:39:51 +0530, Shubhrajyoti Datta wrote:
> Add basic clock support for xilinx gpio.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> ---
> v2 :
> no change
>
> drivers/gpio/gpio-xilinx.c | 22 ++++++++++++++++++++++
> 1 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
> index 14b2a62..923cab8 100644
> --- a/drivers/gpio/gpio-xilinx.c
> +++ b/drivers/gpio/gpio-xilinx.c
> @@ -13,6 +13,7 @@
> */
>
> #include <linux/bitops.h>
> +#include <linux/clk.h>
> #include <linux/init.h>
> #include <linux/errno.h>
> #include <linux/module.h>
> @@ -45,6 +46,7 @@
> * @gpio_state: GPIO state shadow register
> * @gpio_dir: GPIO direction shadow register
> * @gpio_lock: Lock used for synchronization
> + * @clk: Clock resource for this controller
> */
> struct xgpio_instance {
> struct of_mm_gpio_chip mmchip;
> @@ -52,6 +54,7 @@ struct xgpio_instance {
> u32 gpio_state[2];
> u32 gpio_dir[2];
> spinlock_t gpio_lock[2];
> + struct clk *clk;
> };
>
> static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
> @@ -282,6 +285,7 @@ static int xgpio_remove(struct platform_device *pdev)
> struct xgpio_instance *chip = platform_get_drvdata(pdev);
>
> of_mm_gpiochip_remove(&chip->mmchip);
> + clk_disable_unprepare(chip->clk);
>
> return 0;
> }
> @@ -307,6 +311,23 @@ static int xgpio_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, chip);
>
> + /* Retrieve GPIO clock */
> + chip->clk = devm_clk_get(&pdev->dev, NULL);
The driver should use the clock-name documented in the binding to do the
clock lookup.
> + if (IS_ERR(chip->clk)) {
> + if (PTR_ERR(chip->clk) == -ENOENT) {
> + dev_info(&pdev->dev, "No clocks found for clk\n");
This is pretty much just noise. The clocks property is optional. No need
to be too verbose about that. It would be quite a lot of printing if
every driver would report absent optional DT properties.
Sören
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^ permalink raw reply
* Re: [PATCHv2 2/2] gpio: xilinx: Add clock support
From: Shubhrajyoti Datta @ 2016-11-09 6:46 UTC (permalink / raw)
To: Sören Brinkmann
Cc: Shubhrajyoti Datta, linux-gpio, devicetree, Michal Simek
In-Reply-To: <20161109062734.GX14444@xsjsorenbubuntu>
On Wed, Nov 9, 2016 at 11:57 AM, Sören Brinkmann
<soren.brinkmann@xilinx.com> wrote:
> On Wed, 2016-11-09 at 10:39:51 +0530, Shubhrajyoti Datta wrote:
>> Add basic clock support for xilinx gpio.
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>> ---
>> v2 :
>> no change
>>
>> drivers/gpio/gpio-xilinx.c | 22 ++++++++++++++++++++++
>> 1 files changed, 22 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
>> index 14b2a62..923cab8 100644
>> --- a/drivers/gpio/gpio-xilinx.c
>> +++ b/drivers/gpio/gpio-xilinx.c
>> @@ -13,6 +13,7 @@
>> */
>>
>> #include <linux/bitops.h>
>> +#include <linux/clk.h>
>> #include <linux/init.h>
>> #include <linux/errno.h>
>> #include <linux/module.h>
>> @@ -45,6 +46,7 @@
>> * @gpio_state: GPIO state shadow register
>> * @gpio_dir: GPIO direction shadow register
>> * @gpio_lock: Lock used for synchronization
>> + * @clk: Clock resource for this controller
>> */
>> struct xgpio_instance {
>> struct of_mm_gpio_chip mmchip;
>> @@ -52,6 +54,7 @@ struct xgpio_instance {
>> u32 gpio_state[2];
>> u32 gpio_dir[2];
>> spinlock_t gpio_lock[2];
>> + struct clk *clk;
>> };
>>
>> static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
>> @@ -282,6 +285,7 @@ static int xgpio_remove(struct platform_device *pdev)
>> struct xgpio_instance *chip = platform_get_drvdata(pdev);
>>
>> of_mm_gpiochip_remove(&chip->mmchip);
>> + clk_disable_unprepare(chip->clk);
>>
>> return 0;
>> }
>> @@ -307,6 +311,23 @@ static int xgpio_probe(struct platform_device *pdev)
>>
>> platform_set_drvdata(pdev, chip);
>>
>> + /* Retrieve GPIO clock */
>> + chip->clk = devm_clk_get(&pdev->dev, NULL);
>
> The driver should use the clock-name documented in the binding to do the
> clock lookup.
My idea was to keep the clk name optional since there is only one clock.
Or do you think we should mandate the name if clk is provided.
>
>> + if (IS_ERR(chip->clk)) {
>> + if (PTR_ERR(chip->clk) == -ENOENT) {
>> + dev_info(&pdev->dev, "No clocks found for clk\n");
>
> This is pretty much just noise. The clocks property is optional. No need
> to be too verbose about that. It would be quite a lot of printing if
> every driver would report absent optional DT properties.
Ok will remove the print
>
> Sören
^ permalink raw reply
* Re: [PATCH 6/9 v2] arm64: dts: m3ulcb: enable SDHI0
From: Simon Horman @ 2016-11-09 7:44 UTC (permalink / raw)
To: Vladimir Barinov
Cc: Magnus Damm, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478614461-9918-1-git-send-email-vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Tue, Nov 08, 2016 at 05:14:21PM +0300, Vladimir Barinov wrote:
> This supports SDHI0 on M3ULCB board SD card slot
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> Reviewed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Thanks Vladimir,
I have queued up the following patches:
arm64: dts: h3ulcb: rename SDHI0 pins
arm64: dts: h3ulcb: enable SDHI2
arm64: dts: m3ulcb: enable SDHI2
arm64: dts: m3ulcb: enable SDHI0
For reference I would, however, like to make some comments regarding the
way you have submitted these:
1. I did not provide a Reviewed-off-by tag or any other tag as far as I
recall. So its not appropriate for you to add one when posting patches.
I have removed it.
2. Not withstanding the above, Reviewed-off-by is an invalid tag.
Perhaps you mean Reviewed-by.
3. When you repost patches I have a slight preference for you to repost
them in a fresh thread. And if the patchset has more than one patch then
with a fresh cover letter. This makes it a little easier for me
to see what is going on. And gives a more natural place for
me to respond to a patchset.
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 01/30] usb: dwc2: Deprecate g-use-dma binding
From: Felipe Balbi @ 2016-11-09 7:53 UTC (permalink / raw)
To: John Youn
In-Reply-To: <6e90b835-73b1-3970-24a4-eab72381b469-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 3378 bytes --]
Hi,
John Youn <John.Youn-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> writes:
> On 11/8/2016 1:12 AM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> writes:
>>> Add a vendor prefix and make the name more consistent by renaming it to
>>> "snps,gadget-dma-enable".
>>>
>>> Signed-off-by: John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
>>> ---
>>> Documentation/devicetree/bindings/usb/dwc2.txt | 5 ++++-
>>> arch/arm/boot/dts/rk3036.dtsi | 2 +-
>>> arch/arm/boot/dts/rk3288.dtsi | 2 +-
>>> arch/arm/boot/dts/rk3xxx.dtsi | 2 +-
>>> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +-
>>> arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +-
>>> drivers/usb/dwc2/params.c | 9 ++++++++-
>>> drivers/usb/dwc2/pci.c | 2 +-
>>> 8 files changed, 18 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
>>> index 9472111..389a461 100644
>>> --- a/Documentation/devicetree/bindings/usb/dwc2.txt
>>> +++ b/Documentation/devicetree/bindings/usb/dwc2.txt
>>> @@ -26,11 +26,14 @@ Refer to phy/phy-bindings.txt for generic phy consumer properties
>>> - dr_mode: shall be one of "host", "peripheral" and "otg"
>>> Refer to usb/generic.txt
>>> - snps,host-dma-disable: disable host DMA mode.
>>> -- g-use-dma: enable dma usage in gadget driver.
>>> +- snps,gadget-dma-enable: enable gadget DMA mode.
>>
>> I don't see why you even have this binding. Looking through the code,
>> you have:
>>
>> #define GHWCFG2_SLAVE_ONLY_ARCH 0
>> #define GHWCFG2_EXT_DMA_ARCH 1
>> #define GHWCFG2_INT_DMA_ARCH 2
>>
>> void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
>> {
>> int valid = 1;
>>
>> if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
>> valid = 0;
>> if (val < 0)
>> valid = 0;
>>
>> if (!valid) {
>> if (val >= 0)
>> dev_err(hsotg->dev,
>> "%d invalid for dma_enable parameter. Check HW configuration.\n",
>> val);
>> val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
>> dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
>> }
>>
>> hsotg->core_params->dma_enable = val;
>> }
>>
>> which seems to hint that DMA support is discoverable. If there is DMA,
>> why would disable it?
>>
>
> Yes that's the case and I would prefer to make it discoverable and
> enabled by default.
>
> But the legacy behavior has always been like this because DMA was
> never fully implemented in the gadget driver and it was an opt-in
> feature. Periodic support was only added recently.
legacy behavior can be changed if another 'policy' makes more
sense. IMHO, whatever can be discovered in runtime, should be enabled by
default. That way, we force people to use it and find bugs in certain
features.
> What do you think about enabling it by default now? I think most
> platforms already use DMA.
I think it should be discovered. Drop all these "*-use-dma" bindings
because they're not needed if you can probe a register to answer the
same question.
> We would still need a "disable" binding for IP validation purposes at
> least.
Yeah, could be a quirk.
--
balbi
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^ permalink raw reply
* 1804 devicetree
From: sushildhimanphotography-/E1597aS9LQAvxtiuMwx3w @ 2016-11-09 7:54 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: MESSAGE_077122902700505_devicetree.zip --]
[-- Type: application/zip, Size: 2992 bytes --]
^ permalink raw reply
* Re: [PATCH 6/9 v2] arm64: dts: m3ulcb: enable SDHI0
From: Vladimir Barinov @ 2016-11-09 8:06 UTC (permalink / raw)
To: Simon Horman
Cc: Magnus Damm, Rob Herring, Mark Rutland, devicetree,
linux-renesas-soc
In-Reply-To: <20161109074418.GC30093@verge.net.au>
Hi Simon,
On 09.11.2016 10:44, Simon Horman wrote:
> On Tue, Nov 08, 2016 at 05:14:21PM +0300, Vladimir Barinov wrote:
>> This supports SDHI0 on M3ULCB board SD card slot
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Reviewed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Thanks Vladimir,
>
> I have queued up the following patches:
>
> arm64: dts: h3ulcb: rename SDHI0 pins
> arm64: dts: h3ulcb: enable SDHI2
> arm64: dts: m3ulcb: enable SDHI2
> arm64: dts: m3ulcb: enable SDHI0
>
> For reference I would, however, like to make some comments regarding the
> way you have submitted these:
>
> 1. I did not provide a Reviewed-off-by tag or any other tag as far as I
> recall. So its not appropriate for you to add one when posting patches.
> I have removed it.
>
> 2. Not withstanding the above, Reviewed-off-by is an invalid tag.
> Perhaps you mean Reviewed-by.
>
> 3. When you repost patches I have a slight preference for you to repost
> them in a fresh thread. And if the patchset has more than one patch then
> with a fresh cover letter. This makes it a little easier for me
> to see what is going on. And gives a more natural place for
> me to respond to a patchset.
Thank you for these valuable comments!
I will follow them for further work.
Regards,
Vladimir
^ permalink raw reply
* Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
From: Radosław Pietrzyk @ 2016-11-09 8:10 UTC (permalink / raw)
To: Gabriel Fernandez
Cc: Rob Herring, Mark Rutland, Russell King, Maxime Coquelin,
Alexandre Torgue, Michael Turquette, Stephen Boyd, Nicolas Pitre,
Arnd Bergmann, Daniel Thompson, Andrea Merello,
devicetree-u79uwXL29TY76Z2rM5mHXA, amelie.delaunay-qxv4g6HH51o,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, olivier.bideau-qxv4g6HH51o,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, ludovic.barre-qxv4g6HH51o,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <0368d067-461d-2edb-5561-9717934e0dde-qxv4g6HH51o@public.gmane.org>
I would expect that VCO clock will force recalculation for all its
children if I am not mistaken.
2016-11-08 17:19 GMT+01:00 Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>:
> On 11/08/2016 09:52 AM, Radosław Pietrzyk wrote:
>>
>> 2016-11-08 9:35 GMT+01:00 Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>:
>>>
>>> Hi Radosław
>>>
>>> Many thanks for reviewing.
>>>
>>> On 11/07/2016 03:57 PM, Radosław Pietrzyk wrote:
>>>>>
>>>>> +static struct clk_hw *clk_register_pll_div(const char *name,
>>>>> + const char *parent_name, unsigned long flags,
>>>>> + void __iomem *reg, u8 shift, u8 width,
>>>>> + u8 clk_divider_flags, const struct clk_div_table
>>>>> *table,
>>>>> + struct clk_hw *pll_hw, spinlock_t *lock)
>>>>> +{
>>>>> + struct stm32f4_pll_div *pll_div;
>>>>> + struct clk_hw *hw;
>>>>> + struct clk_init_data init;
>>>>> + int ret;
>>>>> +
>>>>> + /* allocate the divider */
>>>>> + pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
>>>>> + if (!pll_div)
>>>>> + return ERR_PTR(-ENOMEM);
>>>>> +
>>>>> + init.name = name;
>>>>> + init.ops = &stm32f4_pll_div_ops;
>>>>> + init.flags = flags;
>>>>
>>>> Maybe it's worth to have CLK_SET_RATE_PARENT here and the VCO clock
>>>> should have CLK_SET_RATE_GATE flag and we can get rid of custom
>>>> divider ops.
>>>
>>> I don't want to offer the possibility to change the vco clock through the
>>> divisor of the pll (only by a boot-loader or by DT).
>>>
>>> e.g. if i make a set rate on lcd-tft clock, i don't want to change the
>>> SAI
>>> frequencies.
>>>
>>> I used same structure for internal divisors of the pll (p, q, r) and for
>>> post divisors (plli2s-q-div, pllsai-q-div & pllsai-r-div).
>>> That why the CLK_SET_RATE_PARENT flag is transmit by parameter.
>>>
>>> These divisors are similar because we have to switch off the pll before
>>> changing the rate.
>>>
>> But changing pll and lcd dividers only may not be enough for getting
>> very specific pixelclocks and that might require changing the VCO
>> frequency itself. The rest of the SAI tree should be recalculated
>> then.
>
> I agree but it seems to be too much complicated to recalculate all PLL
> divisors if we change the vco clock.
> You mean to use Clock notifier callback ?
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* [PATCH v2 0/3] Add basic support for the I2C units of the Armada 3700
From: Romain Perier @ 2016-11-09 8:14 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
This series add basic support for the I2C bus interface units present
in the Armada 3700 to the pxa-i2c driver. It also add the definitions of
the device nodes to the devicetree at the SoC level and for its official
development board: the Armada 3720 DB.
Romain Perier (3):
i2c: pxa: Add support for the I2C units found in Armada 3700
arm64: dts: marvell: Add I2C definitions for the Armada 3700
dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++--
5 files changed, 47 insertions(+), 3 deletions(-)
--
2.9.3
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^ permalink raw reply
* [PATCH v2 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Romain Perier @ 2016-11-09 8:14 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
In-Reply-To: <20161109081431.10115-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The Armada 3700 has two I2C controllers that is compliant with the I2C
Bus Specificiation 2.1, supports multi-master and different bus speed:
Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
High speed mode (up to 3.4 Mhz).
This IP block has a lot of similarity with the PXA, except some register
offsets and bitfield. This commits adds a basic support for this I2C
unit.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Tested-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d252276..2f56a26 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -763,7 +763,7 @@ config I2C_PUV3
config I2C_PXA
tristate "Intel PXA2XX I2C adapter"
- depends on ARCH_PXA || ARCH_MMP || (X86_32 && PCI && OF)
+ depends on ARCH_PXA || ARCH_MMP || ARCH_MVEBU || (X86_32 && PCI && OF)
help
If you have devices in the PXA I2C bus, say yes to this option.
This driver can also be built as a module. If so, the module
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index e28b825..34ea830 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -55,6 +55,7 @@ enum pxa_i2c_types {
REGS_PXA3XX,
REGS_CE4100,
REGS_PXA910,
+ REGS_A3700,
};
/*
@@ -91,6 +92,13 @@ static struct pxa_reg_layout pxa_reg_layout[] = {
.ilcr = 0x28,
.iwcr = 0x30,
},
+ [REGS_A3700] = {
+ .ibmr = 0x00,
+ .idbr = 0x04,
+ .icr = 0x08,
+ .isr = 0x0c,
+ .isar = 0x10,
+ },
};
static const struct platform_device_id i2c_pxa_id_table[] = {
@@ -98,6 +106,7 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
{ "pxa3xx-pwri2c", REGS_PXA3XX },
{ "ce4100-i2c", REGS_CE4100 },
{ "pxa910-i2c", REGS_PXA910 },
+ { "armada-3700-i2c", REGS_A3700 },
{ },
};
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
@@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ICR_FM (1 << 15) /* fast mode */
+#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
#define ICR_HS (1 << 16) /* High Speed mode */
+#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
#define ISR_RWM (1 << 0) /* read/write mode */
@@ -193,6 +204,8 @@ struct pxa_i2c {
unsigned char master_code;
unsigned long rate;
bool highmode_enter;
+ unsigned long fm_mask;
+ unsigned long hs_mask;
};
#define _IBMR(i2c) ((i2c)->reg_ibmr)
@@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
- writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
- writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
+ writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
+ writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
@@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
+ { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
{}
};
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
@@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
i2c->fast_mode = 1;
+ if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
+ i2c->fm_mask = ICR_BUSMODE_FM;
+ i2c->hs_mask = ICR_BUSMODE_HS;
+ } else {
+ i2c->fm_mask = ICR_FM;
+ i2c->hs_mask = ICR_HS;
+ }
*i2c_types = (enum pxa_i2c_types)(of_id->data);
--
2.9.3
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^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: marvell: Add I2C definitions for the Armada 3700
From: Romain Perier @ 2016-11-09 8:14 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
In-Reply-To: <20161109081431.10115-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The Armada 3700 has two i2c bus interface units, this commit adds the
definitions of the corresponding device nodes. It also enables the node
on the development board for this SoC.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6..16d84af 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -62,6 +62,10 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
/* CON3 */
&sata {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c476253..bf2d73d 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -98,6 +98,24 @@
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
+ i2c0: i2c@11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x24>;
+ clocks = <&nb_perih_clk 10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11080 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11080 0x24>;
+ clocks = <&nb_perih_clk 9>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 3/3] dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
From: Romain Perier @ 2016-11-09 8:14 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
In-Reply-To: <20161109081431.10115-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
This commit documents the compatible string to have the compatibility for
the I2C unit found in the Armada 3700.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Changes in v2:
- Fixed wrong compatible string, it should be "marvell,armada-3700-i2c"
and not "marvell,armada-3700".
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
index 12b78ac..d30f0b1 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
@@ -7,6 +7,7 @@ Required properties :
compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
as shown in the example below.
+ For the Armada 3700, the compatible should be "marvell,armada-3700-i2c".
Recommended properties :
--
2.9.3
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^ permalink raw reply related
* Re: [PATCH v2 1/2] pinctrl: sunxi: Add support for interrupt debouncing
From: Linus Walleij @ 2016-11-09 8:50 UTC (permalink / raw)
To: Maxime Ripard
Cc: Alexandre Courbot,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Chen-Yu Tsai
In-Reply-To: <7dbb47b16d83b843705aa05d4a5f1f7dfdc4e9a3.1478636546.git-series.maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Tue, Nov 8, 2016 at 9:24 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> The pin controller found in the Allwinner SoCs has support for interrupts
> debouncing.
>
> However, this is not done per-pin, preventing us from using the generic
> pinconf binding for that, but per irq bank, which, depending on the SoC,
> ranges from one to five.
>
> Introduce a device-wide property to deal with this using a microsecond
> resolution. We can re-use the per-pin input-debounce property for that, so
> let's do it!
>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
I like this! Minor nits inline:
> +- clocks: phandle to the clocks feeding the pin controller:
> + - "apb": the gated APB parent clock
> + - "hosc": the high frequency oscillator in the system
> + - "losc": the low frequency oscillator in the system
> +
> +Note: For backward compatibility reasons, the hosc and losc clocks are only
> +required if you need to use the optional input-debounce property. Any new
> +device tree should set them.
> +
> +Optional properties:
> + - input-debounce: Array of debouncing periods in microseconds. One period per
> + irq bank found in the controller
Looks good to me. Cutting the DT people some slack to look at this
before merging.
> +static int sunxi_pinctrl_compute_debounce(struct clk *clk, int freq, int *diff)
> +{
> + unsigned long clock = clk_get_rate(clk);
> + unsigned int best_diff = ~0, best_div;
> + int i;
> +
> + for (i = 0; i < 8; i++) {
> + int cur_diff = abs(freq - (clock >> i));
> +
> + if (cur_diff < best_diff) {
> + best_diff = cur_diff;
> + best_div = i;
> + }
> + }
> +
> + *diff = best_diff;
> + return best_div;
> +}
Kerneldoc or function name should reflect that what this function
does is to find the best divisor.
> +static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
> + struct device_node *node)
> +{
> + unsigned int hosc_diff, losc_diff;
> + unsigned int hosc_div, losc_div;
> + struct clk *hosc, *losc;
> + u8 div, src;
> + int i, ret;
> +
> + /* Deal with old DTs that didn't have the oscillators */
> + if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
> + return 0;
Clever, nice.
> + /* If we don't have any setup, bail out */
> + if (!of_find_property(node, "input-debounce", NULL))
> + return 0;
> +
> + losc = devm_clk_get(pctl->dev, "losc");
> + if (IS_ERR(losc))
> + return PTR_ERR(losc);
> +
> + hosc = devm_clk_get(pctl->dev, "hosc");
> + if (IS_ERR(hosc))
> + return PTR_ERR(hosc);
> +
> + for (i = 0; i < pctl->desc->irq_banks; i++) {
> + unsigned long debounce_freq;
> + u32 debounce;
> +
> + ret = of_property_read_u32_index(node, "input-debounce",
> + i, &debounce);
> + if (ret)
> + return ret;
> +
> + debounce_freq = USEC_PER_SEC / debounce;
Arithmetics! Would you like to use
DIV_ROUND_UP()? or DIV_ROUND_CLOSEST()?
Apart from that I like this patch a lot.
Yours,
Linus Walleij
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^ permalink raw reply
* Re: [PATCH v2 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Baruch Siach @ 2016-11-09 8:59 UTC (permalink / raw)
To: Romain Perier
Cc: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Yahuda Yitschak, Jason Cooper,
Pawel Moll, Ian Campbell, Igal Liberman, Hanna Hawa, Omri Itach,
Nadav Haklai, Rob Herring, Andrew Lunn, Neta Zur Hershkovits,
Kumar Gala, Gregory Clement, Shadi Ammouri, Marcin Wojtas,
Thomas Petazzoni, linux-arm-kernel-IAPFreCvJWMP3drIcvDWNA
In-Reply-To: <20161109081431.10115-2-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Hi Romain,
On Wed, Nov 09, 2016 at 09:14:29AM +0100, Romain Perier wrote:
> The Armada 3700 has two I2C controllers that is compliant with the I2C
> Bus Specificiation 2.1, supports multi-master and different bus speed:
> Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
> High speed mode (up to 3.4 Mhz).
>
> This IP block has a lot of similarity with the PXA, except some register
> offsets and bitfield. This commits adds a basic support for this I2C
> unit.
>
> Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Tested-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[...]
> @@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
> #define ICR_SADIE (1 << 13) /* slave address detected int enable */
> #define ICR_UR (1 << 14) /* unit reset */
> #define ICR_FM (1 << 15) /* fast mode */
> +#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
> #define ICR_HS (1 << 16) /* High Speed mode */
> +#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
> #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
>
> #define ISR_RWM (1 << 0) /* read/write mode */
> @@ -193,6 +204,8 @@ struct pxa_i2c {
> unsigned char master_code;
> unsigned long rate;
> bool highmode_enter;
> + unsigned long fm_mask;
> + unsigned long hs_mask;
Do you really need 64bit for that?
baruch
> };
>
> #define _IBMR(i2c) ((i2c)->reg_ibmr)
> @@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
> writel(i2c->slave_addr, _ISAR(i2c));
>
> /* set control register values */
> - writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
> - writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
> + writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
> + writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
>
> #ifdef CONFIG_I2C_PXA_SLAVE
> dev_info(&i2c->adap.dev, "Enabling slave mode\n");
> @@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
> { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
> { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
> { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
> + { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
> {}
> };
> MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
> @@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
> i2c->use_pio = 1;
> if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
> i2c->fast_mode = 1;
> + if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
> + i2c->fm_mask = ICR_BUSMODE_FM;
> + i2c->hs_mask = ICR_BUSMODE_HS;
> + } else {
> + i2c->fm_mask = ICR_FM;
> + i2c->hs_mask = ICR_HS;
> + }
>
> *i2c_types = (enum pxa_i2c_types)(of_id->data);
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org - tel: +972.52.368.4656, http://www.tkos.co.il -
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^ permalink raw reply
* Re: [v16, 0/7] Fix eSDHC host version register bug
From: Wolfram Sang @ 2016-11-09 9:18 UTC (permalink / raw)
To: Yangbo Lu
Cc: linux-mmc, ulf.hansson, Scott Wood, Arnd Bergmann, linuxppc-dev,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-i2c,
iommu, netdev, Greg Kroah-Hartman, Mark Rutland, Rob Herring,
Russell King, Jochen Friedrich, Joerg Roedel, Claudiu Manoil,
Bhupesh Sharma, Qiang Zhao, Kumar Gala, Leo Li
In-Reply-To: <1478661252-42439-1-git-send-email-yangbo.lu@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 121 bytes --]
Can you please update your CC list? There is nothing i2c related in this
patch series, so you could drop the i2c-list.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* [PATCH 0/6] USB support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
This patch set contains the usb support for Broadcom NSP SoC.
The usb phy is connected through mdio interface. The mdio interface
can be used to access either internal phys or external phys using a
multiplexer.
The first patch provides the documentation details for mdio-mux and
second patch provides the documentation details for usb3 phy. The third
patch contains the mdio-mux support and fourth patch contains the
changes to the mdio bus driver.
The fifth patch provides the phy driver and sixth patch provides the
enable method for usb.
This patch series has been tested on NSP bcm958625HR board.
This patch series is based on v4.9.0-rc1 and is available from github-
repo: https://github.com/Broadcom/cygnus-linux.git
branch:nsp-usb-v1
Yendapally Reddy Dhananjaya Reddy (6):
dt-bindings: mdio-mux: Add documentation for mdio mux for NSP SoC
dt-bindings: phy: Add documentation for NSP USB3 PHY
net: mdio-mux: Add MDIO mux driver for NSP SoC
net: phy: Initialize mdio clock at probe function
phy: Add USB3 PHY support for Broadcom NSP SoC
arm: dts: nsp: Add USB nodes to device tree
.../devicetree/bindings/net/brcm,mdio-mux-nsp.txt | 57 +++++++
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 +++++
arch/arm/boot/dts/bcm-nsp.dtsi | 57 +++++++
arch/arm/boot/dts/bcm958625k.dts | 16 ++
drivers/net/phy/Kconfig | 9 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-bcm-iproc.c | 6 +-
drivers/net/phy/mdio-mux-bcm-nsp.c | 121 ++++++++++++++
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++
11 files changed, 488 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
create mode 100644 drivers/net/phy/mdio-mux-bcm-nsp.c
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
--
2.1.0
^ permalink raw reply
* [PATCH 1/6] dt-bindings: mdio-mux: Add documentation for mdio mux for NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add documentation for mdio mux available in Broadcom NSP SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
.../devicetree/bindings/net/brcm,mdio-mux-nsp.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
diff --git a/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt b/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
new file mode 100644
index 0000000..b749a2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/brcm,mdio-mux-nsp.txt
@@ -0,0 +1,57 @@
+Properties for an MDIO bus multiplexer available in Broadcom NSP SoC.
+
+This MDIO bus multiplexer defines buses that could access the internal
+phys as well as external to SoCs. When child bus is selected, one needs
+to select the below properties to generate desired MDIO transaction on
+appropriate bus.
+
+Required properties in addition to the generic multiplexer properties:
+
+MDIO multiplexer node:
+- compatible: brcm,mdio-mux-iproc.
+- reg: Should contain registers location and length.
+- reg-names: Should contain the resource reg names.
+ - bus-ctrl: mdio bus control register address space required to
+ select the bus master. This property is not required for SoC's
+ that doesn't provide master selection.
+ - mgmt-ctrl: mdio management control register address space
+
+Sub-nodes:
+ Each bus master should be represented as a sub-node.
+
+Sub-nodes required properties:
+- reg: Bus master number. Should be 0x10 to access the external mdio devices.
+- address-cells: should be 1
+- size-cells: should be 0
+
+Every non-ethernet PHY requires a compatible property so that it could be
+probed based on this compatible string.
+
+Additional information regarding generic multiplexer properties can be found
+at- Documentation/devicetree/bindings/net/mdio-mux.txt
+
+example:
+
+ mdio_mux: mdio-mux@3f190 {
+ compatible = "brcm,mdio-mux-nsp";
+ reg = <0x3f190 0x4>,
+ <0x32000 0x4>;
+ reg-names = "bus-ctrl", "mgmt-ctrl";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: phy: Add documentation for NSP USB3 PHY
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: devicetree, netdev, linux-kernel,
Yendapally Reddy Dhananjaya Reddy, bcm-kernel-feedback-list,
linux-arm-kernel
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add documentation for USB3 PHY available in Northstar plus SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
.../devicetree/bindings/phy/brcm,nsp-usb3-phy.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
new file mode 100644
index 0000000..30cf4b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
@@ -0,0 +1,39 @@
+Broadcom USB3 phy binding northstar plus SoC
+This is a child bus node of "brcm,mdio-mux-nsp" node.
+
+Required mdio bus properties:
+- reg: MDIO Bus number for the MDIO interface
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required PHY properties:
+- compatible: should be "brcm,nsp-usb3-phy"
+- reg: Phy address in the MDIO interface
+- usb3-ctrl-syscon: handler of syscon node defining physical address
+ of usb3 control register.
+- #phy-cells: must be 0
+
+Required usb3 control properties:
+- compatible: should be "brcm,nsp-usb3-ctrl"
+- reg: offset and length of the control registers
+
+Example:
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ }
+
+ usb3_ctrl: syscon@104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
--
2.1.0
^ permalink raw reply related
* [PATCH 3/6] net: mdio-mux: Add MDIO mux driver for NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
NSP SoC supports the mdio multiplexer which has the bus
selection logic.
This multiplexer has child buses for PCIe, USB. The bus
could be internal or external to SOC where PHYs are attached.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/net/phy/Kconfig | 9 +++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-mux-bcm-nsp.c | 121 +++++++++++++++++++++++++++++++++++++
3 files changed, 131 insertions(+)
create mode 100644 drivers/net/phy/mdio-mux-bcm-nsp.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 2651c8d..41cc583 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -63,6 +63,15 @@ config MDIO_BUS_MUX_BCM_IPROC
child MDIO bus to a parent bus. Buses could be internal as well as
external and selection logic lies inside the same multiplexer.
+config MDIO_BUS_MUX_BCM_NSP
+ tristate "Broadcom NSP MDIO bus controller"
+ depends on ARCH_BCM_NSP || COMPILE_TEST
+ depends on HAS_IOMEM && OF_MDIO
+ default ARCH_BCM_NSP
+ help
+ This module provides a driver MDIO multiplexing the busses available
+ in the Broadcom NSP SoC.
+
config MDIO_BUS_MUX_GPIO
tristate "GPIO controlled MDIO bus multiplexers"
depends on OF_GPIO && OF_MDIO
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e58667d..d5969b2 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o
obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+obj-$(CONFIG_MDIO_BUS_MUX_BCM_NSP) += mdio-mux-bcm-nsp.o
obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
diff --git a/drivers/net/phy/mdio-mux-bcm-nsp.c b/drivers/net/phy/mdio-mux-bcm-nsp.c
new file mode 100644
index 0000000..75dcb04
--- /dev/null
+++ b/drivers/net/phy/mdio-mux-bcm-nsp.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License version 2 (GPLv2) for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/mdio-mux.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+
+#define NSP_MDIO_EXT_BUS_START_ADDR 16
+#define NSP_MDIO_EXT_SELECT_BIT BIT(9)
+
+struct nsp_mdiomux_desc {
+ void __iomem *bus_ctrl;
+ void __iomem *mgmt_ctrl;
+ void *mux_handle;
+};
+
+static int mdio_mux_nsp_switch_fn(int current_child, int desired_child,
+ void *priv)
+{
+ struct nsp_mdiomux_desc *md = priv;
+ u32 data, bus_id;
+
+ /* select internal or external bus */
+ data = readl(md->mgmt_ctrl);
+ if (desired_child == NSP_MDIO_EXT_BUS_START_ADDR)
+ data |= NSP_MDIO_EXT_SELECT_BIT;
+ else
+ data &= ~NSP_MDIO_EXT_SELECT_BIT;
+ writel(data, md->mgmt_ctrl);
+
+ /* select bus number */
+ if (md->bus_ctrl) {
+ bus_id = desired_child & (NSP_MDIO_EXT_BUS_START_ADDR - 1);
+ writel(bus_id, md->bus_ctrl);
+ }
+
+ return 0;
+}
+
+static int mdio_mux_nsp_probe(struct platform_device *pdev)
+{
+ struct nsp_mdiomux_desc *md;
+ struct resource *res;
+ int ret;
+
+ md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
+ if (!md)
+ return -ENOMEM;
+
+ /* Bus control is not available in some SoC's */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus-ctrl");
+ if (res) {
+ md->bus_ctrl = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(md->bus_ctrl)) {
+ dev_err(&pdev->dev, "failed to ioremap register\n");
+ return PTR_ERR(md->bus_ctrl);
+ }
+ }
+
+ /* Get management control */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mgmt-ctrl");
+ if (!res)
+ return -EINVAL;
+
+ md->mgmt_ctrl = ioremap(res->start, resource_size(res));
+ if (!md->mgmt_ctrl)
+ return -ENOMEM;
+
+ ret = mdio_mux_init(&pdev->dev, mdio_mux_nsp_switch_fn,
+ &md->mux_handle, md, NULL);
+ if (ret != 0) {
+ iounmap(md->mgmt_ctrl);
+ return ret;
+ }
+
+ pdev->dev.platform_data = md;
+ return 0;
+}
+
+static int mdio_mux_nsp_remove(struct platform_device *pdev)
+{
+ struct nsp_mdiomux_desc *md = dev_get_platdata(&pdev->dev);
+
+ iounmap(md->mgmt_ctrl);
+ mdio_mux_uninit(md->mux_handle);
+ return 0;
+}
+
+static const struct of_device_id mdio_mux_nsp_match[] = {
+ { .compatible = "brcm,mdio-mux-nsp" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mdio_mux_nsp_match);
+
+static struct platform_driver mdio_mux_nsp_driver = {
+ .driver = {
+ .name = "mdio-mux-nsp",
+ .of_match_table = mdio_mux_nsp_match,
+ },
+ .probe = mdio_mux_nsp_probe,
+ .remove = mdio_mux_nsp_remove,
+};
+
+module_platform_driver(mdio_mux_nsp_driver);
+
+MODULE_DESCRIPTION("NSP MDIO Mux Bus Driver");
+MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");
+MODULE_LICENSE("GPL v2");
--
2.1.0
^ permalink raw reply related
* [PATCH 4/6] net: phy: Initialize mdio clock at probe function
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Initialize mdio clock divisor in probe function. The ext bus
bit available in the same register will be used by mdio mux
to enable external mdio.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/net/phy/mdio-bcm-iproc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/mdio-bcm-iproc.c b/drivers/net/phy/mdio-bcm-iproc.c
index c0b4e65..46fe1ae 100644
--- a/drivers/net/phy/mdio-bcm-iproc.c
+++ b/drivers/net/phy/mdio-bcm-iproc.c
@@ -81,8 +81,6 @@ static int iproc_mdio_read(struct mii_bus *bus, int phy_id, int reg)
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the read operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -112,8 +110,6 @@ static int iproc_mdio_write(struct mii_bus *bus, int phy_id,
if (rc)
return rc;
- iproc_mdio_config_clk(priv->base);
-
/* Prepare the write operation */
cmd = (MII_DATA_TA_VAL << MII_DATA_TA_SHIFT) |
(reg << MII_DATA_RA_SHIFT) |
@@ -163,6 +159,8 @@ static int iproc_mdio_probe(struct platform_device *pdev)
bus->read = iproc_mdio_read;
bus->write = iproc_mdio_write;
+ iproc_mdio_config_clk(priv->base);
+
rc = of_mdiobus_register(bus, pdev->dev.of_node);
if (rc) {
dev_err(&pdev->dev, "MDIO bus registration failed\n");
--
2.1.0
^ permalink raw reply related
* [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
This patch adds support for Broadcom NSP USB3 PHY
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
drivers/phy/Kconfig | 9 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-bcm-nsp-usb3.c | 176 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 186 insertions(+)
create mode 100644 drivers/phy/phy-bcm-nsp-usb3.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index fe00f91..85cc556 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -489,4 +489,13 @@ config PHY_NS2_PCIE
help
Enable this to support the Broadcom Northstar2 PCIe PHY.
If unsure, say N.
+
+config PHY_NSP_USB3
+ tristate "Broadcom NorthStar plus USB3 PHY driver"
+ depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
+ select GENERIC_PHY
+ default ARCH_BCM_NSP
+ help
+ Enable this to support the Broadcom Northstar plus USB3 PHY.
+ If unsure, say N.
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a534cf5..ba9b4c0 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
+obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
diff --git a/drivers/phy/phy-bcm-nsp-usb3.c b/drivers/phy/phy-bcm-nsp-usb3.c
new file mode 100644
index 0000000..0033382
--- /dev/null
+++ b/drivers/phy/phy-bcm-nsp-usb3.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#define NSP_USB3_RST_CTRL_OFFSET 0x3f8
+
+/* mdio reg access */
+#define NSP_USB3_PHY_BASE_ADDR_REG 0x1f
+
+#define NSP_USB3_PHY_PLL30_BLOCK 0x8000
+#define NSP_USB3_PLL_CONTROL 0x01
+#define NSP_USB3_PLLA_CONTROL0 0x0a
+#define NSP_USB3_PLLA_CONTROL1 0x0b
+
+#define NSP_USB3_PHY_TX_PMD_BLOCK 0x8040
+#define NSP_USB3_TX_PMD_CONTROL1 0x01
+
+#define NSP_USB3_PHY_PIPE_BLOCK 0x8060
+#define NSP_USB3_LFPS_CMP 0x02
+#define NSP_USB3_LFPS_DEGLITCH 0x03
+
+struct nsp_usb3_phy {
+ struct regmap *usb3_ctrl;
+ struct phy *phy;
+ struct mdio_device *mdiodev;
+};
+
+static int nsp_usb3_phy_init(struct phy *phy)
+{
+ struct nsp_usb3_phy *iphy = phy_get_drvdata(phy);
+ struct mii_bus *bus = iphy->mdiodev->bus;
+ int addr = iphy->mdiodev->addr;
+ u32 data;
+ int rc;
+
+ rc = regmap_read(iphy->usb3_ctrl, 0, &data);
+ if (rc)
+ return rc;
+ data |= 1;
+ rc = regmap_write(iphy->usb3_ctrl, 0, data);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 1);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PLL30_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x1000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL0, 0x6400);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0xc000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0x8000);
+ if (rc)
+ return rc;
+
+ rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 0);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x9000);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_PIPE_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_CMP, 0xf30d);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_DEGLITCH, 0x6302);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
+ NSP_USB3_PHY_TX_PMD_BLOCK);
+ if (rc)
+ return rc;
+
+ rc = mdiobus_write(bus, addr, NSP_USB3_TX_PMD_CONTROL1, 0x1003);
+
+ return rc;
+}
+
+static struct phy_ops nsp_usb3_phy_ops = {
+ .init = nsp_usb3_phy_init,
+};
+
+static int nsp_usb3_phy_probe(struct mdio_device *mdiodev)
+{
+ struct device *dev = &mdiodev->dev;
+ struct phy_provider *provider;
+ struct nsp_usb3_phy *iphy;
+
+ iphy = devm_kzalloc(dev, sizeof(*iphy), GFP_KERNEL);
+ if (!iphy)
+ return -ENOMEM;
+ iphy->mdiodev = mdiodev;
+
+ iphy->usb3_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "usb3-ctrl-syscon");
+ if (IS_ERR(iphy->usb3_ctrl))
+ return PTR_ERR(iphy->usb3_ctrl);
+
+ iphy->phy = devm_phy_create(dev, dev->of_node, &nsp_usb3_phy_ops);
+ if (IS_ERR(iphy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(iphy->phy);
+ }
+
+ phy_set_drvdata(iphy->phy, iphy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "could not register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id nsp_usb3_phy_of_match[] = {
+ {.compatible = "brcm,nsp-usb3-phy",},
+ { /* sentinel */ }
+};
+
+static struct mdio_driver nsp_usb3_phy_driver = {
+ .mdiodrv = {
+ .driver = {
+ .name = "nsp-usb3-phy",
+ .of_match_table = nsp_usb3_phy_of_match,
+ },
+ },
+ .probe = nsp_usb3_phy_probe,
+};
+
+mdio_module_driver(nsp_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Broadcom NSP USB3 PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");
--
2.1.0
^ permalink raw reply related
* [PATCH 6/6] arm: dts: nsp: Add USB nodes to device tree
From: Yendapally Reddy Dhananjaya Reddy @ 2016-11-09 9:33 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Russell King, Ray Jui, Scott Branden,
Jon Mason, Florian Fainelli, Kishon Vijay Abraham I
Cc: bcm-kernel-feedback-list, netdev, devicetree, linux-kernel,
linux-arm-kernel, Yendapally Reddy Dhananjaya Reddy
In-Reply-To: <1478683994-12008-1-git-send-email-yendapally.reddy@broadcom.com>
Add USB nodes to the Northstar plus device tree file
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 57 ++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 16 +++++++++++
2 files changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7c9e0fa..acdb576 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -249,6 +249,34 @@
status = "disabled";
};
+ xhci: usb@29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci0: usb@2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x32000 0x8>;
+ };
+
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@@ -319,6 +347,30 @@
"sata2";
};
+ mdio_mux: mdio-mux@3f190 {
+ compatible = "brcm,mdio-mux-nsp";
+ reg = <0x3f190 0x4>,
+ <0x32000 0x4>;
+ reg-names = "bus-ctrl", "mgmt-ctrl";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,nsp-usb3-phy";
+ reg = <0x10>;
+ usb3-ctrl-syscon = <&usb3_ctrl>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
pinctrl: pinctrl@3f1c0 {
compatible = "brcm,nsp-pinmux";
reg = <0x3f1c0 0x04>,
@@ -367,6 +419,11 @@
phy-names = "sata-phy";
};
};
+
+ usb3_ctrl: syscon@104408 {
+ compatible = "brcm,nsp-usb3-ctrl", "syscon";
+ reg = <0x104408 0x3fc>;
+ };
};
pcie0: pcie@18012000 {
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 05c5f98..c7303fa 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -53,6 +53,22 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.1.0
^ permalink raw reply related
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