* [PATCH v3] usb: dwc2: add amcc,dwc-otg support
From: John Youn @ 2016-11-15 23:03 UTC (permalink / raw)
To: Felipe Balbi
Cc: Christian Lamparter, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Mark Rutland, Rob Herring,
Greg Kroah-Hartman, John Youn
From: Christian Lamparter <chunkeey-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This patch adds support for the "amcc,usb-otg" device
which is found in the PowerPC Canyonlands' dts.
The device definition was added by:
commit c89b3458d8cc ("powerpc/44x: Add USB DWC DTS entry to Canyonlands
board")
but without any driver support as the dwc2 driver wasn't available at
that time.
Note: The system can't use the generic "snps,dwc2" compatible
because of the special ahbcfg configuration. The default
GAHBCFG_HBSTLEN_INCR4 of snps,dwc2 can cause a system hang
when the USB and SATA is used concurrently.
Signed-off-by: Christian Lamparter <chunkeey-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
---
Sorry, the previous one broke compilation. This fixes it.
Regards,
John
v3 [johnyoun]:
* Fixed compilation issue
v2 [johnyoun]:
* Removed params struct
* Minor commit message formatting
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
drivers/usb/dwc2/params.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index ad8f7ff..6c7c2bce 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -12,6 +12,7 @@ Required properties:
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 513556a..a786256 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -239,6 +239,7 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
+ { .compatible = "amcc,dwc-otg", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.10.0
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^ permalink raw reply related
* [PATCH v3] usb: dwc2: add amcc,dwc-otg support
From: John Youn @ 2016-11-15 23:03 UTC (permalink / raw)
To: Felipe Balbi
Cc: Christian Lamparter, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Mark Rutland, Rob Herring,
Greg Kroah-Hartman, John Youn
From: Christian Lamparter <chunkeey-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This patch adds support for the "amcc,usb-otg" device
which is found in the PowerPC Canyonlands' dts.
The device definition was added by:
commit c89b3458d8cc ("powerpc/44x: Add USB DWC DTS entry to Canyonlands
board")
but without any driver support as the dwc2 driver wasn't available at
that time.
Note: The system can't use the generic "snps,dwc2" compatible
because of the special ahbcfg configuration. The default
GAHBCFG_HBSTLEN_INCR4 of snps,dwc2 can cause a system hang
when the USB and SATA is used concurrently.
Signed-off-by: Christian Lamparter <chunkeey-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
---
Sorry, the previous one broke compilation. This fixes it.
Regards,
John
v3 [johnyoun]:
* Fixed compilation issue
v2 [johnyoun]:
* Removed params struct
* Minor commit message formatting
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
drivers/usb/dwc2/params.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index ad8f7ff..6c7c2bce 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -12,6 +12,7 @@ Required properties:
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 513556a..a786256 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -239,6 +239,7 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
+ { .compatible = "amcc,dwc-otg", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.10.0
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^ permalink raw reply related
* [PATCH v3] usb: dwc2: add amcc,dwc-otg support
From: John Youn @ 2016-11-15 23:03 UTC (permalink / raw)
To: Felipe Balbi
Cc: Mark Rutland, devicetree, John Youn, Greg Kroah-Hartman,
linux-usb, linux-kernel, Rob Herring, Christian Lamparter,
linuxppc-dev
From: Christian Lamparter <chunkeey@googlemail.com>
This patch adds support for the "amcc,usb-otg" device
which is found in the PowerPC Canyonlands' dts.
The device definition was added by:
commit c89b3458d8cc ("powerpc/44x: Add USB DWC DTS entry to Canyonlands
board")
but without any driver support as the dwc2 driver wasn't available at
that time.
Note: The system can't use the generic "snps,dwc2" compatible
because of the special ahbcfg configuration. The default
GAHBCFG_HBSTLEN_INCR4 of snps,dwc2 can cause a system hang
when the USB and SATA is used concurrently.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Youn <johnyoun@synopsys.com>
---
Sorry, the previous one broke compilation. This fixes it.
Regards,
John
v3 [johnyoun]:
* Fixed compilation issue
v2 [johnyoun]:
* Removed params struct
* Minor commit message formatting
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
drivers/usb/dwc2/params.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index ad8f7ff..6c7c2bce 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -12,6 +12,7 @@ Required properties:
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 513556a..a786256 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -239,6 +239,7 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
+ { .compatible = "amcc,dwc-otg", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.10.0
^ permalink raw reply related
* [PATCH v3] usb: dwc2: add amcc,dwc-otg support
From: John Youn @ 2016-11-15 23:03 UTC (permalink / raw)
To: Felipe Balbi
Cc: Mark Rutland, devicetree, John Youn, Greg Kroah-Hartman,
linux-usb, linux-kernel, Rob Herring, Christian Lamparter,
linuxppc-dev
From: Christian Lamparter <chunkeey@googlemail.com>
This patch adds support for the "amcc,usb-otg" device
which is found in the PowerPC Canyonlands' dts.
The device definition was added by:
commit c89b3458d8cc ("powerpc/44x: Add USB DWC DTS entry to Canyonlands
board")
but without any driver support as the dwc2 driver wasn't available at
that time.
Note: The system can't use the generic "snps,dwc2" compatible
because of the special ahbcfg configuration. The default
GAHBCFG_HBSTLEN_INCR4 of snps,dwc2 can cause a system hang
when the USB and SATA is used concurrently.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Youn <johnyoun@synopsys.com>
---
Sorry, the previous one broke compilation. This fixes it.
Regards,
John
v3 [johnyoun]:
* Fixed compilation issue
v2 [johnyoun]:
* Removed params struct
* Minor commit message formatting
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
drivers/usb/dwc2/params.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index ad8f7ff..6c7c2bce 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -12,6 +12,7 @@ Required properties:
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 513556a..a786256 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -239,6 +239,7 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
{ .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
+ { .compatible = "amcc,dwc-otg", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.10.0
^ permalink raw reply related
* Re: specifying order of /dev/mmcblk devices via device-tree?
From: Russell King - ARM Linux @ 2016-11-15 23:55 UTC (permalink / raw)
To: Tim Harvey
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Ulf Hansson, Fabio Estevam, Javier Martinez Canillas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20161115221002.GA1041-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
On Tue, Nov 15, 2016 at 10:10:02PM +0000, Russell King - ARM Linux wrote:
> On Tue, Nov 15, 2016 at 01:39:42PM -0800, Tim Harvey wrote:
> > On Tue, Nov 15, 2016 at 1:35 PM, Russell King - ARM Linux
> > <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> > > On Tue, Nov 15, 2016 at 12:27:53PM -0800, Tim Harvey wrote:
> > >> On Mon, Nov 14, 2016 at 11:08 AM, Russell King - ARM Linux
> > >> <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> > >> > So, someone merged a patch which makes mmcblk devices follow the
> > >> > host controller numbering.
> > >> >
> > >> > Now my cubox-i fails to boot correctly because the SD card in the
> > >> > _only_ SD card slot now gets called "mmcblk1" and not "mmcblk0".
> > >> >
> > >> > USDHC1 is wired to the on-microsom WiFi, and never has anything
> > >> > remotely near a SD card or eMMC present. So, this change is
> > >> > confusing on these platforms.
> > >> >
> > >> > Moreover, this is _going_ to break SolidRun distros if people upgrade
> > >> > their kernels.
> > >> >
> > >> > It may be appropriate for eMMC, but it's not appropriate everywhere.
> > >> >
> > >> > This is a user visible _regression_ in 4.9-rc. Whoever did this,
> > >> > please revert whatever change caused this, and next time limit it
> > >> > to only eMMC.
> > >> >
> > >> > Thanks.
> > >>
> > >> I see the same thing on newer kernels, which is why I asked the
> > >> question. I didn't expect (or even want honestly) a non mmcblk0 boot
> > >> device and was looking for a way to control that via dt. Now I'm
> > >> understanding that to avoid this kind of bootloader/kernel dependence
> > >> issue I should be using UUID's to identify the boot device.
> > >>
> > >> >From my testing it looks like the change your looking for occurred
> > >> some time ago and is somewhere between 4.5 and 4.6 and not a 4.9
> > >> regression specifically.
> > >
> > > That depends how you look at it. Yes, there's a change in 4.5 to 4.6
> > > which ties the block device number to the host device index, but that's
> > > really only part of the story here.
> > >
> > > 4.8 definitely identifies the SD card in iMX6 usdhc2 as "mmcblk0".
> > > 4.9-rc identifies the SD card as "mmcblk1". This makes it a 4.9 change
> > > of behaviour - there can be no argument about that.
> > >
> > > Now, digging further into this today, it appears that:
> > >
> > > v4.8: usdhc2 was probed first, and is given mmc0.
> > > usdhc1 is probed second, and is given mmc1.
> > >
> > > v4.9-rc: usdhc1 is probed first, and is given mmc0.
> > > usdhc2 is probed second, and is given mmc1.
> > >
> > > I haven't yet been able to figure out why there's been this change
> > > of probe order. There's no change that I can see in the iMX6 DT
> > > files that would account for this.
> > >
> >
> > I bisected it and the commit your looking for is
> > 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d
>
> No it's not.
>
> Let me try and put it plainer:
>
> * Commit 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d ties the mmc block
> device number (mmcblkN) to the mmc host interface number (mmcN).
> This change happened between 4.5 and 4.6.
>
> * The change I'm seeing happened between 4.8 and 4.9-rc. I'm not
> seeing a change of behaviour between 4.5 and 4.6.
>
> * The change I'm seeing changes the order of the physical device
> associated with the hosts named mmc0 and mmc1 in the kernel.
>
> * Because physical devices associated with the mmc0 and mmc1 hosts
> swap over, the mmcblkN number changes due to the commit you point
> out.
>
> * So, the change that I'm seeing between 4.8 and 4.9-rc is not caused
> by commit 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d, but by something
> else changing the order in which the two usdhc physical hardware
> blocks get probed.
>
> Does this make it clearer?
It turns out to be this commit:
commit 6eb1c9496b81680f2cd2e0eda06c531317e2e28d
Author: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Date: Mon Sep 19 01:16:44 2016 +0900
clk: probe common clock drivers earlier
Several SoCs implement platform drivers for clocks rather than
CLK_OF_DECLARE(). Clocks should come earlier because they are
prerequisites for many of other drivers. It will help to mitigate
EPROBE_DEFER issues.
Also, drop the comment since it does not carry much value.
Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Acked-by: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Signed-off-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
which changes the init order. In 4.8, we get:
calling mmc_pwrseq_simple_driver_init+0x0/0x20 @ 1
bus: 'platform': driver_probe_device: matched device usdhc1_pwrseq with driver pwrseq_simple
bus: 'platform': really_probe: probing driver pwrseq_simple with device usdhc1_pwrseq
platform usdhc1_pwrseq: Driver pwrseq_simple requests probe deferral
platform usdhc1_pwrseq: Added to deferred list
initcall mmc_pwrseq_simple_driver_init+0x0/0x20 returned 0 after 737 usecs
which then goes on to cause:
calling sdhci_esdhc_imx_driver_init+0x0/0x20 @ 1
bus: 'platform': driver_probe_device: matched device 2190000.usdhc with driver sdhci-esdhc-imx
bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2190000.usdhc
platform 2190000.usdhc: Driver sdhci-esdhc-imx requests probe deferral
platform 2190000.usdhc: Added to deferred list
followed by:
bus: 'platform': driver_probe_device: matched device 2194000.usdhc with driver sdhci-esdhc-imx
bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2194000.usdhc
sdhci-esdhc-imx 2194000.usdhc: Got CD GPIO
driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2194000.usdhc'
bus: 'platform': really_probe: bound device 2194000.usdhc to driver sdhci-esdhc-imx
initcall sdhci_esdhc_imx_driver_init+0x0/0x20 returned 0 after 58205 usecs
and eventually:
mmc0: host does not support reading read-only switch, assuming write-enable
mmc0: new ultra high speed SDR104 SDHC card at address 0001
mmcblk0: mmc0:0001 00000 14.9 GiB
mmcblk0: p1 p2
In 4.9-rc5, we instead get:
calling gpio_clk_driver_init+0x0/0x20 @ 1
bus: 'platform': driver_probe_device: matched device sdio-clock with driver gpio-clk
bus: 'platform': really_probe: probing driver gpio-clk with device sdio-clock
driver: 'gpio-clk': driver_bound: bound to device 'sdio-clock'
bus: 'platform': really_probe: bound device sdio-clock to driver gpio-clk
...
calling mmc_pwrseq_simple_driver_init+0x0/0x20 @ 1
bus: 'platform': driver_probe_device: matched device usdhc1_pwrseq with driver pwrseq_simple
bus: 'platform': really_probe: probing driver pwrseq_simple with device usdhc1_pwrseq
driver: 'pwrseq_simple': driver_bound: bound to device 'usdhc1_pwrseq'
bus: 'platform': really_probe: bound device usdhc1_pwrseq to driver pwrseq_simple
initcall mmc_pwrseq_simple_driver_init+0x0/0x20 returned 0 after 876 usecs
...
calling sdhci_esdhc_imx_driver_init+0x0/0x20 @ 1
bus: 'platform': driver_probe_device: matched device 2190000.usdhc with driver sdhci-esdhc-imx
bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2190000.usdhc
sdhci-esdhc-imx 2190000.usdhc: allocated mmc-pwrseq
driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2190000.usdhc'
bus: 'platform': really_probe: bound device 2190000.usdhc to driver sdhci-esdhc-imx
bus: 'platform': driver_probe_device: matched device 2194000.usdhc with driver sdhci-esdhc-imx
bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2194000.usdhc
driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2194000.usdhc'
bus: 'platform': really_probe: bound device 2194000.usdhc to driver sdhci-esdhc-imx
initcall sdhci_esdhc_imx_driver_init+0x0/0x20 returned 0 after 384864 usecs
...
mmc1: host does not support reading read-only switch, assuming write-enable
mmc1: new ultra high speed SDR104 SDHC card at address 0001
mmcblk1: mmc1:0001 00000 14.9 GiB
mmcblk1: p1 p2
--
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^ permalink raw reply
* Re: [PATCH 1/2] drivers: usb: phy: Add qoriq usb 3.0 phy driver support
From: Rob Herring @ 2016-11-16 0:07 UTC (permalink / raw)
To: Sriram Dash
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
mark.rutland-5wv7dgnIgG8, kishon-l0cyMroinI0,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz,
pku.leo-Re5JQEeQqe8AvxtiuMwx3w,
mathias.nyman-ral2JQCrhuEAvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, suresh.gupta-3arQi8VN3Tc,
felipe.balbi-VuQAYsv1563Yd54FQh9/CA
In-Reply-To: <1479101215-26954-2-git-send-email-sriram.dash-3arQi8VN3Tc@public.gmane.org>
On Mon, Nov 14, 2016 at 10:56:54AM +0530, Sriram Dash wrote:
> Adds qoriq usb 3.0 phy driver support for LS1043A platform.
> Describes the qoriq usb 2.0 phy driver binding, currently used
> for LS1043A platform.
>
> Signed-off-by: Sriram Dash <sriram.dash-3arQi8VN3Tc@public.gmane.org>
> ---
> .../devicetree/bindings/phy/phy-qoriq-usb3.txt | 36 ++++
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qoriq-usb3.c | 202 +++++++++++++++++++++
> 4 files changed, 247 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt
> create mode 100644 drivers/phy/phy-qoriq-usb3.c
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt b/Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt
> new file mode 100644
> index 0000000..d934c80
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt
> @@ -0,0 +1,36 @@
> +Driver for Freescale USB 3.0 PHY
> +
> +Required properties:
> +
> +- compatible : fsl,qoriq-usb3-phy
> +- reg : register mappings for Parameter Configuration Register
> + and Phy base offset.
> +- reg-names : "param_ctrl" and "phy_base"
> +- phy_type : For multi port host USB controllers, should be one of
> + "ulpi", or "serial". For dual role USB controllers,
> + should be one of "ulpi", "utmi", "utmi_wide", or "serial".
Do any of these really apply to a USB3 PHY?
Rob
> +
> +Example:
> + usbphy0: usb3-phy@084F0000 {
usb-phy@...
> + compatible = "fsl,qoriq-usb3-phy";
> + reg = <0x0 0x01570070 0x0 0xC>, <0x0 0x084F0000 0x0 0x5000>;
> + reg-names = "param_ctrl", "phy_base";
> + #phy-cells = <0>;
> + phy_type = "utmi";
> + };
> +
> + usbphy1: usb3-phy@08500000 {
> + compatible = "fsl,qoriq-usb3-phy";
> + reg = <0x0 0x0157007C 0x0 0xC>, <0x0 0x08500000 0x0 0x5000>;
> + reg-names = "param_ctrl", "phy_base";
> + #phy-cells = <0>;
> + phy_type = "utmi";
> + };
> +
> + usbphy2: usb3-phy@08510000 {
> + compatible = "fsl,qoriq-usb3-phy";
> + reg = <0x0 0x01570088 0x0 0xC>, <0x0 0x08510000 0x0 0x5000>;
> + reg-names = "param_ctrl", "phy_base";
> + #phy-cells = <0>;
> + phy_type = "utmi";
> + };
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* Re: [RFC PATCH] ARM64: dts: Add support for Meson GXM
From: Rob Herring @ 2016-11-16 0:13 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, carlo, linux-amlogic, linux-arm-kernel, linux-kernel,
devicetree
In-Reply-To: <20161114094411.30199-1-narmstrong@baylibre.com>
On Mon, Nov 14, 2016 at 10:44:11AM +0100, Neil Armstrong wrote:
> Following the Amlogic Linux kernel, it seem the only differences
> between the GXL and GXM SoCs are the CPU Clusters.
>
> Simply add a meson-gxm dtsi and reproduce the P23x to Q20x boards
> dts files since the S905D and S912 SoCs shares the same pinout
> and the P23x and Q20x boards are identical.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/arm/amlogic.txt | 6 +
> arch/arm64/boot/dts/amlogic/Makefile | 2 +
> .../arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 76 +++++++++
> .../arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts | 57 +++++++
> .../boot/dts/amlogic/meson-gxm-s912-q20x.dtsi | 188 +++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 114 +++++++++++++
> 6 files changed, 443 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q20x.dtsi
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: mxsfb: Indentation cleanup
From: Rob Herring @ 2016-11-16 0:16 UTC (permalink / raw)
To: Marek Vasut
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Lucas Stach,
Fabio Estevam, Shawn Guo, Daniel Vetter,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161114101036.3505-1-marex-ynQEQJNshbs@public.gmane.org>
On Mon, Nov 14, 2016 at 11:10:34AM +0100, Marek Vasut wrote:
> Clean up the ad-hoc indentation in the documentation, no functional change.
>
> Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Documentation/devicetree/bindings/display/mxsfb.txt | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH V2 2/3] dt-bindings: mxsfb: Add new bindings for the MXSFB driver
From: Rob Herring @ 2016-11-16 0:24 UTC (permalink / raw)
To: Marek Vasut
Cc: devicetree, Daniel Vetter, dri-devel, Fabio Estevam, Shawn Guo
In-Reply-To: <20161114101036.3505-2-marex@denx.de>
On Mon, Nov 14, 2016 at 11:10:35AM +0100, Marek Vasut wrote:
> Add new DT bindings for new MXSFB driver that is using the
> OF graph to parse the video output structure instead of
> hard-coding the display properties into the MXSFB node.
> The old MXSFB fbdev driver bindings are preserved in the
> same file in the "Old bindings" section.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: devicetree@vger.kernel.org
> --
> V2: - Merge the new bindings into mxsfb.txt file instead of keeping
> them in separate mxsfb-drm.txt file.
> - Add dedicated compatible for i.MX6SX
> - Drop all references to DRM/KMS
> - Repair the required bits in clock node
> ---
> .../devicetree/bindings/display/mxsfb.txt | 37 ++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt
> index a4431f2..6e92593 100644
> --- a/Documentation/devicetree/bindings/display/mxsfb.txt
> +++ b/Documentation/devicetree/bindings/display/mxsfb.txt
> @@ -1,5 +1,42 @@
> * Freescale MXS LCD Interface (LCDIF)
>
> +New bindings:
> +=============
> +Required properties:
> +- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
> + Should be "fsl,imx28-lcdif" for i.MX28.
> + Should be "fsl,imx6sx-lcdif" for i.MX6SX.
> +- reg: Address and length of the register set for lcdif
s/lcdif/LCDIF/
> +- interrupts: Should contain lcdif interrupts
How many?
> +- clocks: A list of phandle + clock-specifier pairs, one for each
> + entry in 'clock-names'.
> +- clock-names: A list of clock names. For MXSFB it should contain:
> + - "pix" for the MXSFB block clock
MXSFB is not a h/w block. LCDIF is the name.
> + - (MX6SX-only) "axi", "disp_axi" for the bus interface clock
> +
> +Required sub-nodes:
> + - port: The connection to an encoder chip.
> +
> +Example:
> +
> + lcdif1: lcdif@02220000 {
display-controller@...
Drop the leading 0 too.
> + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
I'm not sure compatibility with mx28 is appropriate since you have the
extra clocks. I guess if they don't need to be managed then it's okay.
> + reg = <0x02220000 0x4000>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
> + <&clks IMX6SX_CLK_LCDIF_APB>,
> + <&clks IMX6SX_CLK_DISPLAY_AXI>;
> + clock-names = "pix", "axi", "disp_axi";
> +
> + port {
> + parallel_out: endpoint {
> + remote-endpoint = <&panel_in_parallel>;
> + };
> + };
> + };
> +
> +Old bindings:
s/Old/Deprecated/
> +=============
> Required properties:
> - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
> Should be "fsl,imx28-lcdif" for i.MX28.
> --
> 2.10.2
>
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: specifying order of /dev/mmcblk devices via device-tree?
From: Fabio Estevam @ 2016-11-16 0:33 UTC (permalink / raw)
To: Russell King - ARM Linux, Masahiro Yamada, Michael Turquette
Cc: Tim Harvey, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ulf Hansson,
Fabio Estevam, Javier Martinez Canillas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20161115235503.GC1041-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
[Adding Masahiro and Michael]
On Tue, Nov 15, 2016 at 9:55 PM, Russell King - ARM Linux
<linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
> On Tue, Nov 15, 2016 at 10:10:02PM +0000, Russell King - ARM Linux wrote:
>> On Tue, Nov 15, 2016 at 01:39:42PM -0800, Tim Harvey wrote:
>> > On Tue, Nov 15, 2016 at 1:35 PM, Russell King - ARM Linux
>> > <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
>> > > On Tue, Nov 15, 2016 at 12:27:53PM -0800, Tim Harvey wrote:
>> > >> On Mon, Nov 14, 2016 at 11:08 AM, Russell King - ARM Linux
>> > >> <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org> wrote:
>> > >> > So, someone merged a patch which makes mmcblk devices follow the
>> > >> > host controller numbering.
>> > >> >
>> > >> > Now my cubox-i fails to boot correctly because the SD card in the
>> > >> > _only_ SD card slot now gets called "mmcblk1" and not "mmcblk0".
>> > >> >
>> > >> > USDHC1 is wired to the on-microsom WiFi, and never has anything
>> > >> > remotely near a SD card or eMMC present. So, this change is
>> > >> > confusing on these platforms.
>> > >> >
>> > >> > Moreover, this is _going_ to break SolidRun distros if people upgrade
>> > >> > their kernels.
>> > >> >
>> > >> > It may be appropriate for eMMC, but it's not appropriate everywhere.
>> > >> >
>> > >> > This is a user visible _regression_ in 4.9-rc. Whoever did this,
>> > >> > please revert whatever change caused this, and next time limit it
>> > >> > to only eMMC.
>> > >> >
>> > >> > Thanks.
>> > >>
>> > >> I see the same thing on newer kernels, which is why I asked the
>> > >> question. I didn't expect (or even want honestly) a non mmcblk0 boot
>> > >> device and was looking for a way to control that via dt. Now I'm
>> > >> understanding that to avoid this kind of bootloader/kernel dependence
>> > >> issue I should be using UUID's to identify the boot device.
>> > >>
>> > >> >From my testing it looks like the change your looking for occurred
>> > >> some time ago and is somewhere between 4.5 and 4.6 and not a 4.9
>> > >> regression specifically.
>> > >
>> > > That depends how you look at it. Yes, there's a change in 4.5 to 4.6
>> > > which ties the block device number to the host device index, but that's
>> > > really only part of the story here.
>> > >
>> > > 4.8 definitely identifies the SD card in iMX6 usdhc2 as "mmcblk0".
>> > > 4.9-rc identifies the SD card as "mmcblk1". This makes it a 4.9 change
>> > > of behaviour - there can be no argument about that.
>> > >
>> > > Now, digging further into this today, it appears that:
>> > >
>> > > v4.8: usdhc2 was probed first, and is given mmc0.
>> > > usdhc1 is probed second, and is given mmc1.
>> > >
>> > > v4.9-rc: usdhc1 is probed first, and is given mmc0.
>> > > usdhc2 is probed second, and is given mmc1.
>> > >
>> > > I haven't yet been able to figure out why there's been this change
>> > > of probe order. There's no change that I can see in the iMX6 DT
>> > > files that would account for this.
>> > >
>> >
>> > I bisected it and the commit your looking for is
>> > 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d
>>
>> No it's not.
>>
>> Let me try and put it plainer:
>>
>> * Commit 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d ties the mmc block
>> device number (mmcblkN) to the mmc host interface number (mmcN).
>> This change happened between 4.5 and 4.6.
>>
>> * The change I'm seeing happened between 4.8 and 4.9-rc. I'm not
>> seeing a change of behaviour between 4.5 and 4.6.
>>
>> * The change I'm seeing changes the order of the physical device
>> associated with the hosts named mmc0 and mmc1 in the kernel.
>>
>> * Because physical devices associated with the mmc0 and mmc1 hosts
>> swap over, the mmcblkN number changes due to the commit you point
>> out.
>>
>> * So, the change that I'm seeing between 4.8 and 4.9-rc is not caused
>> by commit 9aaf3437aa72ed5370bf32c99580a3fa2c330e3d, but by something
>> else changing the order in which the two usdhc physical hardware
>> blocks get probed.
>>
>> Does this make it clearer?
>
> It turns out to be this commit:
>
> commit 6eb1c9496b81680f2cd2e0eda06c531317e2e28d
> Author: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Date: Mon Sep 19 01:16:44 2016 +0900
>
> clk: probe common clock drivers earlier
>
> Several SoCs implement platform drivers for clocks rather than
> CLK_OF_DECLARE(). Clocks should come earlier because they are
> prerequisites for many of other drivers. It will help to mitigate
> EPROBE_DEFER issues.
>
> Also, drop the comment since it does not carry much value.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Acked-by: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
>
> which changes the init order. In 4.8, we get:
>
> calling mmc_pwrseq_simple_driver_init+0x0/0x20 @ 1
> bus: 'platform': driver_probe_device: matched device usdhc1_pwrseq with driver pwrseq_simple
> bus: 'platform': really_probe: probing driver pwrseq_simple with device usdhc1_pwrseq
> platform usdhc1_pwrseq: Driver pwrseq_simple requests probe deferral
> platform usdhc1_pwrseq: Added to deferred list
> initcall mmc_pwrseq_simple_driver_init+0x0/0x20 returned 0 after 737 usecs
>
> which then goes on to cause:
>
> calling sdhci_esdhc_imx_driver_init+0x0/0x20 @ 1
> bus: 'platform': driver_probe_device: matched device 2190000.usdhc with driver sdhci-esdhc-imx
> bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2190000.usdhc
> platform 2190000.usdhc: Driver sdhci-esdhc-imx requests probe deferral
> platform 2190000.usdhc: Added to deferred list
>
> followed by:
>
> bus: 'platform': driver_probe_device: matched device 2194000.usdhc with driver sdhci-esdhc-imx
> bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2194000.usdhc
> sdhci-esdhc-imx 2194000.usdhc: Got CD GPIO
> driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2194000.usdhc'
> bus: 'platform': really_probe: bound device 2194000.usdhc to driver sdhci-esdhc-imx
> initcall sdhci_esdhc_imx_driver_init+0x0/0x20 returned 0 after 58205 usecs
>
> and eventually:
>
> mmc0: host does not support reading read-only switch, assuming write-enable
> mmc0: new ultra high speed SDR104 SDHC card at address 0001
> mmcblk0: mmc0:0001 00000 14.9 GiB
> mmcblk0: p1 p2
>
> In 4.9-rc5, we instead get:
>
> calling gpio_clk_driver_init+0x0/0x20 @ 1
> bus: 'platform': driver_probe_device: matched device sdio-clock with driver gpio-clk
> bus: 'platform': really_probe: probing driver gpio-clk with device sdio-clock
> driver: 'gpio-clk': driver_bound: bound to device 'sdio-clock'
> bus: 'platform': really_probe: bound device sdio-clock to driver gpio-clk
> ...
> calling mmc_pwrseq_simple_driver_init+0x0/0x20 @ 1
> bus: 'platform': driver_probe_device: matched device usdhc1_pwrseq with driver pwrseq_simple
> bus: 'platform': really_probe: probing driver pwrseq_simple with device usdhc1_pwrseq
> driver: 'pwrseq_simple': driver_bound: bound to device 'usdhc1_pwrseq'
> bus: 'platform': really_probe: bound device usdhc1_pwrseq to driver pwrseq_simple
> initcall mmc_pwrseq_simple_driver_init+0x0/0x20 returned 0 after 876 usecs
> ...
> calling sdhci_esdhc_imx_driver_init+0x0/0x20 @ 1
> bus: 'platform': driver_probe_device: matched device 2190000.usdhc with driver sdhci-esdhc-imx
> bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2190000.usdhc
> sdhci-esdhc-imx 2190000.usdhc: allocated mmc-pwrseq
> driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2190000.usdhc'
> bus: 'platform': really_probe: bound device 2190000.usdhc to driver sdhci-esdhc-imx
> bus: 'platform': driver_probe_device: matched device 2194000.usdhc with driver sdhci-esdhc-imx
> bus: 'platform': really_probe: probing driver sdhci-esdhc-imx with device 2194000.usdhc
> driver: 'sdhci-esdhc-imx': driver_bound: bound to device '2194000.usdhc'
> bus: 'platform': really_probe: bound device 2194000.usdhc to driver sdhci-esdhc-imx
> initcall sdhci_esdhc_imx_driver_init+0x0/0x20 returned 0 after 384864 usecs
> ...
> mmc1: host does not support reading read-only switch, assuming write-enable
> mmc1: new ultra high speed SDR104 SDHC card at address 0001
> mmcblk1: mmc1:0001 00000 14.9 GiB
> mmcblk1: p1 p2
>
>
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> according to speedtest.net.
> --
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^ permalink raw reply
* [PATCH 0/4] usb: dwc2: Add AHB burst configuration
From: John Youn @ 2016-11-16 0:36 UTC (permalink / raw)
To: John Youn, Felipe Balbi, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland
Cc: Christian Lamparter, Stefan Wahren
This series adds a binding for AHB burst, reads it in, and configures
the controller for the specified burst type.
Tested on HAPS platform with DWC_hsotg IP version 3.30a.
John Youn (4):
usb: dwc2: Fix AHB burst type for bcm2835
usb: dwc2: Add binding for AHB burst
usb: dwc2: Use the ahb_burst param
usb: dwc2: pci: Add AHB burst property for HAPS
Documentation/devicetree/bindings/usb/dwc2.txt | 2 +
drivers/usb/dwc2/core.h | 9 ++++
drivers/usb/dwc2/gadget.c | 2 +-
drivers/usb/dwc2/hcd.c | 8 ++-
drivers/usb/dwc2/params.c | 68 +++++++++++++++++++++-----
drivers/usb/dwc2/pci.c | 1 +
6 files changed, 73 insertions(+), 17 deletions(-)
--
2.10.0
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* [PATCH 0/4] usb: dwc2: Add AHB burst configuration
From: John Youn @ 2016-11-16 0:36 UTC (permalink / raw)
To: John Youn, Felipe Balbi, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland
Cc: Christian Lamparter, Stefan Wahren
This series adds a binding for AHB burst, reads it in, and configures
the controller for the specified burst type.
Tested on HAPS platform with DWC_hsotg IP version 3.30a.
John Youn (4):
usb: dwc2: Fix AHB burst type for bcm2835
usb: dwc2: Add binding for AHB burst
usb: dwc2: Use the ahb_burst param
usb: dwc2: pci: Add AHB burst property for HAPS
Documentation/devicetree/bindings/usb/dwc2.txt | 2 +
drivers/usb/dwc2/core.h | 9 ++++
drivers/usb/dwc2/gadget.c | 2 +-
drivers/usb/dwc2/hcd.c | 8 ++-
drivers/usb/dwc2/params.c | 68 +++++++++++++++++++++-----
drivers/usb/dwc2/pci.c | 1 +
6 files changed, 73 insertions(+), 17 deletions(-)
--
2.10.0
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^ permalink raw reply
* [PATCH 2/4] usb: dwc2: Add binding for AHB burst
From: John Youn @ 2016-11-16 0:36 UTC (permalink / raw)
To: John Youn, Felipe Balbi, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland
Cc: Christian Lamparter, Stefan Wahren
In-Reply-To: <cover.1479256193.git.johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
Add the "snps,ahb-burst" binding and read it in.
This property controls which burst type to perform on the AHB bus as a
master in internal DMA mode. This overrides the legacy param value,
which we need to keep around for now since several platforms use it.
Some platforms may see better or worse performance based on this
value. The HAPS platform is one example where all INCRx have worse
performance than INCR.
Other platforms (such as the Canyonlands board) report that the default
value causes system hangs.
Signed-off-by: John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
Cc: Christian Lamparter <chunkeey-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 2 +
drivers/usb/dwc2/core.h | 9 +++++
drivers/usb/dwc2/params.c | 56 ++++++++++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce..9e7b4b4 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -26,6 +26,8 @@ Optional properties:
Refer to phy/phy-bindings.txt for generic phy consumer properties
- dr_mode: shall be one of "host", "peripheral" and "otg"
Refer to usb/generic.txt
+- snps,ahb-burst: specifies the ahb burst length. Valid arguments are:
+ "SINGLE", "INCR", "INCR4", "INCR8", "INCR16". Defaults to "INCR4".
- g-rx-fifo-size: size of rx fifo size in gadget mode.
- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.
- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 9548d3e..75c238c 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -430,6 +430,12 @@ enum dwc2_ep0_state {
* needed.
* 0 - No (default)
* 1 - Yes
+ * @ahb_burst: Specifies the AHB burst.
+ * 0 - Single
+ * 1 - INCR
+ * 3 - INCR4 (default)
+ * 5 - INCR8
+ * 7 - INCR16
* @g_dma: Enables gadget dma usage (default: autodetect).
* @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
* @g_rx_fifo_size: The periodic rx fifo size for the device, in
@@ -507,6 +513,9 @@ struct dwc2_core_params {
* properties and cannot be set directly in this structure.
*/
+ /* Global parameters */
+ u8 ahb_burst;
+
/* Host parameters */
bool host_dma;
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 96387de..20f2697 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -1091,6 +1091,60 @@ static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
}
}
+static const char *const ahb_bursts[] = {
+ [GAHBCFG_HBSTLEN_SINGLE] = "SINGLE",
+ [GAHBCFG_HBSTLEN_INCR] = "INCR",
+ [GAHBCFG_HBSTLEN_INCR4] = "INCR4",
+ [GAHBCFG_HBSTLEN_INCR8] = "INCR8",
+ [GAHBCFG_HBSTLEN_INCR16] = "INCR16",
+};
+
+static int dwc2_get_property_ahb_burst(struct dwc2_hsotg *hsotg)
+{
+ const char *str = NULL;
+ int burst;
+ int ret;
+
+ ret = device_property_read_string(hsotg->dev,
+ "snps,ahb-burst", &str);
+ if (ret < 0)
+ return ret;
+
+ burst = match_string(ahb_bursts,
+ ARRAY_SIZE(ahb_bursts), str);
+ if (burst < 0) {
+ dev_err(hsotg->dev,
+ "Invalid parameter '%s' for ahb-burst\n", str);
+ }
+
+ return burst;
+}
+
+static void dwc2_set_ahb_burst(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_core_params *p = &hsotg->params;
+ int burst;
+ int ret;
+
+ /* Default burst value */
+ burst = GAHBCFG_HBSTLEN_INCR4;
+
+ /* Get the legacy param value, if set. */
+ if (p->ahbcfg != -1) {
+ burst = (p->ahbcfg & GAHBCFG_HBSTLEN_MASK) >>
+ GAHBCFG_HBSTLEN_SHIFT;
+ }
+
+ /* Override it from devicetree, if set. */
+ ret = dwc2_get_property_ahb_burst(hsotg);
+ if (ret >= 0)
+ burst = ret;
+
+ /* Set the parameter */
+ p->ahb_burst = (u8)burst;
+ dev_dbg(hsotg->dev, "Setting ahb-burst to %d\n", burst);
+}
+
static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg)
{
struct dwc2_hw_params *hw = &hsotg->hw_params;
@@ -1171,6 +1225,8 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
dwc2_set_param_hibernation(hsotg, params->hibernation);
+ dwc2_set_ahb_burst(hsotg);
+
/*
* Set devicetree-only parameters. These parameters do not
* take any values from @params.
--
2.10.0
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^ permalink raw reply related
* Re: [PATCH v2 03/10] clk: rockchip: add dt-binding header for rk1108
From: Shawn Lin @ 2016-11-16 0:40 UTC (permalink / raw)
To: Heiko Stuebner, Andy Yan
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <4684383.I4rhnr9WVC@phil>
On 2016/11/15 17:41, Heiko Stuebner wrote:
> Am Montag, 14. November 2016, 20:04:52 CET schrieb Andy Yan:
>> From: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>
>> Add the dt-bindings header for the rk1108, that gets shared
>> between the clock controller and the clock references in the dts.
>>
>> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>>
>> Changes in v2:
>> - split dt-binding header from clk driver
>>
>> include/dt-bindings/clock/rk1108-cru.h | 270
>> +++++++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+)
>> create mode 100644 include/dt-bindings/clock/rk1108-cru.h
>>
>> diff --git a/include/dt-bindings/clock/rk1108-cru.h
>> b/include/dt-bindings/clock/rk1108-cru.h new file mode 100644
>> index 0000000..6f30008
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/rk1108-cru.h
>> @@ -0,0 +1,270 @@
>> +/*
>> + * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
>> + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
>> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
>> +
>> +/* pll id */
>> +#define RK1108_APLL_ID 0
>> +#define RK1108_DPLL_ID 1
>> +#define RK1108_GPLL_ID 2
>> +#define RK1108_ARMCLK 3
>
> any particular reason for diverging from namings set in the other binding
> headers (PLL_APLL, ARMCLK, ...)?
>
nope, will make it consistent with others. :)
>
>> +
>> +/* sclk gates (special clocks) */
>> +#define SCLK_SPI0 65
>> +#define SCLK_NANDC 67
>> +#define SCLK_SDMMC 68
>> +#define SCLK_SDIO 69
>> +#define SCLK_EMMC 71
>> +#define SCLK_UART0 72
>> +#define SCLK_UART1 73
>> +#define SCLK_UART2 74
>> +#define SCLK_I2S0 75
>> +#define SCLK_I2S1 76
>> +#define SCLK_I2S2 77
>> +#define SCLK_TIMER0 78
>> +#define SCLK_TIMER1 79
>> +#define SCLK_SFC 80
>> +#define SCLK_SDMMC_DRV 81
>> +#define SCLK_SDIO_DRV 82
>> +#define SCLK_EMMC_DRV 83
>> +#define SCLK_SDMMC_SAMPLE 84
>> +#define SCLK_SDIO_SAMPLE 85
>> +#define SCLK_EMMC_SAMPLE 86
>
> the rk1108 seems to have a pretty small clock tree, so maybe you can reduce
> the gap here a bit, like starting at 128 or 192 for the ACLKs and move
> everything up a bit?
>
okay.
> That way you save a bit of space, as we're allocation CLK_NR_CLKS entries or
> the lookup array when probing the clock driver.
>
>
> Heiko
>
>> +/* aclk gates */
>> +#define ACLK_DMAC 251
>> +#define ACLK_PRE 252
>> +#define ACLK_CORE 253
>> +#define ACLK_ENMCORE 254
>> +
>> +/* pclk gates */
>> +#define PCLK_GPIO1 321
>> +#define PCLK_GPIO2 322
>> +#define PCLK_GPIO3 323
>> +#define PCLK_GRF 329
>> +#define PCLK_I2C1 333
>> +#define PCLK_I2C2 334
>> +#define PCLK_I2C3 335
>> +#define PCLK_SPI 338
>> +#define PCLK_SFC 339
>> +#define PCLK_UART0 341
>> +#define PCLK_UART1 342
>> +#define PCLK_UART2 343
>> +#define PCLK_TSADC 344
>> +#define PCLK_PWM 350
>> +#define PCLK_TIMER 353
>> +#define PCLK_PERI 363
>> +
>> +/* hclk gates */
>> +#define HCLK_I2S0_8CH 442
>> +#define HCLK_I2S1_8CH 443
>> +#define HCLK_I2S2_2CH 444
>> +#define HCLK_NANDC 453
>> +#define HCLK_SDMMC 456
>> +#define HCLK_SDIO 457
>> +#define HCLK_EMMC 459
>> +#define HCLK_PERI 478
>> +#define HCLK_SFC 479
>> +
>> +#define CLK_NR_CLKS (HCLK_SFC + 1)
>> +
>> +/* reset id */
>> +#define SRST_CORE_PO_AD 0
>> +#define SRST_CORE_AD 1
>> +#define SRST_L2_AD 2
>> +#define SRST_CPU_NIU_AD 3
>> +#define SRST_CORE_PO 4
>> +#define SRST_CORE 5
>> +#define SRST_L2 6
>> +#define SRST_CORE_DBG 8
>> +#define PRST_DBG 9
>> +#define RST_DAP 10
>> +#define PRST_DBG_NIU 11
>> +#define ARST_STRC_SYS_AD 15
>> +
>> +#define SRST_DDRPHY_CLKDIV 16
>> +#define SRST_DDRPHY 17
>> +#define PRST_DDRPHY 18
>> +#define PRST_HDMIPHY 19
>> +#define PRST_VDACPHY 20
>> +#define PRST_VADCPHY 21
>> +#define PRST_MIPI_CSI_PHY 22
>> +#define PRST_MIPI_DSI_PHY 23
>> +#define PRST_ACODEC 24
>> +#define ARST_BUS_NIU 25
>> +#define PRST_TOP_NIU 26
>> +#define ARST_INTMEM 27
>> +#define HRST_ROM 28
>> +#define ARST_DMAC 29
>> +#define SRST_MSCH_NIU 30
>> +#define PRST_MSCH_NIU 31
>> +
>> +#define PRST_DDRUPCTL 32
>> +#define NRST_DDRUPCTL 33
>> +#define PRST_DDRMON 34
>> +#define HRST_I2S0_8CH 35
>> +#define MRST_I2S0_8CH 36
>> +#define HRST_I2S1_2CH 37
>> +#define MRST_IS21_2CH 38
>> +#define HRST_I2S2_2CH 39
>> +#define MRST_I2S2_2CH 40
>> +#define HRST_CRYPTO 41
>> +#define SRST_CRYPTO 42
>> +#define PRST_SPI 43
>> +#define SRST_SPI 44
>> +#define PRST_UART0 45
>> +#define PRST_UART1 46
>> +#define PRST_UART2 47
>> +
>> +#define SRST_UART0 48
>> +#define SRST_UART1 49
>> +#define SRST_UART2 50
>> +#define PRST_I2C1 51
>> +#define PRST_I2C2 52
>> +#define PRST_I2C3 53
>> +#define SRST_I2C1 54
>> +#define SRST_I2C2 55
>> +#define SRST_I2C3 56
>> +#define PRST_PWM1 58
>> +#define SRST_PWM1 60
>> +#define PRST_WDT 61
>> +#define PRST_GPIO1 62
>> +#define PRST_GPIO2 63
>> +
>> +#define PRST_GPIO3 64
>> +#define PRST_GRF 65
>> +#define PRST_EFUSE 66
>> +#define PRST_EFUSE512 67
>> +#define PRST_TIMER0 68
>> +#define SRST_TIMER0 69
>> +#define SRST_TIMER1 70
>> +#define PRST_TSADC 71
>> +#define SRST_TSADC 72
>> +#define PRST_SARADC 73
>> +#define SRST_SARADC 74
>> +#define HRST_SYSBUS 75
>> +#define PRST_USBGRF 76
>> +
>> +#define ARST_PERIPH_NIU 80
>> +#define HRST_PERIPH_NIU 81
>> +#define PRST_PERIPH_NIU 82
>> +#define HRST_PERIPH 83
>> +#define HRST_SDMMC 84
>> +#define HRST_SDIO 85
>> +#define HRST_EMMC 86
>> +#define HRST_NANDC 87
>> +#define NRST_NANDC 88
>> +#define HRST_SFC 89
>> +#define SRST_SFC 90
>> +#define ARST_GMAC 91
>> +#define HRST_OTG 92
>> +#define SRST_OTG 93
>> +#define SRST_OTG_ADP 94
>> +#define HRST_HOST0 95
>> +
>> +#define HRST_HOST0_AUX 96
>> +#define HRST_HOST0_ARB 97
>> +#define SRST_HOST0_EHCIPHY 98
>> +#define SRST_HOST0_UTMI 99
>> +#define SRST_USBPOR 100
>> +#define SRST_UTMI0 101
>> +#define SRST_UTMI1 102
>> +
>> +#define ARST_VIO0_NIU 102
>> +#define ARST_VIO1_NIU 103
>> +#define HRST_VIO_NIU 104
>> +#define PRST_VIO_NIU 105
>> +#define ARST_VOP 106
>> +#define HRST_VOP 107
>> +#define DRST_VOP 108
>> +#define ARST_IEP 109
>> +#define HRST_IEP 110
>> +#define ARST_RGA 111
>> +#define HRST_RGA 112
>> +#define SRST_RGA 113
>> +#define PRST_CVBS 114
>> +#define PRST_HDMI 115
>> +#define SRST_HDMI 116
>> +#define PRST_MIPI_DSI 117
>> +
>> +#define ARST_ISP_NIU 118
>> +#define HRST_ISP_NIU 119
>> +#define HRST_ISP 120
>> +#define SRST_ISP 121
>> +#define ARST_VIP0 122
>> +#define HRST_VIP0 123
>> +#define PRST_VIP0 124
>> +#define ARST_VIP1 125
>> +#define HRST_VIP1 126
>> +#define PRST_VIP1 127
>> +#define ARST_VIP2 128
>> +#define HRST_VIP2 129
>> +#define PRST_VIP2 120
>> +#define ARST_VIP3 121
>> +#define HRST_VIP3 122
>> +#define PRST_VIP4 123
>> +
>> +#define PRST_CIF1TO4 124
>> +#define SRST_CVBS_CLK 125
>> +#define HRST_CVBS 126
>> +
>> +#define ARST_VPU_NIU 140
>> +#define HRST_VPU_NIU 141
>> +#define ARST_VPU 142
>> +#define HRST_VPU 143
>> +#define ARST_RKVDEC_NIU 144
>> +#define HRST_RKVDEC_NIU 145
>> +#define ARST_RKVDEC 146
>> +#define HRST_RKVDEC 147
>> +#define SRST_RKVDEC_CABAC 148
>> +#define SRST_RKVDEC_CORE 149
>> +#define ARST_RKVENC_NIU 150
>> +#define HRST_RKVENC_NIU 151
>> +#define ARST_RKVENC 152
>> +#define HRST_RKVENC 153
>> +#define SRST_RKVENC_CORE 154
>> +
>> +#define SRST_DSP_CORE 156
>> +#define SRST_DSP_SYS 157
>> +#define SRST_DSP_GLOBAL 158
>> +#define SRST_DSP_OECM 159
>> +#define PRST_DSP_IOP_NIU 160
>> +#define ARST_DSP_EPP_NIU 161
>> +#define ARST_DSP_EDP_NIU 162
>> +#define PRST_DSP_DBG_NIU 163
>> +#define PRST_DSP_CFG_NIU 164
>> +#define PRST_DSP_GRF 165
>> +#define PRST_DSP_MAILBOX 166
>> +#define PRST_DSP_INTC 167
>> +#define PRST_DSP_PFM_MON 169
>> +#define SRST_DSP_PFM_MON 170
>> +#define ARST_DSP_EDAP_NIU 171
>> +
>> +#define SRST_PMU 172
>> +#define SRST_PMU_I2C0 173
>> +#define PRST_PMU_I2C0 174
>> +#define PRST_PMU_GPIO0 175
>> +#define PRST_PMU_INTMEM 176
>> +#define PRST_PMU_PWM0 177
>> +#define SRST_PMU_PWM0 178
>> +#define PRST_PMU_GRF 179
>> +#define SRST_PMU_NIU 180
>> +#define SRST_PMU_PVTM 181
>> +#define ARST_DSP_EDP_PERF 184
>> +#define ARST_DSP_EPP_PERF 185
>> +
>> +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */
>> +
>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
--
Best Regards
Shawn Lin
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^ permalink raw reply
* Re: [PATCH v2 02/10] dt-bindings: add documentation for rk1108 cru
From: Shawn Lin @ 2016-11-16 0:44 UTC (permalink / raw)
To: Heiko Stuebner, Andy Yan
Cc: shawn.lin, mark.rutland, devicetree, sboyd, linux-kernel,
linux-rockchip, robh+dt, mturquette
In-Reply-To: <2131710.LesyKkLYAr@phil>
On 2016/11/15 17:35, Heiko Stuebner wrote:
> Hi Andy,
>
> Am Montag, 14. November 2016, 20:03:01 CET schrieb Andy Yan:
>> From: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> This adds the dt-binding documentation for the clock and reset unit
>> found on Rockchip rk1108 SoCs.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>> ---
>>
>> Changes in v2: None
>>
>> .../bindings/clock/rockchip,rk1108-cru.txt | 60
>> ++++++++++++++++++++++ 1 file changed, 60 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt
>> b/Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt new file
>> mode 100644
>> index 0000000..4d2356b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt
>> @@ -0,0 +1,60 @@
>> +* Rockchip RK1108 Clock and Reset Unit
>> +
>> +The RK1108 clock controller generates and supplies clock to various
>> +controllers within the SoC and also implements a reset controller for SoC
>> +peripherals.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "rockchip,rk1108-cru"
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +- #clock-cells: should be 1.
>> +- #reset-cells: should be 1.
>> +
>> +Optional Properties:
>> +
>> +- rockchip,grf: phandle to the syscon managing the "general register files"
>> + If missing pll rates are not changeable, due to the missing pll lock
>> status. +
>> +Each clock is assigned an identifier and client nodes can use this
>> identifier +to specify the clock which they consume. All available clocks
>> are defined as +preprocessor macros in the dt-bindings/clock/rk1108-cru.h
>> headers and can be +used in device tree sources. Similar macros exist for
>> the reset sources in +these files.
>> +
>> +External clocks:
>> +
>> +There are several clocks that are generated outside the SoC. It is expected
>> +that they are defined using standard clock bindings with following
>> +clock-output-names:
>> + - "xin24m" - crystal input - required,
>> + - "cif_clkout" - output clock for the cif - optional
>> + - "mipi_csi_clkout" - output clock for the mipi csi - optional
>> + - "pclkin_vip" - external VIP clock - optional
>> + - "ext_i2s" - external I2S clock - optional
>> + - "ext_gmac" - external GMAC clock - optional
>> + - "mac_ref_clkout" - output clock of the pll in the mac phy
>
> we really only want to list the actual input clocks here, not outputs.
>
> Also, the list of actual input clocks seems incomplete (hdmiphy, usbphy) and
> some clocks listed here do not match the clock controller 2 patches later
> (pclkin_vip, ext_gmac [rk1108 only has 10/100], ext_i2s, ...)
>
yup, I was just listing the basic clock for Andy to bring up rk1108
board, so some of them was missing here. I will fix them here as well
as adding all of the input clocks in the clock driver. :)
>
> Heiko
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* Re: [RESEND PATCH 2/2] PCI: rockchip: Add quirk to disable RC's ASPM L0s
From: Shawn Lin @ 2016-11-16 0:52 UTC (permalink / raw)
To: Rob Herring
Cc: Shawn Lin, Bjorn Helgaas, linux-pci-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Wenrui Li,
Brian Norris, Jeffy Chen, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161115222649.uymslcg2fyfwtxpd@rob-hp-laptop>
Hi Rob,
On 2016/11/16 6:26, Rob Herring wrote:
> On Mon, Nov 14, 2016 at 12:11:06PM +0800, Shawn Lin wrote:
>> Rockchip's RC outputs 100MHz reference clock but there are
>> two methods for PHY to generate it.
>>
>> (1)One of them is to use system PLL to generate 100MHz clock and
>> the PHY will relock it and filter signal noise then outputs the
>> reference clock.
>>
>> (2)Another way is to share Soc's 24MHZ crystal oscillator with
>> PHY and force PHY's DLL to generate 100MHz internally.
>>
>> When using case(2), the exit from L0s doesn't work fine occasionally
>> due to the broken design of RC receiver's logical circuit. So even if
>> we use extended-synch, it still fails for PHY to relock the bits from
>> FTS sometimes. This will hang the system.
>>
>> Maybe we could argue that why not use case(1) to avoid it? The reason
>> is that as we could see the reference clock is derived from system PLL
>> and the path from it to PHY isn't so clean which means there are some
>> noise introduced by power-domain and other buses can't be filterd out
>> by PHY and we could see noise from the frequency spectrum by oscilloscope.
>> This makes the TX compatibility test a little difficult to pass the spec.
>> So case(1) and case(2) are both used indeed now. If using case(2), we
>> should disable RC's L0s support, and that is why we need this property to
>> indicate this quirk.
>
> Doesn't the driver know which case it is using? I don't see why you need
> the quirk property.
Unfortunately it doesn't. This is one of the pre-input clock for PHY but
doesn't get any indication from the register of both PHY and controller.
So assigning a quirk seems quite straightforward.
>>
>> Also after checking quirk.c, I noticed there is already a quirk for
>> disabling L0s unconditionally, quirk_disable_aspm_l0s. But obviously we
>> shouldn't do that as mentioned above that case(1) could still works fine
>> with L0s.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
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>
--
Best Regards
Shawn Lin
--
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^ permalink raw reply
* [PATCH v3 0/3] Remove clocks dependency from SCM driver
From: Sarangdhar Joshi @ 2016-11-16 1:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Bjorn Andersson
Cc: Sarangdhar Joshi, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, Stephen Boyd, Trilok Soni
On earlier chiptsets (APQ8064, MSM8660, MSM8690, MSM8916,
APQ8084, MSM8974) crypto operations of TZ were depends on crypto
clocks controlled by users/clients. However on MSM8996 crypto clocks
control is handled internally in TZ itself. The current series of
patches handle this clock dependency in SCM driver.
Changes since v2:
- Use typecast of 'unsigned long' for pointer (Stephen)
Changes since v1:
- Added Rob's Acked-by
- Removed of_device_is_compatible check from probe (Stephen)
- Modified typecast to take care of 32-bit pointer
Sarangdhar Joshi (3):
dt-bindings: firmware: scm: Add MSM8996 DT bindings
firmware: qcom: scm: Remove core, iface and bus clocks dependency
firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails
.../devicetree/bindings/firmware/qcom,scm.txt | 2 +
drivers/firmware/qcom_scm.c | 49 ++++++++++++++++------
2 files changed, 39 insertions(+), 12 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/3] dt-bindings: firmware: scm: Add MSM8996 DT bindings
From: Sarangdhar Joshi @ 2016-11-16 1:19 UTC (permalink / raw)
To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon
Cc: Sarangdhar Joshi, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, Bjorn Andersson, Jordan Crouse,
Stephen Boyd, Trilok Soni
In-Reply-To: <1479259165-1601-1-git-send-email-spjoshi@codeaurora.org>
Add SCM DT bindings for Qualcomm's MSM8996 platform.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 3b4436e..20f26fb 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -10,8 +10,10 @@ Required properties:
* "qcom,scm-apq8064" for APQ8064 platforms
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
+ * "qcom,scm-msm8996" for MSM8996 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
+ * No clock required for "qcom,scm-msm8996"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH 2/2] mtd: spi-nor: add rockchip serial flash controller driver
From: Shawn Lin @ 2016-11-16 1:59 UTC (permalink / raw)
To: Marek Vasut, Rob Herring, David Woodhouse, Brian Norris
Cc: Shawn Lin, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <b1420e9d-b6a1-7fe8-4381-e32e0bc7dd53-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Marek,
Thanks for reviewing my patch, and it's really
helpful to improve it. :) See my feedback for
your comments below.
On 2016/11/16 4:52, Marek Vasut wrote:
> On 11/11/2016 10:16 AM, Shawn Lin wrote:
>> Add rockchip serial flash controller driver
>>
>> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
>
> [...]
>
>> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
>> index 4a682ee..48c5e0e 100644
>> --- a/drivers/mtd/spi-nor/Kconfig
>> +++ b/drivers/mtd/spi-nor/Kconfig
>> @@ -65,6 +65,13 @@ config SPI_HISI_SFC
>> help
>> This enables support for hisilicon SPI-NOR flash controller.
>>
>> +config SPI_ROCKCHIP_SFC
>
> Keep this list sorted please.
yup, will fix.
>
>> + tristate "Rockchip Serial Flash Controller(SFC)"
>> + depends on ARCH_ROCKCHIP || COMPILE_TEST
>> + depends on HAS_IOMEM && HAS_DMA
>> + help
>> + This enables support for rockchip serial flash controller.
>> +
>> config SPI_NXP_SPIFI
>> tristate "NXP SPI Flash Interface (SPIFI)"
>> depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
>
>
> [...]
>
>> +/* Interrypt mask */
>
> Interrupt :)
will fix. :)
>
>> +#define SFC_IMR 0x4
>> +#define SFC_IMR_RX_FULL BIT(0)
>> +#define SFC_IMR_RX_UFLOW BIT(1)
>> +#define SFC_IMR_TX_OFLOW BIT(2)
>> +#define SFC_IMR_TX_EMPTY BIT(3)
>> +#define SFC_IMR_TRAN_FINISH BIT(4)
>> +#define SFC_IMR_BUS_ERR BIT(5)
>> +#define SFC_IMR_NSPI_ERR BIT(6)
>> +#define SFC_IMR_DMA BIT(7)
>
>
> [...]
>
>> +enum rockchip_sfc_iftype {
>> + IF_TYPE_STD,
>> + IF_TYPE_DUAL,
>> + IF_TYPE_QUAD,
>> +};
>> +
>> +struct rockchip_sfc {
>> + struct device *dev;
>> + struct mutex lock;
>> + void __iomem *regbase;
>> + struct clk *hclk;
>> + struct clk *clk;
>> + void *buffer;
>> + dma_addr_t dma_buffer;
>
> The naming (buffer) could use some improvement or comment for clarification.
>
>> + struct completion cp;
>> + struct spi_nor *nor[SFC_MAX_CHIP_NUM];
>
> Should be MAX_CHIPSELECT_NUM , for clarity.
seems sane, will fix.
>
>> + u32 num_chip;
>
> u8
>
>> + bool use_dma;
>> + bool negative_edge;
>
> Negative edge ... of what ?
For how the inner sample logic to letch the data. It should be
configured differently for different Socs. I will add a comment
here to clarify it.
>
>> +};
>> +
>> +struct rockchip_sfc_priv {
>> + u32 cs;
>
> Doesn't this board support only 4 CS ? Use u8 :-)
>
good catch, will fix it.
>> + u32 clk_rate;
>> + struct rockchip_sfc *sfc;
>> +};
>> +
>> +static int get_if_type(enum read_mode flash_read)
>> +{
>> + enum rockchip_sfc_iftype if_type;
>> +
>> + switch (flash_read) {
>> + case SPI_NOR_DUAL:
>> + if_type = IF_TYPE_DUAL;
>> + break;
>> + case SPI_NOR_QUAD:
>> + if_type = IF_TYPE_QUAD;
>> + break;
>> + case SPI_NOR_NORMAL:
>> + case SPI_NOR_FAST:
>> + default:
>
> Should the default case really fall back to 1-bit mode or should it
> rather report error ?
It's derived from nor->flash_read, so personlly I think there should
never fall into the default case, but it would make sense to return
-EINVAL instead of falling into 1-bit mode. I will fix it.
>
>> + if_type = IF_TYPE_STD;
>> + break;
>> + }
>> +
>> + return if_type;
>> +}
>> +
>> +static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
>> +{
>> + unsigned long timeout = jiffies + HZ;
>> + int err = -ETIMEDOUT;
>> + u32 status;
>> +
>> + writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
>> +
>> + while (time_before(jiffies, timeout)) {
>
> Would readl_poll_*() from include/linux/iopoll.h help here ?
>
Brilliant, it looks great to me.
>> + status = readl_relaxed(sfc->regbase + SFC_RCVR);
>> + if (!(status & SFC_RCVR_RESET)) {
>> + err = 0;
>> + break;
>> + }
>> + msleep(20);
>> + }
>> +
>> + if (err)
>> + dev_err(sfc->dev, "SFC reset never finished\n");
>
> Should the writel() below be executed if an error happened ?
It's needed since when doing reset after failing to finish
a previous transfer for whatever reason, we could observed some of the
interrupts triggered. Although we masked them but we could still
find them from the raw interrupt status register. So cleaning
it explicitly make senses.
>
>> + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW |
>> + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY |
>> + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR |
>> + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA,
>> + sfc->regbase + SFC_ICLR);
>> + return err;
>> +}
>> +
>> +static int rockchip_sfc_init(struct rockchip_sfc *sfc)
>> +{
>> + int err;
>> +
>> + err = rockchip_sfc_reset(sfc);
>> + if (err)
>> + return err;
>> +
>> + /* Mask all eight interrupts */
>> + writel_relaxed(0xff, sfc->regbase + SFC_IMR);
>> + /* Phase configure */
>
> What phase ? Please clarify the comment. Also, don't you have to
> configure the register if sfc->negative_edge == 0 too ?
will elaborate more.
Your comment makes me think it twice. The loader should
already set this but we could override it agian in case
of some other code clear it. I was assuming that the reset
value of it meets what we need for "sfc->negative_edge == 0",
but I think I am wrong since we still need to prevent some other
whatever code modified it before jumping into rockchip_sfc_probe.
So yes, I will fix it. :)
>
>> + if (sfc->negative_edge)
>> + writel_relaxed(SFC_CTRL_PHASE_SEL_NEGETIVE <<
>> + SFC_CTRL_PHASE_SEL_SHIFT,
>> + sfc->regbase + SFC_CTRL);
>> + return 0;
>> +}
>> +
>> +static int rockchip_sfc_prep(struct spi_nor *nor, enum spi_nor_ops ops)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + int ret;
>> +
>> + mutex_lock(&sfc->lock);
>> +
>> + ret = clk_set_rate(sfc->clk, priv->clk_rate);
>> + if (ret)
>> + goto out;
>> +
>> + ret = clk_prepare_enable(sfc->clk);
>> + if (ret)
>> + goto out;
>> +
>> + return 0;
>> +
>> +out:
>> + mutex_unlock(&sfc->lock);
>> + return ret;
>> +}
>> +
>> +static void rockchip_sfc_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> +
>> + clk_disable_unprepare(sfc->clk);
>> + mutex_unlock(&sfc->lock);
>> +}
>> +
>> +static int rockchip_sfc_wait_op_finish(struct rockchip_sfc *sfc)
>> +{
>> + unsigned long timeout = jiffies + 2 * HZ;
>> + int err = -ETIMEDOUT;
>> + u32 status;
>> +
>> + /*
>> + * Note: tx and rx share the same fifo, so the rx's water level
>> + * is the same as rx's, which means this function could be reused
>> + * for checking the read operations as well.
>> + */
>> + while (time_before(jiffies, timeout)) {
>
> readl_poll_*() ?
sure.
>
>> + status = readl_relaxed(sfc->regbase + SFC_FSR);
>> + if (((status >> SFC_FSR_TX_EMPTY_SHIFT) &
>> + SFC_FSR_TX_EMPTY_MASK) == SFC_FSR_TX_IS_EMPTY) {
>> + err = 0;
>> + break;
>> + }
>> + msleep(20);
>> + }
>> +
>> + if (err)
>> + dev_err(sfc->dev, "SFC tx never empty\n");
>> +
>> + return err;
>> +}
>> +
>> +static int rockchip_sfc_op_reg(struct spi_nor *nor,
>> + u8 opcode, int len, u8 optype)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + u32 reg;
>> +
>> + if (((readl_relaxed(sfc->regbase + SFC_FSR) >> SFC_FSR_TX_EMPTY_SHIFT) &
>> + SFC_FSR_TX_EMPTY_MASK) != SFC_FSR_TX_IS_EMPTY ||
>> + ((readl_relaxed(sfc->regbase + SFC_FSR) >>
>> + SFC_FSR_RX_EMPTY_SHIFT) &
>> + SFC_FSR_RX_EMPTY_MASK) != SFC_FSR_RX_IS_EMPTY ||
>> + (readl_relaxed(sfc->regbase + SFC_SR) == SFC_SR_IS_BUSY))
>> + rockchip_sfc_reset(sfc);
>
> This is chaos, please fix this condition so it's actually readable. You
> can ie. read the FSR into a variable, do your shifting/anding magic and
> then do if (var1 || var2 || var3) {} .
okay, will make it more clearly.
>
>> + reg = (opcode & SFC_CMD_IDX_MASK) << SFC_CMD_IDX_SHIFT;
>> + reg |= (len & SFC_CMD_TRAN_BYTES_MASK) << SFC_CMD_TRAN_BYTES_SHIFT;
>> + reg |= (priv->cs & SFC_CMD_CS_MASK) << SFC_CMD_CS_SHIFT;
>> + reg |= (optype & SFC_CMD_DIR_MASK) << SFC_CMD_DIR_SHIFT;
>> +
>> + writel_relaxed(reg, sfc->regbase + SFC_CMD);
>> +
>> + return rockchip_sfc_wait_op_finish(sfc);
>> +}
>> +
>> +static int rockchip_sfc_read_reg(struct spi_nor *nor, u8 opcode,
>> + u8 *buf, int len)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + int ret;
>> + u32 tmp;
>> + u32 i;
>> +
>> + ret = rockchip_sfc_op_reg(nor, opcode, len, SFC_CMD_DIR_RD);
>> + if (ret)
>> + return ret;
>> +
>> + while (len > 0) {
>> + tmp = readl_relaxed(sfc->regbase + SFC_DATA);
>> + for (i = 0; i < len; i++)
>> + *buf++ = (u8)((tmp >> (i * 8)) & 0xff);
>
> Won't this fail for len > 4 ?
nope, this loop will reduce 4 for each successful readl. And
reading the remained bytes which isn't aligned to DWORD, isn't it?
>
> Also, you can use ioread32_rep() here, but (!) that won't work for
> unaligned reads, which I dunno if they can happen here, but please do
> double-check.
yes, I have checked this API as well as others like memcpy_{to,from}io
, etc. They will generate a external abort for arm core as the unaligned
(DWORD) read/write via AHB aren't supported by Rockchip Socs. So I have
to open code these stuff. This could be easily found for other
upstreamed rockchip drivers. :)
>
>> + len = len - 4;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_sfc_write_reg(struct spi_nor *nor, u8 opcode,
>> + u8 *buf, int len)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + u32 words, i;
>> +
>> + /* Align bytes to words */
>> + words = (len + 3) >> 2;
>> +
>> + for (i = 0; i < words; i++)
>> + writel_relaxed(*(buf + 4 * i), sfc->regbase + SFC_DATA);
>
> See above about the ioread32_rep()/iowrite32_rep(), but careful about
> unaligned (len % 4 != 0) case.
Ditto for above. :)
>
>> + return rockchip_sfc_op_reg(nor, opcode, len, SFC_CMD_DIR_WR);
>> +}
>> +
>> +static int rockchip_sfc_dma_transfer(struct spi_nor *nor, loff_t from_to,
>> + dma_addr_t dma_buf, size_t len, u8 op_type)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + u32 reg;
>> + u8 if_type = 0;
>> +
>> + init_completion(&sfc->cp);
>> +
>> + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW |
>> + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY |
>> + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR |
>> + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA,
>> + sfc->regbase + SFC_ICLR);
>> +
>> + /* Enable transfer complete interrupt */
>> + reg = readl_relaxed(sfc->regbase + SFC_IMR);
>> + reg &= ~SFC_IMR_TRAN_FINISH;
>> + writel_relaxed(reg, sfc->regbase + SFC_IMR);
>> +
>> + if (op_type == SFC_CMD_DIR_WR)
>> + reg = (SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT) |
>> + ((nor->program_opcode & SFC_CMD_IDX_MASK) <<
>> + SFC_CMD_IDX_SHIFT);
>> + else
>> + reg = (SFC_CMD_DIR_RD << SFC_CMD_DIR_SHIFT) |
>> + ((nor->read_opcode & SFC_CMD_IDX_MASK) <<
>> + SFC_CMD_IDX_SHIFT);
>
> reg = nor->read_opcode & SFC_CMD_IDX_MASK) << SFC_CMD_IDX_SHIFT;
> reg |= op_type << SFC_CMD_DIR_SHIFT;
will improve.
>
>> + reg |= ((nor->addr_width == 4) ? SFC_CMD_ADDR_32BITS
>> + : SFC_CMD_ADDR_24BITS) << SFC_CMD_ADDR_SHIFT;
>
> Why don't you just define those SFC_CMD_ADDR_24BITS and co. with the
> shift in those bitfields already ? Then you wouldn't have to riddle this
> driver with FOO << BAR, but you'd only have FOO all over the place.
>
sounds good, will improve them..
>> + if_type = get_if_type(nor->flash_read);
>> + writel_relaxed(if_type << SFC_CTRL_DATA_BITS_SHIFT |
>> + if_type << SFC_CTRL_ADDR_BITS_SHIFT |
>> + if_type << SFC_CTRL_CMD_BITS_SHIFT |
>
> Parenthesis missing around the statements ,
> (if_type << FOO) | (... << bar)
>
will improve it.
>> + sfc->negative_edge ?
>> + SFC_CTRL_PHASE_SEL_NEGETIVE << SFC_CTRL_PHASE_SEL_SHIFT :
>> + SFC_CTRL_PHASE_SEL_POSITIVE << SFC_CTRL_PHASE_SEL_SHIFT,
>> + sfc->regbase + SFC_CTRL);
>> +
>> + reg |= (priv->cs & SFC_CMD_CS_MASK) << SFC_CMD_CS_SHIFT;
>> + reg |= (len & SFC_CMD_TRAN_BYTES_MASK) << SFC_CMD_TRAN_BYTES_SHIFT;
>> +
>> + if (op_type == SFC_CMD_DIR_RD)
>> + reg |= (nor->read_dummy & SFC_CMD_DUMMY_MASK) <<
>> + SFC_CMD_DUMMY_SHIFT;
>
> Just define SFC_CMD_DUMMY(x) \
> (((x) & SFC_CMD_DUMMY_MASK) << SFC_CMD_DUMMY_SHIFT)
>
> And then use it ... reg |= SFC_CMD_DUMMY(nor->read_dummy);
sure.
>
>> + /* Should minus one as 0x0 means 1 bit flash address */
>> + writel_relaxed(nor->addr_width * 8 - 1, sfc->regbase + SFC_ABIT);
>> + writel_relaxed(reg, sfc->regbase + SFC_CMD);
>> + writel_relaxed(from_to, sfc->regbase + SFC_ADDR);
>> + writel_relaxed(dma_buf, sfc->regbase + SFC_DMA_ADDR);
>
> I hope the DMA buffer management is implemented correctly and you're not
> running into any weird cache issues.
you are right. I should sync it after doing read and before doing write.
>
>> + /* Start dma */
>> + writel_relaxed(0x1, sfc->regbase + SFC_DMA_TRIGGER);
>> +
>> + /* Wait for the interrupt. */
>> + if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) {
>> + dev_err(sfc->dev, "DMA wait for transfer finish timeout.");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + /* Disable transfer finish interrupt */
>> + reg = readl_relaxed(sfc->regbase + SFC_IMR);
>> + reg |= SFC_IMR_TRAN_FINISH;
>> + writel_relaxed(reg, sfc->regbase + SFC_IMR);
>> +
>> + return rockchip_sfc_wait_op_finish(sfc);
>> +}
>> +
>> +static inline int rockchip_sfc_pio_write(struct rockchip_sfc *sfc, u_char *buf,
>> + size_t len)
>> +{
>> + u32 words, tx_wl, count, i;
>> + unsigned long timeout;
>> + int ret = 0;
>> + u32 *tbuf = (u32 *)buf;
>> +
>> + /* Align bytes to words */
>> + words = (len + 3) >> 2;
>> +
>> + while (words) {
>
> See iowrite32_rep() above, but I suspect you'll run into problems with
> $len which is not multiple of 4 .
>
Ditto for above.
>> + tx_wl = (readl_relaxed(sfc->regbase + SFC_FSR) >>
>> + SFC_FSR_TX_WATER_LVL_SHIFT) &
>> + SFC_FSR_TX_WATER_LVL_MASK;
>> +
>> + if (tx_wl > 0) {
>> + count = min_t(u32, words, tx_wl);
>> + for (i = 0; i < count; i++) {
>> + writel_relaxed(*tbuf++,
>> + sfc->regbase + SFC_DATA);
>> + words--;
>> + }
>> +
>> + if (words == 0)
>> + break;
>> + timeout = 0;
>> + } else {
>> + mdelay(1);
>> + if (timeout++ > SFC_MAX_IDLE_RETRY) {
>> + ret = -ETIMEDOUT;
>> + break;
>> + }
>> + }
>> + }
>> +
>> + if (ret)
>> + return ret;
>> + else
>> + return rockchip_sfc_wait_op_finish(sfc);
>> +}
>> +
>> +static inline int rockchip_sfc_pio_read(struct rockchip_sfc *sfc, u_char *buf,
>> + size_t len)
>> +{
>> + u32 words, rx_wl, count, i;
>> + unsigned long timeout;
>> + int ret = 0;
>> + u32 tmp;
>> + u32 *tbuf = (u32 *)buf;
>> + u_char *tbuf2;
>> +
>> + words = len >> 2;
>> + /* Get the remained bytes */
>> + len = len & 0x3;
>
> See above.
>
>> + while (words) {
>> + rx_wl = (readl_relaxed(sfc->regbase + SFC_FSR) >>
>> + SFC_FSR_RX_WATER_LVL_SHIFT) &
>> + SFC_FSR_RX_WATER_LVL_MASK;
>> +
>> + if (rx_wl > 0) {
>> + count = min_t(u32, words, rx_wl);
>> + for (i = 0; i < count; i++) {
>> + *tbuf++ = readl_relaxed(sfc->regbase +
>> + SFC_DATA);
>> + words--;
>> + }
>> +
>> + if (words == 0)
>> + break;
>> + timeout = 0;
>> + } else {
>> + mdelay(1);
>> + if (timeout++ > SFC_MAX_IDLE_RETRY) {
>> + ret = -ETIMEDOUT;
>> + break;
>> + }
>> + }
>> + }
>> +
>> + if (ret)
>> + return ret;
>> +
>> + /* Read the remained bytes */
>> + timeout = 0;
>> + tbuf2 = (u_char *)tbuf;
>> + while (len) {
>> + rx_wl = (readl_relaxed(sfc->regbase + SFC_FSR) >>
>> + SFC_FSR_RX_WATER_LVL_SHIFT) &
>> + SFC_FSR_RX_WATER_LVL_MASK;
>> + if (rx_wl > 0) {
>> + tmp = readl_relaxed(sfc->regbase + SFC_DATA);
>> + for (i = 0; i < len; i++)
>> + tbuf2[i] = (u8)((tmp >> (i * 8)) & 0xff);
>> + goto done;
>> + } else {
>> + mdelay(1);
>> + if (timeout++ > SFC_MAX_IDLE_RETRY) {
>> + ret = -ETIMEDOUT;
>> + break;
>> + }
>> + }
>> + }
>> +done:
>> + if (ret)
>> + return ret;
>> + else
>> + return rockchip_sfc_wait_op_finish(sfc);
>> +}
>> +
>> +static int rockchip_sfc_pio_transfer(struct spi_nor *nor, loff_t from_to,
>> + size_t len, u_char *buf, u8 op_type)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + u32 reg;
>> + u8 if_type = 0;
>> +
>> + if (op_type == SFC_CMD_DIR_WR)
>> + reg = (SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT) |
>> + ((nor->program_opcode & SFC_CMD_IDX_MASK) <<
>> + SFC_CMD_IDX_SHIFT);
>> + else
>> + reg = (SFC_CMD_DIR_RD << SFC_CMD_DIR_SHIFT) |
>> + ((nor->read_opcode & SFC_CMD_IDX_MASK) <<
>> + SFC_CMD_IDX_SHIFT);
>
> See above regarding this condition. I think you can factor out this
> common code too. Also nuke the bitshifts , see my comments on
> rockchip_sfc_dma_transfer .
>
sure. Will fix the bitshifts and factor out the common code.
>> + reg |= ((nor->addr_width == 4) ? SFC_CMD_ADDR_32BITS
>> + : SFC_CMD_ADDR_24BITS) << SFC_CMD_ADDR_SHIFT;
>> +
>> + if_type = get_if_type(nor->flash_read);
>> + writel_relaxed(if_type << SFC_CTRL_DATA_BITS_SHIFT |
>> + if_type << SFC_CTRL_ADDR_BITS_SHIFT |
>> + if_type << SFC_CTRL_CMD_BITS_SHIFT |
>> + sfc->negative_edge ?
>> + SFC_CTRL_PHASE_SEL_NEGETIVE << SFC_CTRL_PHASE_SEL_SHIFT :
>> + SFC_CTRL_PHASE_SEL_POSITIVE << SFC_CTRL_PHASE_SEL_SHIFT,
>> + sfc->regbase + SFC_CTRL);
>> +
>> + reg |= (priv->cs & SFC_CMD_CS_MASK) << SFC_CMD_CS_SHIFT;
>> + reg |= (len & SFC_CMD_TRAN_BYTES_MASK) << SFC_CMD_TRAN_BYTES_SHIFT;
>> +
>> + if (op_type == SFC_CMD_DIR_RD)
>> + reg |= (nor->read_dummy & SFC_CMD_DUMMY_MASK) <<
>> + SFC_CMD_DUMMY_SHIFT;
>> +
>> + /* Should minus one as 0x0 means 1 bit flash address */
>> + writel_relaxed(nor->addr_width * 8 - 1, sfc->regbase + SFC_ABIT);
>> + writel_relaxed(reg, sfc->regbase + SFC_CMD);
>> + writel_relaxed(from_to, sfc->regbase + SFC_ADDR);
>> +
>> + if (op_type == SFC_CMD_DIR_WR)
>> + return rockchip_sfc_pio_write(sfc, buf, len);
>> + else
>> + return rockchip_sfc_pio_read(sfc, buf, len);
>> +}
>> +
>> +static ssize_t rockchip_sfc_read(struct spi_nor *nor, loff_t from, size_t len,
>> + u_char *read_buf)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + size_t offset;
>> + int ret;
>> + dma_addr_t dma_addr = 0;
>> +
>> + if (!sfc->use_dma)
>> + goto no_dma;
>> +
>> + for (offset = 0; offset < len; offset += SFC_DMA_MAX_LEN) {
>> + size_t trans = min_t(size_t, SFC_DMA_MAX_LEN, len - offset);
>> +
>> + dma_addr = dma_map_single(NULL, (void *)read_buf,
>> + trans, DMA_FROM_DEVICE);
>> + if (dma_mapping_error(sfc->dev, dma_addr))
>> + dma_addr = 0;
>> +
>> + /* Fail to map dma, use pre-allocated area instead */
>> + ret = rockchip_sfc_dma_transfer(nor, from + offset,
>> + dma_addr ? dma_addr :
>> + sfc->dma_buffer,
>> + trans, SFC_CMD_DIR_RD);
>> + if (ret) {
>> + dev_warn(nor->dev, "DMA read timeout\n");
>> + return ret;
>> + }
>> + if (!dma_addr)
>> + memcpy(read_buf + offset, sfc->buffer, trans);
>> + }
>> +
>> + return len;
>> +
>> +no_dma:
>> + ret = rockchip_sfc_pio_transfer(nor, from, len,
>> + read_buf, SFC_CMD_DIR_RD);
>> + if (ret) {
>> + dev_warn(nor->dev, "PIO read timeout\n");
>> + return ret;
>> + }
>> + return len;
>> +}
>> +
>> +static ssize_t rockchip_sfc_write(struct spi_nor *nor, loff_t to,
>> + size_t len, const u_char *write_buf)
>> +{
>> + struct rockchip_sfc_priv *priv = nor->priv;
>> + struct rockchip_sfc *sfc = priv->sfc;
>> + size_t offset;
>> + int ret;
>> + dma_addr_t dma_addr = 0;
>> +
>> + if (!sfc->use_dma)
>> + goto no_dma;
>
> Seems like there's a lot of similarity between read/write .
I was thinking to combine read/write with a extra argument to
indicate WR/RD. But as we could see still some differece between
WR and RD and there are already some condiction checks. So it
will make the code hard to read with stuffing lots of condition
checks. So I splited out read and write strightforward. :)
>
>> + for (offset = 0; offset < len; offset += SFC_DMA_MAX_LEN) {
>> + size_t trans = min_t(size_t, SFC_DMA_MAX_LEN, len - offset);
>> +
>> + dma_addr = dma_map_single(NULL, (void *)write_buf,
>> + trans, DMA_TO_DEVICE);
>> + if (dma_mapping_error(sfc->dev, dma_addr)) {
>> + dma_addr = 0;
>> + memcpy(sfc->buffer, write_buf + offset, trans);
>> + }
>> +
>> + /* Fail to map dma, use pre-allocated area instead */
>> + ret = rockchip_sfc_dma_transfer(nor, to + offset,
>> + dma_addr ? dma_addr :
>> + sfc->dma_buffer,
>> + trans, SFC_CMD_DIR_WR);
>> + if (dma_addr)
>> + dma_unmap_single(NULL, dma_addr,
>> + trans, DMA_TO_DEVICE);
>> + if (ret) {
>> + dev_warn(nor->dev, "DMA write timeout\n");
>> + return ret;
>> + }
>> + }
>> +
>> + return len;
>> +no_dma:
>> + ret = rockchip_sfc_pio_transfer(nor, to, len,
>> + (u_char *)write_buf, SFC_CMD_DIR_WR);
>> + if (ret) {
>> + dev_warn(nor->dev, "PIO write timeout\n");
>> + return ret;
>> + }
>> + return len;
>> +}
>> +
>> +/**
>> + * Get spi flash device information and register it as a mtd device.
>> + */
>> +static int rockchip_sfc_register(struct device_node *np,
>> + struct rockchip_sfc *sfc)
>> +{
>> + struct device *dev = sfc->dev;
>> + struct spi_nor *nor;
>> + struct rockchip_sfc_priv *priv;
>> + struct mtd_info *mtd;
>> + int ret;
>> +
>> + nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
>> + if (!nor)
>> + return -ENOMEM;
>
> You can embed struct spi_nor in struct rockchip_sfc_priv and drop this
> allocation . Also it'd be a good idea to rename rockchip_sfc_priv to
> something like rockchip_sfc_chip_priv to make it explicit this is a
> per-chip private data -- which you can even pre-allocate in rockchi_sfc
> structure as a static array of (four) such structures (see cadence qspi
> driver for how this is done there).
>
sure, will improve it.
>> + nor->dev = dev;
>> + spi_nor_set_flash_node(nor, np);
>> +
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + ret = of_property_read_u32(np, "reg", &priv->cs);
>> + if (ret) {
>> + dev_err(dev, "No reg property for %s\n",
>> + np->full_name);
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(np, "spi-max-frequency",
>> + &priv->clk_rate);
>> + if (ret) {
>> + dev_err(dev, "No spi-max-frequency property for %s\n",
>> + np->full_name);
>> + return ret;
>> + }
>> +
>> + priv->sfc = sfc;
>> + nor->priv = priv;
>> +
>> + nor->prepare = rockchip_sfc_prep;
>> + nor->unprepare = rockchip_sfc_unprep;
>> + nor->read_reg = rockchip_sfc_read_reg;
>> + nor->write_reg = rockchip_sfc_write_reg;
>> + nor->read = rockchip_sfc_read;
>> + nor->write = rockchip_sfc_write;
>> + nor->erase = NULL;
>> + ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
>> + if (ret)
>> + return ret;
>> +
>> + mtd = &nor->mtd;
>> + mtd->name = np->name;
>> + ret = mtd_device_register(mtd, NULL, 0);
>> + if (ret)
>> + return ret;
>> +
>> + sfc->nor[sfc->num_chip] = nor;
>> + sfc->num_chip++;
>> + return 0;
>> +}
>> +
>> +static void rockchip_sfc_unregister_all(struct rockchip_sfc *sfc)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < sfc->num_chip; i++)
>> + mtd_device_unregister(&sfc->nor[i]->mtd);
>> +}
>> +
>> +static int rockchip_sfc_register_all(struct rockchip_sfc *sfc)
>> +{
>> + struct device *dev = sfc->dev;
>> + struct device_node *np;
>> + int ret;
>> +
>> + for_each_available_child_of_node(dev->of_node, np) {
>> + ret = rockchip_sfc_register(np, sfc);
>> + if (ret)
>> + goto fail;
>> +
>> + if (sfc->num_chip == SFC_MAX_CHIP_NUM) {
>> + dev_warn(dev, "Exceeds the max cs limitation\n");
>> + break;
>> + }
>> + }
>> +
>> + return 0;
>> +
>> +fail:
>> + dev_err(dev, "Failed to register all chip\n");
>> + rockchip_sfc_unregister_all(sfc);
>
> See cadence qspi where we only unregister the registered flashes.
> Implement it the same way here.
>
yup, but I'm afraid that rockchip_sfc_unregister_all confused you
as it actually unregisters the registered ones, not for all.
static void rockchip_sfc_unregister_all(struct rockchip_sfc *sfc)
{
int i;
for (i = 0; i < sfc->num_chip; i++)
mtd_device_unregister(&sfc->nor[i]->mtd);
}
sfc->num_chip stands for how many flashes registered successfully.
>> + return ret;
>> +}
>> +
>> +static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
>> +{
>> + struct rockchip_sfc *sfc = dev_id;
>> + u32 reg;
>> +
>> + reg = readl_relaxed(sfc->regbase + SFC_RISR);
>> + dev_dbg(sfc->dev, "Get irq: 0x%x\n", reg);
>> +
>> + /* Clear interrupt */
>> + writel_relaxed(reg, sfc->regbase + SFC_ICLR);
>> +
>> + if (reg & SFC_IRQ_TRAN_FINISH)
>> + complete(&sfc->cp);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int rockchip_sfc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct resource *res;
>> + struct rockchip_sfc *sfc;
>> + int ret;
>> +
>> + sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL);
>> + if (!sfc)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, sfc);
>> + sfc->dev = dev;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + sfc->regbase = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(sfc->regbase))
>> + return PTR_ERR(sfc->regbase);
>> +
>> + sfc->clk = devm_clk_get(&pdev->dev, "sfc");
>> + if (IS_ERR(sfc->clk)) {
>> + dev_err(&pdev->dev, "Failed to get sfc interface clk\n");
>> + return PTR_ERR(sfc->clk);
>> + }
>> +
>> + sfc->hclk = devm_clk_get(&pdev->dev, "hsfc");
>> + if (IS_ERR(sfc->hclk)) {
>> + dev_err(&pdev->dev, "Failed to get sfc ahp clk\n");
>> + return PTR_ERR(sfc->hclk);
>> + }
>> +
>> + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
>> + if (ret) {
>> + dev_warn(dev, "Unable to set dma mask\n");
>> + return ret;
>> + }
>> +
>> + sfc->buffer = dmam_alloc_coherent(dev, SFC_DMA_MAX_LEN,
>> + &sfc->dma_buffer, GFP_KERNEL);
>> + if (!sfc->buffer)
>> + return -ENOMEM;
>> +
>> + mutex_init(&sfc->lock);
>> +
>> + ret = clk_prepare_enable(sfc->hclk);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Failed to enable hclk\n");
>> + goto err_hclk;
>> + }
>> +
>> + ret = clk_prepare_enable(sfc->clk);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Failed to enable clk\n");
>> + goto err_clk;
>> + }
>> +
>> + if (of_property_read_bool(sfc->dev->of_node, "rockchip,sfc-no-dma"))
>> + sfc->use_dma = false;
>> + else
>> + sfc->use_dma = true;
>
> sfc->use_dma = !of_property_read_bool(sfc->dev->of_node,
> "rockchip,sfc-no-dma");
>
will improve.
>> + if (of_device_is_compatible(sfc->dev->of_node,
>> + "rockchip,rk1108-sfc"))
>> + sfc->negative_edge = true;
>> + else
>> + sfc->negative_edge = false;
>
> See above
>
Ditto.
>> + /* Find the irq */
>> + ret = platform_get_irq(pdev, 0);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to get the irq\n");
>> + goto err_irq;
>> + }
>> +
>> + ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler,
>> + 0, pdev->name, sfc);
>> + if (ret) {
>> + dev_err(dev, "Failed to request irq\n");
>> + goto err_irq;
>> + }
>> +
>> + ret = rockchip_sfc_init(sfc);
>> + if (ret)
>> + goto err_init;
>> +
>> + ret = rockchip_sfc_register_all(sfc);
>> + if (ret)
>> + goto err_init;
>> +
>> + clk_disable_unprepare(sfc->clk);
>> + return 0;
>> +
>> +err_irq:
>> +err_init:
>
> Drop the err_irq: label unless you plan to handle the error (which you
> should).
will remove.
>
>> + clk_disable_unprepare(sfc->clk);
>> +err_clk:
>> + clk_disable_unprepare(sfc->hclk);
>> +err_hclk:
>> + mutex_destroy(&sfc->lock);
>> + return ret;
>> +}
>> +
>> +static int rockchip_sfc_remove(struct platform_device *pdev)
>> +{
>> + struct rockchip_sfc *sfc = platform_get_drvdata(pdev);
>> +
>> + rockchip_sfc_unregister_all(sfc);
>> + mutex_destroy(&sfc->lock);
>> + clk_disable_unprepare(sfc->clk);
>> + clk_disable_unprepare(sfc->hclk);
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id rockchip_sfc_dt_ids[] = {
>> + { .compatible = "rockchip,sfc"},
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids);
>> +
>> +static struct platform_driver rockchip_sfc_driver = {
>> + .driver = {
>> + .name = "rockchip-sfc",
>> + .of_match_table = rockchip_sfc_dt_ids,
>> + },
>> + .probe = rockchip_sfc_probe,
>> + .remove = rockchip_sfc_remove,
>> +};
>> +module_platform_driver(rockchip_sfc_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver");
>
> MODULE_AUTHOR is missing
sure.
>
>
>
--
Best Regards
Shawn Lin
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^ permalink raw reply
* Re: [PATCH v3 12/17] ASoC: simple-card-utils: add asoc_simple_card_try_to_probe_graph_card()
From: Kuninori Morimoto @ 2016-11-16 2:07 UTC (permalink / raw)
To: Rob Herring, Mark Brown, Linux-ALSA, Liam Girdwood, Simon,
Laurent, Guennadi, Grant Likely, Frank Rowand, Linux-DT,
Linux-Kernel
In-Reply-To: <201611111036.Ye7DcBzl%fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Hi
> [auto build test ERROR on asoc/for-next]
> [also build test ERROR on v4.9-rc4 next-20161110]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Kuninori-Morimoto/ASoC-add-OF-graph-base-simple-card/20161111-093231
> base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
> config: x86_64-randconfig-x010-201645 (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=x86_64
>
> All error/warnings (new ones prefixed by >>):
>
> sound/soc/generic/simple-card-utils.c: In function 'asoc_simple_card_try_to_probe_graph_card':
> >> sound/soc/generic/simple-card-utils.c:297:9: error: implicit declaration of function 'of_graph_get_top_port' [-Werror=implicit-function-declaration]
> node = of_graph_get_top_port(dev);
> ^~~~~~~~~~~~~~~~~~~~~
> >> sound/soc/generic/simple-card-utils.c:297:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
> node = of_graph_get_top_port(dev);
> ^
> cc1: some warnings being treated as errors
This patch didn't care about non-OF case.
I will post v4 patch soon
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^ permalink raw reply
* [PATCH v4 00/12] ASoC: add OF graph base simple-card
From: Kuninori Morimoto @ 2016-11-16 2:16 UTC (permalink / raw)
To: Rob Herring, Mark Brown
Cc: Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi, Grant Likely,
Frank Rowand, Linux-DT, Linux-Kernel
Hi Rob, Mark
These are v4 of OF graph base simple-card patch-set.
v3 patch had ALSA SoC side prepare patches as [1/xx] - [5/xx],
but these are already accepted by Mark, thus, this v4 doesn't
include these.
Mainly, v4 solved non-OF case compile error which was reported
by kbuild.
1) - 5) : OF graph new feature
6) - 12) : OF graph base simple-card (depends on above 2 patch-set)
Kuninori Morimoto (12):
1) of_graph: add of_graph_get_remote_endpoint()
2) of_graph: add of_graph_get_port_parent()
3) of_graph: add of_graph_get_top_port()
4) of_graph: add for_each_of_port() / for_each_of_endpoint_in_port()
5) of_graph: add of_graph_get_port/endpoint_count()
6) ASoC: simple-card-utils: add asoc_simple_card_parse_graph_dai()
7) ASoC: simple-card-utils: add asoc_simple_card_try_to_probe_graph_card()
8) ASoC: simple-card-utils: adjust for graph on asoc_simple_card_parse_card_name
9) ASoC: add simple-graph-card document
10) ASoC: add simple-graph-card support
11) ASoC: add simple-graph-scu-card document
12) ASoC: add simple-graph-scu-card support
.../bindings/sound/simple-graph-card.txt | 65 +++
.../bindings/sound/simple-graph-scu-card.txt | 65 +++
drivers/of/base.c | 160 ++++++-
include/linux/of_graph.h | 59 +++
include/sound/simple_card_utils.h | 19 +
sound/soc/generic/Kconfig | 15 +
sound/soc/generic/Makefile | 4 +
sound/soc/generic/simple-card-utils.c | 98 ++++-
sound/soc/generic/simple-card.c | 2 +-
sound/soc/generic/simple-graph-card.c | 462 +++++++++++++++++++++
sound/soc/generic/simple-graph-scu-card.c | 417 +++++++++++++++++++
sound/soc/generic/simple-scu-card.c | 2 +-
12 files changed, 1355 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/simple-graph-card.txt
create mode 100644 Documentation/devicetree/bindings/sound/simple-graph-scu-card.txt
create mode 100644 sound/soc/generic/simple-graph-card.c
create mode 100644 sound/soc/generic/simple-graph-scu-card.c
--
1.9.1
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* [PATCH v4 01/12] of_graph: add of_graph_get_remote_endpoint()
From: Kuninori Morimoto @ 2016-11-16 2:18 UTC (permalink / raw)
To: Rob Herring, Mark Brown
Cc: Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi, Grant Likely,
Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <87polww4o2.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
It should use same method to get same result.
To getting remote-endpoint node,
let's use of_graph_get_remote_endpoint()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v3 -> v4
- no change
drivers/of/base.c | 18 ++++++++++++++++--
include/linux/of_graph.h | 8 ++++++++
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index d687e6d..810acf4 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2425,6 +2425,20 @@ struct device_node *of_graph_get_endpoint_by_regs(
EXPORT_SYMBOL(of_graph_get_endpoint_by_regs);
/**
+ * of_graph_get_remote_endpoint() - get remote endpoint node
+ * @node: pointer to a local endpoint device_node
+ *
+ * Return: Remote endpoint node associated with remote endpoint node linked
+ * to @node. Use of_node_put() on it when done.
+ */
+struct device_node *of_graph_get_remote_endpoint(const struct device_node *node)
+{
+ /* Get remote endpoint node. */
+ return of_parse_phandle(node, "remote-endpoint", 0);
+}
+EXPORT_SYMBOL(of_graph_get_remote_endpoint);
+
+/**
* of_graph_get_remote_port_parent() - get remote port's parent node
* @node: pointer to a local endpoint device_node
*
@@ -2438,7 +2452,7 @@ struct device_node *of_graph_get_remote_port_parent(
unsigned int depth;
/* Get remote endpoint node. */
- np = of_parse_phandle(node, "remote-endpoint", 0);
+ np = of_graph_get_remote_endpoint(node);
/* Walk 3 levels up only if there is 'ports' node. */
for (depth = 3; depth && np; depth--) {
@@ -2462,7 +2476,7 @@ struct device_node *of_graph_get_remote_port(const struct device_node *node)
struct device_node *np;
/* Get remote endpoint node. */
- np = of_parse_phandle(node, "remote-endpoint", 0);
+ np = of_graph_get_remote_endpoint(node);
if (!np)
return NULL;
return of_get_next_parent(np);
diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
index bb3a5a2..d9d6d9c 100644
--- a/include/linux/of_graph.h
+++ b/include/linux/of_graph.h
@@ -48,6 +48,8 @@ struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
struct device_node *previous);
struct device_node *of_graph_get_endpoint_by_regs(
const struct device_node *parent, int port_reg, int reg);
+struct device_node *of_graph_get_remote_endpoint(
+ const struct device_node *node);
struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node);
struct device_node *of_graph_get_remote_port(const struct device_node *node);
@@ -78,6 +80,12 @@ static inline struct device_node *of_graph_get_endpoint_by_regs(
return NULL;
}
+static inline struct device_node *of_graph_get_remote_endpoint(
+ const struct device_node *node)
+{
+ return NULL;
+}
+
static inline struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node)
{
--
1.9.1
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* [PATCH v4 02/12] of_graph: add of_graph_get_port_parent()
From: Kuninori Morimoto @ 2016-11-16 2:18 UTC (permalink / raw)
To: Rob Herring, Mark Brown
Cc: Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi, Grant Likely,
Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <87polww4o2.wl%kuninori.morimoto.gx@renesas.com>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Linux kernel already has of_graph_get_remote_port_parent(),
but, sometimes we want to get own port parent.
This patch adds of_graph_get_port_parent()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
v3 -> v4
- no change
drivers/of/base.c | 30 ++++++++++++++++++++++--------
include/linux/of_graph.h | 7 +++++++
2 files changed, 29 insertions(+), 8 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 810acf4..fed0b023 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2439,6 +2439,27 @@ struct device_node *of_graph_get_remote_endpoint(const struct device_node *node)
EXPORT_SYMBOL(of_graph_get_remote_endpoint);
/**
+ * of_graph_get_port_parent() - get port's parent node
+ * @node: pointer to a local endpoint device_node
+ *
+ * Return: device node associated with endpoint node linked
+ * to @node. Use of_node_put() on it when done.
+ */
+struct device_node *of_graph_get_port_parent(struct device_node *node)
+{
+ unsigned int depth;
+
+ /* Walk 3 levels up only if there is 'ports' node. */
+ for (depth = 3; depth && node; depth--) {
+ node = of_get_next_parent(node);
+ if (depth == 2 && of_node_cmp(node->name, "ports"))
+ break;
+ }
+ return node;
+}
+EXPORT_SYMBOL(of_graph_get_port_parent);
+
+/**
* of_graph_get_remote_port_parent() - get remote port's parent node
* @node: pointer to a local endpoint device_node
*
@@ -2449,18 +2470,11 @@ struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node)
{
struct device_node *np;
- unsigned int depth;
/* Get remote endpoint node. */
np = of_graph_get_remote_endpoint(node);
- /* Walk 3 levels up only if there is 'ports' node. */
- for (depth = 3; depth && np; depth--) {
- np = of_get_next_parent(np);
- if (depth == 2 && of_node_cmp(np->name, "ports"))
- break;
- }
- return np;
+ return of_graph_get_port_parent(np);
}
EXPORT_SYMBOL(of_graph_get_remote_port_parent);
diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
index d9d6d9c..80ced0c 100644
--- a/include/linux/of_graph.h
+++ b/include/linux/of_graph.h
@@ -50,6 +50,7 @@ struct device_node *of_graph_get_endpoint_by_regs(
const struct device_node *parent, int port_reg, int reg);
struct device_node *of_graph_get_remote_endpoint(
const struct device_node *node);
+struct device_node *of_graph_get_port_parent(struct device_node *node);
struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node);
struct device_node *of_graph_get_remote_port(const struct device_node *node);
@@ -86,6 +87,12 @@ static inline struct device_node *of_graph_get_remote_endpoint(
return NULL;
}
+static inline struct device_node *of_graph_get_port_parent(
+ struct device_node *node)
+{
+ return NULL;
+}
+
static inline struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node)
{
--
1.9.1
^ permalink raw reply related
* [PATCH v4 03/12] of_graph: add of_graph_get_top_port()
From: Kuninori Morimoto @ 2016-11-16 2:19 UTC (permalink / raw)
To: Rob Herring, Mark Brown
Cc: Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi, Grant Likely,
Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <87polww4o2.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
driver want to get top level of port[s] node. This patch adds
of_graph_get_top_port() for this purpose
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v3 -> v4
- care non-OF case
drivers/of/base.c | 24 ++++++++++++++++++++++++
include/linux/of_graph.h | 7 +++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index fed0b023..e49eb28 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2330,6 +2330,30 @@ struct device_node *of_graph_get_port_by_id(struct device_node *parent, u32 id)
EXPORT_SYMBOL(of_graph_get_port_by_id);
/**
+ * of_graph_get_top_port() - get the top port node
+ * @dev: pointer to the device
+ *
+ * Return: A 'port' node pointer with refcount incremented. The caller
+ * has to use of_node_put() on it when done.
+ */
+struct device_node *of_graph_get_top_port(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct device_node *node;
+
+ node = of_get_child_by_name(np, "ports");
+ if (node)
+ return node;
+
+ node = of_get_child_by_name(np, "port");
+ if (node)
+ return node;
+
+ return NULL;
+}
+EXPORT_SYMBOL(of_graph_get_top_port);
+
+/**
* of_graph_get_next_endpoint() - get next endpoint node
* @parent: pointer to the parent device node
* @prev: previous endpoint node, or NULL to get first
diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
index 80ced0c..23b1c6e 100644
--- a/include/linux/of_graph.h
+++ b/include/linux/of_graph.h
@@ -14,6 +14,7 @@
#ifndef __LINUX_OF_GRAPH_H
#define __LINUX_OF_GRAPH_H
+#include <linux/device.h>
#include <linux/types.h>
#include <linux/errno.h>
@@ -44,6 +45,7 @@ struct of_endpoint {
int of_graph_parse_endpoint(const struct device_node *node,
struct of_endpoint *endpoint);
struct device_node *of_graph_get_port_by_id(struct device_node *node, u32 id);
+struct device_node *of_graph_get_top_port(struct device *dev);
struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
struct device_node *previous);
struct device_node *of_graph_get_endpoint_by_regs(
@@ -68,6 +70,11 @@ static inline struct device_node *of_graph_get_port_by_id(
return NULL;
}
+static inline struct device_node *of_graph_get_top_port(struct device *dev)
+{
+ return NULL;
+}
+
static inline struct device_node *of_graph_get_next_endpoint(
const struct device_node *parent,
struct device_node *previous)
--
1.9.1
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* [PATCH v4 04/12] of_graph: add for_each_of_port() / for_each_of_endpoint_in_port()
From: Kuninori Morimoto @ 2016-11-16 2:19 UTC (permalink / raw)
To: Rob Herring, Mark Brown
Cc: Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi, Grant Likely,
Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <87polww4o2.wl%kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
OF graph is used mainly from V4L2, but ALSA needs to use it. It already
has for_each_endpoint_of_node() which is for-loop for each endpoint.
But, ALSA needs for-loop for each port[s], and for-loop for each
endpoint of inside port[s]. This patch adds for_each_of_port()
and for_each_of_endpoint_in_port() for this purpose.
And it also adds for_each_of_endpoint() which is similar to
for_each_endpoint_of_node(). The difference is it can catch port
handle during for-loop.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
v3 -> v4
- no change
drivers/of/base.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/of_graph.h | 29 ++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index e49eb28..b11f533 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2354,6 +2354,70 @@ struct device_node *of_graph_get_top_port(struct device *dev)
EXPORT_SYMBOL(of_graph_get_top_port);
/**
+ * of_graph_get_next_port() - get next port node
+ * @parent: pointer to the parent device node
+ * @prev: previous endpoint node, or NULL to get first
+ *
+ * Return: An 'endpoint' node pointer with refcount incremented. Refcount
+ * of the passed @prev node is decremented.
+ */
+struct device_node *of_graph_get_next_port(const struct device_node *parent,
+ struct device_node *prev)
+{
+ struct device_node *port;
+ struct device_node *node;
+
+ if (!parent)
+ return NULL;
+
+ node = of_get_child_by_name(parent, "ports");
+ if (node)
+ parent = node;
+
+ /*
+ * Start by locating the port node. If no previous endpoint is specified
+ * search for the first port node, otherwise get the previous endpoint
+ * parent port node.
+ */
+ if (!prev) {
+ port = of_get_child_by_name(parent, "port");
+ if (!port)
+ pr_err("%s(): no port node found in %s\n",
+ __func__, parent->full_name);
+ } else {
+ do {
+ port = of_get_next_child(parent, prev);
+ if (!port)
+ break;
+ } while (of_node_cmp(port->name, "port"));
+ }
+
+ of_node_put(node);
+
+ return port;
+}
+EXPORT_SYMBOL(of_graph_get_next_port);
+
+/**
+ * of_graph_get_next_endpoint_in_port() - get next endpoint node in port
+ * @parent: pointer to the parent device node
+ * @prev: previous endpoint node, or NULL to get first
+ *
+ * Return: An 'endpoint' node pointer with refcount incremented. Refcount
+ * of the passed @prev node is decremented.
+ */
+struct device_node *of_graph_get_next_endpoint_in_port(
+ const struct device_node *port,
+ struct device_node *prev)
+{
+ if (!port)
+ return NULL;
+
+ return of_get_next_child(port, prev);
+}
+EXPORT_SYMBOL(of_graph_get_next_endpoint_in_port);
+
+/**
* of_graph_get_next_endpoint() - get next endpoint node
* @parent: pointer to the parent device node
* @prev: previous endpoint node, or NULL to get first
diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
index 23b1c6e..8207631 100644
--- a/include/linux/of_graph.h
+++ b/include/linux/of_graph.h
@@ -30,6 +30,16 @@ struct of_endpoint {
const struct device_node *local_node;
};
+#define for_each_of_port(parent, port) \
+ for (port = of_graph_get_next_port(parent, NULL); port != NULL; \
+ port = of_graph_get_next_port(parent, port))
+#define for_each_of_endpoint_in_port(port, ep) \
+ for (ep = of_graph_get_next_endpoint_in_port(port, NULL); ep != NULL; \
+ ep = of_graph_get_next_endpoint_in_port(port, ep))
+#define for_each_of_endpoint(parent, port, ep) \
+ for_each_of_port(parent, port) \
+ for_each_of_endpoint_in_port(port, ep)
+
/**
* for_each_endpoint_of_node - iterate over every endpoint in a device node
* @parent: parent device node containing ports and endpoints
@@ -46,6 +56,11 @@ int of_graph_parse_endpoint(const struct device_node *node,
struct of_endpoint *endpoint);
struct device_node *of_graph_get_port_by_id(struct device_node *node, u32 id);
struct device_node *of_graph_get_top_port(struct device *dev);
+struct device_node *of_graph_get_next_port(const struct device_node *parent,
+ struct device_node *prev);
+struct device_node *of_graph_get_next_endpoint_in_port(
+ const struct device_node *port,
+ struct device_node *prev);
struct device_node *of_graph_get_next_endpoint(const struct device_node *parent,
struct device_node *previous);
struct device_node *of_graph_get_endpoint_by_regs(
@@ -75,6 +90,20 @@ static inline struct device_node *of_graph_get_top_port(struct device *dev)
return NULL;
}
+static inline struct device_node *of_graph_get_next_port(
+ const struct device_node *parent,
+ struct device_node *prev)
+{
+ return NULL;
+}
+
+static inline struct device_node *of_graph_get_next_endpoint_in_port(
+ const struct device_node *port,
+ struct device_node *prev)
+{
+ return NULL;
+}
+
static inline struct device_node *of_graph_get_next_endpoint(
const struct device_node *parent,
struct device_node *previous)
--
1.9.1
--
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