* Re: [PATCH v6 7/8] ARM: dts: stm32: add Timers driver for stm32f429 MCU
From: Rob Herring @ 2016-12-12 18:59 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1481292919-26587-8-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On Fri, Dec 09, 2016 at 03:15:18PM +0100, Benjamin Gaignard wrote:
> Add Timers and it sub-nodes into DT for stm32f429 family.
>
> version 6:
> - split patch in two: one for SoC family and one for stm32f469
> discovery board.
>
> version 5:
> - rename gptimer node to timers
> - re-order timers node par addresses
>
> version 4:
> - remove unwanted indexing in pwm@ and timer@ node name
> - use "reg" instead of additional parameters to set timer
> configuration
>
> version 3:
> - use "st,stm32-timer-trigger" in DT
>
> version 2:
> - use parameters to describe hardware capabilities
> - do not use references for pwm and iio timer subnodes
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 275 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index bca491d..d0fb9cc 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -355,6 +355,21 @@
> slew-rate = <2>;
> };
> };
> +
> + pwm1_pins: pwm@1 {
No reg prop, so should not have a unit-address. Given the names in the
define below, seems like "timer1" would be appropriate.
> + pins {
> + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
> + <STM32F429_PB13_FUNC_TIM1_CH1N>,
> + <STM32F429_PB12_FUNC_TIM1_BKIN>;
> + };
> + };
> +
> + pwm3_pins: pwm@3 {
> + pins {
> + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
> + <STM32F429_PB5_FUNC_TIM3_CH2>;
> + };
> + };
> };
>
> rcc: rcc@40023810 {
> @@ -426,6 +441,266 @@
> interrupts = <80>;
> clocks = <&rcc 0 38>;
> };
> +
> + timers2: timers@40000000 {
timer@...
It may be more than just a timer, there's not a better generic name.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000000 0x400>;
> + clocks = <&rcc 0 128>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> +
> + timers3: timers@40000400 {
ditto
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000400 0x400>;
> + clocks = <&rcc 0 129>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <2>;
> + status = "disabled";
> + };
> + };
> +
> + timers4: timers@40000800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000800 0x400>;
> + clocks = <&rcc 0 130>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <3>;
> + status = "disabled";
> + };
> + };
> +
> + timers5: timers@40000C00 {
timer@...
And use lowercase hex.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000C00 0x400>;
ditto
> + clocks = <&rcc 0 131>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <4>;
> + status = "disabled";
> + };
> + };
> +
> + timers6: timers@40001000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001000 0x400>;
> + clocks = <&rcc 0 132>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <5>;
> + status = "disabled";
> + };
> + };
> +
> + timers7: timers@40001400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001400 0x400>;
> + clocks = <&rcc 0 133>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <6>;
> + status = "disabled";
> + };
> + };
> +
> + timers12: timers@40001800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001800 0x400>;
> + clocks = <&rcc 0 134>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <9>;
> + status = "disabled";
> + };
> + };
> +
> + timers13: timers@40001C00 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001C00 0x400>;
> + clocks = <&rcc 0 135>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers14: timers@40002000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40002000 0x400>;
> + clocks = <&rcc 0 136>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers1: timers@40010000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <0>;
> + status = "disabled";
> + };
> + };
> +
> + timers8: timers@40010400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010400 0x400>;
> + clocks = <&rcc 0 161>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <7>;
> + status = "disabled";
> + };
> + };
> +
> + timers9: timers@40014000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014000 0x400>;
> + clocks = <&rcc 0 176>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <8>;
> + status = "disabled";
> + };
> + };
> +
> + timers10: timers@40014400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014400 0x400>;
> + clocks = <&rcc 0 177>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers11: timers@40014800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014800 0x400>;
> + clocks = <&rcc 0 178>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> };
> };
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v6 3/8] PWM: add pwm-stm32 DT bindings
From: Rob Herring @ 2016-12-12 19:02 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones, mark.rutland, alexandre.torgue, devicetree,
linux-kernel, thierry.reding, linux-pwm, jic23, knaack.h, lars,
pmeerw, linux-iio, linux-arm-kernel, fabrice.gasnier,
gerald.baeza, arnaud.pouliquen, linus.walleij, linaro-kernel,
Benjamin Gaignard
In-Reply-To: <1481292919-26587-4-git-send-email-benjamin.gaignard@st.com>
On Fri, Dec 09, 2016 at 03:15:14PM +0100, Benjamin Gaignard wrote:
> Define bindings for pwm-stm32
>
> version 6:
> - change st,breakinput parameter format to make it usuable on stm32f7 too.
>
> version 2:
> - use parameters instead of compatible of handle the hardware configuration
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> new file mode 100644
> index 0000000..866f222
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> @@ -0,0 +1,33 @@
> +STMicroelectronics STM32 Timers PWM bindings
> +
> +Must be a sub-node of an STM32 Timers device tree node.
> +See ../mfd/stm32-timers.txt for details about the parent node.
> +
> +Required parameters:
> +- compatible: Must be "st,stm32-pwm".
> +- pinctrl-names: Set to "default".
> +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
> + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
> +
> +Optional parameters:
> +- st,breakinput: Arrays of three u32 <index level filter> to describe break input configurations.
> + "index" indicates on which break input the configuration should be applied.
> + "level" gives the active level (0=low or 1=high) for this configuration.
> + "filter" gives the filtering value to be applied.
> +
> +Example:
> + timers@40010000 {
timer@...
With that,
Acked-by: Rob Herring <robh@kernel.org>
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + st,breakinput = <0 1 5>;
> + };
> + };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v6 5/8] IIO: add bindings for STM32 timer trigger driver
From: Rob Herring @ 2016-12-12 19:28 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones, mark.rutland, alexandre.torgue, devicetree,
linux-kernel, thierry.reding, linux-pwm, jic23, knaack.h, lars,
pmeerw, linux-iio, linux-arm-kernel, fabrice.gasnier,
gerald.baeza, arnaud.pouliquen, linus.walleij, linaro-kernel,
Benjamin Gaignard
In-Reply-To: <1481292919-26587-6-git-send-email-benjamin.gaignard@st.com>
On Fri, Dec 09, 2016 at 03:15:16PM +0100, Benjamin Gaignard wrote:
> Define bindings for STM32 timer trigger
>
> version 4:
> - remove triggers enumeration from DT
> - add reg parameter
>
> version 3:
> - change file name
> - add cross reference with mfd bindings
>
> version 2:
> - only keep one compatible
> - add DT parameters to set lists of the triggers:
> one list describe the triggers created by the device
> another one give the triggers accepted by the device
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
Other than same comments I made in the other patches for the example,
looks fine.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support
From: Stephen Boyd @ 2016-12-12 19:38 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-clk, mturquette, ssantosh, nm, linux-arm-kernel, devicetree
In-Reply-To: <22dacb0c-a3bc-50ce-e4b9-f74a0c706f20@ti.com>
On 12/09, Tero Kristo wrote:
> On 08/12/16 23:10, Stephen Boyd wrote:
> >On 12/08, Tero Kristo wrote:
> >>On 08/12/16 02:13, Stephen Boyd wrote:
> >>>On 10/21, Tero Kristo wrote:
> >>>>diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> >>>>new file mode 100644
> >>>>index 0000000..f6af5bd
> >>>>--- /dev/null
> >>>>+++ b/drivers/clk/keystone/sci-clk.c
> >>
> >>>
> >>>>+
> >>>>+ handle = devm_ti_sci_get_handle(dev);
> >>>>+ if (IS_ERR(handle))
> >>>>+ return PTR_ERR(handle);
> >>>>+
> >>>>+ provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> >>>>+ if (!provider)
> >>>>+ return -ENOMEM;
> >>>>+
> >>>>+ provider->clocks = data;
> >>>>+
> >>>>+ provider->sci = handle;
> >>>>+ provider->ops = &handle->ops.clk_ops;
> >>>>+ provider->dev = dev;
> >>>>+
> >>>>+ ti_sci_init_clocks(provider);
> >>>
> >>>And if this fails?
> >>
> >>Yea this is kind of controversial. ti_sci_init_clocks() can fail if
> >>any of the clocks registered will fail. I decided to have it this
> >>way so that at least some clocks might work in failure cause, and
> >>you might have a booting device instead of total lock-up.
> >>
> >>Obviously it could be done so that if any clock fails, we would
> >>de-register all clocks at that point, but personally I think this is
> >>a worse option.
> >>
> >>ti_sci_init_clocks could probably be modified to continue
> >>registering clocks when a single clock fails though. Currently it
> >>aborts at first failure.
> >>
> >
> >That sounds like a better approach if we don't care about
> >failures to register a clock. Returning a value from a function
> >and not using it isn't really a great design.
> >
> >I worry that if we start returning errors from clk_hw_register()
> >that something will go wrong though, so really I don't know why
> >we want to ignore errors at all. Just for debugging a boot hang?
> >Can't we use early console to at least see that this driver is
> >failing to probe and debug that way?
>
> Early console can be used to debug that, but it is kind of annoying
> to recompile most of the kernel when you suddenly need to use it.
I thought SERIAL_EARLYCON was selected by drivers that support
it? So there shouldn't be any rebuilding required.
>
> How about modifying the ti_sci_init_clocks func to print an error
> for each failed clock?
Ok that's fine too. I'd prefer the function had a return type of
void if we're not planning on using the return value, that's all.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 16/16] drivers/fsi: Add GPIO based FSI master
From: Christopher Bostic @ 2016-12-12 19:49 UTC (permalink / raw)
To: Jeremy Kerr
Cc: Rob Herring, Mark Rutland, linux-I+IVW8TIWO2tmTQ+vhA3Yw, Greg KH,
sre-DgEjT+Ai2ygdnm+yROfE0A, Michael Turquette,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
Open List OF Flattened dev tree bindings,
Moderated list: ARM PORT, Chris Bostic, Joel Stanley,
Linux open list, Andrew Jeffery, Alistair Popple,
Benjamin Herrenschmidt
In-Reply-To: <6a39f4d9-0f20-a146-3122-86d3f75c58fa-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>
On Thu, Dec 8, 2016 at 10:12 PM, Jeremy Kerr <jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org> wrote:
> Hi Chris,
>
>> +static ssize_t store_scan(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t count)
>> +{
>> + struct fsi_master_gpio *master = dev_get_drvdata(dev);
>> +
>> + fsi_master_gpio_init(master);
>> +
>> + /* clear out any old scan data if present */
>> + fsi_master_unregister(&master->master);
>> + fsi_master_register(&master->master);
>> +
>> + return count;
>> +}
>> +
>> +static DEVICE_ATTR(scan, 0200, NULL, store_scan);
>
> I think it would make more sense to have the scan attribute populated by
> the fsi core; we want this on all masters, not just GPIO.
>
Hi Jeremy,
Sure, will move that to the core.
> Currently, the only GPIO-master-specific functionality here is the
> fsi_master_gpio_init() - but isn't this something that we can do at
> probe time instead?
>
Yes that can be done at probe time. Will change.
>> +static int fsi_master_gpio_probe(struct platform_device *pdev)
>> +{
>> + struct fsi_master_gpio *master;
>> + struct gpio_desc *gpio;
>> +
>> + master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
>> + if (!master)
>> + return -ENOMEM;
>
> We should be populating master->dev.parent, see
>
> https://github.com/jk-ozlabs/linux/commit/5225d6c47
>
>
Will make the change.
>> + /* Optional pins */
>> +
>> + gpio = devm_gpiod_get(&pdev->dev, "trans", 0);
>> + if (IS_ERR(gpio))
>> + dev_dbg(&pdev->dev, "probe: failed to get trans pin\n");
>> + else
>> + master->gpio_trans = gpio;
>
> I found devm_gpiod_get_optional(), which might make this a little
> neater.
Will make this change.
Thanks,
Chris
>
> Cheers,
>
>
> Jeremy
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^ permalink raw reply
* Re: [PATCH] Documentation: ti-syscon-reset: fix header path
From: Yegor Yefremov @ 2016-12-12 19:52 UTC (permalink / raw)
To: Rob Herring
Cc: kernel list, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8
In-Reply-To: <20161212184021.hewybkfaygrle63a@rob-hp-laptop>
On Mon, Dec 12, 2016 at 7:40 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Fri, Dec 09, 2016 at 11:11:27AM +0100, yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org wrote:
>> From: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> 'include' was missing from path.
>>
>> Signed-off-by: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> index 164c7f3..5b20e20 100644
>> --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> @@ -44,7 +44,7 @@ Required properties:
>> reset status register
>> Cell #7 : Flags used to control reset behavior,
>> availible flags defined in the DT include
>> - file <dt-bindings/reset/ti-syscon.h>
>> + file <include/dt-bindings/reset/ti-syscon.h>
>
> There's pretty much equal mixture of include or not. Not really much
> point in fixing 1 instance if there's no clear correct way. Given it is
> written with <...>, that matches how you write the include statement.
OK I see the point of omitting include now. I was looking at this from
VIM point of view. I cannot automatically jump to the file via 'gf'.
Yegor
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^ permalink raw reply
* Re: [PATCH v2 0/7] ath9k: EEPROM swapping improvements
From: Martin Blumenstingl @ 2016-12-12 20:05 UTC (permalink / raw)
To: Valo, Kalle
Cc: ath9k-devel,
linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
ath9k-devel-xDcbHBWguxHbcTqmT+pZeQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
arnd-r2nGTMty4D4@public.gmane.org,
chunkeey-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org,
nbd-Vt+b4OUoWG0@public.gmane.org
In-Reply-To: <871sxza9al.fsf-HodKDYzPHsUD5k0oWYwrnHL1okKdlPRT@public.gmane.org>
Hello Kalle,
On Fri, Nov 25, 2016 at 4:06 PM, Valo, Kalle <kvalo-A+ZNKFmMK5xy9aJCnZT0Uw@public.gmane.org> wrote:
> Kalle Valo <kvalo-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> writes:
>
>> Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
>>
>>> There are two types of swapping the EEPROM data in the ath9k driver.
>>> Before this series one type of swapping could not be used without the
>>> other.
>>>
>>> The first type of swapping looks at the "magic bytes" at the start of
>>> the EEPROM data and performs swab16 on the EEPROM contents if needed.
>>> The second type of swapping is EEPROM format specific and swaps
>>> specific fields within the EEPROM itself (swab16, swab32 - depends on
>>> the EEPROM format).
>>>
>>> With this series the second part now looks at the EEPMISC register
>>> inside the EEPROM, which uses a bit to indicate if the EEPROM data
>>> is Big Endian (this is also done by the FreeBSD kernel).
>>> This has a nice advantage: currently there are some out-of-tree hacks
>>> (in OpenWrt and LEDE) where the EEPROM has a Big Endian header on a
>>> Big Endian system (= no swab16 is performed) but the EEPROM itself
>>> indicates that it's data is Little Endian. Until now the out-of-tree
>>> code simply did a swab16 before passing the data to ath9k, so ath9k
>>> first did the swab16 - this also enabled the format specific swapping.
>>> These out-of-tree hacks are still working with the new logic, but it
>>> is recommended to remove them. This implementation is based on a
>>> discussion with Arnd Bergmann who raised concerns about the
>>> robustness and portability of the swapping logic in the original OF
>>> support patch review, see [0].
>>>
>>> After a second round of patches (= v1 of this series) neither Arnd
>>> Bergmann nor I were really happy with the complexity of the EEPROM
>>> swapping logic. Based on a discussion (see [1] and [2]) we decided
>>> that ath9k should use a defined format (specifying the endianness
>>> of the data - I went with __le16 and __le32) when accessing the
>>> EEPROM fields. A benefit of this is that we enable the EEPMISC based
>>> swapping logic by default, just like the FreeBSD driver, see [3]. On
>>> the devices which I have tested (see below) ath9k now works without
>>> having to specify the "endian_check" field in ath9k_platform_data (or
>>> a similar logic which could provide this via devicetree) as ath9k now
>>> detects the endianness automatically. Only EEPROMs which are mangled
>>> by some out-of-tree code still need the endian_check flag (or one can
>>> simply remove that mangling from the out-of-tree code).
>>>
>>> Testing:
>>> - tested by myself on AR9287 with Big Endian EEPROM
>>> - tested by myself on AR9227 with Little Endian EEPROM
>>> - tested by myself on AR9381 (using the ar9003_eeprom implementation,
>>> which did not suffer from this whole problem)
>>> - how do we proceed with testing? maybe we could keep this in a
>>> feature-branch and add these patches to LEDE once we have an ACK to
>>> get more people to test this
>>>
>>> This series depends on my other series (v7):
>>> "add devicetree support to ath9k" - see [4]
>>
>> I think this looks pretty good. If there's a bug somewhere it should be
>> quite easy to fix so I'm not that worried and would be willing to take
>> these as soon as I have applied the dependency series. IIRC your
>> devicetree patches will have at least one more review round so that will
>> take some time still. In the meantime it would be great if LEDE folks
>> could take a look at these and comment (or test).
>
> So are everyone happy with this? I haven't seen any comments. If I don't
> here anything I'm planning to take these, most likely for 4.11.
the patches have been in LEDE for almost two weeks now and I did not
see any reports of ath9k breakage (footnote below).
It seems that there are a few devices out there where the whole EEPROM
is swab16'ed which switches the position of the 1-byte fields
opCapFlags and eepMisc.
those still work fine with the new code, however I had a second patch
in LEDE [0] which results in ath9k_platform_data.endian_check NOT
being set anymore.
that endian_check flag was used before to swab16 the whole EEPROM, to
correct the position of the 1-byte fields again.
Currently we are fixing this in the firmware hotplug script: [1]
This is definitely not a blocker for this series though (if we want to
have a devicetree replacement for "ath9k_platform_data.endian_check"
then I'd work on that within a separate series, but I somewhat
consider these EEPROMs as "broken" so fixing them in
userspace/firmware hotplug script is fine for me)
Regards,
Martin
[0] https://git.lede-project.org/?p=source.git;a=commitdiff;h=a20616863d32d91163043b6657a63c836bd9c5ba
[1] https://git.lede-project.org/?p=source.git;a=commitdiff;h=afa37092663d00aa0abf8c61943d9a1b5558b144
^ permalink raw reply
* [PATCH v2 1/2] ASoC: Add support for CS43130 codec
From: Li Xu @ 2016-12-12 20:17 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
Add support for Cirrus Logic CS43130 codec.
Support I2C control and I2S audio playback.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
sound/soc/codecs/Kconfig | 6 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/cs43130.c | 1164 ++++++++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/cs43130.h | 268 ++++++++++
4 files changed, 1440 insertions(+)
create mode 100644 sound/soc/codecs/cs43130.c
create mode 100644 sound/soc/codecs/cs43130.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 9e1718a..d6ede2b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS4271_I2C if I2C
select SND_SOC_CS4271_SPI if SPI_MASTER
select SND_SOC_CS42XX8_I2C if I2C
+ select SND_SOC_CS43130 if I2C
select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
@@ -473,6 +474,11 @@ config SND_SOC_CS42XX8_I2C
select SND_SOC_CS42XX8
select REGMAP_I2C
+# Cirrus Logic CS43130 HiFi DAC
+config SND_SOC_CS43130
+ tristate "Cirrus Logic CS43130 CODEC"
+ depends on I2C
+
# Cirrus Logic CS4349 HiFi DAC
config SND_SOC_CS4349
tristate "Cirrus Logic CS4349 CODEC"
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 7e1dad7..2f15228 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,6 +52,7 @@ snd-soc-cs4271-i2c-objs := cs4271-i2c.o
snd-soc-cs4271-spi-objs := cs4271-spi.o
snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
+snd-soc-cs43130-objs := cs43130.o
snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
@@ -281,6 +282,7 @@ obj-$(CONFIG_SND_SOC_CS4271_I2C) += snd-soc-cs4271-i2c.o
obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o
obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
+obj-$(CONFIG_SND_SOC_CS43130) += snd-soc-cs43130.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
diff --git a/sound/soc/codecs/cs43130.c b/sound/soc/codecs/cs43130.c
new file mode 100644
index 0000000..79e4d2a
--- /dev/null
+++ b/sound/soc/codecs/cs43130.c
@@ -0,0 +1,1164 @@
+/*
+ * cs43130.c -- CS43130 ALSA Soc Audio driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Authors: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/of_irq.h>
+
+#include "cs43130.h"
+
+
+static const struct reg_default cs43130_reg_defaults[] = {
+ { CS43130_SYS_CLK_CTL_1, 0x06 },
+ { CS43130_SP_SRATE, 0x01 },
+ { CS43130_SP_BITSIZE, 0x05 },
+ { CS43130_PAD_INT_CFG, 0x03 },
+ { CS43130_PWDN_CTL, 0xFE },
+ { CS43130_CRYSTAL_SET, 0x04 },
+ { CS43130_PLL_SET_1, 0x00 },
+ { CS43130_PLL_SET_2, 0x00 },
+ { CS43130_PLL_SET_3, 0x00 },
+ { CS43130_PLL_SET_4, 0x00 },
+ { CS43130_PLL_SET_5, 0x40 },
+ { CS43130_PLL_SET_6, 0x10 },
+ { CS43130_PLL_SET_7, 0x80 },
+ { CS43130_PLL_SET_8, 0x03 },
+ { CS43130_PLL_SET_9, 0x02 },
+ { CS43130_PLL_SET_10, 0x02 },
+ { CS43130_CLKOUT_CTL, 0x00 },
+ { CS43130_ASP_NUM_1, 0x01 },
+ { CS43130_ASP_NUM_2, 0x00 },
+ { CS43130_ASP_DENOM_1, 0x08 },
+ { CS43130_ASP_DENOM_2, 0x00 },
+ { CS43130_ASP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_ASP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_ASP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_ASP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_ASP_CLOCK_CONF, 0x0C },
+ { CS43130_ASP_FRAME_CONF, 0x0A },
+ { CS43130_XSP_NUM_1, 0x01 },
+ { CS43130_XSP_NUM_2, 0x00 },
+ { CS43130_XSP_DENOM_1, 0x02 },
+ { CS43130_XSP_DENOM_2, 0x00 },
+ { CS43130_XSP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_XSP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_XSP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_XSP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_XSP_CLOCK_CONF, 0x0C },
+ { CS43130_XSP_FRAME_CONF, 0x0A },
+ { CS43130_ASP_CH_1_LOC, 0x00 },
+ { CS43130_ASP_CH_2_LOC, 0x00 },
+ { CS43130_ASP_CH_1_SZ_EN, 0x06 },
+ { CS43130_ASP_CH_2_SZ_EN, 0x0E },
+ { CS43130_XSP_CH_1_LOC, 0x00 },
+ { CS43130_XSP_CH_2_LOC, 0x00 },
+ { CS43130_XSP_CH_1_SZ_EN, 0x06 },
+ { CS43130_XSP_CH_2_SZ_EN, 0x0E },
+ { CS43130_DSD_VOL_B, 0x78 },
+ { CS43130_DSD_VOL_A, 0x78 },
+ { CS43130_DSD_PATH_CTL_1, 0xA8 },
+ { CS43130_DSD_INT_CFG, 0x00 },
+ { CS43130_DSD_PATH_CTL_2, 0x00 },
+ { CS43130_DSD_PCM_MIX_CTL, 0x00 },
+ { CS43130_DSD_PATH_CTL_3, 0x40 },
+ { CS43130_HP_OUT_CTL_1, 0x30 },
+ { CS43130_PCM_FILT_OPT, 0x02 },
+ { CS43130_PCM_VOL_B, 0x78 },
+ { CS43130_PCM_VOL_A, 0x78 },
+ { CS43130_PCM_PATH_CTL_1, 0xA8 },
+ { CS43130_PCM_PATH_CTL_2, 0x00 },
+ { CS43130_CLASS_H_CTL, 0x1E },
+ { CS43130_HP_DETECT, 0x04 },
+ { CS43130_HP_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_2, 0x00 },
+ { CS43130_INT_MASK_1, 0xFF },
+ { CS43130_INT_MASK_2, 0xFF },
+ { CS43130_INT_MASK_3, 0xFF },
+ { CS43130_INT_MASK_4, 0xFF },
+ { CS43130_INT_MASK_5, 0xFF },
+};
+
+static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
+ case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
+ case CS43130_DXD1:
+ case CS43130_PWDN_CTL:
+ case CS43130_DXD2:
+ case CS43130_CRYSTAL_SET:
+ case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
+ case CS43130_PLL_SET_6:
+ case CS43130_PLL_SET_7:
+ case CS43130_PLL_SET_8:
+ case CS43130_PLL_SET_9:
+ case CS43130_PLL_SET_10:
+ case CS43130_CLKOUT_CTL:
+ case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
+ case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
+ case CS43130_ASP_CH_1_LOC:
+ case CS43130_ASP_CH_2_LOC:
+ case CS43130_ASP_CH_1_SZ_EN:
+ case CS43130_ASP_CH_2_SZ_EN:
+ case CS43130_XSP_CH_1_LOC:
+ case CS43130_XSP_CH_2_LOC:
+ case CS43130_XSP_CH_1_SZ_EN:
+ case CS43130_XSP_CH_2_SZ_EN:
+ case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
+ case CS43130_HP_OUT_CTL_1:
+ case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
+ case CS43130_CLASS_H_CTL:
+ case CS43130_HP_DETECT:
+ case CS43130_HP_STATUS:
+ case CS43130_HP_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_2:
+ case CS43130_HP_DC_STAT_1:
+ case CS43130_HP_DC_STAT_2:
+ case CS43130_HP_AC_STAT_1:
+ case CS43130_HP_AC_STAT_2:
+ case CS43130_HP_LOAD_STAT:
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_precious_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+struct cs43130_pll_params {
+ u32 pll_in;
+ u8 mclk_int;
+ u8 sclk_prediv;
+ u8 pll_div_int;
+ u32 pll_div_frac;
+ u8 pll_mode;
+ u8 pll_divout;
+ u32 pll_out;
+ u8 pll_cal_ratio;
+};
+
+static const struct cs43130_pll_params pll_ratio_table[] = {
+ { 9600000, 1, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151 },
+ { 9600000, 0, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164 },
+
+ { 11289600, 1, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128 },
+ { 11289600, 0, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139 },
+
+ { 12000000, 1, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 12000000, 0, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 12288000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 12288000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 13000000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 13000000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 19200000, 1, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 19200000, 0, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+
+ { 22579200, 1, 0, 0, 0, 0, 0, 22579200, 0 },
+ { 22579200, 0, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139 },
+
+ { 24000000, 1, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 24000000, 0, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 24576000, 1, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 128 },
+ { 24576000, 0, 0, 0, 0, 0, 0, 24576000, 0 },
+
+ { 26000000, 1, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 26000000, 0, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+};
+
+static int cs43130_pll_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int i;
+
+ dev_dbg(codec->dev, "%s: cs43130->mclk = %d, cs43130->pll_out = %d",
+ __func__, cs43130->mclk, cs43130->pll_out);
+ for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
+ if (pll_ratio_table[i].pll_in == cs43130->mclk &&
+ pll_ratio_table[i].pll_out == cs43130->pll_out) {
+
+ cs43130->mclk_int = pll_ratio_table[i].mclk_int;
+
+ if (pll_ratio_table[i].pll_cal_ratio == 0) {
+ if (cs43130->xtal_ibias > 0) {
+ usleep_range(1000, 1050);
+ /*PDN_XTAL = 0,enable*/
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK,
+ 0 << CS43130_PDN_XTAL_SHIFT);
+ }
+
+ /* PLL_START = 0, disable PLL_START */
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK,
+ 0 << CS43130_PLL_START_MASK);
+
+ cs43130->pll_bypass = true;
+ return 0;
+ }
+
+ /* PDN_PLL= 0,enable */
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK,
+ 0 << CS43130_PDN_PLL_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
+ CS43130_PLL_REF_PREDIV_MASK,
+ pll_ratio_table[i].sclk_prediv);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
+ pll_ratio_table[i].pll_div_int);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_2,
+ pll_ratio_table[i].pll_div_frac &
+ CS43130_7_0_MASK);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_3,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_15_8_MASK) >> 8);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_4,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_23_16_MASK) >> 16);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
+ CS43130_PLL_MODE_MASK,
+ pll_ratio_table[i].pll_mode
+ << CS43130_PLL_MODE_SHIFT);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_6,
+ pll_ratio_table[i].pll_divout);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
+ pll_ratio_table[i].pll_cal_ratio);
+
+ /* PLL_START = 1, enable PLL_START */
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK, CS43130_PLL_START_MASK);
+ cs43130->pll_bypass = false;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int cs43130_format_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ int period_size = 0;
+ int pulse_width = 0;
+ int asp_fsd;
+ int asp_stp;
+ int bick_inv;
+ int asp_m = 0;
+ int asp_sprate = 0;
+ int ret = 0;
+ unsigned int bitwidth_sclk = (cs43130->sclk / cs43130->fs) / 2;
+ unsigned int bitwidth_dai = (cs43130->dai_bit + 1) * 8;
+
+ if (cs43130->fs) {
+ if (bitwidth_sclk < bitwidth_dai) {
+ dev_err(codec->dev, "Format not supported\n");
+ return -EINVAL;
+ }
+ period_size = cs43130->sclk / cs43130->fs;
+ pulse_width = period_size/2;
+
+ if (cs43130->sclk != 0)
+ asp_m = cs43130->pll_out / cs43130->sclk;
+ }
+ dev_dbg(codec->dev, "%s: cs43130->sclk = %d, cs43130->fs = %d, cs43130->dai_bit = %d",
+ __func__, cs43130->sclk, cs43130->fs, cs43130->dai_bit);
+ dev_dbg(codec->dev, "%s: period_size = %d, pulse_width = %d, asp_m = %d",
+ __func__, period_size, pulse_width, asp_m);
+
+ if (cs43130->dai_format) {
+ /*MSB*/
+ bick_inv = 0;
+ asp_fsd = 0;
+ asp_stp = 1;
+
+ } else {
+ /*I2S*/
+ bick_inv = 1;
+ asp_fsd = 2; /* one bick delay */
+ asp_stp = 0;
+ }
+ dev_dbg(codec->dev,
+ "%s: cs43130->dai_format = %d, bick_inv = %d, asp_fsd = %d, asp_stp = %d",
+ __func__, cs43130->dai_format, bick_inv, asp_fsd, asp_stp);
+
+ switch (cs43130->fs) {
+ case 32000:
+ asp_sprate = CS43130_ASP_SPRATE_32K;
+ break;
+ case 44100:
+ asp_sprate = CS43130_ASP_SPRATE_44_1K;
+ break;
+ case 48000:
+ asp_sprate = CS43130_ASP_SPRATE_48K;
+ break;
+ case 88200:
+ asp_sprate = CS43130_ASP_SPRATE_88_2K;
+ break;
+ case 96000:
+ asp_sprate = CS43130_ASP_SPRATE_96K;
+ break;
+ case 176400:
+ asp_sprate = CS43130_ASP_SPRATE_176_4K;
+ break;
+ case 192000:
+ asp_sprate = CS43130_ASP_SPRATE_192K;
+ break;
+ case 352800:
+ asp_sprate = CS43130_ASP_SPRATE_352_8K;
+ break;
+ case 384000:
+ asp_sprate = CS43130_ASP_SPRATE_384K;
+ break;
+ default:
+ dev_err(codec->dev, "sample rate(%d) not supported\n",
+ cs43130->fs);
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: asp_sprate = %d, cs43130->asp_size = %d",
+ __func__, asp_sprate, cs43130->asp_size);
+
+ /* ASP_SPRATE = fs*/
+ regmap_write(cs43130->regmap, CS43130_SP_SRATE, asp_sprate);
+ /*ASP_SPSIZE*/
+ regmap_update_bits(cs43130->regmap, CS43130_SP_BITSIZE,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->asp_size);
+
+
+ /* Set up slave mode */
+ /*BICK = ASP_N/ASP_M * PLL_OUT */
+ /* ASP_N = 1 */
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, 1);
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, 0);
+
+ /*ASP_M*/
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_1, asp_m & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_2, (asp_m >> 8) & 0x3f);
+
+
+ /* H / L ratio of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
+ (pulse_width-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
+ ((pulse_width-1) >> 8) & 0xff);
+
+ /* the period of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
+ (period_size-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
+ ((period_size-1) >> 8) & 0xff);
+
+ /*resolution*/
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_FSD_MASK, asp_fsd << CS43130_ASP_FSD_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_STP_MASK, asp_stp << CS43130_ASP_STP_SHIFT);
+
+ /* set clk master/slave */
+ dev_dbg(codec->dev, "%s: cs43130->dai_mode = %d",
+ __func__, cs43130->dai_mode);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CLOCK_CONF,
+ CS43130_ASP_MODE_MASK, cs43130->dai_mode << CS43130_ASP_MODE_SHIFT);
+
+ return ret;
+}
+
+static int cs43130_change_clksrc(struct snd_soc_codec *codec,
+ enum cs43130_mclk_src_sel src)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_SRC_SEL_MASK, src << CS43130_MCLK_SRC_SEL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_INT_MASK, cs43130->mclk_int << CS43130_MCLK_INT_SHIFT);
+
+ usleep_range(150, 200);
+
+ return ret;
+}
+
+static int cs43130_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ unsigned int bitwidth;
+ int ret = 0;
+
+ cs43130->fs = params_rate(params);
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_8;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_32;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_16;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_24;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_24;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_16;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_32;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_8;
+ break;
+ default:
+ dev_err(codec->dev, "Format(%d) not supported",
+ params_format(params));
+ return -EINVAL;
+ }
+
+ bitwidth = (cs43130->dai_bit+1)*8;
+ dev_dbg(codec->dev, "(data bit)%d: (rate)%d",
+ bitwidth, cs43130->fs);
+
+ ret = cs43130_format_config(codec);
+ return ret;
+}
+
+static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
+
+static const struct snd_kcontrol_new cs43130_snd_controls[] = {
+ SOC_DOUBLE_R_TLV("Master Playback Volume",
+ CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
+ pcm_vol_tlv),
+ SOC_SINGLE("Swap L/R", CS43130_PCM_PATH_CTL_2, 1, 1, 0),
+ SOC_SINGLE("Copy L/R", CS43130_PCM_PATH_CTL_2, 0, 1, 0),
+};
+
+static int cs43130_aspin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (cs43130->pll_bypass)
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
+ else
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
+
+ usleep_range(10000, 10050);
+ /* ASP_3ST = 0 in master mode */
+ if (cs43130->dai_mode)
+ regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
+ 0x01, 0x00);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_CLKOUT_MASK, 0
+ << CS43130_PDN_CLKOUT_SHIFT);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ break;
+ default:
+ dev_err(codec->dev, "Invalid ASPOUT event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_RCO);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK, 1
+ << CS43130_PDN_XTAL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK, 1
+ << CS43130_PDN_PLL_SHIFT);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid DAC event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 0 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x00);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x01);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 1 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid HPIN event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget cs43130_dapm_widgets[] = {
+
+ SND_SOC_DAPM_OUTPUT("HPOUTA"),
+ SND_SOC_DAPM_OUTPUT("HPOUTB"),
+
+ SND_SOC_DAPM_AIF_IN_E("ASPIN", NULL, 0, CS43130_PWDN_CTL,
+ CS43130_PDN_ASP_SHIFT, 1, cs43130_aspin_event,
+ (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
+
+ SND_SOC_DAPM_DAC_E("HiFi DAC",
+ NULL, CS43130_PWDN_CTL, CS43130_PDN_HP_SHIFT, 1,
+ cs43130_dac_event,
+ (SND_SOC_DAPM_PRE_PMD)
+ ),
+
+ SND_SOC_DAPM_LINE("Analog Playback", cs43130_hpin_event),
+};
+
+static const struct snd_soc_dapm_route cs43130_routes[] = {
+ {"ASPIN", NULL, "DAC Playback"},
+ {"HiFi DAC", NULL, "ASPIN"},
+
+ {"HPOUTA", NULL, "HiFi DAC"},
+ {"HPOUTB", NULL, "HiFi DAC"},
+ {"HPOUTA", NULL, "Analog Playback"},
+ {"HPOUTB", NULL, "Analog Playback"},
+};
+
+static const unsigned int cs43130_src_rates[] = {
+ 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
+};
+
+static const struct snd_pcm_hw_constraint_list cs43130_constraints = {
+ .count = ARRAY_SIZE(cs43130_src_rates),
+ .list = cs43130_src_rates,
+};
+
+static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, &cs43130_constraints);
+ return 0;
+}
+
+static int cs43130_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ cs43130->dai_mode = CS43130_SLAVE_MODE;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ cs43130->dai_mode = CS43130_MASTER_MODE;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported i2s master mode\n");
+ return -EINVAL;
+ }
+
+ /* interface format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ cs43130->dai_format = 0;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ cs43130->dai_format = 1;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio format except I2S and MSB\n");
+ return -EINVAL;
+ }
+
+ /* BICK/LRCK pority */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = true;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = true;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio polarity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+static int cs43130_set_mute(struct snd_soc_dai *dai, int mute)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int ret = 0;
+ unsigned int reg;
+ u8 mute_reg;
+
+ regmap_read(cs43130->regmap, CS43130_PCM_PATH_CTL_1, ®);
+ mute_reg = reg & 0xfc;
+ if (mute)
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
+ mute_reg | 0x03);
+ else
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1, mute_reg);
+
+ return ret;
+}
+
+static int cs43130_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+
+ switch (div_id) {
+ case CS43130_AIF_BICK_RATE:
+ cs43130->bick = div;
+ break;
+ default:
+ dev_err(codec->dev,
+ "Unsupported divide value: div_id = %d", div_id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
+ unsigned int freq_in, unsigned int freq_out)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ if (freq_in < 9600000 || freq_in > 26000000) {
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_in) {
+ case 9600000:
+ case 11289600:
+ case 12000000:
+ case 12288000:
+ case 13000000:
+ case 19200000:
+ case 22579200:
+ case 24000000:
+ case 24576000:
+ case 26000000:
+ cs43130->mclk = freq_in;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_out) {
+ case 22579200:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 1;
+ break;
+ case 24576000:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 0;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll output reference clock:%d\n",
+ freq_out);
+ return -EINVAL;
+ }
+
+ ret = cs43130_pll_config(codec);
+ dev_dbg(codec->dev, "%s: cs43130->pll_bypass = %d",
+ __func__, cs43130->pll_bypass);
+ return ret;
+}
+
+static int cs43130_dai_set_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, freq = %d, dir = %d",
+ __func__, clk_id, freq, dir);
+ cs43130->sclk = freq;
+ return 0;
+}
+
+static const struct snd_soc_dai_ops cs43130_dai_ops = {
+ .startup = cs43130_pcm_startup,
+ .hw_params = cs43130_pcm_hw_params,
+ .set_sysclk = cs43130_dai_set_sysclk,
+ .set_fmt = cs43130_set_dai_fmt,
+ .digital_mute = cs43130_set_mute,
+ .set_clkdiv = cs43130_set_clkdiv,
+};
+
+static struct snd_soc_dai_driver cs43130_dai[] = {
+ {
+ .name = "cs43130_hifi",
+ .id = 0,
+ .playback = {
+ .stream_name = "DAC Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_ASP_FORMATS,
+ },
+ .ops = &cs43130_dai_ops,
+ .symmetric_rates = 1,
+ },
+ {
+ .name = "cs43130-xsp",
+ .id = 1,
+ .playback = {
+ .stream_name = "XSP Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_XSP_FORMATS,
+ },
+ .symmetric_rates = 1,
+ },
+};
+
+static int cs43130_codec_set_sysclk(struct snd_soc_codec *codec,
+ int clk_id, int source, unsigned int freq, int dir)
+{
+ /* 24576000 is not supported */
+ unsigned int mclk_int_freq = 22579200;
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, source = %d, freq = %d, dir = %d\n",
+ __func__, clk_id, source, freq, dir);
+ /*
+ * freq is external mclk freq
+ * if freq == mclk_int_freq, pll is bypassed
+ * modify mclk_int_freq as needed for application
+ */
+ cs43130_set_pll(codec, 0, 0, freq, mclk_int_freq);
+ return 0;
+}
+
+static irqreturn_t cs43130_irq_thread(int irq, void *data)
+{
+ struct cs43130_private *cs43130 =
+ (struct cs43130_private *)data;
+ struct snd_soc_codec *codec = cs43130->codec;
+ unsigned int stickies[CS43130_NUM_INT];
+ unsigned int masks[CS43130_NUM_INT];
+ unsigned int i;
+
+ /* Read all INT status and mask reg */
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_STATUS_1,
+ stickies, CS43130_NUM_INT * sizeof(unsigned int));
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_MASK_1,
+ masks, CS43130_NUM_INT * sizeof(unsigned int));
+
+ for (i = 0; i < ARRAY_SIZE(stickies); i++)
+ stickies[i] = stickies[i] & (~masks[i]);
+
+ if (stickies[0] & CS43130_XTAL_RDY_INT)
+ dev_dbg(codec->dev, "%s: Crystal ready", __func__);
+
+ if (stickies[0] & CS43130_XTAL_ERR_INT)
+ dev_err(codec->dev, "%s: Crystal err", __func__);
+
+ if (stickies[0] & CS43130_HP_PLUG_INT)
+ dev_dbg(codec->dev, "%s: HP plugged", __func__);
+
+ if (stickies[0] & CS43130_HP_UNPLUG_INT)
+ dev_dbg(codec->dev, "%s: HP unplugged", __func__);
+
+ return IRQ_HANDLED;
+}
+
+static int cs43130_probe(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ cs43130->codec = codec;
+
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_cs43130 = {
+ .probe = cs43130_probe,
+ .component_driver = {
+ .controls = cs43130_snd_controls,
+ .num_controls = ARRAY_SIZE(cs43130_snd_controls),
+ .dapm_widgets = cs43130_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(cs43130_dapm_widgets),
+ .dapm_routes = cs43130_routes,
+ .num_dapm_routes = ARRAY_SIZE(cs43130_routes),
+ },
+ .set_sysclk = cs43130_codec_set_sysclk,
+ .set_pll = cs43130_set_pll,
+};
+
+static const struct regmap_config cs43130_regmap = {
+ .reg_bits = 24,
+ .pad_bits = 8,
+ .val_bits = 8,
+
+ .max_register = CS43130_LASTREG,
+ .reg_defaults = cs43130_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults),
+ .readable_reg = cs43130_readable_register,
+ .precious_reg = cs43130_precious_register,
+ .volatile_reg = cs43130_volatile_register,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static int cs43130_handle_device_data(
+ struct i2c_client *i2c_client, struct cs43130_private *cs43130)
+{
+ struct device_node *np = i2c_client->dev.of_node;
+ unsigned int val;
+ int ret = 0;
+
+ of_property_read_u32(np, "cirrus,xtal-ibias", &val);
+ switch (val) {
+ case 1:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
+ break;
+ case 2:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
+ break;
+ case 3:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
+ break;
+ default:
+ dev_info(&i2c_client->dev,
+ "cirrus,xtal-ibias value or xtal unused %d",
+ val);
+ }
+ return ret;
+}
+
+static int cs43130_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct cs43130_private *cs43130;
+ int ret;
+ unsigned int devid = 0;
+ unsigned int reg;
+ int i;
+
+ cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
+ if (cs43130 == NULL)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, cs43130);
+
+ cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
+ if (IS_ERR(cs43130->regmap)) {
+ ret = PTR_ERR(cs43130->regmap);
+ return ret;
+ }
+
+ if (client->dev.of_node) {
+ ret = cs43130_handle_device_data(client, cs43130);
+ if (ret != 0)
+ return ret;
+ }
+ for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
+ cs43130->supplies[i].supply = cs43130_supply_names[i];
+
+ ret = devm_regulator_bulk_get(&client->dev,
+ ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to request supplies: %d\n", ret);
+ return ret;
+ }
+ ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to enable supplies: %d\n", ret);
+ return ret;
+ }
+
+ cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
+ "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(cs43130->reset_gpio))
+ return PTR_ERR(cs43130->reset_gpio);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ /* initialize codec */
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®);
+
+ devid = (reg & 0xFF) << 12;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®);
+ devid |= (reg & 0xFF) << 4;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®);
+ devid |= (reg & 0xF0) >> 4;
+
+ switch (devid) {
+ case CS43130_CHIP_ID:
+ break;
+ case CS4399_CHIP_ID:
+ break;
+ default:
+ dev_err(&client->dev,
+ "CS43130 Device ID (%X). Expected ID %X or %X\n",
+ devid, CS43130_CHIP_ID, CS4399_CHIP_ID);
+ ret = -ENODEV;
+ goto err;
+ }
+
+ cs43130->dev_id = devid;
+ ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
+ if (ret < 0) {
+ dev_err(&client->dev, "Get Revision ID failed\n");
+ goto err;
+ }
+
+ dev_info(&client->dev,
+ "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
+ reg & 0xFF);
+
+ /* Enable interrupt handler */
+ ret = devm_request_threaded_irq(&client->dev,
+ client->irq,
+ NULL, cs43130_irq_thread,
+ IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+ "cs43130", cs43130);
+ if (ret != 0) {
+ dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
+ return ret;
+ }
+
+ /* Unmask INT */
+ regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
+ CS43130_XTAL_RDY_INT | CS43130_XTAL_ERR_INT |
+ CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0);
+
+ /* Enable HP detect */
+ regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
+ CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
+
+ regmap_write(cs43130->regmap,
+ CS43130_CRYSTAL_SET, cs43130->xtal_ibias);
+ ret = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_cs43130, cs43130_dai,
+ ARRAY_SIZE(cs43130_dai));
+
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "%s: snd_soc_register_codec failed with ret = %d\n",
+ __func__, ret);
+ goto err;
+ }
+ return 0;
+err:
+ return ret;
+
+}
+
+static int cs43130_i2c_remove(struct i2c_client *client)
+{
+ struct cs43130_private *cs43130 = i2c_get_clientdata(client);
+
+ snd_soc_unregister_codec(&client->dev);
+
+ if (cs43130->reset_gpio)
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ pm_runtime_disable(&client->dev);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int cs43130_runtime_suspend(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+
+ regcache_cache_only(cs43130->regmap, true);
+ regcache_mark_dirty(cs43130->regmap);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ return 0;
+}
+
+static int cs43130_runtime_resume(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(dev, "Failed to enable supplies: %d\n",
+ ret);
+ return ret;
+ }
+
+ regcache_cache_only(cs43130->regmap, false);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ ret = regcache_sync(cs43130->regmap);
+ if (ret != 0) {
+ dev_err(dev, "Failed to restore register cache\n");
+ goto err;
+ }
+ return 0;
+err:
+ regcache_cache_only(cs43130->regmap, true);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops cs43130_runtime_pm = {
+ SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id cs43130_of_match[] = {
+ { .compatible = "cirrus,cs43130", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, cs43130_of_match);
+
+static const struct i2c_device_id cs43130_i2c_id[] = {
+ {"cs43130", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
+
+static struct i2c_driver cs43130_i2c_driver = {
+ .driver = {
+ .name = "cs43130",
+ .of_match_table = cs43130_of_match,
+ },
+ .id_table = cs43130_i2c_id,
+ .probe = cs43130_i2c_probe,
+ .remove = cs43130_i2c_remove,
+};
+
+module_i2c_driver(cs43130_i2c_driver);
+
+MODULE_AUTHOR("Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs43130.h b/sound/soc/codecs/cs43130.h
new file mode 100644
index 0000000..bceae76
--- /dev/null
+++ b/sound/soc/codecs/cs43130.h
@@ -0,0 +1,268 @@
+/*
+ * ALSA SoC CS43130 codec driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Author: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#ifndef __CS43130_H__
+#define __CS43130_H__
+
+/* CS43130 registers addresses */
+/* all reg address is shifted by a byte for control byte to be LSB */
+#define CS43130_FIRSTREG 0x010000
+#define CS43130_LASTREG 0x0F0014
+#define CS43130_CHIP_ID 0x00043130
+#define CS4399_CHIP_ID 0x00043990
+#define CS43130_DEVID_AB 0x010000 /*Device ID A & B [RO]*/
+#define CS43130_DEVID_CD 0x010001 /*Device ID C & D [RO]*/
+#define CS43130_DEVID_E 0x010002 /*Device ID E [RO]*/
+#define CS43130_FAB_ID 0x010003 /*Fab ID [RO]*/
+#define CS43130_REV_ID 0x010004 /*Revision ID [RO]*/
+#define CS43130_SUBREV_ID 0x010005 /*Subrevision ID*/
+#define CS43130_SYS_CLK_CTL_1 0x010006 /*System Clocking Ctl 1*/
+#define CS43130_SP_SRATE 0x01000B /*Serial Port Sample Rate*/
+#define CS43130_SP_BITSIZE 0x01000C /*Serial Port Bit Size*/
+#define CS43130_PAD_INT_CFG 0x01000D /*Pad Interface Config*/
+#define CS43130_DXD1 0x010010 /*DXD1*/
+#define CS43130_PWDN_CTL 0x020000 /*Power Down Ctl*/
+#define CS43130_DXD2 0x020019 /*DXD2*/
+#define CS43130_CRYSTAL_SET 0x020052 /*Crystal Setting*/
+#define CS43130_PLL_SET_1 0x030001 /*PLL Setting 1*/
+#define CS43130_PLL_SET_2 0x030002 /*PLL Setting 2*/
+#define CS43130_PLL_SET_3 0x030003 /*PLL Setting 3*/
+#define CS43130_PLL_SET_4 0x030004 /*PLL Setting 4*/
+#define CS43130_PLL_SET_5 0x030005 /*PLL Setting 5*/
+#define CS43130_PLL_SET_6 0x030008 /*PLL Setting 6*/
+#define CS43130_PLL_SET_7 0x03000A /*PLL Setting 7*/
+#define CS43130_PLL_SET_8 0x03001B /*PLL Setting 8*/
+#define CS43130_PLL_SET_9 0x040002 /*PLL Setting 9*/
+#define CS43130_PLL_SET_10 0x040003 /*PLL Setting 10*/
+#define CS43130_CLKOUT_CTL 0x040004 /*CLKOUT Ctl*/
+#define CS43130_ASP_NUM_1 0x040010 /*ASP Numerator 1*/
+#define CS43130_ASP_NUM_2 0x040011 /*ASP Numerator 2*/
+#define CS43130_ASP_DENOM_1 0x040012 /*ASP Denominator 1*/
+#define CS43130_ASP_DENOM_2 0x040013 /*ASP Denominator 2*/
+#define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /*ASP LRCK High Time 1*/
+#define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /*ASP LRCK High Time 2*/
+#define CS43130_ASP_LRCK_PERIOD_1 0x040016 /*ASP LRCK Period 1*/
+#define CS43130_ASP_LRCK_PERIOD_2 0x040017 /*ASP LRCK Period 2*/
+#define CS43130_ASP_CLOCK_CONF 0x040018 /*ASP Clock Config*/
+#define CS43130_ASP_FRAME_CONF 0x040019 /*ASP Frame Config*/
+#define CS43130_XSP_NUM_1 0x040020 /*XSP Numerator 1*/
+#define CS43130_XSP_NUM_2 0x040021 /*XSP Numerator 2*/
+#define CS43130_XSP_DENOM_1 0x040022 /*XSP Denominator 1*/
+#define CS43130_XSP_DENOM_2 0x040023 /*XSP Denominator 2*/
+#define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /*XSP LRCK High Time 1*/
+#define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /*XSP LRCK High Time 2*/
+#define CS43130_XSP_LRCK_PERIOD_1 0x040026 /*XSP LRCK Period 1*/
+#define CS43130_XSP_LRCK_PERIOD_2 0x040027 /*XSP LRCK Period 2*/
+#define CS43130_XSP_CLOCK_CONF 0x040028 /*XSP Clock Config*/
+#define CS43130_XSP_FRAME_CONF 0x040029 /*XSP Frame Config*/
+#define CS43130_ASP_CH_1_LOC 0x050000 /*ASP Chan 1 Location*/
+#define CS43130_ASP_CH_2_LOC 0x050001 /*ASP Chan 2 Location*/
+#define CS43130_ASP_CH_1_SZ_EN 0x05000A /*ASP Chan 1 Size, Enable*/
+#define CS43130_ASP_CH_2_SZ_EN 0x05000B /*ASP Chan 2 Size, Enable*/
+#define CS43130_XSP_CH_1_LOC 0x060000 /*XSP Chan 1 Location*/
+#define CS43130_XSP_CH_2_LOC 0x060001 /*XSP Chan 2 Location*/
+#define CS43130_XSP_CH_1_SZ_EN 0x06000A /*XSP Chan 1 Size, Enable*/
+#define CS43130_XSP_CH_2_SZ_EN 0x06000B /*XSP Chan 2 Size, Enable*/
+#define CS43130_DSD_VOL_B 0x070000 /*DSD Volume B*/
+#define CS43130_DSD_VOL_A 0x070001 /*DSD Volume A*/
+#define CS43130_DSD_PATH_CTL_1 0x070002 /*DSD Proc Path Sig Ctl 1*/
+#define CS43130_DSD_INT_CFG 0x070003 /*DSD Interface Config*/
+#define CS43130_DSD_PATH_CTL_2 0x070004 /*DSD Proc Path Sig Ctl 2*/
+#define CS43130_DSD_PCM_MIX_CTL 0x070005 /*DSD and PCM Mixing Ctl*/
+#define CS43130_DSD_PATH_CTL_3 0x070006 /*DSD Proc Path Sig Ctl 3*/
+#define CS43130_HP_OUT_CTL_1 0x080000 /*HP Output Ctl 1*/
+#define CS43130_PCM_FILT_OPT 0x090000 /*PCM Filter Option*/
+#define CS43130_PCM_VOL_B 0x090001 /*PCM Volume B*/
+#define CS43130_PCM_VOL_A 0x090002 /*PCM Volume A*/
+#define CS43130_PCM_PATH_CTL_1 0x090003 /*PCM Path Signal Ctl 1*/
+#define CS43130_PCM_PATH_CTL_2 0x090004 /*PCM Path Signal Ctl 2*/
+#define CS43130_CLASS_H_CTL 0x0B0000 /*Class H Ctl*/
+#define CS43130_HP_DETECT 0x0D0000 /*HP Detect*/
+#define CS43130_HP_STATUS 0x0D0001 /*HP Status [RO]*/
+#define CS43130_HP_LOAD_1 0x0E0000 /*HP Load 1*/
+#define CS43130_HP_MEAS_LOAD_1 0x0E0003 /*HP Load Measurement 1*/
+#define CS43130_HP_MEAS_LOAD_2 0x0E0004 /*HP Load Measurement 2*/
+#define CS43130_HP_DC_STAT_1 0x0E000D /*HP DC Load Status 0 [RO]*/
+#define CS43130_HP_DC_STAT_2 0x0E000E /*HP DC Load Status 1 [RO]*/
+#define CS43130_HP_AC_STAT_1 0x0E0010 /*HP AC Load Status 0 [RO]*/
+#define CS43130_HP_AC_STAT_2 0x0E0011 /*HP AC Load Status 1 [RO]*/
+#define CS43130_HP_LOAD_STAT 0x0E001A /*HP Load Status [RO]*/
+#define CS43130_INT_STATUS_1 0x0F0000 /*Interrupt Status 1*/
+#define CS43130_INT_STATUS_2 0x0F0001 /*Interrupt Status 2*/
+#define CS43130_INT_STATUS_3 0x0F0002 /*Interrupt Status 3*/
+#define CS43130_INT_STATUS_4 0x0F0003 /*Interrupt Status 4*/
+#define CS43130_INT_STATUS_5 0x0F0004 /*Interrupt Status 5*/
+#define CS43130_INT_MASK_1 0x0F0010 /*Interrupt Mask 1*/
+#define CS43130_INT_MASK_2 0x0F0011 /*Interrupt Mask 2*/
+#define CS43130_INT_MASK_3 0x0F0012 /*Interrupt Mask 3*/
+#define CS43130_INT_MASK_4 0x0F0013 /*Interrupt Mask 4*/
+#define CS43130_INT_MASK_5 0x0F0014 /*Interrupt Mask 5*/
+
+#define CS43130_MCLK_SRC_SEL_MASK 0x03
+#define CS43130_MCLK_SRC_SEL_SHIFT 0
+#define CS43130_MCLK_INT_MASK 0x04
+#define CS43130_MCLK_INT_SHIFT 2
+#define CS43130_SP_SRATE_MASK 0x0F
+#define CS43130_SP_SRATE_SHIFT 0
+#define CS43130_SP_BITSIZE_ASP_MASK 0x03
+#define CS43130_SP_BITSIZE_ASP_SHIFT 0
+#define CS43130_HP_DETECT_CTRL_SHIFT 6
+#define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
+#define CS43130_HP_DETECT_INV_SHIFT 5
+#define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)
+
+/* CS43130_INT_MASK_1 */
+#define CS43130_HP_PLUG_INT_SHIFT 6
+#define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)
+#define CS43130_HP_UNPLUG_INT_SHIFT 5
+#define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)
+#define CS43130_XTAL_RDY_INT_SHIFT 4
+#define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)
+#define CS43130_XTAL_ERR_INT_SHIFT 3
+#define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)
+
+/*Reg CS43130_SP_BITSIZE*/
+#define CS43130_SP_BIT_SIZE_8 0x00
+#define CS43130_SP_BIT_SIZE_16 0x01
+#define CS43130_SP_BIT_SIZE_24 0x02
+#define CS43130_SP_BIT_SIZE_32 0x03
+
+/*PLL*/
+#define CS43130_PLL_START_MASK (0x1<<0)
+#define CS43130_PLL_MODE_MASK 0x02
+#define CS43130_PLL_MODE_SHIFT 1
+
+#define CS43130_PLL_REF_PREDIV_MASK 0x3
+
+#define CS43130_ASP_STP_MASK 0x10
+#define CS43130_ASP_STP_SHIFT 4
+#define CS43130_ASP_5050_MASK 0x08
+#define CS43130_ASP_5050_SHIFT 3
+#define CS43130_ASP_FSD_MASK 0x07
+#define CS43130_ASP_FSD_SHIFT 0
+
+#define CS43130_ASP_MODE_MASK 0x10
+#define CS43130_ASP_MODE_SHIFT 4
+#define CS43130_ASP_SCPOL_OUT_MASK 0x08
+#define CS43130_ASP_SCPOL_OUT_SHIFT 3
+#define CS43130_ASP_SCPOL_IN_MASK 0x04
+#define CS43130_ASP_SCPOL_IN_SHIFT 2
+#define CS43130_ASP_LCPOL_OUT_MASK 0x02
+#define CS43130_ASP_LCPOL_OUT_SHIFT 1
+#define CS43130_ASP_LCPOL_IN_MASK 0x01
+#define CS43130_ASP_LCPOL_IN_SHIFT 0
+
+/*Reg CS43130_PWDN_CTL*/
+#define CS43130_PDN_XSP_MASK 0x80
+#define CS43130_PDN_XSP_SHIFT 7
+#define CS43130_PDN_ASP_MASK 0x40
+#define CS43130_PDN_ASP_SHIFT 6
+#define CS43130_PDN_DSPIF_MASK 0x20
+#define CS43130_PDN_DSDIF_SHIFT 5
+#define CS43130_PDN_HP_MASK 0x10
+#define CS43130_PDN_HP_SHIFT 4
+#define CS43130_PDN_XTAL_MASK 0x08
+#define CS43130_PDN_XTAL_SHIFT 3
+#define CS43130_PDN_PLL_MASK 0x04
+#define CS43130_PDN_PLL_SHIFT 2
+#define CS43130_PDN_CLKOUT_MASK 0x02
+#define CS43130_PDN_CLKOUT_SHIFT 1
+
+#define CS43130_7_0_MASK 0xFF
+#define CS43130_15_8_MASK 0xFF00
+#define CS43130_23_16_MASK 0xFF0000
+
+/* Reg CS43130_HP_OUT_CTL_1 */
+#define CS43130_HP_IN_EN_SHIFT 3
+#define CS43130_HP_IN_EN_MASK 0x08
+
+#define CS43130_ASP_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
+ SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#define CS43130_XSP_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+enum cs43130_asp_rate {
+ CS43130_ASP_SPRATE_32K = 0,
+ CS43130_ASP_SPRATE_44_1K,
+ CS43130_ASP_SPRATE_48K,
+ CS43130_ASP_SPRATE_88_2K,
+ CS43130_ASP_SPRATE_96K,
+ CS43130_ASP_SPRATE_176_4K,
+ CS43130_ASP_SPRATE_192K,
+ CS43130_ASP_SPRATE_352_8K,
+ CS43130_ASP_SPRATE_384K,
+};
+
+enum cs43130_mclk_src_sel {
+ CS43130_MCLK_SRC_XTAL = 0,
+ CS43130_MCLK_SRC_PLL,
+ CS43130_MCLK_SRC_RCO
+};
+
+enum cs43130_mode {
+ CS43130_SLAVE_MODE = 0,
+ CS43130_MASTER_MODE
+};
+
+enum cs43130_xtal_ibias {
+ CS43130_XTAL_IBIAS_15UA = 2,
+ CS43130_XTAL_IBIAS_12_5UA = 4,
+ CS43130_XTAL_IBIAS_7_5UA = 6,
+};
+
+#define CS43130_AIF_BICK_RATE 1
+#define CS43130_SYSCLK_MCLK 1
+#define CS43130_NUM_SUPPLIES 5
+static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
+ "VA",
+ "VP",
+ "VCP",
+ "VD",
+ "VL",
+};
+
+#define CS43130_NUM_INT 5 /* number of interrupt status reg */
+
+struct cs43130_private {
+ struct snd_soc_codec *codec;
+ struct regmap *regmap;
+ struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];
+ /* codec device ID */
+ unsigned int dev_id;
+ int mclk;
+ int sclk;
+ int xtal_ibias;
+
+ bool pll_bypass;
+ int pll_out;
+ int mclk_int;
+ int dai_format;
+ int dai_mode;
+ int dai_bit;
+ int asp_size;
+ int fs;
+ bool bick_invert;
+ bool lrck_invert;
+ int bick;
+ struct gpio_desc *reset_gpio;
+};
+
+#endif /* __CS43130_H__ */
--
1.9.1
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^ permalink raw reply related
* [PATCH v2 2/2] ASoC: cs43130: Add devicetree bindings for CS43130
From: Li Xu @ 2016-12-12 20:17 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
In-Reply-To: <1481573851-1421-1-git-send-email-li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
Add devicetree bindings documentation file for Cirrus
Logic CS43130 codec.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/sound/cs43130.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/cs43130.txt
diff --git a/Documentation/devicetree/bindings/sound/cs43130.txt b/Documentation/devicetree/bindings/sound/cs43130.txt
new file mode 100644
index 0000000..1af6b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs43130.txt
@@ -0,0 +1,41 @@
+CS43130 DAC
+
+Required properties:
+
+ - compatible : "cirrus,cs43130"
+
+ - reg : the I2C address of the device for I2C
+
+ - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
+ power supplies for the device, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+
+Optional properties:
+
+ - reset-gpios : Active low GPIO used to reset the device
+
+ - cirrus,xtal-ibias:
+ When external MCLK is generated by external crystal
+ oscillator, CS43130 can be used to provide bias current
+ for external crystal. Amount of bias current sent is
+ set as:
+ 1 = 7.5uA
+ 2 = 12.5uA
+ 3 = 15uA
+
+Example:
+
+cs43130: audio-codec@30 {
+ compatible = "cirrus,cs43130";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio 54 1>;
+ VA-supply = <&dummy_vreg>;
+ VP-supply = <&dummy_vreg>;
+ VL-supply = <&dummy_vreg>;
+ VCP-supply = <&dummy_vreg>;
+ VD-supply = <&dummy_vreg>;
+ cirrus,xtal-ibias = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <55 8>;
+};
--
1.9.1
--
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^ permalink raw reply related
* Re: [PATCH v2] PCI: rockchip: Add quirk to disable RC's ASPM L0s
From: Brian Norris @ 2016-12-12 20:19 UTC (permalink / raw)
To: Shawn Lin
Cc: Bjorn Helgaas, Rob Herring, linux-pci, linux-rockchip, Wenrui Li,
Jeffy Chen, devicetree, Doug Anderson
In-Reply-To: <1481543487-33152-1-git-send-email-shawn.lin@rock-chips.com>
Hi,
On Mon, Dec 12, 2016 at 07:51:27PM +0800, Shawn Lin wrote:
> Rockchip's RC outputs 100MHz reference clock but there are
> two methods for PHY to generate it.
>
> (1)One of them is to use system PLL to generate 100MHz clock and
> the PHY will relock it and filter signal noise then outputs the
> reference clock.
>
> (2)Another way is to share Soc's 24MHZ crystal oscillator with
> PHY and force PHY's DLL to generate 100MHz internally.
>
> When using case(2), the exit from L0s doesn't work fine occasionally
> due to the broken design of RC receiver's logical circuit. So even if
> we use extended-synch, it still fails for PHY to relock the bits from
> FTS sometimes. This will hang the system.
>
> Maybe we could argue that why not use case(1) to avoid it? The reason
> is that as we could see the reference clock is derived from system PLL
> and the path from it to PHY isn't so clean which means there are some
> noise introduced by power-domain and other buses can't be filterd out
> by PHY and we could see noise from the frequency spectrum by
> oscilloscope. This makes the TX compatibility test a little difficult
> to pass the spec. So case(1) and case(2) are both used indeed now. If
> using case(2), we should disable RC's L0s support, and that is why we
> need this property to indicate this quirk.
>
> Also after checking quirk.c, I noticed there is already a quirk for
> disabling L0s unconditionally, quirk_disable_aspm_l0s. But obviously we
> shouldn't do that as mentioned above that case(1) could still works fine
> with L0s.
Side note: I think Doug mentioned previously that the default
rk3399.dtsi actually leaves the default clock choice (i.e., case 2), so
it might be good to patch this property into the rk3399.dtsi instead of
the board files. If any board goes with option 1, they can delete the
property.
I can patch this up myself if you don't, as I'm working on upstreaming
the rk3399-gbased Gru/Kevin device trees.
> Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> Cc: Brian Norris <briannorris@chromium.org>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
>
> Changes in v2:
> - drop the quirk prefix
>
> Documentation/devicetree/bindings/pci/rockchip-pcie.txt | 2 ++
> drivers/pci/host/pcie-rockchip.c | 9 +++++++++
> 2 files changed, 11 insertions(+)
FWIW:
Reviewed-by: Brian Norris <briannorris@chromium.org>
^ permalink raw reply
* RE: [PATCH 1/2] ASoC: Add support for CS43130 codec
From: li.xu-jGc1dHjMKG3QT0dZR+AlfA @ 2016-12-12 20:21 UTC (permalink / raw)
To: Mark Brown
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
perex-/Fr2/VpizcU@public.gmane.org,
tiwai-IBi9RG/b67k@public.gmane.org, Austin, Brian,
Handrigan, Paul
In-Reply-To: <20161208162336.l5g5cbcc2bzt65ke-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
Thank you for timely feedback.
I have fixed all except following.
---------------------------------------------------------------------------------------------------------------------------------------------------
> + case SND_SOC_DAPM_PRE_PMU:
> + if (cs43130->pll_bypass)
> + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
> + else
> + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
> +
> + usleep_range(10000, 10050);
> + /*ASP_3ST = 0 in master mode*/
> + if (cs43130->dai_mode)
> + regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
> + 0x01, 0x00);
No need to undo this in slave mode?
Master mode specific configuration
---------------------------------------------------------------------------------------------------------------------------------------------------
> + /* Enable HP detect */
> + regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
> + CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
Why enable this when the only handling is a couple of log messages?
Placeholder for driver modification when the driver is integrated to system such as Android OS.
I suppose I could remove it, but when the driver is integrated into actual system, it may not be clear to system integrators,
where to add HP DET IRQ hooks
---------------------------------------------------------------------------------------------------------------------------------------------------
> + regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
> + CS43130_PLL_REF_PREDIV_MASK,
> + pll_ratio_table[i].sclk_prediv
> + );
There's no need for the ); to be on a new line here, nor for the extra
indentation on the line before. There are lots more coding style
issues, checkpatch will probably pick up many of them.
Fixed.
Regarding regmap_update_bits(), while I could make this API call in two lines,
often the two lines exceed 80 character limit, mandated by Linux.
If exceeding 80 char limit is ok, then I can certainly modify the API call.
checkpatch.pl did not flag additional formatting issues except for
"Possible switch case/default not preceeded by break or fallthrough comment"
which I believe should be ok
________________________________________
From: Mark Brown [broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
Sent: Thursday, December 08, 2016 10:23 AM
To: Xu, Li
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; perex-/Fr2/VpizcU@public.gmane.org; tiwai-IBi9RG/b67k@public.gmane.org; Austin, Brian; Handrigan, Paul
Subject: Re: [PATCH 1/2] ASoC: Add support for CS43130 codec
On Wed, Dec 07, 2016 at 02:17:27PM -0600, Li Xu wrote:
Overall this looks pretty good - there's a fair number of issues below
but they're all fairly simple stylistic things rather than anything
majorly wrong so hopefully should be easy to correct.
> select SND_SOC_CS53L30 if I2C
> + select SND_SOC_CS43130 if I2C
> select SND_SOC_CX20442 if TTY
Please keep Kconfig and Makefile sorted.
> +static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case CS43130_DEVID_AB ... CS43130_SUBREV_ID:
> + case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
> + return true;
You don't need to mark the device ID volatile, just don't provide
defaults and regmap will cache it the first time it reads it. If the
device ID is volatile you've got bigger problems.
> + /*PDN_PLL= 0,enable*/
Please use the standard kernel coding style, need spaces here.
> + regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
> + CS43130_PLL_REF_PREDIV_MASK,
> + pll_ratio_table[i].sclk_prediv
> + );
There's no need for the ); to be on a new line here, nor for the extra
indentation on the line before. There are lots more coding style
issues, checkpatch will probably pick up many of them.
> + case SND_SOC_DAPM_PRE_PMU:
> + if (cs43130->pll_bypass)
> + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
> + else
> + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
> +
> + usleep_range(10000, 10050);
> + /*ASP_3ST = 0 in master mode*/
> + if (cs43130->dai_mode)
> + regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
> + 0x01, 0x00);
No need to undo this in slave mode?
> + if (stickies[0] & CS43130_XTAL_ERR_INT)
> + pr_debug("%s: Crystal err\n", __func__);
dev_ prints and shouldn't this one be an error?
> + /* Enable HP detect */
> + regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
> + CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
Why enable this when the only handling is a couple of log messages?
> +#ifdef CONFIG_PM
> +static int cs43130_runtime_suspend(struct device *dev)
> +{
> + return 0;
> +}
Remove empty functions, they don't serve any purpose.
--
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^ permalink raw reply
* Re: [PATCH 2/2] ASoC: cs43130: Add devicetree bindings for CS43130
From: Li Xu @ 2016-12-12 20:41 UTC (permalink / raw)
To: Rob Herring
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA
In-Reply-To: <20161212170425.zbmh4yu5dr65iwir@rob-hp-laptop>
Thank you for your feedback.
All issues have been fixed. See v2 patch
On Mon, Dec 12, 2016 at 11:04:25AM -0600, Rob Herring wrote:
> On Wed, Dec 07, 2016 at 02:17:28PM -0600, Li Xu wrote:
> > Add devicetree bindings documentation file for Cirrus
> > Logic CS43130 codec.
> >
> > Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
> > ---
> > .../devicetree/bindings/sound/cs43130.txt | 41 ++++++++++++++++++++++
> > 1 file changed, 41 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/sound/cs43130.txt
> >
> > diff --git a/Documentation/devicetree/bindings/sound/cs43130.txt b/Documentation/devicetree/bindings/sound/cs43130.txt
> > new file mode 100644
> > index 0000000..9a2a22a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/cs43130.txt
> > @@ -0,0 +1,41 @@
> > +CS43130 DAC
> > +
> > +Required properties:
> > +
> > + - compatible : "cirrus,cs43130"
> > +
> > + - reg : the I2C address of the device for I2C
> > +
> > + - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
> > + power supplies for the device, as covered in
> > + Documentation/devicetree/bindings/regulator/regulator.txt.
> > +
> > +
> > +Optional properties:
> > +
> > + - reset-gpios : gpio used to reset the Device
>
> Please state the active state and set that in the flag cell.
>
> > +
> > + - cirrus,xtal-ibias:
> > + When external MCLK is generated by external crystal
> > + oscillator, CS43130 can be used to provide bias current
> > + for external crystal. Amount of bias current sent is
> > + set as:
> > + 1 = 7.5uA
> > + 2 = 12.5uA
> > + 3 = 15uA
> > +
> > +Example:
> > +
> > +cs43130: cs43130@30 {
>
> audio-codec@30
>
> > + compatible = "cirrus,cs43130";
> > + reg = <0x30>;
> > + reset-gpios = <&axi_gpio 54 0>;
> > + VA-supply = <&dummy_vreg>;
>
> Some whitespace problems here.
>
> > + VP-supply = <&dummy_vreg>;
> > + VL-supply = <&dummy_vreg>;
> > + VCP-supply = <&dummy_vreg>;
> > + VD-supply = <&dummy_vreg>;
> > + cirrus,xtal-ibias = <2>;
> > + interrupt-parent = <&gpio0>;
> > + interrupts = <55 8>;
> > +};
> > --
> > 1.9.1
> >
--
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^ permalink raw reply
* Re: [PATCH 1/2] ASoC: Add support for CS43130 codec
From: Li Xu @ 2016-12-12 21:05 UTC (permalink / raw)
To: Mark Brown
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA
In-Reply-To: <20161208162336.l5g5cbcc2bzt65ke-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
Thank you for your prompt reply.
I have updated v2 patch to include your recommmendations except
following:
----------------------------------------------------------------------------
> > + regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
> > + CS43130_PLL_REF_PREDIV_MASK,
> > + pll_ratio_table[i].sclk_prediv
> > + );
>
> There's no need for the ); to be on a new line here, nor for the extra
> indentation on the line before. There are lots more coding style
> issues, checkpatch will probably pick up many of them.
Fixed.
In v2 patch, checkpatch do not show addional formatting issues.
I have cleaned 'regmap_update_bits' API call with 80-char line
constraint.
----------------------------------------------------------------------------
> > + case SND_SOC_DAPM_PRE_PMU:
> > + if (cs43130->pll_bypass)
> > + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
> > + else
> > + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
> > +
> > + usleep_range(10000, 10050);
> > + /*ASP_3ST = 0 in master mode*/
> > + if (cs43130->dai_mode)
> > + regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
> > + 0x01, 0x00);
>
> No need to undo this in slave mode?
Only needed for master mode, so no need for slave mode
----------------------------------------------------------------------------
> > + /* Enable HP detect */
> > + regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
> > + CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
>
> Why enable this when the only handling is a couple of log messages?
I suppose I could remove it, but it may be helpful for
system integrators to know where HP detect hooks are.
But if you insist, I could remove it.
----------------------------------------------------------------------------
On Thu, Dec 08, 2016 at 04:23:36PM +0000, Mark Brown wrote:
> On Wed, Dec 07, 2016 at 02:17:27PM -0600, Li Xu wrote:
>
> Overall this looks pretty good - there's a fair number of issues below
> but they're all fairly simple stylistic things rather than anything
> majorly wrong so hopefully should be easy to correct.
>
> > select SND_SOC_CS53L30 if I2C
> > + select SND_SOC_CS43130 if I2C
> > select SND_SOC_CX20442 if TTY
>
> Please keep Kconfig and Makefile sorted.
>
> > +static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
> > +{
> > + switch (reg) {
> > + case CS43130_DEVID_AB ... CS43130_SUBREV_ID:
> > + case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
> > + return true;
>
> You don't need to mark the device ID volatile, just don't provide
> defaults and regmap will cache it the first time it reads it. If the
> device ID is volatile you've got bigger problems.
>
> > + /*PDN_PLL= 0,enable*/
>
> Please use the standard kernel coding style, need spaces here.
>
> > + regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
> > + CS43130_PLL_REF_PREDIV_MASK,
> > + pll_ratio_table[i].sclk_prediv
> > + );
>
> There's no need for the ); to be on a new line here, nor for the extra
> indentation on the line before. There are lots more coding style
> issues, checkpatch will probably pick up many of them.
>
> > + case SND_SOC_DAPM_PRE_PMU:
> > + if (cs43130->pll_bypass)
> > + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
> > + else
> > + cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
> > +
> > + usleep_range(10000, 10050);
> > + /*ASP_3ST = 0 in master mode*/
> > + if (cs43130->dai_mode)
> > + regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
> > + 0x01, 0x00);
>
> No need to undo this in slave mode?
>
> > + if (stickies[0] & CS43130_XTAL_ERR_INT)
> > + pr_debug("%s: Crystal err\n", __func__);
>
> dev_ prints and shouldn't this one be an error?
>
> > + /* Enable HP detect */
> > + regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
> > + CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
>
> Why enable this when the only handling is a couple of log messages?
>
> > +#ifdef CONFIG_PM
> > +static int cs43130_runtime_suspend(struct device *dev)
> > +{
> > + return 0;
> > +}
>
> Remove empty functions, they don't serve any purpose.
--
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^ permalink raw reply
* Re: [PATCH v4 4/4] regulator: Prevent falling too fast
From: Matthias Kaehlcke @ 2016-12-12 21:15 UTC (permalink / raw)
To: Mark Brown
Cc: Doug Anderson, Liam Girdwood, Brian Norris,
Javier Martinez Canillas, Rob Herring, Mark Rutland,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161028181521.ywzmow6bgndfotq3-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
El Fri, Oct 28, 2016 at 07:15:21PM +0100 Mark Brown ha dit:
> On Mon, Sep 26, 2016 at 10:41:59AM -0700, Doug Anderson wrote:
>
> > I guess I think of the whole network of components as the PWM
> > regulator and not the individual discreet BUCK. I'm also not quite
> > sure how you would model it as you're asking. I suppose you could say
> > that all of the resistors / capacitors / inductors end up producing a
> > voltage and this voltage is an input to the BUCK. ...then the BUCK
>
> Yes, that's what's happening.
>
> > I know for sure that our EEs have massively modified the behavior of
> > the whole thing by just changing the resistors / capacitors /
> > inductors, changing the undershoot, OVP issue, voltage ranges, default
> > voltage, etc. That's what leads me to believe it's not so separable.
>
> What you're describing to me is a discrete DCDC that has an input
> voltage that sets the output voltage which happens to be set with a PWM.
> It's of course going to be the case that the passives are important to
> the system performance but it seems we have two bits here - the PWM
> regulator providing an input to the DCDC and the DCDC itself which is
> sensitive to rate changes.
I experimented a bit with this. Besides the question of how to model
the passives I wonder how the two regulators would interact. The
correct thing seems to be to specify the input regulator as a supply
of the DCDC. dcdc->set_voltage breaks down a voltage transition into
steps (if needed) and calls regulator_set_voltage(supply) for each
step. The problem with that is that regulator_set_voltage(dcdc)
acquires the supply lock(s), later regulator_set_voltage(supply) tries
to acquire its own lock which is already held. This can be worked
around by only using the supply regulator in the DCDC, but not
specify it as a supply. However this seems more a hack than a proper
solution.
Am I missing something obvious here or approaching this from a wrong
angle?
Thanks
Matthias
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^ permalink raw reply
* Re: [PATCH v8 3/8] drivers:input:tsc2007: add iio interface to read external ADC input and temperature
From: H. Nikolaus Schaller @ 2016-12-12 21:21 UTC (permalink / raw)
To: Jonathan Cameron, Dmitry Torokhov
Cc: Jonathan Cameron, Sebastian Reichel, Mark Rutland,
Benoît Cousson, Tony Lindgren, Russell King, Arnd Bergmann,
Michael Welling, Mika Penttilä, Javier Martinez Canillas,
Igor Grinberg, Andrew F. Davis, Mark Brown, Rob Herring,
Alexander Stein, Eric Engestrom, Hans de Goede,
Benjamin Tissoires
In-Reply-To: <AC7B3C1C-C05B-45B5-8426-5225F151DC26-xXXSsgcRVICgSpxsJD1C4w@public.gmane.org>
Hi,
> Am 27.11.2016 um 16:47 schrieb H. Nikolaus Schaller <hns-xXXSsgcRVICgSpxsJD1C4w@public.gmane.org>:
>
> Hi Jonathan,
>
>> Am 27.11.2016 um 12:02 schrieb Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
>>
>> On 24/11/16 18:05, H. Nikolaus Schaller wrote:
>>>
>>>> Am 24.11.2016 um 18:38 schrieb Jonathan Cameron <jic23-tko9wxEg+fIOOJlXag/Snyp2UmYkHbXO@public.gmane.org>:
>>>>
>>>>
>>>>
>>>> On 22 November 2016 14:02:30 GMT+00:00, "H. Nikolaus Schaller" <hns-xXXSsgcRVICgSpxsJD1C4w@public.gmane.org> wrote:
>
>> - hence cc'd Yann and the Kbuild list
>> to see if they can offer some advices.
no response / advice so far.
>
> Thanks!
>
> BTW, the other tsc2007 and ads7846 patches could already be merged (if there
> are no more changes needed) since this one only depends on the result of applying
> all others before.
I wonder if input maintainers can already merge the other patches of this patch series?
BR and thanks,
Nikolaus
^ permalink raw reply
* Re: [RFT PATCH] ARM64: dts: meson-gxbb: Add reserved memory zone and usable memory range
From: Heinrich Schuchardt @ 2016-12-12 21:22 UTC (permalink / raw)
To: Neil Armstrong, khilman-rdvid1DuHRBWk0Htik3J/w,
carlo-KA+7E9HrN00dnm+yROfE0A
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161212101801.28491-1-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On 12/12/2016 11:18 AM, Neil Armstrong wrote:
> The Amlogic Meson GXBB secure monitor uses part of the memory space, this
> patch adds these reserved zones and redefines the usable memory range for
> each boards.
>
> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 21 +++++++++++++++++++++
> .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts | 2 +-
> .../boot/dts/amlogic/meson-gxl-nexbox-a95x.dts | 2 +-
> .../arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +-
> 11 files changed, 31 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
> index 7a078be..ac40b2d 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
> @@ -56,7 +56,7 @@
>
> memory@0 {
> device_type = "memory";
> - reg = <0x0 0x0 0x0 0x80000000>;
> + reg = <0x0 0x1000000 0x0 0x7f000000>;
> };
>
> vddio_boot: regulator-vddio_boot {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index fc033c0..e085588 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -55,6 +55,27 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secos: secos {
> + reg = <0x0 0x05300000 0x0 0x2000000>;
> + no-map;
> + };
Hello Neil,
In
https://github.com/hardkernel/linux/blob/odroidc2-3.14.y/arch/arm64/boot/dts/meson64_odroidc2.dts
the secos region does not exist. In linux-next I find no reference to
the secos label. Where is the consumer of the region defined?
> +
> + pstore: pstore {
> + reg = <0x0 0x07300000 0x0 0x100000>;
> + no-map;
> + };
In
https://github.com/hardkernel/linux/blob/odroidc2-3.14.y/arch/arm64/boot/dts/amlogic/gxbb_skt.dts
and other files pstore uses a different position
(reg = <0x0 0x20000000 0x0 0x100000>;).
Why are we moving this?
Should this region be marked
compatible = "ramoops"; ?
Cf. Documentation/devicetree/bindings/reserved-memory/ramoops.txt.
It would be nice if you could add a short description of each reserved
area to the commit message.
Regards
Heinrich Schuchardt
> +
> + secmon: secmon {
> + reg = <0x0 0x10000000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +
> cpus {
> #address-cells = <0x2>;
> #size-cells = <0x0>;
--
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^ permalink raw reply
* Re: [PATCH v2 2/2] eeprom: Add IDT 89HPESx driver bindings file
From: Rob Herring @ 2016-12-12 23:04 UTC (permalink / raw)
To: Serge Semin
Cc: Greg Kroah-Hartman, Srinivas Kandagatla, Andrew Lunn,
Mark Rutland, Sergey.Semin-vHJ8rsvMqnUPfZBKTuL5GA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161205190456.GA25116@mobilestation>
On Mon, Dec 5, 2016 at 1:04 PM, Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Mon, Dec 05, 2016 at 11:27:07AM -0600, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> On Mon, Dec 5, 2016 at 9:25 AM, Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> > On Mon, Dec 05, 2016 at 08:46:21AM -0600, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> >> On Tue, Nov 29, 2016 at 01:38:21AM +0300, Serge Semin wrote:
>> >> > See cover-letter for changelog
>> >> >
>> >> > Signed-off-by: Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> >> >
>> >> > ---
>> >> > .../devicetree/bindings/misc/idt_89hpesx.txt | 41 ++++++++++++++++++++++
>> >>
>> >> There's not a better location for this? I can't tell because you don't
>> >> describe what the device is.
>> >>
>> >
>> > The device is PCIe-switch EEPROM driver with additional debug-interface to
>> > access the switch CSRs. EEPROM is accesses via a separate i2c-slave
>> > interface of the switch.
>> >
>> > There might be another place to put the binding file in. There is a special
>> > location for EEPROM drivers bindings - Documentation/devicetree/bindings/eeprom/ .
>> > But as far as I understood from the files put in there, it's intended for
>> > pure EEPROM drivers only. On the other hand the directory I've chosen:
>> > Documentation/devicetree/bindings/misc/
>> > mostly intended for some unusual devices. My device isn't usual, since it
>> > has CSRs debug-interface as well. Additionally I've found
>> > eeprom-93xx46.txt binding file there, which describes EEPROM bindings.
>> >
>> > Anyway if you find the file should be placed in
>> > Documentation/devicetree/bindings/eeprom/ instead, I'll move it, it's not
>> > that a big problem.
>> >
>
> What about this comment? Shall the file be left at the path I placed it?
>
>> >> > 1 file changed, 41 insertions(+)
>> >> > create mode 100644 Documentation/devicetree/bindings/misc/idt_89hpesx.txt
>> >> >
>> >> > diff --git a/Documentation/devicetree/bindings/misc/idt_89hpesx.txt b/Documentation/devicetree/bindings/misc/idt_89hpesx.txt
>> >> > index 0000000..469cc93
>> >> > --- /dev/null
>> >> > +++ b/Documentation/devicetree/bindings/misc/idt_89hpesx.txt
>> >> > @@ -0,0 +1,41 @@
>> >> > +EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
>> >> > +
>> >> > +Required properties:
>> >> > + - compatible : should be "<manufacturer>,<type>"
>> >> > + Basically there is only one manufacturer: idt, but some
>> >> > + compatible devices may be produced in future. Following devices
>> >> > + are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2,
>> >> > + 89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2,
>> >> > + 89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2;
>> >> > + 89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a;
>> >> > + 89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2,
>> >> > + 89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2,
>> >> > + 89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2,
>> >> > + 89hpes64h16ag2;
>> >> > + 89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2,
>> >> > + 89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5,
>> >> > + 89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2,
>> >> > + 89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2,
>> >> > + 89hpes48t12, 89hpes48t12g2.
>> >> > + Current implementation of the driver doesn't have any device-
>> >>
>> >> Driver capabilties are irrelevant to bindings.
>> >>
>> >
>> > Why? I've told in the comment, that the devices actually differ by the CSRs
>> > map. Even though it's not reflected in the code at the moment, the CSRs
>> > read/write restrictions can be added by some concerned programmer in
>> > future. But If I left something like "compatible : idt,89hpesx" device
>> > only, it will be problematic to add that functionality.
>>
>> Bindings describe the h/w, not what the Linux, FreeBSD, etc. driver
>> does. You don't want to be changing the binding doc when the driver
>> changes.
>>
>> > Howbeit If you think it's not necessary and "compatible = idt,89hpesx" is
>> > ok, it's perfectly fine for me to make it this way. The property will be
>> > even simpler, than current approach.
>>
>> NO! That's not at all what I'm suggesting. Specific compatible strings
>> are the right way to go for the reasons you give. You just don't need
>> to state why here (because it is true for all bindings).
>>
>
> Oh, I just misunderstood what you said. I'll discard the comment.
>
>> >> > + specific functionalities. But since each of them differs
>> >> > + by registers mapping, CSRs read/write restrictions can be
>> >> > + added in future.
>> >> > + - reg : I2C address of the IDT 89HPES device.
>> >> > +
>> >> > +Optional properties:
>> >> > + - read-only : Parameterless property disables writes to the EEPROM
>> >> > + - idt,eesize : Size of EEPROM device connected to IDT 89HPES i2c-master bus
>> >> > + (default value is 4096 bytes if option isn't specified)
>> >> > + - idt,eeaddr : Custom address of EEPROM device
>> >> > + (If not specified IDT 89HPESx device will try to communicate
>> >> > + with EEPROM sited by default address - 0x50)
>> >>
>> >> Don't we already have standard EEPROM properties that could be used
>> >> here?
>> >>
>> >
>> > If we do, just tell me which one. There are standard options:
>>
>> You can grep thru bindings as easily as I can. I can't do that for
>> everyone's binding.
>>
>
> It won't be necessary due to the next comment.
>
>> > "compatible, reg, pagesize, read-only". There isn't any connected with
>> > EEPROM actual size.
>> > Why so? Because standard EEPROM-drivers determine the device size from the
>> > compatible-string name. Such approach won't work in this case, because
>> > PCIe-switch and it EEPROM are actually two different devices. Look at the
>> > chain of the usual platform board design:
>> > Host <--- i2c ----> i2c-slave iface |PCIe-switch| i2c-master iface <--- i2c ---> EEPROM
>> >
>> > As you cas see the Host reaches EEPROM through the set of PCIe-switch
>> > i2c-interfaces. In order to properly get data from it my driver needs actual
>> > EEPROM size and it address in the i2c-master bus of the PCIe-switch, in
>> > addition to the standard reg-field, which is address of PCIe-switch i2c-slave
>> > interface and read-only parameter if EEPROM-device has got WP pin asserted.
>>
>> Ah, this needs to be much different than I thought. You need to model
>> (i.e. use the same binding) the EEPROM node just like it was directly
>> attached to the host. So this means you need the 2nd i2c bus modeled
>> which means you need the PCIe switch modeled. A rough outline of the
>> nodes would look like this:
>>
>> host-i2c: i2c {
>> compatible ="host-i2c"
>> };
>>
>> pcie {
>> pcie-switch {
>> i2c-bus = <&host-i2c>;
>> i2c-bus {
>> eeprom@50 {
>> };
>> };
>> };
>> };
>>
>> So this models the PCIe switch as a PCIe device, it has a phandle back
>> to it's controller since it's not a child of the i2c controller. Then
>> the devices on switches i2c bus are modeled as children of the switch.
>>
>> Alternatively, it could be described all as children of host-i2c node.
>> It's common for i2c devices to have downstream i2c buses. I2C muxes
>> are one example and there are bindings defined for all this. There's
>> also chips like mpu-6050 that have slave buses.
>>
>> Rob
>
> I think I understand what you says. However let me just bring some details
> to make things clear.
>
> First of all the driver doesn't do any PCI-Express-related work. The device
> !IDT PCI Express switch! just has two additional i2c interfaces: i2c-slave
> and i2c-master. As it is obvious from the bus-names i2c-slave is the interface,
> where IDT PCIe-switch device is actually slave. This interface can be reached
> from the host by ordinary i2c buses. i2c-master interface is connected to an
> i2c-bus, where IDT PCIe-switch is single master. This bus can have just one
> EEPROM device to store some initialization data. Host can send some specific
> smbus-packets to i2c-slave interface of IDT PCIe-switch in order to
> preinitialize EEPROM data, connected to i2c-master interface of the device.
>
> Additionally IDT PCIe-switch handles some special smbus packets coming to it
> i2c-slave interface to read/write its internal CSR. This interface can be
> used to debug the device, when there are problems with it usual PCI Express
> related functioning.
>
> So to speak, it wouldn't be good to have PCIe-switch declared in dts as a
> PCI-device, since PCI-bus is actually dynamically populated by PCI-core
> subsystem.
Why not? The DT is just extra data for what is not discoverable. Is
the device actually hotplugable and in a dynamic location/slot? If
not, then describing the device in DT is not uncommon. If it is
hotplugable, you still have same problem of knowing which I2C bus it
is on. Even if you know for your design, generally speaking you may
not know.
> According to what you said and the device/driver design I described, the
> following bindings can be suggested:
>
> i2c0: i2c@FFFF0000 {
> compatible = "vendor,i2c-adapter";
> #address-cells = <1>;
> #size-cells = <0>;
>
> idt_i2c_iface: idt@60 {
> compatible = "idt,89hpes32nt8ag2";
> reg = <0x60>;
> #address-cells = <1>;
> #size-cells = <0>;
>
> eeprom@51 {
> compatible = "at,24c64";
> reg = <0x51>;
> read-only;
> };
> };
> };
>
> Suppose there is some host-i2c adapter like "vendor,i2c-adapter" and
> i2c-slave interface of IDT PCIe-switch is connected to it. In this way
> i2c-slave interface will be visible like ordinary i2c-device with just
> one subnode. This subnode explains the actual EEPROM connected to
> IDT PCIe-switch i2c-master interface.
>
> Does it look acceptable? It seems like your last suggestion. Is it?
That is the 2nd option. My concern is this may work for your immediate
case, but if you started to need to describe the PCIe interface it
would not work. Similarly, we started out describing USB hubs with I2C
interfaces this way and it has proven to be in adequate for some
cases. So we're moving to describing the USB hierarchy in DT. I'm
concerned that while it may work for you, if the PCIe interface has
any dependencies like regulators or something, then you would need to
have a PCIe node.
Rob
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^ permalink raw reply
* Re: [PATCH v4 3/5] i2c: designware: Add slave definitions
From: Rob Herring @ 2016-12-12 23:15 UTC (permalink / raw)
To: Luis de Oliveira
Cc: wsa@the-dreams.de, mark.rutland@arm.com,
jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com,
mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Ramiro.Oliveira@synopsys.com, Joao.Pinto@synopsys.com,
CARLOS.PALMINHA@synopsys.com
In-Reply-To: <BCF0D4927F9C694C9AEA8827D4A9C7C897CE12@de02wembxa.internal.synopsys.com>
On Mon, Dec 12, 2016 at 12:35 PM, Luis de Oliveira
<Luis.Oliveira@synopsys.com> wrote:
> Hi all,
Please don't top post.
>
> The slave address could be set by the I2C slave backend so I can't use it to setup the controller.
> A boolean property was my initial approach then Andy and Wolfram Sang suggested the use of compatible strings and later It was suggested to use a property to select mode but I can do it again if it's the best way.
> Can you please tell me where should it be documented?
bindings/i2c/i2c.txt.
Actually, looking at this some more, we already have a way to describe
the controller being a slave device with the I2C_OWN_SLAVE_ADDRESS
flag in the reg property. We should just need a helper to read reg
property of each child and check for the bit set.
Rob
^ permalink raw reply
* [PATCH resend] ARM: dts: sun8i: Support DTB build for NanoPi M1
From: Milo Kim @ 2016-12-12 23:18 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Milo Kim
The commit 10efbf5f1633 ("ARM: dts: sun8i: Add dts file for NanoPi M1 SBC")
introduced NanoPi M1 board but it's missing in Allwinner H3 DTB build.
Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb..359041f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -845,6 +845,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
+ sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
--
2.9.3
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^ permalink raw reply related
* Re: [PATCH] ARM: dts: sun8i: Support DTB build for NanoPi M1
From: Milo Kim @ 2016-12-12 23:20 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161212154903.wy3vgp3grr3y3bs3@lukather>
On 12/13/2016 12:49 AM, Maxime Ripard wrote:
> Hi,
>
> On Fri, Dec 09, 2016 at 10:47:58AM +0900, Milo Kim wrote:
>> The commit 10efbf5f1633 introduced NanoPi M1 board but it's missing in
>> Allwinner H3 DTB build.
>>
>> Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> checkpatch reports an error on this one (commit format), please fix
> and resend.
Thanks! I need to run the script automatically prior to sending patches.
Best regards,
Milo
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^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: mfd: Remove TPS65217 interrupts
From: Milo Kim @ 2016-12-12 23:24 UTC (permalink / raw)
To: Rob Herring, Arnd Bergmann
Cc: bcousson-rdvid1DuHRBWk0Htik3J/w, Tony Lindgren, Lee Jones,
Sebastian Reichel, Dmitry Torokhov,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161212172511.5nj7whzytpkmrk7z@rob-hp-laptop>
On 12/13/2016 02:25 AM, Rob Herring wrote:
> On Fri, Dec 09, 2016 at 03:28:31PM +0900, Milo Kim wrote:
>> Interrupt numbers are from the datasheet, so no need to keep them in
>> the ABI. Use the number in the DT file.
> I don't see the purpose of ripping this out. The headers have always
> been for convienence, not whether the values come from the datasheet or
> not.
My understanding is it's a same rule as other interrupt controllers.
I'd like to have Arnd's opinion for this.
Best regards,
Milo
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^ permalink raw reply
* Re: [PATCH v4 3/4] mtd: spi-nor: bindings for the Aspeed memory controllers
From: Joel Stanley @ 2016-12-12 23:43 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, David Woodhouse,
Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger,
Cyrille Pitchen, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
Mark Rutland
In-Reply-To: <1481557252-13656-4-git-send-email-clg-Bxea+6Xhats@public.gmane.org>
On Tue, Dec 13, 2016 at 2:40 AM, Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org> wrote:
> Signed-off-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
Acked-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> ---
> .../devicetree/bindings/mtd/aspeed-smc.txt | 51 ++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt
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^ permalink raw reply
* [PATCH v1 07/12] scsi: ufs: add option to change default UFS power management level
From: Subhash Jadavani @ 2016-12-13 0:54 UTC (permalink / raw)
To: vinholikatti-Re5JQEeQqe8AvxtiuMwx3w,
jejb-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
martin.petersen-QHcLZuEGTsvQT0dZR+AlfA
Cc: linux-scsi-u79uwXL29TY76Z2rM5mHXA, Subhash Jadavani, Rob Herring,
Mark Rutland, Hannes Reinecke, Yaniv Gardi, Joao Pinto,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
UFS device and link can be put in multiple different low power modes hence
UFS driver supports multiple different low power modes. By default UFS
driver selects the default (optimal) low power mode (which gives moderate
power savings and have relatively less enter and exit latencies) but
we might have to tune this default power mode for different chipset
platforms to meet the low power requirements/goals. Hence this patch
adds option to change default UFS low power mode (level).
Reviewed-by: Yaniv Gardi <ygardi-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Subhash Jadavani <subhashj-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 ++++++
drivers/scsi/ufs/ufshcd-pltfrm.c | 14 ++++++++
drivers/scsi/ufs/ufshcd.c | 39 ++++++++++++++++++++++
drivers/scsi/ufs/ufshcd.h | 4 +--
4 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
index a99ed55..c3836c5 100644
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -41,6 +41,14 @@ Optional properties:
-lanes-per-direction : number of lanes available per direction - either 1 or 2.
Note that it is assume same number of lanes is used both
directions at once. If not specified, default is 2 lanes per direction.
+- rpm-level : UFS Runtime power management level. Following PM levels are supported:
+ 0 - Both UFS device and Link in active state (Highest power consumption)
+ 1 - UFS device in active state but Link in Hibern8 state
+ 2 - UFS device in Sleep state but Link in active state
+ 3 - UFS device in Sleep state and Link in hibern8 state (default PM level)
+ 4 - UFS device in Power-down state and Link in Hibern8 state
+ 5 - UFS device in Power-down state and Link in OFF state (Lowest power consumption)
+- spm-level : UFS System power management level. Allowed PM levels are same as rpm-level.
Note: If above properties are not defined it can be assumed that the supply
regulators or clocks are always on.
@@ -66,4 +74,6 @@ Example:
freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
phys = <&ufsphy1>;
phy-names = "ufsphy";
+ rpm-level = <3>;
+ spm-level = <5>;
};
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index a72a4ba..896943d 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -223,6 +223,19 @@ static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
return err;
}
+static void ufshcd_parse_pm_levels(struct ufs_hba *hba)
+{
+ struct device *dev = hba->dev;
+ struct device_node *np = dev->of_node;
+
+ if (np) {
+ if (of_property_read_u32(np, "rpm-level", &hba->rpm_lvl))
+ hba->rpm_lvl = -1;
+ if (of_property_read_u32(np, "spm-level", &hba->spm_lvl))
+ hba->spm_lvl = -1;
+ }
+}
+
#ifdef CONFIG_PM
/**
* ufshcd_pltfrm_suspend - suspend power management function
@@ -342,6 +355,7 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
goto dealloc_host;
}
+ ufshcd_parse_pm_levels(hba);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 470ea99..43f9b44 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -191,6 +191,22 @@ enum {
return ufs_pm_lvl_states[lvl].link_state;
}
+static inline enum ufs_pm_level
+ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
+ enum uic_link_state link_state)
+{
+ enum ufs_pm_level lvl;
+
+ for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
+ if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
+ (ufs_pm_lvl_states[lvl].link_state == link_state))
+ return lvl;
+ }
+
+ /* if no match found, return the level 0 */
+ return UFS_PM_LVL_0;
+}
+
static struct ufs_dev_fix ufs_fixups[] = {
/* UFS cards deviations table */
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
@@ -215,6 +231,14 @@ enum {
END_FIX
};
+static inline bool ufshcd_is_valid_pm_lvl(int lvl)
+{
+ if (lvl >= 0 && lvl < ARRAY_SIZE(ufs_pm_lvl_states))
+ return true;
+ else
+ return false;
+}
+
static void ufshcd_tmc_handler(struct ufs_hba *hba);
static void ufshcd_async_scan(void *data, async_cookie_t cookie);
static int ufshcd_reset_and_restore(struct ufs_hba *hba);
@@ -7290,6 +7314,21 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
ufshcd_clkscaling_init_sysfs(hba);
}
+ /*
+ * If rpm_lvl and and spm_lvl are not already set to valid levels,
+ * set the default power management level for UFS runtime and system
+ * suspend. Default power saving mode selected is keeping UFS link in
+ * Hibern8 state and UFS device in sleep.
+ */
+ if (!ufshcd_is_valid_pm_lvl(hba->rpm_lvl))
+ hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
+ UFS_SLEEP_PWR_MODE,
+ UIC_LINK_HIBERN8_STATE);
+ if (!ufshcd_is_valid_pm_lvl(hba->spm_lvl))
+ hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
+ UFS_SLEEP_PWR_MODE,
+ UIC_LINK_HIBERN8_STATE);
+
/* Hold auto suspend until async scan completes */
pm_runtime_get_sync(dev);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 787323b..97fbe4a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -432,9 +432,9 @@ struct ufs_hba {
enum ufs_dev_pwr_mode curr_dev_pwr_mode;
enum uic_link_state uic_link_state;
/* Desired UFS power management level during runtime PM */
- enum ufs_pm_level rpm_lvl;
+ int rpm_lvl;
/* Desired UFS power management level during system PM */
- enum ufs_pm_level spm_lvl;
+ int spm_lvl;
struct device_attribute rpm_lvl_attr;
struct device_attribute spm_lvl_attr;
int pm_op_in_progress;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply related
* Re: [PATCH v3 2/2] mtd: spi-nor: add rockchip serial flash controller driver
From: Shawn Lin @ 2016-12-13 1:24 UTC (permalink / raw)
To: Cyrille Pitchen, Marek Vasut, David Woodhouse, Brian Norris
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner
In-Reply-To: <8fae0968-5e3d-2454-c79c-599bc55ac0e5-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
On 2016/12/6 23:44, Cyrille Pitchen wrote:
> Hi all,
>
> Le 06/12/2016 à 04:08, Marek Vasut a écrit :
>> On 12/06/2016 03:56 AM, Shawn Lin wrote:
>>
>> [...]
>>
>>>>> +static inline void rockchip_sfc_setup_transfer(struct spi_nor *nor,
>>>>> + loff_t from_to,
>>>>> + size_t len, u8 op_type)
>>>>> +{
>>>>> + struct rockchip_sfc_chip_priv *priv = nor->priv;
>>>>> + struct rockchip_sfc *sfc = priv->sfc;
>>>>> + u32 reg;
>>>>> + u8 if_type = 0;
>>>>> +
>>>>> + if_type = get_if_type(sfc, nor->flash_read);
>>>>> + writel_relaxed((if_type << SFC_CTRL_DATA_BITS_SHIFT) |
>>>>> + (if_type << SFC_CTRL_ADDR_BITS_SHIFT) |
>>>>> + (if_type << SFC_CTRL_CMD_BITS_SHIFT) |
>>>>
>>>> Hm, looking at this, does the controller only support n-n-n mode (1-1-1,
>>>> 2-2-2, 4-4-4) ? Or why don't you allow 1-1-n/1-n-n/2-n-n ?
>>>
>>> No, it also could support 1-1-n, etc.
>>> By looking at the cadence-quadspi.c, it only allows
>>> CQSPI_INST_TYPE_SINGLE for f_pdata->addr_width and f_pdata->inst_width,
>>> so finally it only supports 1-1-1, 1-1-2, 1-1-4?
>>>
>>>> I would like to hear some input from Cyrille on this one.
>>
>> The CQSPI driver indeed does only 1-1-x read thus far.
>> I am not sure whether support for the other modes in the SPI NOR
>> subsystem landed already, which is why I'd like to hear from
>> Cyrille here.
>>
>> [...]
>>
>
> No, the support of SPI protocols other than 1-1-z has not been merged yet
> into the spi-nor subsystem. I've sent it as part of the SFDP series, since
> then I've been waiting for more reviews and approvals before merging it
> because I don't want to force anything and wait to avoid regression.
>
> Recently I was thinking about splitting the series into smaller and almost
> independent topics. For instance the Macronix patch to improve the
> management of the Quad Enable bit is a stand alone patch.
>
> Then the patch about improving support of > 128Mbit memory by using the
> dedicated 4-byte instruction set only depends on the patch renaming some
> SPINOR_OP_* macros to unify the use of the "_4B" suffix. Those two patches
> solve the issue of bootloaders which fail to read from SPI flash when the
> memory has entered its statefull 4-byte address mode.
>
> Next, there are 3 patches to add support to SPI protocols 1-y-z. I guess
> they are the patches your are talking about. Those patches prepares the
> move to the SFDP support but actually they can be also be used as is just
> to use SPI 1-y-z protocol without talking about SFDP.
>
> Finally, the last patches introduce the SFDP support. As I said, there are
> not mandatory for your use case if you only want to test SPI protocols such
> as 1-4-4.
>
> In your case, you might be interested in reviewing/testing:
>
Thanks for sharing these patches and I will test them. :)
> [v4, 4/8] mtd: spi-nor: add support of SPI protocols like SPI 1-2-2 and
> SPI-1-4-4
> http://patchwork.ozlabs.org/patch/697268/
> This is the main patch.
>
> [v4, 5/8] mtd: spi-nor: remove unused set_quad_mode() function
> http://patchwork.ozlabs.org/patch/697269/
> Only small cleanup, please read the commit message for more explination
>
> [v4, 6/8] mtd: m25p80: add support of dual and quad spi protocols to all
> commands
> http://patchwork.ozlabs.org/patch/697270/
> This one is not need when testing with this rockchip serial flash
> controller driver as it directly calls spi_nor_scan() from
> rockchip_sfc_register.
>
> Please note there might be a small dependence to the SPINOR_OP_* macro
> renaming patch:
> [v4, 2/8] mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op
> codes
> http://patchwork.ozlabs.org/patch/697266/
> Indeed this patch introduces in spi-nor.h the SPINOR_OP_READ_1_2_2 and
> SPINOR_OP_READ_1_4_4 macros and their associated op codes.
>
> About the support of SPI 2-2-2 and SPI 4-4-4, I also have patches to add
> support to those two protocols however I decided not to submit them for now
> for many reasons. First, the series is already long and hard enough to
> review. Secondly, in most cases the performance increase between SPI 1-4-4
> and SPI 4-4-4 isn't worth it when you read 512 byte pages or 64KB sectors.
>
> I think it was a mistake to send all those patches in a single big series
> since actually most of them have nothing to do with SFDP. They just prepare
> the transition. I understand big series might scare people and discourage
> them from reviewing or testing.
>
> However, if you are interested in some of those features, I think I should
> send the patches step by step.
>
> Best regards,
>
> Cyrille
>
>>>>> +#ifdef CONFIG_PM
>>>>> +int rockchip_sfc_runtime_suspend(struct device *dev)
>>>>> +{
>>>>> + struct rockchip_sfc *sfc = dev_get_drvdata(dev);
>>>>> +
>>>>> + clk_disable_unprepare(sfc->hclk);
>>>>> + return 0;
>>>>> +}
>>>>
>>>> Was the suspend ever really tested with this block ? Is disabling clock
>>>> really enough ?
>>>
>>> It was tested and we could do more, for instance power off the genpd,
>>> but disabling clcok should be enough.
>>
>> What about putting the controller into some reset state , is that possible?
>>
>>>>> +int rockchip_sfc_runtime_resume(struct device *dev)
>>>>> +{
>>>>> + struct rockchip_sfc *sfc = dev_get_drvdata(dev);
>>>>> +
>>>>> + clk_prepare_enable(sfc->hclk);
>>>>> + return 0;
>>>>> +}
>>>>> +#endif /* CONFIG_PM */
>>>>
>>>> [...]
>>>>
>>>
>>>
>>
>>
>
>
>
>
--
Best Regards
Shawn Lin
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^ permalink raw reply
* [PATCH v2 0/2] Add MediaTek crypto accelerator driver
From: Ryder Lee @ 2016-12-13 1:31 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Matthias Brugger
Cc: devicetree, linux-mediatek, linux-kernel, linux-crypto,
linux-arm-kernel, Sean Wang, Roy Luo, Ryder Lee
Hello,
This adds support for the MediaTek hardware accelerator on
some SoCs.
This driver currently implement:
- SHA1 and SHA2 family(HMAC) hash algorithms.
- AES block cipher in CBC/ECB mode with 128/196/256 bits keys.
Changes since v2:
- use byteorder conversion macros and type identifiers for descriptors
- revise register definition macros to make it more clear
- revise DT compatiable string
Changes since v1:
- remove EXPORT_SYMBOL
- remove unused PRNG setting
- sort headers in alphabetical order
- add a definition for IRQ unmber
- replace ambiguous definition
- add more annotation and function comment
- add COMPILE_TEST in Kconfig
Ryder Lee (2):
Add crypto driver support for some MediaTek chips
crypto: mediatek - add DT bindings documentation
.../devicetree/bindings/crypto/mediatek-crypto.txt | 32 +
drivers/crypto/Kconfig | 17 +
drivers/crypto/Makefile | 1 +
drivers/crypto/mediatek/Makefile | 2 +
drivers/crypto/mediatek/mtk-aes.c | 766 +++++++++++
drivers/crypto/mediatek/mtk-platform.c | 604 ++++++++
drivers/crypto/mediatek/mtk-platform.h | 238 ++++
drivers/crypto/mediatek/mtk-regs.h | 194 +++
drivers/crypto/mediatek/mtk-sha.c | 1437 ++++++++++++++++++++
9 files changed, 3291 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
create mode 100644 drivers/crypto/mediatek/Makefile
create mode 100644 drivers/crypto/mediatek/mtk-aes.c
create mode 100644 drivers/crypto/mediatek/mtk-platform.c
create mode 100644 drivers/crypto/mediatek/mtk-platform.h
create mode 100644 drivers/crypto/mediatek/mtk-regs.h
create mode 100644 drivers/crypto/mediatek/mtk-sha.c
--
1.9.1
^ permalink raw reply
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