* [PATCH v2 2/2] ASoC: cs43130: Add devicetree bindings for CS43130
From: Li Xu @ 2016-12-12 20:17 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
In-Reply-To: <1481573851-1421-1-git-send-email-li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
Add devicetree bindings documentation file for Cirrus
Logic CS43130 codec.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/sound/cs43130.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/cs43130.txt
diff --git a/Documentation/devicetree/bindings/sound/cs43130.txt b/Documentation/devicetree/bindings/sound/cs43130.txt
new file mode 100644
index 0000000..1af6b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs43130.txt
@@ -0,0 +1,41 @@
+CS43130 DAC
+
+Required properties:
+
+ - compatible : "cirrus,cs43130"
+
+ - reg : the I2C address of the device for I2C
+
+ - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
+ power supplies for the device, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+
+Optional properties:
+
+ - reset-gpios : Active low GPIO used to reset the device
+
+ - cirrus,xtal-ibias:
+ When external MCLK is generated by external crystal
+ oscillator, CS43130 can be used to provide bias current
+ for external crystal. Amount of bias current sent is
+ set as:
+ 1 = 7.5uA
+ 2 = 12.5uA
+ 3 = 15uA
+
+Example:
+
+cs43130: audio-codec@30 {
+ compatible = "cirrus,cs43130";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio 54 1>;
+ VA-supply = <&dummy_vreg>;
+ VP-supply = <&dummy_vreg>;
+ VL-supply = <&dummy_vreg>;
+ VCP-supply = <&dummy_vreg>;
+ VD-supply = <&dummy_vreg>;
+ cirrus,xtal-ibias = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <55 8>;
+};
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v2 1/2] ASoC: Add support for CS43130 codec
From: Li Xu @ 2016-12-12 20:17 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
Add support for Cirrus Logic CS43130 codec.
Support I2C control and I2S audio playback.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
sound/soc/codecs/Kconfig | 6 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/cs43130.c | 1164 ++++++++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/cs43130.h | 268 ++++++++++
4 files changed, 1440 insertions(+)
create mode 100644 sound/soc/codecs/cs43130.c
create mode 100644 sound/soc/codecs/cs43130.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 9e1718a..d6ede2b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS4271_I2C if I2C
select SND_SOC_CS4271_SPI if SPI_MASTER
select SND_SOC_CS42XX8_I2C if I2C
+ select SND_SOC_CS43130 if I2C
select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
@@ -473,6 +474,11 @@ config SND_SOC_CS42XX8_I2C
select SND_SOC_CS42XX8
select REGMAP_I2C
+# Cirrus Logic CS43130 HiFi DAC
+config SND_SOC_CS43130
+ tristate "Cirrus Logic CS43130 CODEC"
+ depends on I2C
+
# Cirrus Logic CS4349 HiFi DAC
config SND_SOC_CS4349
tristate "Cirrus Logic CS4349 CODEC"
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 7e1dad7..2f15228 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,6 +52,7 @@ snd-soc-cs4271-i2c-objs := cs4271-i2c.o
snd-soc-cs4271-spi-objs := cs4271-spi.o
snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
+snd-soc-cs43130-objs := cs43130.o
snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
@@ -281,6 +282,7 @@ obj-$(CONFIG_SND_SOC_CS4271_I2C) += snd-soc-cs4271-i2c.o
obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o
obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
+obj-$(CONFIG_SND_SOC_CS43130) += snd-soc-cs43130.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
diff --git a/sound/soc/codecs/cs43130.c b/sound/soc/codecs/cs43130.c
new file mode 100644
index 0000000..79e4d2a
--- /dev/null
+++ b/sound/soc/codecs/cs43130.c
@@ -0,0 +1,1164 @@
+/*
+ * cs43130.c -- CS43130 ALSA Soc Audio driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Authors: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/of_irq.h>
+
+#include "cs43130.h"
+
+
+static const struct reg_default cs43130_reg_defaults[] = {
+ { CS43130_SYS_CLK_CTL_1, 0x06 },
+ { CS43130_SP_SRATE, 0x01 },
+ { CS43130_SP_BITSIZE, 0x05 },
+ { CS43130_PAD_INT_CFG, 0x03 },
+ { CS43130_PWDN_CTL, 0xFE },
+ { CS43130_CRYSTAL_SET, 0x04 },
+ { CS43130_PLL_SET_1, 0x00 },
+ { CS43130_PLL_SET_2, 0x00 },
+ { CS43130_PLL_SET_3, 0x00 },
+ { CS43130_PLL_SET_4, 0x00 },
+ { CS43130_PLL_SET_5, 0x40 },
+ { CS43130_PLL_SET_6, 0x10 },
+ { CS43130_PLL_SET_7, 0x80 },
+ { CS43130_PLL_SET_8, 0x03 },
+ { CS43130_PLL_SET_9, 0x02 },
+ { CS43130_PLL_SET_10, 0x02 },
+ { CS43130_CLKOUT_CTL, 0x00 },
+ { CS43130_ASP_NUM_1, 0x01 },
+ { CS43130_ASP_NUM_2, 0x00 },
+ { CS43130_ASP_DENOM_1, 0x08 },
+ { CS43130_ASP_DENOM_2, 0x00 },
+ { CS43130_ASP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_ASP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_ASP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_ASP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_ASP_CLOCK_CONF, 0x0C },
+ { CS43130_ASP_FRAME_CONF, 0x0A },
+ { CS43130_XSP_NUM_1, 0x01 },
+ { CS43130_XSP_NUM_2, 0x00 },
+ { CS43130_XSP_DENOM_1, 0x02 },
+ { CS43130_XSP_DENOM_2, 0x00 },
+ { CS43130_XSP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_XSP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_XSP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_XSP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_XSP_CLOCK_CONF, 0x0C },
+ { CS43130_XSP_FRAME_CONF, 0x0A },
+ { CS43130_ASP_CH_1_LOC, 0x00 },
+ { CS43130_ASP_CH_2_LOC, 0x00 },
+ { CS43130_ASP_CH_1_SZ_EN, 0x06 },
+ { CS43130_ASP_CH_2_SZ_EN, 0x0E },
+ { CS43130_XSP_CH_1_LOC, 0x00 },
+ { CS43130_XSP_CH_2_LOC, 0x00 },
+ { CS43130_XSP_CH_1_SZ_EN, 0x06 },
+ { CS43130_XSP_CH_2_SZ_EN, 0x0E },
+ { CS43130_DSD_VOL_B, 0x78 },
+ { CS43130_DSD_VOL_A, 0x78 },
+ { CS43130_DSD_PATH_CTL_1, 0xA8 },
+ { CS43130_DSD_INT_CFG, 0x00 },
+ { CS43130_DSD_PATH_CTL_2, 0x00 },
+ { CS43130_DSD_PCM_MIX_CTL, 0x00 },
+ { CS43130_DSD_PATH_CTL_3, 0x40 },
+ { CS43130_HP_OUT_CTL_1, 0x30 },
+ { CS43130_PCM_FILT_OPT, 0x02 },
+ { CS43130_PCM_VOL_B, 0x78 },
+ { CS43130_PCM_VOL_A, 0x78 },
+ { CS43130_PCM_PATH_CTL_1, 0xA8 },
+ { CS43130_PCM_PATH_CTL_2, 0x00 },
+ { CS43130_CLASS_H_CTL, 0x1E },
+ { CS43130_HP_DETECT, 0x04 },
+ { CS43130_HP_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_2, 0x00 },
+ { CS43130_INT_MASK_1, 0xFF },
+ { CS43130_INT_MASK_2, 0xFF },
+ { CS43130_INT_MASK_3, 0xFF },
+ { CS43130_INT_MASK_4, 0xFF },
+ { CS43130_INT_MASK_5, 0xFF },
+};
+
+static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
+ case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
+ case CS43130_DXD1:
+ case CS43130_PWDN_CTL:
+ case CS43130_DXD2:
+ case CS43130_CRYSTAL_SET:
+ case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
+ case CS43130_PLL_SET_6:
+ case CS43130_PLL_SET_7:
+ case CS43130_PLL_SET_8:
+ case CS43130_PLL_SET_9:
+ case CS43130_PLL_SET_10:
+ case CS43130_CLKOUT_CTL:
+ case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
+ case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
+ case CS43130_ASP_CH_1_LOC:
+ case CS43130_ASP_CH_2_LOC:
+ case CS43130_ASP_CH_1_SZ_EN:
+ case CS43130_ASP_CH_2_SZ_EN:
+ case CS43130_XSP_CH_1_LOC:
+ case CS43130_XSP_CH_2_LOC:
+ case CS43130_XSP_CH_1_SZ_EN:
+ case CS43130_XSP_CH_2_SZ_EN:
+ case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
+ case CS43130_HP_OUT_CTL_1:
+ case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
+ case CS43130_CLASS_H_CTL:
+ case CS43130_HP_DETECT:
+ case CS43130_HP_STATUS:
+ case CS43130_HP_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_2:
+ case CS43130_HP_DC_STAT_1:
+ case CS43130_HP_DC_STAT_2:
+ case CS43130_HP_AC_STAT_1:
+ case CS43130_HP_AC_STAT_2:
+ case CS43130_HP_LOAD_STAT:
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_precious_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+struct cs43130_pll_params {
+ u32 pll_in;
+ u8 mclk_int;
+ u8 sclk_prediv;
+ u8 pll_div_int;
+ u32 pll_div_frac;
+ u8 pll_mode;
+ u8 pll_divout;
+ u32 pll_out;
+ u8 pll_cal_ratio;
+};
+
+static const struct cs43130_pll_params pll_ratio_table[] = {
+ { 9600000, 1, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151 },
+ { 9600000, 0, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164 },
+
+ { 11289600, 1, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128 },
+ { 11289600, 0, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139 },
+
+ { 12000000, 1, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 12000000, 0, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 12288000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 12288000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 13000000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 13000000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 19200000, 1, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 19200000, 0, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+
+ { 22579200, 1, 0, 0, 0, 0, 0, 22579200, 0 },
+ { 22579200, 0, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139 },
+
+ { 24000000, 1, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 24000000, 0, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 24576000, 1, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 128 },
+ { 24576000, 0, 0, 0, 0, 0, 0, 24576000, 0 },
+
+ { 26000000, 1, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 26000000, 0, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+};
+
+static int cs43130_pll_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int i;
+
+ dev_dbg(codec->dev, "%s: cs43130->mclk = %d, cs43130->pll_out = %d",
+ __func__, cs43130->mclk, cs43130->pll_out);
+ for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
+ if (pll_ratio_table[i].pll_in == cs43130->mclk &&
+ pll_ratio_table[i].pll_out == cs43130->pll_out) {
+
+ cs43130->mclk_int = pll_ratio_table[i].mclk_int;
+
+ if (pll_ratio_table[i].pll_cal_ratio == 0) {
+ if (cs43130->xtal_ibias > 0) {
+ usleep_range(1000, 1050);
+ /*PDN_XTAL = 0,enable*/
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK,
+ 0 << CS43130_PDN_XTAL_SHIFT);
+ }
+
+ /* PLL_START = 0, disable PLL_START */
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK,
+ 0 << CS43130_PLL_START_MASK);
+
+ cs43130->pll_bypass = true;
+ return 0;
+ }
+
+ /* PDN_PLL= 0,enable */
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK,
+ 0 << CS43130_PDN_PLL_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
+ CS43130_PLL_REF_PREDIV_MASK,
+ pll_ratio_table[i].sclk_prediv);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
+ pll_ratio_table[i].pll_div_int);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_2,
+ pll_ratio_table[i].pll_div_frac &
+ CS43130_7_0_MASK);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_3,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_15_8_MASK) >> 8);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_4,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_23_16_MASK) >> 16);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
+ CS43130_PLL_MODE_MASK,
+ pll_ratio_table[i].pll_mode
+ << CS43130_PLL_MODE_SHIFT);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_6,
+ pll_ratio_table[i].pll_divout);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
+ pll_ratio_table[i].pll_cal_ratio);
+
+ /* PLL_START = 1, enable PLL_START */
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK, CS43130_PLL_START_MASK);
+ cs43130->pll_bypass = false;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int cs43130_format_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ int period_size = 0;
+ int pulse_width = 0;
+ int asp_fsd;
+ int asp_stp;
+ int bick_inv;
+ int asp_m = 0;
+ int asp_sprate = 0;
+ int ret = 0;
+ unsigned int bitwidth_sclk = (cs43130->sclk / cs43130->fs) / 2;
+ unsigned int bitwidth_dai = (cs43130->dai_bit + 1) * 8;
+
+ if (cs43130->fs) {
+ if (bitwidth_sclk < bitwidth_dai) {
+ dev_err(codec->dev, "Format not supported\n");
+ return -EINVAL;
+ }
+ period_size = cs43130->sclk / cs43130->fs;
+ pulse_width = period_size/2;
+
+ if (cs43130->sclk != 0)
+ asp_m = cs43130->pll_out / cs43130->sclk;
+ }
+ dev_dbg(codec->dev, "%s: cs43130->sclk = %d, cs43130->fs = %d, cs43130->dai_bit = %d",
+ __func__, cs43130->sclk, cs43130->fs, cs43130->dai_bit);
+ dev_dbg(codec->dev, "%s: period_size = %d, pulse_width = %d, asp_m = %d",
+ __func__, period_size, pulse_width, asp_m);
+
+ if (cs43130->dai_format) {
+ /*MSB*/
+ bick_inv = 0;
+ asp_fsd = 0;
+ asp_stp = 1;
+
+ } else {
+ /*I2S*/
+ bick_inv = 1;
+ asp_fsd = 2; /* one bick delay */
+ asp_stp = 0;
+ }
+ dev_dbg(codec->dev,
+ "%s: cs43130->dai_format = %d, bick_inv = %d, asp_fsd = %d, asp_stp = %d",
+ __func__, cs43130->dai_format, bick_inv, asp_fsd, asp_stp);
+
+ switch (cs43130->fs) {
+ case 32000:
+ asp_sprate = CS43130_ASP_SPRATE_32K;
+ break;
+ case 44100:
+ asp_sprate = CS43130_ASP_SPRATE_44_1K;
+ break;
+ case 48000:
+ asp_sprate = CS43130_ASP_SPRATE_48K;
+ break;
+ case 88200:
+ asp_sprate = CS43130_ASP_SPRATE_88_2K;
+ break;
+ case 96000:
+ asp_sprate = CS43130_ASP_SPRATE_96K;
+ break;
+ case 176400:
+ asp_sprate = CS43130_ASP_SPRATE_176_4K;
+ break;
+ case 192000:
+ asp_sprate = CS43130_ASP_SPRATE_192K;
+ break;
+ case 352800:
+ asp_sprate = CS43130_ASP_SPRATE_352_8K;
+ break;
+ case 384000:
+ asp_sprate = CS43130_ASP_SPRATE_384K;
+ break;
+ default:
+ dev_err(codec->dev, "sample rate(%d) not supported\n",
+ cs43130->fs);
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: asp_sprate = %d, cs43130->asp_size = %d",
+ __func__, asp_sprate, cs43130->asp_size);
+
+ /* ASP_SPRATE = fs*/
+ regmap_write(cs43130->regmap, CS43130_SP_SRATE, asp_sprate);
+ /*ASP_SPSIZE*/
+ regmap_update_bits(cs43130->regmap, CS43130_SP_BITSIZE,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->asp_size);
+
+
+ /* Set up slave mode */
+ /*BICK = ASP_N/ASP_M * PLL_OUT */
+ /* ASP_N = 1 */
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, 1);
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, 0);
+
+ /*ASP_M*/
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_1, asp_m & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_2, (asp_m >> 8) & 0x3f);
+
+
+ /* H / L ratio of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
+ (pulse_width-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
+ ((pulse_width-1) >> 8) & 0xff);
+
+ /* the period of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
+ (period_size-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
+ ((period_size-1) >> 8) & 0xff);
+
+ /*resolution*/
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_FSD_MASK, asp_fsd << CS43130_ASP_FSD_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_STP_MASK, asp_stp << CS43130_ASP_STP_SHIFT);
+
+ /* set clk master/slave */
+ dev_dbg(codec->dev, "%s: cs43130->dai_mode = %d",
+ __func__, cs43130->dai_mode);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CLOCK_CONF,
+ CS43130_ASP_MODE_MASK, cs43130->dai_mode << CS43130_ASP_MODE_SHIFT);
+
+ return ret;
+}
+
+static int cs43130_change_clksrc(struct snd_soc_codec *codec,
+ enum cs43130_mclk_src_sel src)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_SRC_SEL_MASK, src << CS43130_MCLK_SRC_SEL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_INT_MASK, cs43130->mclk_int << CS43130_MCLK_INT_SHIFT);
+
+ usleep_range(150, 200);
+
+ return ret;
+}
+
+static int cs43130_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ unsigned int bitwidth;
+ int ret = 0;
+
+ cs43130->fs = params_rate(params);
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_8;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_32;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_16;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_24;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_24;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_16;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_32;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_8;
+ break;
+ default:
+ dev_err(codec->dev, "Format(%d) not supported",
+ params_format(params));
+ return -EINVAL;
+ }
+
+ bitwidth = (cs43130->dai_bit+1)*8;
+ dev_dbg(codec->dev, "(data bit)%d: (rate)%d",
+ bitwidth, cs43130->fs);
+
+ ret = cs43130_format_config(codec);
+ return ret;
+}
+
+static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
+
+static const struct snd_kcontrol_new cs43130_snd_controls[] = {
+ SOC_DOUBLE_R_TLV("Master Playback Volume",
+ CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
+ pcm_vol_tlv),
+ SOC_SINGLE("Swap L/R", CS43130_PCM_PATH_CTL_2, 1, 1, 0),
+ SOC_SINGLE("Copy L/R", CS43130_PCM_PATH_CTL_2, 0, 1, 0),
+};
+
+static int cs43130_aspin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (cs43130->pll_bypass)
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
+ else
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
+
+ usleep_range(10000, 10050);
+ /* ASP_3ST = 0 in master mode */
+ if (cs43130->dai_mode)
+ regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
+ 0x01, 0x00);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_CLKOUT_MASK, 0
+ << CS43130_PDN_CLKOUT_SHIFT);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ break;
+ default:
+ dev_err(codec->dev, "Invalid ASPOUT event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_RCO);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK, 1
+ << CS43130_PDN_XTAL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK, 1
+ << CS43130_PDN_PLL_SHIFT);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid DAC event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 0 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x00);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x01);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 1 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid HPIN event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget cs43130_dapm_widgets[] = {
+
+ SND_SOC_DAPM_OUTPUT("HPOUTA"),
+ SND_SOC_DAPM_OUTPUT("HPOUTB"),
+
+ SND_SOC_DAPM_AIF_IN_E("ASPIN", NULL, 0, CS43130_PWDN_CTL,
+ CS43130_PDN_ASP_SHIFT, 1, cs43130_aspin_event,
+ (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
+
+ SND_SOC_DAPM_DAC_E("HiFi DAC",
+ NULL, CS43130_PWDN_CTL, CS43130_PDN_HP_SHIFT, 1,
+ cs43130_dac_event,
+ (SND_SOC_DAPM_PRE_PMD)
+ ),
+
+ SND_SOC_DAPM_LINE("Analog Playback", cs43130_hpin_event),
+};
+
+static const struct snd_soc_dapm_route cs43130_routes[] = {
+ {"ASPIN", NULL, "DAC Playback"},
+ {"HiFi DAC", NULL, "ASPIN"},
+
+ {"HPOUTA", NULL, "HiFi DAC"},
+ {"HPOUTB", NULL, "HiFi DAC"},
+ {"HPOUTA", NULL, "Analog Playback"},
+ {"HPOUTB", NULL, "Analog Playback"},
+};
+
+static const unsigned int cs43130_src_rates[] = {
+ 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
+};
+
+static const struct snd_pcm_hw_constraint_list cs43130_constraints = {
+ .count = ARRAY_SIZE(cs43130_src_rates),
+ .list = cs43130_src_rates,
+};
+
+static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, &cs43130_constraints);
+ return 0;
+}
+
+static int cs43130_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ cs43130->dai_mode = CS43130_SLAVE_MODE;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ cs43130->dai_mode = CS43130_MASTER_MODE;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported i2s master mode\n");
+ return -EINVAL;
+ }
+
+ /* interface format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ cs43130->dai_format = 0;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ cs43130->dai_format = 1;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio format except I2S and MSB\n");
+ return -EINVAL;
+ }
+
+ /* BICK/LRCK pority */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = true;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = true;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio polarity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+static int cs43130_set_mute(struct snd_soc_dai *dai, int mute)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int ret = 0;
+ unsigned int reg;
+ u8 mute_reg;
+
+ regmap_read(cs43130->regmap, CS43130_PCM_PATH_CTL_1, ®);
+ mute_reg = reg & 0xfc;
+ if (mute)
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
+ mute_reg | 0x03);
+ else
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1, mute_reg);
+
+ return ret;
+}
+
+static int cs43130_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+
+ switch (div_id) {
+ case CS43130_AIF_BICK_RATE:
+ cs43130->bick = div;
+ break;
+ default:
+ dev_err(codec->dev,
+ "Unsupported divide value: div_id = %d", div_id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
+ unsigned int freq_in, unsigned int freq_out)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ if (freq_in < 9600000 || freq_in > 26000000) {
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_in) {
+ case 9600000:
+ case 11289600:
+ case 12000000:
+ case 12288000:
+ case 13000000:
+ case 19200000:
+ case 22579200:
+ case 24000000:
+ case 24576000:
+ case 26000000:
+ cs43130->mclk = freq_in;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_out) {
+ case 22579200:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 1;
+ break;
+ case 24576000:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 0;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll output reference clock:%d\n",
+ freq_out);
+ return -EINVAL;
+ }
+
+ ret = cs43130_pll_config(codec);
+ dev_dbg(codec->dev, "%s: cs43130->pll_bypass = %d",
+ __func__, cs43130->pll_bypass);
+ return ret;
+}
+
+static int cs43130_dai_set_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, freq = %d, dir = %d",
+ __func__, clk_id, freq, dir);
+ cs43130->sclk = freq;
+ return 0;
+}
+
+static const struct snd_soc_dai_ops cs43130_dai_ops = {
+ .startup = cs43130_pcm_startup,
+ .hw_params = cs43130_pcm_hw_params,
+ .set_sysclk = cs43130_dai_set_sysclk,
+ .set_fmt = cs43130_set_dai_fmt,
+ .digital_mute = cs43130_set_mute,
+ .set_clkdiv = cs43130_set_clkdiv,
+};
+
+static struct snd_soc_dai_driver cs43130_dai[] = {
+ {
+ .name = "cs43130_hifi",
+ .id = 0,
+ .playback = {
+ .stream_name = "DAC Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_ASP_FORMATS,
+ },
+ .ops = &cs43130_dai_ops,
+ .symmetric_rates = 1,
+ },
+ {
+ .name = "cs43130-xsp",
+ .id = 1,
+ .playback = {
+ .stream_name = "XSP Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_XSP_FORMATS,
+ },
+ .symmetric_rates = 1,
+ },
+};
+
+static int cs43130_codec_set_sysclk(struct snd_soc_codec *codec,
+ int clk_id, int source, unsigned int freq, int dir)
+{
+ /* 24576000 is not supported */
+ unsigned int mclk_int_freq = 22579200;
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, source = %d, freq = %d, dir = %d\n",
+ __func__, clk_id, source, freq, dir);
+ /*
+ * freq is external mclk freq
+ * if freq == mclk_int_freq, pll is bypassed
+ * modify mclk_int_freq as needed for application
+ */
+ cs43130_set_pll(codec, 0, 0, freq, mclk_int_freq);
+ return 0;
+}
+
+static irqreturn_t cs43130_irq_thread(int irq, void *data)
+{
+ struct cs43130_private *cs43130 =
+ (struct cs43130_private *)data;
+ struct snd_soc_codec *codec = cs43130->codec;
+ unsigned int stickies[CS43130_NUM_INT];
+ unsigned int masks[CS43130_NUM_INT];
+ unsigned int i;
+
+ /* Read all INT status and mask reg */
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_STATUS_1,
+ stickies, CS43130_NUM_INT * sizeof(unsigned int));
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_MASK_1,
+ masks, CS43130_NUM_INT * sizeof(unsigned int));
+
+ for (i = 0; i < ARRAY_SIZE(stickies); i++)
+ stickies[i] = stickies[i] & (~masks[i]);
+
+ if (stickies[0] & CS43130_XTAL_RDY_INT)
+ dev_dbg(codec->dev, "%s: Crystal ready", __func__);
+
+ if (stickies[0] & CS43130_XTAL_ERR_INT)
+ dev_err(codec->dev, "%s: Crystal err", __func__);
+
+ if (stickies[0] & CS43130_HP_PLUG_INT)
+ dev_dbg(codec->dev, "%s: HP plugged", __func__);
+
+ if (stickies[0] & CS43130_HP_UNPLUG_INT)
+ dev_dbg(codec->dev, "%s: HP unplugged", __func__);
+
+ return IRQ_HANDLED;
+}
+
+static int cs43130_probe(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ cs43130->codec = codec;
+
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_cs43130 = {
+ .probe = cs43130_probe,
+ .component_driver = {
+ .controls = cs43130_snd_controls,
+ .num_controls = ARRAY_SIZE(cs43130_snd_controls),
+ .dapm_widgets = cs43130_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(cs43130_dapm_widgets),
+ .dapm_routes = cs43130_routes,
+ .num_dapm_routes = ARRAY_SIZE(cs43130_routes),
+ },
+ .set_sysclk = cs43130_codec_set_sysclk,
+ .set_pll = cs43130_set_pll,
+};
+
+static const struct regmap_config cs43130_regmap = {
+ .reg_bits = 24,
+ .pad_bits = 8,
+ .val_bits = 8,
+
+ .max_register = CS43130_LASTREG,
+ .reg_defaults = cs43130_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults),
+ .readable_reg = cs43130_readable_register,
+ .precious_reg = cs43130_precious_register,
+ .volatile_reg = cs43130_volatile_register,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static int cs43130_handle_device_data(
+ struct i2c_client *i2c_client, struct cs43130_private *cs43130)
+{
+ struct device_node *np = i2c_client->dev.of_node;
+ unsigned int val;
+ int ret = 0;
+
+ of_property_read_u32(np, "cirrus,xtal-ibias", &val);
+ switch (val) {
+ case 1:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
+ break;
+ case 2:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
+ break;
+ case 3:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
+ break;
+ default:
+ dev_info(&i2c_client->dev,
+ "cirrus,xtal-ibias value or xtal unused %d",
+ val);
+ }
+ return ret;
+}
+
+static int cs43130_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct cs43130_private *cs43130;
+ int ret;
+ unsigned int devid = 0;
+ unsigned int reg;
+ int i;
+
+ cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
+ if (cs43130 == NULL)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, cs43130);
+
+ cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
+ if (IS_ERR(cs43130->regmap)) {
+ ret = PTR_ERR(cs43130->regmap);
+ return ret;
+ }
+
+ if (client->dev.of_node) {
+ ret = cs43130_handle_device_data(client, cs43130);
+ if (ret != 0)
+ return ret;
+ }
+ for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
+ cs43130->supplies[i].supply = cs43130_supply_names[i];
+
+ ret = devm_regulator_bulk_get(&client->dev,
+ ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to request supplies: %d\n", ret);
+ return ret;
+ }
+ ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to enable supplies: %d\n", ret);
+ return ret;
+ }
+
+ cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
+ "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(cs43130->reset_gpio))
+ return PTR_ERR(cs43130->reset_gpio);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ /* initialize codec */
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®);
+
+ devid = (reg & 0xFF) << 12;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®);
+ devid |= (reg & 0xFF) << 4;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®);
+ devid |= (reg & 0xF0) >> 4;
+
+ switch (devid) {
+ case CS43130_CHIP_ID:
+ break;
+ case CS4399_CHIP_ID:
+ break;
+ default:
+ dev_err(&client->dev,
+ "CS43130 Device ID (%X). Expected ID %X or %X\n",
+ devid, CS43130_CHIP_ID, CS4399_CHIP_ID);
+ ret = -ENODEV;
+ goto err;
+ }
+
+ cs43130->dev_id = devid;
+ ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
+ if (ret < 0) {
+ dev_err(&client->dev, "Get Revision ID failed\n");
+ goto err;
+ }
+
+ dev_info(&client->dev,
+ "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
+ reg & 0xFF);
+
+ /* Enable interrupt handler */
+ ret = devm_request_threaded_irq(&client->dev,
+ client->irq,
+ NULL, cs43130_irq_thread,
+ IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+ "cs43130", cs43130);
+ if (ret != 0) {
+ dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
+ return ret;
+ }
+
+ /* Unmask INT */
+ regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
+ CS43130_XTAL_RDY_INT | CS43130_XTAL_ERR_INT |
+ CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0);
+
+ /* Enable HP detect */
+ regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
+ CS43130_HP_DETECT_CTRL_MASK, CS43130_HP_DETECT_CTRL_MASK);
+
+ regmap_write(cs43130->regmap,
+ CS43130_CRYSTAL_SET, cs43130->xtal_ibias);
+ ret = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_cs43130, cs43130_dai,
+ ARRAY_SIZE(cs43130_dai));
+
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "%s: snd_soc_register_codec failed with ret = %d\n",
+ __func__, ret);
+ goto err;
+ }
+ return 0;
+err:
+ return ret;
+
+}
+
+static int cs43130_i2c_remove(struct i2c_client *client)
+{
+ struct cs43130_private *cs43130 = i2c_get_clientdata(client);
+
+ snd_soc_unregister_codec(&client->dev);
+
+ if (cs43130->reset_gpio)
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ pm_runtime_disable(&client->dev);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int cs43130_runtime_suspend(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+
+ regcache_cache_only(cs43130->regmap, true);
+ regcache_mark_dirty(cs43130->regmap);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ return 0;
+}
+
+static int cs43130_runtime_resume(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(dev, "Failed to enable supplies: %d\n",
+ ret);
+ return ret;
+ }
+
+ regcache_cache_only(cs43130->regmap, false);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ ret = regcache_sync(cs43130->regmap);
+ if (ret != 0) {
+ dev_err(dev, "Failed to restore register cache\n");
+ goto err;
+ }
+ return 0;
+err:
+ regcache_cache_only(cs43130->regmap, true);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops cs43130_runtime_pm = {
+ SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id cs43130_of_match[] = {
+ { .compatible = "cirrus,cs43130", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, cs43130_of_match);
+
+static const struct i2c_device_id cs43130_i2c_id[] = {
+ {"cs43130", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
+
+static struct i2c_driver cs43130_i2c_driver = {
+ .driver = {
+ .name = "cs43130",
+ .of_match_table = cs43130_of_match,
+ },
+ .id_table = cs43130_i2c_id,
+ .probe = cs43130_i2c_probe,
+ .remove = cs43130_i2c_remove,
+};
+
+module_i2c_driver(cs43130_i2c_driver);
+
+MODULE_AUTHOR("Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs43130.h b/sound/soc/codecs/cs43130.h
new file mode 100644
index 0000000..bceae76
--- /dev/null
+++ b/sound/soc/codecs/cs43130.h
@@ -0,0 +1,268 @@
+/*
+ * ALSA SoC CS43130 codec driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Author: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#ifndef __CS43130_H__
+#define __CS43130_H__
+
+/* CS43130 registers addresses */
+/* all reg address is shifted by a byte for control byte to be LSB */
+#define CS43130_FIRSTREG 0x010000
+#define CS43130_LASTREG 0x0F0014
+#define CS43130_CHIP_ID 0x00043130
+#define CS4399_CHIP_ID 0x00043990
+#define CS43130_DEVID_AB 0x010000 /*Device ID A & B [RO]*/
+#define CS43130_DEVID_CD 0x010001 /*Device ID C & D [RO]*/
+#define CS43130_DEVID_E 0x010002 /*Device ID E [RO]*/
+#define CS43130_FAB_ID 0x010003 /*Fab ID [RO]*/
+#define CS43130_REV_ID 0x010004 /*Revision ID [RO]*/
+#define CS43130_SUBREV_ID 0x010005 /*Subrevision ID*/
+#define CS43130_SYS_CLK_CTL_1 0x010006 /*System Clocking Ctl 1*/
+#define CS43130_SP_SRATE 0x01000B /*Serial Port Sample Rate*/
+#define CS43130_SP_BITSIZE 0x01000C /*Serial Port Bit Size*/
+#define CS43130_PAD_INT_CFG 0x01000D /*Pad Interface Config*/
+#define CS43130_DXD1 0x010010 /*DXD1*/
+#define CS43130_PWDN_CTL 0x020000 /*Power Down Ctl*/
+#define CS43130_DXD2 0x020019 /*DXD2*/
+#define CS43130_CRYSTAL_SET 0x020052 /*Crystal Setting*/
+#define CS43130_PLL_SET_1 0x030001 /*PLL Setting 1*/
+#define CS43130_PLL_SET_2 0x030002 /*PLL Setting 2*/
+#define CS43130_PLL_SET_3 0x030003 /*PLL Setting 3*/
+#define CS43130_PLL_SET_4 0x030004 /*PLL Setting 4*/
+#define CS43130_PLL_SET_5 0x030005 /*PLL Setting 5*/
+#define CS43130_PLL_SET_6 0x030008 /*PLL Setting 6*/
+#define CS43130_PLL_SET_7 0x03000A /*PLL Setting 7*/
+#define CS43130_PLL_SET_8 0x03001B /*PLL Setting 8*/
+#define CS43130_PLL_SET_9 0x040002 /*PLL Setting 9*/
+#define CS43130_PLL_SET_10 0x040003 /*PLL Setting 10*/
+#define CS43130_CLKOUT_CTL 0x040004 /*CLKOUT Ctl*/
+#define CS43130_ASP_NUM_1 0x040010 /*ASP Numerator 1*/
+#define CS43130_ASP_NUM_2 0x040011 /*ASP Numerator 2*/
+#define CS43130_ASP_DENOM_1 0x040012 /*ASP Denominator 1*/
+#define CS43130_ASP_DENOM_2 0x040013 /*ASP Denominator 2*/
+#define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /*ASP LRCK High Time 1*/
+#define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /*ASP LRCK High Time 2*/
+#define CS43130_ASP_LRCK_PERIOD_1 0x040016 /*ASP LRCK Period 1*/
+#define CS43130_ASP_LRCK_PERIOD_2 0x040017 /*ASP LRCK Period 2*/
+#define CS43130_ASP_CLOCK_CONF 0x040018 /*ASP Clock Config*/
+#define CS43130_ASP_FRAME_CONF 0x040019 /*ASP Frame Config*/
+#define CS43130_XSP_NUM_1 0x040020 /*XSP Numerator 1*/
+#define CS43130_XSP_NUM_2 0x040021 /*XSP Numerator 2*/
+#define CS43130_XSP_DENOM_1 0x040022 /*XSP Denominator 1*/
+#define CS43130_XSP_DENOM_2 0x040023 /*XSP Denominator 2*/
+#define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /*XSP LRCK High Time 1*/
+#define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /*XSP LRCK High Time 2*/
+#define CS43130_XSP_LRCK_PERIOD_1 0x040026 /*XSP LRCK Period 1*/
+#define CS43130_XSP_LRCK_PERIOD_2 0x040027 /*XSP LRCK Period 2*/
+#define CS43130_XSP_CLOCK_CONF 0x040028 /*XSP Clock Config*/
+#define CS43130_XSP_FRAME_CONF 0x040029 /*XSP Frame Config*/
+#define CS43130_ASP_CH_1_LOC 0x050000 /*ASP Chan 1 Location*/
+#define CS43130_ASP_CH_2_LOC 0x050001 /*ASP Chan 2 Location*/
+#define CS43130_ASP_CH_1_SZ_EN 0x05000A /*ASP Chan 1 Size, Enable*/
+#define CS43130_ASP_CH_2_SZ_EN 0x05000B /*ASP Chan 2 Size, Enable*/
+#define CS43130_XSP_CH_1_LOC 0x060000 /*XSP Chan 1 Location*/
+#define CS43130_XSP_CH_2_LOC 0x060001 /*XSP Chan 2 Location*/
+#define CS43130_XSP_CH_1_SZ_EN 0x06000A /*XSP Chan 1 Size, Enable*/
+#define CS43130_XSP_CH_2_SZ_EN 0x06000B /*XSP Chan 2 Size, Enable*/
+#define CS43130_DSD_VOL_B 0x070000 /*DSD Volume B*/
+#define CS43130_DSD_VOL_A 0x070001 /*DSD Volume A*/
+#define CS43130_DSD_PATH_CTL_1 0x070002 /*DSD Proc Path Sig Ctl 1*/
+#define CS43130_DSD_INT_CFG 0x070003 /*DSD Interface Config*/
+#define CS43130_DSD_PATH_CTL_2 0x070004 /*DSD Proc Path Sig Ctl 2*/
+#define CS43130_DSD_PCM_MIX_CTL 0x070005 /*DSD and PCM Mixing Ctl*/
+#define CS43130_DSD_PATH_CTL_3 0x070006 /*DSD Proc Path Sig Ctl 3*/
+#define CS43130_HP_OUT_CTL_1 0x080000 /*HP Output Ctl 1*/
+#define CS43130_PCM_FILT_OPT 0x090000 /*PCM Filter Option*/
+#define CS43130_PCM_VOL_B 0x090001 /*PCM Volume B*/
+#define CS43130_PCM_VOL_A 0x090002 /*PCM Volume A*/
+#define CS43130_PCM_PATH_CTL_1 0x090003 /*PCM Path Signal Ctl 1*/
+#define CS43130_PCM_PATH_CTL_2 0x090004 /*PCM Path Signal Ctl 2*/
+#define CS43130_CLASS_H_CTL 0x0B0000 /*Class H Ctl*/
+#define CS43130_HP_DETECT 0x0D0000 /*HP Detect*/
+#define CS43130_HP_STATUS 0x0D0001 /*HP Status [RO]*/
+#define CS43130_HP_LOAD_1 0x0E0000 /*HP Load 1*/
+#define CS43130_HP_MEAS_LOAD_1 0x0E0003 /*HP Load Measurement 1*/
+#define CS43130_HP_MEAS_LOAD_2 0x0E0004 /*HP Load Measurement 2*/
+#define CS43130_HP_DC_STAT_1 0x0E000D /*HP DC Load Status 0 [RO]*/
+#define CS43130_HP_DC_STAT_2 0x0E000E /*HP DC Load Status 1 [RO]*/
+#define CS43130_HP_AC_STAT_1 0x0E0010 /*HP AC Load Status 0 [RO]*/
+#define CS43130_HP_AC_STAT_2 0x0E0011 /*HP AC Load Status 1 [RO]*/
+#define CS43130_HP_LOAD_STAT 0x0E001A /*HP Load Status [RO]*/
+#define CS43130_INT_STATUS_1 0x0F0000 /*Interrupt Status 1*/
+#define CS43130_INT_STATUS_2 0x0F0001 /*Interrupt Status 2*/
+#define CS43130_INT_STATUS_3 0x0F0002 /*Interrupt Status 3*/
+#define CS43130_INT_STATUS_4 0x0F0003 /*Interrupt Status 4*/
+#define CS43130_INT_STATUS_5 0x0F0004 /*Interrupt Status 5*/
+#define CS43130_INT_MASK_1 0x0F0010 /*Interrupt Mask 1*/
+#define CS43130_INT_MASK_2 0x0F0011 /*Interrupt Mask 2*/
+#define CS43130_INT_MASK_3 0x0F0012 /*Interrupt Mask 3*/
+#define CS43130_INT_MASK_4 0x0F0013 /*Interrupt Mask 4*/
+#define CS43130_INT_MASK_5 0x0F0014 /*Interrupt Mask 5*/
+
+#define CS43130_MCLK_SRC_SEL_MASK 0x03
+#define CS43130_MCLK_SRC_SEL_SHIFT 0
+#define CS43130_MCLK_INT_MASK 0x04
+#define CS43130_MCLK_INT_SHIFT 2
+#define CS43130_SP_SRATE_MASK 0x0F
+#define CS43130_SP_SRATE_SHIFT 0
+#define CS43130_SP_BITSIZE_ASP_MASK 0x03
+#define CS43130_SP_BITSIZE_ASP_SHIFT 0
+#define CS43130_HP_DETECT_CTRL_SHIFT 6
+#define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
+#define CS43130_HP_DETECT_INV_SHIFT 5
+#define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)
+
+/* CS43130_INT_MASK_1 */
+#define CS43130_HP_PLUG_INT_SHIFT 6
+#define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)
+#define CS43130_HP_UNPLUG_INT_SHIFT 5
+#define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)
+#define CS43130_XTAL_RDY_INT_SHIFT 4
+#define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)
+#define CS43130_XTAL_ERR_INT_SHIFT 3
+#define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)
+
+/*Reg CS43130_SP_BITSIZE*/
+#define CS43130_SP_BIT_SIZE_8 0x00
+#define CS43130_SP_BIT_SIZE_16 0x01
+#define CS43130_SP_BIT_SIZE_24 0x02
+#define CS43130_SP_BIT_SIZE_32 0x03
+
+/*PLL*/
+#define CS43130_PLL_START_MASK (0x1<<0)
+#define CS43130_PLL_MODE_MASK 0x02
+#define CS43130_PLL_MODE_SHIFT 1
+
+#define CS43130_PLL_REF_PREDIV_MASK 0x3
+
+#define CS43130_ASP_STP_MASK 0x10
+#define CS43130_ASP_STP_SHIFT 4
+#define CS43130_ASP_5050_MASK 0x08
+#define CS43130_ASP_5050_SHIFT 3
+#define CS43130_ASP_FSD_MASK 0x07
+#define CS43130_ASP_FSD_SHIFT 0
+
+#define CS43130_ASP_MODE_MASK 0x10
+#define CS43130_ASP_MODE_SHIFT 4
+#define CS43130_ASP_SCPOL_OUT_MASK 0x08
+#define CS43130_ASP_SCPOL_OUT_SHIFT 3
+#define CS43130_ASP_SCPOL_IN_MASK 0x04
+#define CS43130_ASP_SCPOL_IN_SHIFT 2
+#define CS43130_ASP_LCPOL_OUT_MASK 0x02
+#define CS43130_ASP_LCPOL_OUT_SHIFT 1
+#define CS43130_ASP_LCPOL_IN_MASK 0x01
+#define CS43130_ASP_LCPOL_IN_SHIFT 0
+
+/*Reg CS43130_PWDN_CTL*/
+#define CS43130_PDN_XSP_MASK 0x80
+#define CS43130_PDN_XSP_SHIFT 7
+#define CS43130_PDN_ASP_MASK 0x40
+#define CS43130_PDN_ASP_SHIFT 6
+#define CS43130_PDN_DSPIF_MASK 0x20
+#define CS43130_PDN_DSDIF_SHIFT 5
+#define CS43130_PDN_HP_MASK 0x10
+#define CS43130_PDN_HP_SHIFT 4
+#define CS43130_PDN_XTAL_MASK 0x08
+#define CS43130_PDN_XTAL_SHIFT 3
+#define CS43130_PDN_PLL_MASK 0x04
+#define CS43130_PDN_PLL_SHIFT 2
+#define CS43130_PDN_CLKOUT_MASK 0x02
+#define CS43130_PDN_CLKOUT_SHIFT 1
+
+#define CS43130_7_0_MASK 0xFF
+#define CS43130_15_8_MASK 0xFF00
+#define CS43130_23_16_MASK 0xFF0000
+
+/* Reg CS43130_HP_OUT_CTL_1 */
+#define CS43130_HP_IN_EN_SHIFT 3
+#define CS43130_HP_IN_EN_MASK 0x08
+
+#define CS43130_ASP_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
+ SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#define CS43130_XSP_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+enum cs43130_asp_rate {
+ CS43130_ASP_SPRATE_32K = 0,
+ CS43130_ASP_SPRATE_44_1K,
+ CS43130_ASP_SPRATE_48K,
+ CS43130_ASP_SPRATE_88_2K,
+ CS43130_ASP_SPRATE_96K,
+ CS43130_ASP_SPRATE_176_4K,
+ CS43130_ASP_SPRATE_192K,
+ CS43130_ASP_SPRATE_352_8K,
+ CS43130_ASP_SPRATE_384K,
+};
+
+enum cs43130_mclk_src_sel {
+ CS43130_MCLK_SRC_XTAL = 0,
+ CS43130_MCLK_SRC_PLL,
+ CS43130_MCLK_SRC_RCO
+};
+
+enum cs43130_mode {
+ CS43130_SLAVE_MODE = 0,
+ CS43130_MASTER_MODE
+};
+
+enum cs43130_xtal_ibias {
+ CS43130_XTAL_IBIAS_15UA = 2,
+ CS43130_XTAL_IBIAS_12_5UA = 4,
+ CS43130_XTAL_IBIAS_7_5UA = 6,
+};
+
+#define CS43130_AIF_BICK_RATE 1
+#define CS43130_SYSCLK_MCLK 1
+#define CS43130_NUM_SUPPLIES 5
+static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
+ "VA",
+ "VP",
+ "VCP",
+ "VD",
+ "VL",
+};
+
+#define CS43130_NUM_INT 5 /* number of interrupt status reg */
+
+struct cs43130_private {
+ struct snd_soc_codec *codec;
+ struct regmap *regmap;
+ struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];
+ /* codec device ID */
+ unsigned int dev_id;
+ int mclk;
+ int sclk;
+ int xtal_ibias;
+
+ bool pll_bypass;
+ int pll_out;
+ int mclk_int;
+ int dai_format;
+ int dai_mode;
+ int dai_bit;
+ int asp_size;
+ int fs;
+ bool bick_invert;
+ bool lrck_invert;
+ int bick;
+ struct gpio_desc *reset_gpio;
+};
+
+#endif /* __CS43130_H__ */
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH v2 0/7] ath9k: EEPROM swapping improvements
From: Martin Blumenstingl @ 2016-12-12 20:05 UTC (permalink / raw)
To: Valo, Kalle
Cc: ath9k-devel,
linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
ath9k-devel-xDcbHBWguxHbcTqmT+pZeQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
arnd-r2nGTMty4D4@public.gmane.org,
chunkeey-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org,
nbd-Vt+b4OUoWG0@public.gmane.org
In-Reply-To: <871sxza9al.fsf-HodKDYzPHsUD5k0oWYwrnHL1okKdlPRT@public.gmane.org>
Hello Kalle,
On Fri, Nov 25, 2016 at 4:06 PM, Valo, Kalle <kvalo-A+ZNKFmMK5xy9aJCnZT0Uw@public.gmane.org> wrote:
> Kalle Valo <kvalo-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> writes:
>
>> Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
>>
>>> There are two types of swapping the EEPROM data in the ath9k driver.
>>> Before this series one type of swapping could not be used without the
>>> other.
>>>
>>> The first type of swapping looks at the "magic bytes" at the start of
>>> the EEPROM data and performs swab16 on the EEPROM contents if needed.
>>> The second type of swapping is EEPROM format specific and swaps
>>> specific fields within the EEPROM itself (swab16, swab32 - depends on
>>> the EEPROM format).
>>>
>>> With this series the second part now looks at the EEPMISC register
>>> inside the EEPROM, which uses a bit to indicate if the EEPROM data
>>> is Big Endian (this is also done by the FreeBSD kernel).
>>> This has a nice advantage: currently there are some out-of-tree hacks
>>> (in OpenWrt and LEDE) where the EEPROM has a Big Endian header on a
>>> Big Endian system (= no swab16 is performed) but the EEPROM itself
>>> indicates that it's data is Little Endian. Until now the out-of-tree
>>> code simply did a swab16 before passing the data to ath9k, so ath9k
>>> first did the swab16 - this also enabled the format specific swapping.
>>> These out-of-tree hacks are still working with the new logic, but it
>>> is recommended to remove them. This implementation is based on a
>>> discussion with Arnd Bergmann who raised concerns about the
>>> robustness and portability of the swapping logic in the original OF
>>> support patch review, see [0].
>>>
>>> After a second round of patches (= v1 of this series) neither Arnd
>>> Bergmann nor I were really happy with the complexity of the EEPROM
>>> swapping logic. Based on a discussion (see [1] and [2]) we decided
>>> that ath9k should use a defined format (specifying the endianness
>>> of the data - I went with __le16 and __le32) when accessing the
>>> EEPROM fields. A benefit of this is that we enable the EEPMISC based
>>> swapping logic by default, just like the FreeBSD driver, see [3]. On
>>> the devices which I have tested (see below) ath9k now works without
>>> having to specify the "endian_check" field in ath9k_platform_data (or
>>> a similar logic which could provide this via devicetree) as ath9k now
>>> detects the endianness automatically. Only EEPROMs which are mangled
>>> by some out-of-tree code still need the endian_check flag (or one can
>>> simply remove that mangling from the out-of-tree code).
>>>
>>> Testing:
>>> - tested by myself on AR9287 with Big Endian EEPROM
>>> - tested by myself on AR9227 with Little Endian EEPROM
>>> - tested by myself on AR9381 (using the ar9003_eeprom implementation,
>>> which did not suffer from this whole problem)
>>> - how do we proceed with testing? maybe we could keep this in a
>>> feature-branch and add these patches to LEDE once we have an ACK to
>>> get more people to test this
>>>
>>> This series depends on my other series (v7):
>>> "add devicetree support to ath9k" - see [4]
>>
>> I think this looks pretty good. If there's a bug somewhere it should be
>> quite easy to fix so I'm not that worried and would be willing to take
>> these as soon as I have applied the dependency series. IIRC your
>> devicetree patches will have at least one more review round so that will
>> take some time still. In the meantime it would be great if LEDE folks
>> could take a look at these and comment (or test).
>
> So are everyone happy with this? I haven't seen any comments. If I don't
> here anything I'm planning to take these, most likely for 4.11.
the patches have been in LEDE for almost two weeks now and I did not
see any reports of ath9k breakage (footnote below).
It seems that there are a few devices out there where the whole EEPROM
is swab16'ed which switches the position of the 1-byte fields
opCapFlags and eepMisc.
those still work fine with the new code, however I had a second patch
in LEDE [0] which results in ath9k_platform_data.endian_check NOT
being set anymore.
that endian_check flag was used before to swab16 the whole EEPROM, to
correct the position of the 1-byte fields again.
Currently we are fixing this in the firmware hotplug script: [1]
This is definitely not a blocker for this series though (if we want to
have a devicetree replacement for "ath9k_platform_data.endian_check"
then I'd work on that within a separate series, but I somewhat
consider these EEPROMs as "broken" so fixing them in
userspace/firmware hotplug script is fine for me)
Regards,
Martin
[0] https://git.lede-project.org/?p=source.git;a=commitdiff;h=a20616863d32d91163043b6657a63c836bd9c5ba
[1] https://git.lede-project.org/?p=source.git;a=commitdiff;h=afa37092663d00aa0abf8c61943d9a1b5558b144
^ permalink raw reply
* Re: [PATCH] Documentation: ti-syscon-reset: fix header path
From: Yegor Yefremov @ 2016-12-12 19:52 UTC (permalink / raw)
To: Rob Herring
Cc: kernel list, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8
In-Reply-To: <20161212184021.hewybkfaygrle63a@rob-hp-laptop>
On Mon, Dec 12, 2016 at 7:40 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Fri, Dec 09, 2016 at 11:11:27AM +0100, yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org wrote:
>> From: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> 'include' was missing from path.
>>
>> Signed-off-by: Yegor Yefremov <yegorslists-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> index 164c7f3..5b20e20 100644
>> --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
>> @@ -44,7 +44,7 @@ Required properties:
>> reset status register
>> Cell #7 : Flags used to control reset behavior,
>> availible flags defined in the DT include
>> - file <dt-bindings/reset/ti-syscon.h>
>> + file <include/dt-bindings/reset/ti-syscon.h>
>
> There's pretty much equal mixture of include or not. Not really much
> point in fixing 1 instance if there's no clear correct way. Given it is
> written with <...>, that matches how you write the include statement.
OK I see the point of omitting include now. I was looking at this from
VIM point of view. I cannot automatically jump to the file via 'gf'.
Yegor
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^ permalink raw reply
* Re: [PATCH 16/16] drivers/fsi: Add GPIO based FSI master
From: Christopher Bostic @ 2016-12-12 19:49 UTC (permalink / raw)
To: Jeremy Kerr
Cc: Rob Herring, Mark Rutland, linux-I+IVW8TIWO2tmTQ+vhA3Yw, Greg KH,
sre-DgEjT+Ai2ygdnm+yROfE0A, Michael Turquette,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
Open List OF Flattened dev tree bindings,
Moderated list: ARM PORT, Chris Bostic, Joel Stanley,
Linux open list, Andrew Jeffery, Alistair Popple,
Benjamin Herrenschmidt
In-Reply-To: <6a39f4d9-0f20-a146-3122-86d3f75c58fa-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>
On Thu, Dec 8, 2016 at 10:12 PM, Jeremy Kerr <jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org> wrote:
> Hi Chris,
>
>> +static ssize_t store_scan(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t count)
>> +{
>> + struct fsi_master_gpio *master = dev_get_drvdata(dev);
>> +
>> + fsi_master_gpio_init(master);
>> +
>> + /* clear out any old scan data if present */
>> + fsi_master_unregister(&master->master);
>> + fsi_master_register(&master->master);
>> +
>> + return count;
>> +}
>> +
>> +static DEVICE_ATTR(scan, 0200, NULL, store_scan);
>
> I think it would make more sense to have the scan attribute populated by
> the fsi core; we want this on all masters, not just GPIO.
>
Hi Jeremy,
Sure, will move that to the core.
> Currently, the only GPIO-master-specific functionality here is the
> fsi_master_gpio_init() - but isn't this something that we can do at
> probe time instead?
>
Yes that can be done at probe time. Will change.
>> +static int fsi_master_gpio_probe(struct platform_device *pdev)
>> +{
>> + struct fsi_master_gpio *master;
>> + struct gpio_desc *gpio;
>> +
>> + master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
>> + if (!master)
>> + return -ENOMEM;
>
> We should be populating master->dev.parent, see
>
> https://github.com/jk-ozlabs/linux/commit/5225d6c47
>
>
Will make the change.
>> + /* Optional pins */
>> +
>> + gpio = devm_gpiod_get(&pdev->dev, "trans", 0);
>> + if (IS_ERR(gpio))
>> + dev_dbg(&pdev->dev, "probe: failed to get trans pin\n");
>> + else
>> + master->gpio_trans = gpio;
>
> I found devm_gpiod_get_optional(), which might make this a little
> neater.
Will make this change.
Thanks,
Chris
>
> Cheers,
>
>
> Jeremy
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^ permalink raw reply
* Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support
From: Stephen Boyd @ 2016-12-12 19:38 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-clk, mturquette, ssantosh, nm, linux-arm-kernel, devicetree
In-Reply-To: <22dacb0c-a3bc-50ce-e4b9-f74a0c706f20@ti.com>
On 12/09, Tero Kristo wrote:
> On 08/12/16 23:10, Stephen Boyd wrote:
> >On 12/08, Tero Kristo wrote:
> >>On 08/12/16 02:13, Stephen Boyd wrote:
> >>>On 10/21, Tero Kristo wrote:
> >>>>diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> >>>>new file mode 100644
> >>>>index 0000000..f6af5bd
> >>>>--- /dev/null
> >>>>+++ b/drivers/clk/keystone/sci-clk.c
> >>
> >>>
> >>>>+
> >>>>+ handle = devm_ti_sci_get_handle(dev);
> >>>>+ if (IS_ERR(handle))
> >>>>+ return PTR_ERR(handle);
> >>>>+
> >>>>+ provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> >>>>+ if (!provider)
> >>>>+ return -ENOMEM;
> >>>>+
> >>>>+ provider->clocks = data;
> >>>>+
> >>>>+ provider->sci = handle;
> >>>>+ provider->ops = &handle->ops.clk_ops;
> >>>>+ provider->dev = dev;
> >>>>+
> >>>>+ ti_sci_init_clocks(provider);
> >>>
> >>>And if this fails?
> >>
> >>Yea this is kind of controversial. ti_sci_init_clocks() can fail if
> >>any of the clocks registered will fail. I decided to have it this
> >>way so that at least some clocks might work in failure cause, and
> >>you might have a booting device instead of total lock-up.
> >>
> >>Obviously it could be done so that if any clock fails, we would
> >>de-register all clocks at that point, but personally I think this is
> >>a worse option.
> >>
> >>ti_sci_init_clocks could probably be modified to continue
> >>registering clocks when a single clock fails though. Currently it
> >>aborts at first failure.
> >>
> >
> >That sounds like a better approach if we don't care about
> >failures to register a clock. Returning a value from a function
> >and not using it isn't really a great design.
> >
> >I worry that if we start returning errors from clk_hw_register()
> >that something will go wrong though, so really I don't know why
> >we want to ignore errors at all. Just for debugging a boot hang?
> >Can't we use early console to at least see that this driver is
> >failing to probe and debug that way?
>
> Early console can be used to debug that, but it is kind of annoying
> to recompile most of the kernel when you suddenly need to use it.
I thought SERIAL_EARLYCON was selected by drivers that support
it? So there shouldn't be any rebuilding required.
>
> How about modifying the ti_sci_init_clocks func to print an error
> for each failed clock?
Ok that's fine too. I'd prefer the function had a return type of
void if we're not planning on using the return value, that's all.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v6 5/8] IIO: add bindings for STM32 timer trigger driver
From: Rob Herring @ 2016-12-12 19:28 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones, mark.rutland, alexandre.torgue, devicetree,
linux-kernel, thierry.reding, linux-pwm, jic23, knaack.h, lars,
pmeerw, linux-iio, linux-arm-kernel, fabrice.gasnier,
gerald.baeza, arnaud.pouliquen, linus.walleij, linaro-kernel,
Benjamin Gaignard
In-Reply-To: <1481292919-26587-6-git-send-email-benjamin.gaignard@st.com>
On Fri, Dec 09, 2016 at 03:15:16PM +0100, Benjamin Gaignard wrote:
> Define bindings for STM32 timer trigger
>
> version 4:
> - remove triggers enumeration from DT
> - add reg parameter
>
> version 3:
> - change file name
> - add cross reference with mfd bindings
>
> version 2:
> - only keep one compatible
> - add DT parameters to set lists of the triggers:
> one list describe the triggers created by the device
> another one give the triggers accepted by the device
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
Other than same comments I made in the other patches for the example,
looks fine.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 3/8] PWM: add pwm-stm32 DT bindings
From: Rob Herring @ 2016-12-12 19:02 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones, mark.rutland, alexandre.torgue, devicetree,
linux-kernel, thierry.reding, linux-pwm, jic23, knaack.h, lars,
pmeerw, linux-iio, linux-arm-kernel, fabrice.gasnier,
gerald.baeza, arnaud.pouliquen, linus.walleij, linaro-kernel,
Benjamin Gaignard
In-Reply-To: <1481292919-26587-4-git-send-email-benjamin.gaignard@st.com>
On Fri, Dec 09, 2016 at 03:15:14PM +0100, Benjamin Gaignard wrote:
> Define bindings for pwm-stm32
>
> version 6:
> - change st,breakinput parameter format to make it usuable on stm32f7 too.
>
> version 2:
> - use parameters instead of compatible of handle the hardware configuration
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> new file mode 100644
> index 0000000..866f222
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> @@ -0,0 +1,33 @@
> +STMicroelectronics STM32 Timers PWM bindings
> +
> +Must be a sub-node of an STM32 Timers device tree node.
> +See ../mfd/stm32-timers.txt for details about the parent node.
> +
> +Required parameters:
> +- compatible: Must be "st,stm32-pwm".
> +- pinctrl-names: Set to "default".
> +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
> + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
> +
> +Optional parameters:
> +- st,breakinput: Arrays of three u32 <index level filter> to describe break input configurations.
> + "index" indicates on which break input the configuration should be applied.
> + "level" gives the active level (0=low or 1=high) for this configuration.
> + "filter" gives the filtering value to be applied.
> +
> +Example:
> + timers@40010000 {
timer@...
With that,
Acked-by: Rob Herring <robh@kernel.org>
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + st,breakinput = <0 1 5>;
> + };
> + };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v6 7/8] ARM: dts: stm32: add Timers driver for stm32f429 MCU
From: Rob Herring @ 2016-12-12 18:59 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1481292919-26587-8-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On Fri, Dec 09, 2016 at 03:15:18PM +0100, Benjamin Gaignard wrote:
> Add Timers and it sub-nodes into DT for stm32f429 family.
>
> version 6:
> - split patch in two: one for SoC family and one for stm32f469
> discovery board.
>
> version 5:
> - rename gptimer node to timers
> - re-order timers node par addresses
>
> version 4:
> - remove unwanted indexing in pwm@ and timer@ node name
> - use "reg" instead of additional parameters to set timer
> configuration
>
> version 3:
> - use "st,stm32-timer-trigger" in DT
>
> version 2:
> - use parameters to describe hardware capabilities
> - do not use references for pwm and iio timer subnodes
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 275 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index bca491d..d0fb9cc 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -355,6 +355,21 @@
> slew-rate = <2>;
> };
> };
> +
> + pwm1_pins: pwm@1 {
No reg prop, so should not have a unit-address. Given the names in the
define below, seems like "timer1" would be appropriate.
> + pins {
> + pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
> + <STM32F429_PB13_FUNC_TIM1_CH1N>,
> + <STM32F429_PB12_FUNC_TIM1_BKIN>;
> + };
> + };
> +
> + pwm3_pins: pwm@3 {
> + pins {
> + pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
> + <STM32F429_PB5_FUNC_TIM3_CH2>;
> + };
> + };
> };
>
> rcc: rcc@40023810 {
> @@ -426,6 +441,266 @@
> interrupts = <80>;
> clocks = <&rcc 0 38>;
> };
> +
> + timers2: timers@40000000 {
timer@...
It may be more than just a timer, there's not a better generic name.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000000 0x400>;
> + clocks = <&rcc 0 128>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> +
> + timers3: timers@40000400 {
ditto
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000400 0x400>;
> + clocks = <&rcc 0 129>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <2>;
> + status = "disabled";
> + };
> + };
> +
> + timers4: timers@40000800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000800 0x400>;
> + clocks = <&rcc 0 130>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <3>;
> + status = "disabled";
> + };
> + };
> +
> + timers5: timers@40000C00 {
timer@...
And use lowercase hex.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40000C00 0x400>;
ditto
> + clocks = <&rcc 0 131>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <4>;
> + status = "disabled";
> + };
> + };
> +
> + timers6: timers@40001000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001000 0x400>;
> + clocks = <&rcc 0 132>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <5>;
> + status = "disabled";
> + };
> + };
> +
> + timers7: timers@40001400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001400 0x400>;
> + clocks = <&rcc 0 133>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <6>;
> + status = "disabled";
> + };
> + };
> +
> + timers12: timers@40001800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001800 0x400>;
> + clocks = <&rcc 0 134>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <9>;
> + status = "disabled";
> + };
> + };
> +
> + timers13: timers@40001C00 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40001C00 0x400>;
> + clocks = <&rcc 0 135>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers14: timers@40002000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40002000 0x400>;
> + clocks = <&rcc 0 136>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers1: timers@40010000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <0>;
> + status = "disabled";
> + };
> + };
> +
> + timers8: timers@40010400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010400 0x400>;
> + clocks = <&rcc 0 161>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <7>;
> + status = "disabled";
> + };
> + };
> +
> + timers9: timers@40014000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014000 0x400>;
> + clocks = <&rcc 0 176>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <8>;
> + status = "disabled";
> + };
> + };
> +
> + timers10: timers@40014400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014400 0x400>;
> + clocks = <&rcc 0 177>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> +
> + timers11: timers@40014800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40014800 0x400>;
> + clocks = <&rcc 0 178>;
> + clock-names = "clk_int";
> + status = "disabled";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + status = "disabled";
> + };
> + };
> };
> };
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v6 1/8] MFD: add bindings for STM32 Timers driver
From: Rob Herring @ 2016-12-12 18:51 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: lee.jones, mark.rutland, alexandre.torgue, devicetree,
linux-kernel, thierry.reding, linux-pwm, jic23, knaack.h, lars,
pmeerw, linux-iio, linux-arm-kernel, fabrice.gasnier,
gerald.baeza, arnaud.pouliquen, linus.walleij, linaro-kernel,
Benjamin Gaignard
In-Reply-To: <1481292919-26587-2-git-send-email-benjamin.gaignard@st.com>
On Fri, Dec 09, 2016 at 03:15:12PM +0100, Benjamin Gaignard wrote:
> Add bindings information for STM32 Timers
>
> version 6:
> - rename stm32-gtimer to stm32-timers
> - change compatible
> - add description about the IPs
>
> version 2:
> - rename stm32-mfd-timer to stm32-gptimer
> - only keep one compatible string
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
> new file mode 100644
> index 0000000..b30868e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
> @@ -0,0 +1,46 @@
> +STM32 Timers driver bindings
> +
> +This IP provides 3 types of timer along with PWM functionality:
> +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
> + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
> +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
> + programmable prescaler and PWM outputs.
> +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
> +
> +Required parameters:
> +- compatible: must be "st,stm32-timers"
> +
> +- reg: Physical base address and length of the controller's
> + registers.
> +- clock-names: Set to "clk_int".
'clk' is redundant. Also, you don't really need -names when there is
only one of them.
> +- clocks: Phandle to the clock used by the timer module.
> + For Clk properties, please refer to ../clock/clock-bindings.txt
> +
> +Optional parameters:
> +- resets: Phandle to the parent reset controller.
> + See ../reset/st,stm32-rcc.txt
> +
> +Optional subnodes:
> +- pwm: See ../pwm/pwm-stm32.txt
> +- timer: See ../iio/timer/stm32-timer-trigger.txt
> +
> +Example:
> + timers@40010000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "st,stm32-timers";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm {
> + compatible = "st,stm32-pwm";
> + pinctrl-0 = <&pwm1_pins>;
> + pinctrl-names = "default";
> + };
> +
> + timer {
> + compatible = "st,stm32-timer-trigger";
> + reg = <0>;
You don't need reg here as there is only one. In turn, you don't need
#address-cells or #size-cells.
> + };
> + };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v2 04/11] Documentation: DT: binding: axp20x_usb_power: add axp223 compatible
From: Rob Herring @ 2016-12-12 18:44 UTC (permalink / raw)
To: Quentin Schulz
Cc: sre-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wens-jdAy2FN1RRM, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
In-Reply-To: <20161209110419.28981-5-quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
On Fri, Dec 09, 2016 at 12:04:12PM +0100, Quentin Schulz wrote:
> This adds the "x-powers,axp223-usb-power-supply" to the list of
> compatibles for AXP20X VBUS power supply driver.
>
> Signed-off-by: Quentin Schulz <quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>
> v2:
> - adding small explanation on AXP223 variation compared to the AXP221,
>
> Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt | 5 +++++
> 1 file changed, 5 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH 2/2] irqchip/renesas-intc-irqpin: Add R-Car Gen1 fallback binding
From: Rob Herring @ 2016-12-12 18:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Magnus Damm, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linux-Renesas, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdX_Cg6T10pMXe420kOwQn27_PRm-osNb7L4_M==fJnE_Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Dec 09, 2016 at 01:52:20PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Dec 9, 2016 at 11:50 AM, Simon Horman
> <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> > In the case of Renesas R-Car hardware we know that there are generations of
> > SoCs, e.g. Gen 1, Gen 2 and Gen 3. But beyond that its not clear what the
>
> it's
>
> > relationship between IP blocks might be. For example, I believe that
> > r8a7779 is older than r8a7778 but that doesn't imply that the latter is a
> > descendant of the former or vice versa.
> >
> > We can, however, by examining the documentation and behaviour of the
> > hardware at run-time observe that the current driver implementation appears
> > to be compatible with the IP blocks on SoCs within a given generation.
> >
> > For the above reasons and convenience when enabling new SoCs a
> > per-generation fallback compatibility string scheme being adopted for
> > drivers for Renesas SoCs.
> >
> > Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
> > ---
> > .../interrupt-controller/renesas,intc-irqpin.txt | 44 ++++++++++++----------
> > drivers/irqchip/irq-renesas-intc-irqpin.c | 2 +
> > 2 files changed, 26 insertions(+), 20 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> > index 772c550d3b4b..e5a5251be9f5 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> > @@ -2,13 +2,19 @@ DT bindings for the R-/SH-Mobile irqpin controller
> >
> > Required properties:
> >
> > -- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
> > - as fallback.
> > - Examples with soctypes are:
> > +- compatible:
> > - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
> > - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
> > - "renesas,intc-irqpin-r8a7779" (R-Car H1)
> > - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
> > + - "renesas,rcar-gen1-intc-irqpin" (generic R-Car Gen1 compatible device)
>
> Does it make sense to add a new family-specific compatible value to a driver
> that's unlikely to receive more users in the future? More recent SoCs use
> renesas,irqc.
If that's the case, then no. Please don't go crazy with your generic
strings. I don't mind them, but I don't know that I'd call it best
practice.
Rob
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^ permalink raw reply
* Re: [PATCH] Documentation: ti-syscon-reset: fix header path
From: Rob Herring @ 2016-12-12 18:40 UTC (permalink / raw)
To: yegorslists; +Cc: linux-kernel, p.zabel, devicetree, mark.rutland
In-Reply-To: <1481278287-23842-1-git-send-email-yegorslists@googlemail.com>
On Fri, Dec 09, 2016 at 11:11:27AM +0100, yegorslists@googlemail.com wrote:
> From: Yegor Yefremov <yegorslists@googlemail.com>
>
> 'include' was missing from path.
>
> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> ---
> Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> index 164c7f3..5b20e20 100644
> --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
> @@ -44,7 +44,7 @@ Required properties:
> reset status register
> Cell #7 : Flags used to control reset behavior,
> availible flags defined in the DT include
> - file <dt-bindings/reset/ti-syscon.h>
> + file <include/dt-bindings/reset/ti-syscon.h>
There's pretty much equal mixture of include or not. Not really much
point in fixing 1 instance if there's no clear correct way. Given it is
written with <...>, that matches how you write the include statement.
Rob
^ permalink raw reply
* [PATCH] of/platform: depopulate devices in the reverse order of creation
From: Jason Gunthorpe @ 2016-12-12 18:39 UTC (permalink / raw)
To: Rob Herring, Frank Rowand
Cc: Pawel Moll, Grant Likely, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
If the DT has inter-dependencies, then the devices need to be removed
in the right order to avoid removal problems.
Assuming the DT is constructed so that EPROBE_DEFER doesn't happen
during creating then a good way to avoid removal problems is reversing
the order during depopulation.
Signed-off-by: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
---
drivers/of/platform.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
In my specific case I have a gpio driver, followed by a i2c bitbang
using that driver. So gpiolib prints an error if it the gpio driver is
removed before the gpio client..
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index cd72c0156db2ba..5720fe44f991e9 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -568,7 +568,8 @@ static int of_platform_device_destroy(struct device *dev, void *data)
void of_platform_depopulate(struct device *parent)
{
if (parent->of_node && of_node_check_flag(parent->of_node, OF_POPULATED_BUS)) {
- device_for_each_child(parent, NULL, of_platform_device_destroy);
+ device_for_each_child_reverse(parent, NULL,
+ of_platform_device_destroy);
of_node_clear_flag(parent->of_node, OF_POPULATED_BUS);
}
}
--
2.7.4
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^ permalink raw reply related
* RE: [PATCH v4 3/5] i2c: designware: Add slave definitions
From: Luis de Oliveira @ 2016-12-12 18:35 UTC (permalink / raw)
To: Rob Herring, Luis Oliveira
Cc: wsa@the-dreams.de, mark.rutland@arm.com,
jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com,
mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Ramiro.Oliveira@synopsys.com, Joao.Pinto@synopsys.com,
CARLOS.PALMINHA@synopsys.com
In-Reply-To: <20161212170214.4cydp256jsp7srar@rob-hp-laptop>
Hi all,
The slave address could be set by the I2C slave backend so I can't use it to setup the controller.
A boolean property was my initial approach then Andy and Wolfram Sang suggested the use of compatible strings and later It was suggested to use a property to select mode but I can do it again if it's the best way.
Can you please tell me where should it be documented?
Luis
-----Original Message-----
From: Rob Herring [mailto:robh@kernel.org]
Sent: Monday, December 12, 2016 17:02
To: Luis Oliveira <Luis.Oliveira@synopsys.com>
Cc: wsa@the-dreams.de; mark.rutland@arm.com; jarkko.nikula@linux.intel.com; andriy.shevchenko@linux.intel.com; mika.westerberg@linux.intel.com; linux-i2c@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Ramiro.Oliveira@synopsys.com; Joao.Pinto@synopsys.com; CARLOS.PALMINHA@synopsys.com
Subject: Re: [PATCH v4 3/5] i2c: designware: Add slave definitions
On Wed, Dec 07, 2016 at 05:55:50PM +0000, Luis Oliveira wrote:
> - Add slave definitions to i2c-designware-core
> - Changes in Kconfig to auto-enable I2C_SLAVE when compiling the
> modules
> - Add mode property to designware-core.txt that enable the "slave" selection:
> - "mode" is an optional property that could be "slave" or "master"
> - if "mode" is not set the block is considered master by default
>
> Signed-off-by: Luis Oliveira <lolivei@synopsys.com>
> ---
> Changes V3->V4: (Andy Shevchenko)
> - created a common property for modes
> - placed the generic dependency first
>
> .../devicetree/bindings/i2c/i2c-designware.txt | 4 ++++
> drivers/i2c/busses/Kconfig | 1 +
> drivers/i2c/busses/i2c-designware-common.c | 6 +++++
> drivers/i2c/busses/i2c-designware-core.h | 26 ++++++++++++++++++++++
> 4 files changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> index fee26dc3e858..8ed2b532cd54 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> @@ -20,6 +20,9 @@ Optional properties :
> - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
> This value which is by default 300ns is used to compute the tHIGH period.
>
> + - mode : should be either:
> + - "master" to setup the hardware block as a I2C master
> + - "slave" to setup the hardware block as a I2C slave
This should be documented in a common location. Can't it be a boolean to enable slave mode? Or don't you need to set the slave address? That could be enough to enable slave mode and there's already one example doing that.
Rob
^ permalink raw reply
* Re: [PATCH v2 1/2] devicetree: i2c-hid: Add Wacom digitizer + regulator support
From: Brian Norris @ 2016-12-12 18:34 UTC (permalink / raw)
To: Rob Herring
Cc: Benjamin Tissoires, Jiri Kosina, Dmitry Torokhov, Doug Anderson,
Caesar Wang, open list:ARM/Rockchip SoC...,
linux-input-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Mark Rutland
In-Reply-To: <CAL_JsqJ7t=C4+PgCyNTev66V33-cyPkUHKsTcbnsYgvAaffVfw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi all,
On Mon, Dec 12, 2016 at 08:47:06AM -0600, Rob Herring wrote:
[Snip Benjamin's proposal; I agree we don't really want a multi-level DT
layout purely for making the driver look a little nicer (I'm not sure
this would really be nicer anyway). And I think, as Rob notes here, our
disagreement is smaller than appears. But I might be wrong.]
> Anyway, we're only debating this:
OK, so I think we might have a consensus of sorts? I'll describe it
here, in case I'm wrong. Otherwise, I'll send another rev.
> i2c-hid-dev@2c {
> compatible = "wacom,w9013", "hid-over-i2c";
I plan to document the above, but not treat "wacom,w9013" specially in
the driver, apart from possibly listing it in the driver of_match_table.
This was mentioned by Dmitry earlier, and I didn't see any objection.
(Note that there are problems with module autoload when using multiple
compatible strings like above. May not be supremely relevant to the
documentation, but it *is* practically important.)
> reg = <0x2c>;
> hid-descr-addr = <0x0020>;
> interrupt-parent = <&gpx3>;
> interrupts = <3 2>;
> vdd-supply = <sth>;
Document and support 'vdd-supply', optionally.
> init-delay-ms = <100>;
Per Rob's mention below, support this as 'post-power-on-delay-ms',
optionally.
We can use either of these properties on any device, with the
intention that if there are future needs for divergent bindings, the
aforementioned compatible property can help us differentiate.
> };
>
> vs.
>
> i2c-hid-dev@2c {
> compatible = "hid-over-i2c";
> reg = <0x2c>;
> hid-descr-addr = <0x0020>;
> interrupt-parent = <&gpx3>;
> interrupts = <3 2>;
> vdd-supply = <sth>;
> init-delay-ms = <100>;
> };
>
> My only other nit is use "post-power-on-delay-ms" which is already a
> defined property name rather than "init-delay-ms".
Any objections? Speak now or forever [1] hold your peace.
Brian
[1] Who am I kidding? There's always room for more paint on the
bikeshed.
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^ permalink raw reply
* Re: [RFT PATCH] ARM64: dts: meson-gxbb: Add reserved memory zone and usable memory range
From: Heinrich Schuchardt @ 2016-12-12 18:23 UTC (permalink / raw)
To: Neil Armstrong, khilman-rdvid1DuHRBWk0Htik3J/w,
carlo-KA+7E9HrN00dnm+yROfE0A
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161212101801.28491-1-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On 12/12/2016 11:18 AM, Neil Armstrong wrote:
> The Amlogic Meson GXBB secure monitor uses part of the memory space, this
> patch adds these reserved zones and redefines the usable memory range for
> each boards.
>
> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 21 +++++++++++++++++++++
> .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts | 2 +-
> .../boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts | 2 +-
> .../boot/dts/amlogic/meson-gxl-nexbox-a95x.dts | 2 +-
> .../arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 2 +-
> arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +-
> 11 files changed, 31 insertions(+), 10 deletions(-)
>
I added your patch to next-20161212.
My kernel config is available as
https://github.com/xypron/kernel-odroid-c2/blob/5ec4be0c1b45297bbcbc1ce3d3d787e45dac66b6/config/config-next-20161212
To build the same kernel just run ./build-dpkg.sh (or make) on
https://github.com/xypron/kernel-odroid-c2/tree/5ec4be0c1b45297bbcbc1ce3d3d787e45dac66b6
Free showed 0x2301000 less total memory available than next-20161209
without the patch.
When git cloning linux-next I got the following error on Hardkernel
Odroid C2:
[ 811.602365] Bad mode in Error handler detected on CPU2, code
0xbf000000 -- SError
[ 811.604205] CPU: 2 PID: 1447 Comm: git Not tainted
4.9.0-next-20161212-r005-arm64 #1
[ 811.611876] Hardware name: Hardkernel ODROID-C2 (DT)
[ 811.616793] task: ffff8000745c5780 task.stack: ffff800072d3c000
[ 811.622660] PC is at 0xaaaad3770f28
[ 811.626107] LR is at 0xffffab54e53c
[ 811.629558] pc : [<0000aaaad3770f28>] lr : [<0000ffffab54e53c>]
pstate: 20000000
[ 811.636888] sp : 0000ffffd3a1d950
[ 811.640166] x29: 0000ffffd3a1d950 x28: 0000ffff9853a050
[ 811.645427] x27: 00000000000ffc5e x26: 0000ffff8fe00020
[ 811.650688] x25: 0000ffffd3a1da98 x24: 0000000000000000
[ 811.655949] x23: 0000aaaad3770f28 x22: 0000000000000010
[ 811.661211] x21: 0000ffff9809bae0 x20: 000000000003de04
[ 811.666472] x19: 0000ffff8fe00010 x18: 0000000023c57c32
[ 811.671733] x17: 0000ffffab58f988 x16: 0000ffffab660008
[ 811.676994] x15: 00000000000006dc x14: 0000000000000000
[ 811.682255] x13: 00000000002549ea x12: 0000000029555c36
[ 811.687517] x11: 00000000002549eb x10: 0000000029555c36
[ 811.692778] x9 : 00000000002549ea x8 : 0000000029555c36
[ 811.698039] x7 : 00000000002549e9 x6 : 0000000029555c36
[ 811.703300] x5 : 0000ffff98d54b40 x4 : 0000ffff8f93c030
[ 811.708562] x3 : 00000000ffffffff x2 : 0000000000000000
[ 811.713823] x1 : 0000ffff9853a050 x0 : 0000ffff9809bae0
[ 811.720561] Internal error: Attempting to execute userspace memory:
8600000f [#1] PREEMPT SMP
[ 811.729004] Modules linked in: meson_rng rng_core ip_tables x_tables
ipv6 realtek
[ 811.736422] CPU: 2 PID: 1447 Comm: git Not tainted
4.9.0-next-20161212-r005-arm64 #1
[ 811.744097] Hardware name: Hardkernel ODROID-C2 (DT)
[ 811.749014] task: ffff8000745c5780 task.stack: ffff800072d3c000
[ 811.754879] PC is at 0xffffab54e53c
[ 811.758328] LR is at 0xffffab54e53c
[ 811.761779] pc : [<0000ffffab54e53c>] lr : [<0000ffffab54e53c>]
pstate: 600003c5
[ 811.769109] sp : ffff800072d3fec0
[ 811.772387] x29: 0000000000000000 x28: ffff8000745c5780
[ 811.777648] x27: 00000000000ffc5e x26: 0000ffff8fe00020
[ 811.782909] x25: 0000ffffd3a1da98 x24: 0000000000000000
[ 811.788171] x23: 0000000020000000 x22: 0000aaaad3770f28
[ 811.793432] x21: ffffffffffffffff x20: 000080006e538000
[ 811.798693] x19: 0000000000000000 x18: 0000000000000010
[ 811.803954] x17: 0000ffffab58f988 x16: 0000ffffab660008
[ 811.809215] x15: 0000000000000006 x14: ffff000088b2eabf
[ 811.814477] x13: ffff000008b2eacd x12: 0000000000000105
[ 811.819738] x11: 0000000000000002 x10: 0000000000000106
[ 811.824999] x9 : ffff800072d3fb40 x8 : 00000000000af8ec
[ 811.830260] x7 : 0000000000000000 x6 : 0000000000000a65
[ 811.835522] x5 : 000000000a660a65 x4 : 0000000000000000
[ 811.840783] x3 : 0000000000000002 x2 : 0000000000000a66
[ 811.846044] x1 : ffff8000745c5780 x0 : 0000000000000000
[ 811.852773] Process git (pid: 1447, stack limit = 0xffff800072d3c000)
[ 811.859156] Stack: (0xffff800072d3fec0 to 0xffff800072d40000)
[ 811.864849] fec0: 0000ffff9809bae0 0000ffff9853a050 0000000000000000
00000000ffffffff
[ 811.872611] fee0: 0000ffff8f93c030 0000ffff98d54b40 0000000029555c36
00000000002549e9
[ 811.880374] ff00: 0000000029555c36 00000000002549ea 0000000029555c36
00000000002549eb
[ 811.888136] ff20: 0000000029555c36 00000000002549ea 0000000000000000
00000000000006dc
[ 811.895898] ff40: 0000ffffab660008 0000ffffab58f988 0000000023c57c32
0000ffff8fe00010
[ 811.903661] ff60: 000000000003de04 0000ffff9809bae0 0000000000000010
0000aaaad3770f28
[ 811.911423] ff80: 0000000000000000 0000ffffd3a1da98 0000ffff8fe00020
00000000000ffc5e
[ 811.919186] ffa0: 0000ffff9853a050 0000ffffd3a1d950 0000ffffab54e53c
0000ffffd3a1d950
[ 811.926949] ffc0: 0000aaaad3770f28 0000000020000000 0000000000000000
ffffffffffffffff
[ 811.934711] ffe0: 0000000000000000 0000000000000000 3136363920746e61
3064613364666464
[ 811.942473] Call trace:
[ 811.944888] Exception stack(0xffff800072d3fcf0 to 0xffff800072d3fe20)
[ 811.951270] fce0: 0000000000000000
0001000000000000
[ 811.959034] fd00: ffff800072d3fec0 0000ffffab54e53c ffff8000731ab640
0000000000000000
[ 811.966796] fd20: 0000000000000004 ffff000008ab9818 ffff8000745c5780
000000000808540c
[ 811.974559] fd40: ffff800072d3fd90 ffff0000080c8858 ffff800072d3fe40
ffff8000745c5780
[ 811.982321] fd60: 0000000000000004 00000000000003c0 ffff800072d3fe40
0000000000000000
[ 811.990084] fd80: 0000ffffd3a1da98 0000ffff8fe00020 0000000000000000
ffff8000745c5780
[ 811.997846] fda0: 0000000000000a66 0000000000000002 0000000000000000
000000000a660a65
[ 812.005609] fdc0: 0000000000000a65 0000000000000000 00000000000af8ec
ffff800072d3fb40
[ 812.013371] fde0: 0000000000000106 0000000000000002 0000000000000105
ffff000008b2eacd
[ 812.021134] fe00: ffff000088b2eabf 0000000000000006 0000ffffab660008
0000ffffab58f988
[ 812.028896] [<0000ffffab54e53c>] 0xffffab54e53c
[ 812.033382] Code: aa1c03e1 aa1503e0 8b16027a d63f02e0 (7100001f)
[ 812.039501] ---[ end trace e791f586be1831bb ]---
--
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^ permalink raw reply
* Re: [PATCH 4/4] dt-bindings: input: Specify the interrupt number of TPS65217 power button
From: Rob Herring @ 2016-12-12 17:27 UTC (permalink / raw)
To: Milo Kim
Cc: bcousson-rdvid1DuHRBWk0Htik3J/w, Tony Lindgren, Arnd Bergmann,
Lee Jones, Sebastian Reichel, Dmitry Torokhov,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161209062833.5768-5-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Dec 09, 2016 at 03:28:33PM +0900, Milo Kim wrote:
> Specify the power button interrupt number which is from the datasheet.
>
> Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: [PATCH 3/4] dt-bindings: power/supply: Update TPS65217 properties
From: Rob Herring @ 2016-12-12 17:26 UTC (permalink / raw)
To: Milo Kim
Cc: bcousson, Tony Lindgren, Arnd Bergmann, Lee Jones,
Sebastian Reichel, Dmitry Torokhov, linux-omap, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20161209062833.5768-4-woogyom.kim@gmail.com>
On Fri, Dec 09, 2016 at 03:28:32PM +0900, Milo Kim wrote:
> Add interrupt specifiers for USB and AC charger input. Interrupt numbers
> are from the datasheet.
> Fix wrong property for compatible string.
>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
> ---
> .../devicetree/bindings/power/supply/tps65217_charger.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: mfd: Remove TPS65217 interrupts
From: Rob Herring @ 2016-12-12 17:25 UTC (permalink / raw)
To: Milo Kim
Cc: bcousson-rdvid1DuHRBWk0Htik3J/w, Tony Lindgren, Arnd Bergmann,
Lee Jones, Sebastian Reichel, Dmitry Torokhov,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161209062833.5768-3-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Dec 09, 2016 at 03:28:31PM +0900, Milo Kim wrote:
> Interrupt numbers are from the datasheet, so no need to keep them in
> the ABI. Use the number in the DT file.
I don't see the purpose of ripping this out. The headers have always
been for convienence, not whether the values come from the datasheet or
not.
> Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/boot/dts/am335x-bone-common.dtsi | 8 +++-----
> include/dt-bindings/mfd/tps65217.h | 26 --------------------------
> 2 files changed, 3 insertions(+), 31 deletions(-)
> delete mode 100644 include/dt-bindings/mfd/tps65217.h
--
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^ permalink raw reply
* Re: [PATCH] dt-bindings: Document the hi3660 reset bindings
From: Rob Herring @ 2016-12-12 17:20 UTC (permalink / raw)
To: Zhangfei Gao; +Cc: linux-arm-kernel, devicetree, Arnd Bergmann, Philipp Zabel
In-Reply-To: <1481249504-7942-1-git-send-email-zhangfei.gao@linaro.org>
On Fri, Dec 09, 2016 at 10:11:44AM +0800, Zhangfei Gao wrote:
> Add DT bindings documentation for hi3660 SoC reset controller.
>
> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
> .../bindings/reset/hisilicon,hi3660-reset.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] iio: misc: add a generic regulator driver
From: Lars-Peter Clausen @ 2016-12-12 17:15 UTC (permalink / raw)
To: Bartosz Golaszewski, Jonathan Cameron
Cc: Hartmut Knaack, Peter Meerwald-Stadler, Rob Herring, Mark Rutland,
linux-iio, linux-devicetree, LKML, Kevin Hilman, Patrick Titiano,
Neil Armstrong, Liam Girdwood, Mark Brown
In-Reply-To: <CAMpxmJVJ+y9tRbRBsVg+i0EJO_6EFuvrypwC=ETnBWbMnxRFyg@mail.gmail.com>
On 12/06/2016 12:12 PM, Bartosz Golaszewski wrote:
> 2016-12-03 10:11 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
>> On 30/11/16 10:10, Lars-Peter Clausen wrote:
>>> On 11/29/2016 04:35 PM, Bartosz Golaszewski wrote:
>>>> 2016-11-29 16:30 GMT+01:00 Lars-Peter Clausen <lars@metafoo.de>:
>>>>> On 11/29/2016 04:22 PM, Bartosz Golaszewski wrote:
>>>>> [...]
>>>>>> diff --git a/Documentation/devicetree/bindings/iio/misc/iio-regulator.txt b/Documentation/devicetree/bindings/iio/misc/iio-regulator.txt
>>>>>> new file mode 100644
>>>>>> index 0000000..147458f
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/iio/misc/iio-regulator.txt
>>>>>> @@ -0,0 +1,18 @@
>>>>>> +Industrial IO regulator device driver
>>>>>> +-------------------------------------
>>>>>> +
>>>>>> +This document describes the bindings for the iio-regulator - a dummy device
>>>>>> +driver representing a physical regulator within the iio framework.
>>>>>
>>>>> No bindings for drivers, only for hardware. So this wont work.
>>>>>
>>>>
>>>> What about exporting regulator attributes analogous to the one in this
>>>> patch from the iio-core when a *-supply property is specified for a
>>>> node?
>>>
>>> The problem with exposing direct control to the regulator is that it allows
>>> to modify the hardware state without the drivers knowledge. If you
>>> power-cycle a device all previous configuration that has been written to the
>>> device is reset. The device driver needs to be aware of this otherwise its
>>> assumed state and the actual device state can divert which will result in
>>> undefined behavior. Also access to the device will fail unexpectedly when
>>> the regulator is turned off. So I think generally the driver should
>>> explicitly control the regulator, power-up when needed, power-down when not.
>> I agree with what Lars has said.
>>
>> There 'may' be some argument to ultimately have a bridge driver from
>> regulators to IIO. That would be for cases where the divide between a regulator
>> and a DAC is blurred. However it would still have to play nicely with the
>> regulator framework and any other devices registered on that regulator.
>> Ultimately the ideal in that case would then be to describe what the DAC is
>> actually being used to do but that's a more complex issue!
>>
>> That doesn't seem to be what you are targeting here.
>>
>> What it sounds like you need is to have the hardware well enough described that
>> the standard runtime power management can disable the regulator just fine when
>> it is not in use. This may mean improving the power management in the relevant
>> drivers.
>>
>> Jonathan
>>
>> p.s. If ever proposing to do something 'unusual' with a regulator you should
>> bring in the regulator framework maintainers in the cc list.
>>>
>>> - Lars
>>>
>>
>
> I wrote the initial patch quickly and didn't give it much of a
> thought. Now I realized I completely missed the point and managed to
> confuse everybody - myself included.
>
> So the problem we have is not power-cycling the adc - it's
> power-cycling the device connected to a probe on which there's an adc.
> What I was trying to do was adding support for the power-switch on
> baylibre-acme[1] probes.
>
> For example: we have a USB probe on which the VBUS signal goes through
> a power load switch and than through the adc. The adc (in this case
> ina226) is always powered on, while the fixed regulator I wanted to
> enable/disable actually drives the power switch to cut/restore power
> to the connected USB device i.e. there's no real regulator - just a
> GPIO driving the power switch.
>
> A typical use case is measuring the power consumption of development
> boards[2]. Rebooting them remotely using acme probes is already done,
> but we're using the obsolete /sys/class/gpio interface.
>
> We're already using libiio to read the measured data from the power
> monitor, that's why we'd like to use the iio framework for
> power-cycling the devices as well. My question is: would bridging the
> regulator framework be the right solution? Should we look for
> something else? Bridge the GPIO framework instead?
I wouldn't necessaries create bridge, but instead just use the GPIO
framework directly.
We now have the GPIO chardev interface which meant to be used to support
application specific logic that control the GPIOs, but where you don't want
to write a kernel driver.
My idea was to add GPIOs and GPIO chips as high level object inside libiio
that can be accessed through the same context as the IIO devices. Similar to
the current IIO API you have a API for gpios that allows to enumerate the
GPIO devices and their pins as well as modify the pin state.
^ permalink raw reply
* Re: [PATCH v2 3/6] Documentation: DT: Add bmi160 imu binding
From: Rob Herring @ 2016-12-12 17:15 UTC (permalink / raw)
To: Marcin Niestroj
Cc: Jonathan Cameron, Peter Meerwald-Stadler, Hartmut Knaack,
Lars-Peter Clausen, Daniel Baluta, Gregor Boirie, Sanchayan Maity,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161208142259.26230-4-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
On Thu, Dec 08, 2016 at 03:22:56PM +0100, Marcin Niestroj wrote:
> This adds documentation for Bosch BMI160 Inertial Measurement Unit
> device-tree bindings.
>
> Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
> ---
> Changes v1 -> v2 (suggested by Rob):
> * remove "gpio" keyword from interrupts property description
> * describe "INT1" and "INT2" cases for interrupt-names property
>
> .../devicetree/bindings/iio/imu/bmi160.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
> new file mode 100644
> index 0000000..ae0112c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
> @@ -0,0 +1,36 @@
> +Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
> +and externally connectable Magnetometer
> +
> +https://www.bosch-sensortec.com/bst/products/all_products/bmi160
> +
> +Required properties:
> + - compatible : should be "bosch,bmi160"
> + - reg : the I2C address or SPI chip select number of the sensor
> + - spi-max-frequency : set maximum clock frequency (only for SPI)
> +
> +Optional properties:
> + - interrupt-parent : should be the phandle of the interrupt controller
> + - interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW
> + - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
> + input, set to "INT2" if INT2 pin should be used instead
> +
> +Examples:
> +
> +bmi160@68 {
> + compatible = "bosch,bmi160";
> + reg = <0x68>;
> +
> + interrupt-parent = <&gpio4>;
> + interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "INT1";
> +};
> +
> +bmi160@0 {
> + compatible = "bosch,bmi160";
> + reg = <0>;
> + spi-max-frequency = <10000000>;
> +
> + interrupt-parent = <&gpio2>;
> + interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "INT2";
> +};
> --
> 2.10.2
>
^ permalink raw reply
* Re: [PATCH v5 2/2] mmc: sdhci-cadence: add Cadence SD4HC support
From: Rob Herring @ 2016-12-12 17:14 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mmc-u79uwXL29TY76Z2rM5mHXA, Adrian Hunter, Ulf Hansson,
Douglas Anderson, devicetree-u79uwXL29TY76Z2rM5mHXA, Al Cooper,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Stefan Wahren,
Andrei Pistirica, Wolfram Sang, Mark Rutland, Simon Horman
In-Reply-To: <1481201455-3483-3-git-send-email-yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
On Thu, Dec 08, 2016 at 09:50:55PM +0900, Masahiro Yamada wrote:
> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller.
>
> For SD, it basically relies on the SDHCI standard code.
> For eMMC, this driver provides some callbacks to support the
> hardware part that is specific to this IP design.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
>
> Changes in v5:
> - Fix calculation of the center of the tuned window
>
> Changes in v4:
> - Override mmc_host_ops.execute_tuning instead of the
> .platform_execute_tuning implementation
>
> Changes in v3:
> - Remove unneeded explanation about HRS and SRS from DT binding;
> the offsets to HRS/SRS are fixed for this hardware and this is
> quite normal, like each hardware has a fixed register view except
> the register base. The detailed register map is what the driver
> cares about, so no need to explain it in the binding.
>
> Changes in v2:
> - Remove unnecessary "select MMC_SDHCI_IO_ACCESSORS"
>
> .../devicetree/bindings/mmc/sdhci-cadence.txt | 30 +++
> drivers/mmc/host/Kconfig | 11 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-cadence.c | 283 +++++++++++++++++++++
> 4 files changed, 325 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
> create mode 100644 drivers/mmc/host/sdhci-cadence.c
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
> new file mode 100644
> index 0000000..750374f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
> @@ -0,0 +1,30 @@
> +* Cadence SD/SDIO/eMMC Host Controller
> +
> +Required properties:
> +- compatible: should be "cdns,sd4hc".
Needs SoC specific compatible strings too.
> +- reg: offset and length of the register set for the device.
> +- interrupts: a single interrupt specifier.
> +- clocks: phandle to the input clock.
> +
> +Optional properties:
> +For eMMC configuration, supported speed modes are not indicated by the SDHCI
> +Capabilities Register. Instead, the following properties should be specified
> +if supported. See mmc.txt for details.
> +- mmc-ddr-1_8v
> +- mmc-ddr-1_2v
> +- mmc-hs200-1_8v
> +- mmc-hs200-1_2v
> +- mmc-hs400-1_8v
> +- mmc-hs400-1_2v
There's now a property to override SDHCI capabilities register. Maybe
you should use that instead? I'll defer to Ulf.
> +
> +Example:
> + emmc: sdhci@5a000000 {
> + compatible = "cdns,sd4hc";
> + reg = <0x5a000000 0x400>;
> + interrupts = <0 78 4>;
> + clocks = <&clk 4>;
> + bus-width = <8>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + };
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: zx296718-clk: add compatible for audio clock controller
From: Rob Herring @ 2016-12-12 17:10 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, Stephen Boyd, Mark Rutland, Baoyou Xie,
Jun Nie, linux-clk, devicetree, linux-arm-kernel, Shawn Guo
In-Reply-To: <1481189157-8995-1-git-send-email-shawnguo@kernel.org>
On Thu, Dec 08, 2016 at 05:25:56PM +0800, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds the compatible string for zx296718 audio clock controller.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> Documentation/devicetree/bindings/clock/zx296718-clk.txt | 3 +++
> 1 file changed, 3 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
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