* Re: [PATCH v6 1/2] Add OV5647 device tree documentation
From: Pavel Machek @ 2016-12-13 19:05 UTC (permalink / raw)
To: Ramiro Oliveira
Cc: mchehab, linux-kernel, linux-media, robh+dt, devicetree, davem,
gregkh, geert+renesas, akpm, linux, hverkuil, dheitmueller,
slongerbeam, lars, robert.jarzmik, pali.rohar, sakari.ailus,
mark.rutland, CARLOS.PALMINHA
In-Reply-To: <c47834c1c9c2a8e23f41a12c8717601f4a901506.1481639091.git.roliveir@synopsys.com>
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On Tue 2016-12-13 14:32:36, Ramiro Oliveira wrote:
> Create device tree bindings documentation.
>
> Signed-off-by: Ramiro Oliveira <roliveir@synopsys.com>
> ---
> .../devicetree/bindings/media/i2c/ov5647.txt | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/i2c/ov5647.txt
>
> diff --git a/Documentation/devicetree/bindings/media/i2c/ov5647.txt b/Documentation/devicetree/bindings/media/i2c/ov5647.txt
> new file mode 100644
> index 0000000..46e5e30
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/i2c/ov5647.txt
> @@ -0,0 +1,35 @@
> +Omnivision OV5647 raw image sensor
> +---------------------------------
> +
> +OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces
> +and CCI (I2C compatible) control bus.
> +
> +Required properties:
> +
> +- compatible : "ovti,ov5647";
> +- reg : I2C slave address of the sensor;
> +- clocks : Reference to the xclk clock.
> +- clock-names : Should be "xclk".
> +- clock-frequency: Frequency of the xclk clock
Nit pick: you end the lines here with ';', '.' and nothing. Pick one
:-).
Otherwise it looks good.
Acked-by: Pavel Machek <pavel@ucw.cz>
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Re: [PATCH v3 2/2] Documentation: dt: iio: add st_lsm6dsx sensor device binding
From: Rob Herring @ 2016-12-13 19:03 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, lorenzo.bianconi-qxv4g6HH51o
In-Reply-To: <20161210090218.4609-3-lorenzo.bianconi-qxv4g6HH51o@public.gmane.org>
On Sat, Dec 10, 2016 at 10:02:18AM +0100, Lorenzo Bianconi wrote:
> Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi-qxv4g6HH51o@public.gmane.org>
> ---
> .../devicetree/bindings/iio/imu/st_lsm6dsx.txt | 24 ++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply
* Re: [PATCH 1/2] devicetree: add Garmin vendor prefix
From: Rob Herring @ 2016-12-13 19:02 UTC (permalink / raw)
To: Matt Ranostay; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1481351734-23452-1-git-send-email-matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
On Fri, Dec 09, 2016 at 10:35:34PM -0800, Matt Ranostay wrote:
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 64fdc8c1503b..aedd9979d1e9 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -106,6 +106,7 @@ firefly Firefly
> focaltech FocalTech Systems Co.,Ltd
> friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd
> fsl Freescale Semiconductor
> +garmin Garmin Limited
Stock tickers are preferred and Garmin's is grmn.
> ge General Electric Company
> geekbuying GeekBuying
> gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
> --
> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: add DT binding for s3c2410 USB device controller
From: Rob Herring @ 2016-12-13 18:59 UTC (permalink / raw)
To: Sergio Prado
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, mark.rutland-5wv7dgnIgG8,
balbi-DgEjT+Ai2ygdnm+yROfE0A, linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1481310400-28676-2-git-send-email-sergio.prado-1e4yhPs3/ABSwrhanM7KvQ@public.gmane.org>
On Fri, Dec 09, 2016 at 05:06:39PM -0200, Sergio Prado wrote:
> Adds the device tree bindings description for Samsung S3C2410 and
> compatible USB device controller.
>
> Signed-off-by: Sergio Prado <sergio.prado-1e4yhPs3/ABSwrhanM7KvQ@public.gmane.org>
> ---
> .../devicetree/bindings/usb/s3c2410-usb.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt
> index e45b38ce2986..4d3f9894c2d4 100644
> --- a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt
> @@ -20,3 +20,31 @@ usb0: ohci@49000000 {
> clocks = <&clocks UCLK>, <&clocks HCLK_USBH>;
> clock-names = "usb-bus-host", "usb-host";
> };
> +
> +Samsung S3C2410 and compatible USB device controller
> +
> +Required properties:
> + - compatible: Should be one of the following
> + "samsung,s3c2410-udc"
> + "samsung,s3c2440-udc"
> + - reg: address and length of the controller memory mapped region
> + - interrupts: interrupt number for the USB device controller
> + - clocks: Should reference the bus and host clocks
> + - clock-names: Should contain two strings
> + "usb-bus-gadget" for the USB bus clock
Pretty sure the h/w clock name in the datasheet does not use the Linux
term gadget.
> + "usb-device" for the USB device clock
> +
> +Optional properties:
> + - samsung,vbus-gpio: If present, specifies a gpio that needs to be
> + activated for the bus to be powered.
Isn't it the host side that controls Vbus?
> + - samsung,pullup-gpio: If present, specifies a gpio to control the
Both GPIOs need to specify the active state.
> + USB D+ pullup.
> +
> +usb1: udc@52000000 {
> + compatible = "samsung,s3c2440-udc";
> + reg = <0x52000000 0x100000>;
> + interrupts = <0 0 25 3>;
> + clocks = <&clocks UCLK>, <&clocks HCLK_USBD>;
> + clock-names = "usb-bus-gadget", "usb-device";
> + samsung,pullup-gpio = <&gpc 5 GPIO_ACTIVE_HIGH>;
> +};
> --
> 1.9.1
>
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^ permalink raw reply
* Re: [PATCH] MIPS: NI 169445 board support
From: Nathan Sullivan @ 2016-12-13 18:56 UTC (permalink / raw)
To: Paul Burton
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA,
mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3462760.PnFL9sJqBx@np-p-burton>
On Tue, Dec 13, 2016 at 06:40:31PM +0000, Paul Burton wrote:
> Hi Nathan,
>
> On Friday, 2 December 2016 09:42:09 GMT Nathan Sullivan wrote:
> > Support the National Instruments 169445 board.
> >
> > Signed-off-by: Nathan Sullivan <nathan.sullivan-acOepvfBmUk@public.gmane.org>
> > ---
> > "gpio: mmio: add support for NI 169445 NAND GPIO" and
> > "devicetree: add vendor prefix for National Instruments" are required for
> > the NAND on this board to work.
> >
> > Documentation/devicetree/bindings/mips/ni.txt | 7 ++
> > arch/mips/Kbuild.platforms | 1 +
> > arch/mips/Kconfig | 26 ++++++
> > arch/mips/boot/dts/Makefile | 1 +
> > arch/mips/boot/dts/ni/169445.dts | 99 +++++++++++++++++++++
> > arch/mips/boot/dts/ni/Makefile | 9 ++
> > arch/mips/configs/ni169445_defconfig | 120 ++++++++++++++++++++++++++
> > arch/mips/ni169445/169445-console.c | 38 ++++++++
> > arch/mips/ni169445/169445-init.c | 39 +++++++++
> > arch/mips/ni169445/169445-int.c | 34 ++++++++
> > arch/mips/ni169445/169445-setup.c | 58 +++++++++++++
> > arch/mips/ni169445/169445-time.c | 35 ++++++++
> > arch/mips/ni169445/Makefile | 9 ++
> > arch/mips/ni169445/Platform | 6 ++
> > 14 files changed, 482 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
> > create mode 100644 arch/mips/boot/dts/ni/169445.dts
> > create mode 100644 arch/mips/boot/dts/ni/Makefile
> > create mode 100644 arch/mips/configs/ni169445_defconfig
> > create mode 100644 arch/mips/ni169445/169445-console.c
> > create mode 100644 arch/mips/ni169445/169445-init.c
> > create mode 100644 arch/mips/ni169445/169445-int.c
> > create mode 100644 arch/mips/ni169445/169445-setup.c
> > create mode 100644 arch/mips/ni169445/169445-time.c
> > create mode 100644 arch/mips/ni169445/Makefile
> > create mode 100644 arch/mips/ni169445/Platform
> >
> > diff --git a/Documentation/devicetree/bindings/mips/ni.txt
> > b/Documentation/devicetree/bindings/mips/ni.txt new file mode 100644
> > index 0000000..722bf2d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mips/ni.txt
> > @@ -0,0 +1,7 @@
> > +National Instruments MIPS platforms
> > +
> > +required root node properties:
> > + - compatible: must be "ni,169445"
> > +
> > +CPU Nodes
> > + - compatible: must be "mti,mips14KEc"
>
> This doesn't describe anything else you rely on, like the
> mips-hpt-frequency property which you panic without.
>
> > diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> > index f5f1bdb..f2d7b5c 100644
> > --- a/arch/mips/Kbuild.platforms
> > +++ b/arch/mips/Kbuild.platforms
> > @@ -20,6 +20,7 @@ platforms += loongson32
> > platforms += loongson64
> > platforms += mti-malta
> > platforms += netlogic
> > +platforms += ni169445
> > platforms += paravirt
> > platforms += pic32
> > platforms += pistachio
> > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> > index b3c5bde..d24d11f 100644
> > --- a/arch/mips/Kconfig
> > +++ b/arch/mips/Kconfig
> > @@ -574,6 +574,32 @@ config NXP_STB225
> > help
> > Support for NXP Semiconductors STB225 Development Board.
> >
> > +config NI_169445
> > + bool "NI 169445 board"
> > + select ARCH_WANT_OPTIONAL_GPIOLIB
> > + select BOOT_ELF32
> > + select BOOT_RAW
> > + select BUILTIN_DTB
> > + select CEVT_R4K
> > + select CSRC_R4K
> > + select CPU_MIPSR2_IRQ_VI
> > + select CPU_MIPSR2_IRQ_EI
> > + select DMA_NONCOHERENT
> > + select IRQ_MIPS_CPU
> > + select LIBFDT
> > + select MIPS_MSC
> > + select SYS_HAS_CPU_MIPS32_R1
> > + select SYS_HAS_CPU_MIPS32_R2
> > + select SYS_HAS_EARLY_PRINTK
> > + select SYS_SUPPORTS_32BIT_KERNEL
> > + select SYS_SUPPORTS_LITTLE_ENDIAN
> > + select USE_OF
> > + select COMMON_CLK
> > + help
> > + This enables support for the National Instruments 169445A
> > + board.
> > +
> > +
> > config PMC_MSP
> > bool "PMC-Sierra MSP chipsets"
> > select CEVT_R4K
> > diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> > index fc7a0a9..65a0ad8 100644
> > --- a/arch/mips/boot/dts/Makefile
> > +++ b/arch/mips/boot/dts/Makefile
> > @@ -3,6 +3,7 @@ dts-dirs += cavium-octeon
> > dts-dirs += ingenic
> > dts-dirs += lantiq
> > dts-dirs += mti
> > +dts-dirs += ni
> > dts-dirs += netlogic
> > dts-dirs += pic32
> > dts-dirs += qca
> > diff --git a/arch/mips/boot/dts/ni/169445.dts
> > b/arch/mips/boot/dts/ni/169445.dts new file mode 100644
> > index 0000000..a2b49f9
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/ni/169445.dts
> > @@ -0,0 +1,99 @@
> > +/dts-v1/;
> > +
> > +/ {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "ni,169445";
> > +
> > + cpus {
> > + mips-hpt-frequency = <25000000>;
> > +
> > + cpu@0 {
> > + compatible = "mti,mips14KEc";
> > + };
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0x0 0x08000000>;
> > + };
> > +
> > + clocks {
> > + baseclk: baseclock {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > + };
> > +
> > + cpu_intc: cpu_intc {
> > + #address-cells = <0>;
> > + compatible = "mti,cpu-interrupt-controller";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > +
> > + ahb@0 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + gpio1: nand-gpio-out@1f300010 {
> > + compatible = "ni,169445-nand-gpio";
> > + reg = <0x1f300010 0x4>;
> > + reg-names = "dat";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + ngpios = <5>;
> > + };
> > +
> > + gpio2: nand-gpio-in@1f300014 {
> > + compatible = "ni,169445-nand-gpio";
> > + reg = <0x1f300014 0x4>;
> > + reg-names = "dat";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + ngpios = <1>;
> > + };
> > +
> > + nand@1f300000 {
> > + compatible = "gpio-control-nand";
> > + nand-on-flash-bbt;
> > + nand-ecc-mode = "soft_bch";
> > + nand-ecc-step-size = <512>;
> > + nand-ecc-strength = <4>;
> > + reg = <0x1f300000 4>;
> > + gpios = <&gpio2 0 0>, /* rdy */
> > + <&gpio1 1 0>, /* nce */
> > + <&gpio1 2 0>, /* ale */
> > + <&gpio1 3 0>, /* cle */
> > + <&gpio1 4 0>; /* nwp */
> > + };
> > +
> > + serial@1f380000 {
> > + compatible = "ns16550a";
> > + reg = <0x1f380000 0x1000>;
> > + interrupt-parent = <&cpu_intc>;
> > + interrupts = <6>;
> > + clocks = <&baseclk>;
> > + reg-shift = <0>;
> > + };
> > +
> > + ethernet@1f340000 {
> > + compatible = "snps,dwc-qos-ethernet-4.10";
> > + interrupt-parent = <&cpu_intc>;
> > + interrupts = <5>;
> > + reg = <0x1f340000 0x2000>;
> > + clock-names = "apb_pclk", "phy_ref_clk";
> > + clocks = <&baseclk>, <&baseclk>;
> > +
> > + phy-mode = "rgmii";
> > +
> > + fixed-link {
> > + speed = <1000>;
> > + full-duplex;
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
> > new file mode 100644
> > index 0000000..5291c18
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/ni/Makefile
> > @@ -0,0 +1,9 @@
> > +dtb-$(CONFIG_NI_169445) += 169445.dtb
> > +
> > +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> > +
> > +# Force kbuild to make empty built-in.o if necessary
> > +obj- += dummy.o
> > +
> > +always := $(dtb-y)
> > +clean-files := *.dtb *.dtb.S
> > diff --git a/arch/mips/configs/ni169445_defconfig
> > b/arch/mips/configs/ni169445_defconfig new file mode 100644
> > index 0000000..e5a34df
> > --- /dev/null
> > +++ b/arch/mips/configs/ni169445_defconfig
> > @@ -0,0 +1,120 @@
> > +CONFIG_NI_169445=y
> > +CONFIG_CPU_MIPS32_R2=y
> > +CONFIG_HZ_100=y
> > +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
> > +# CONFIG_SWAP is not set
> > +CONFIG_SYSVIPC=y
> > +CONFIG_HZ_PERIODIC=y
> > +CONFIG_NO_HZ=y
> > +CONFIG_HIGH_RES_TIMERS=y
> > +CONFIG_IKCONFIG=y
> > +CONFIG_IKCONFIG_PROC=y
> > +CONFIG_LOG_BUF_SHIFT=15
> > +CONFIG_BLK_DEV_INITRD=y
> > +# CONFIG_RD_GZIP is not set
> > +# CONFIG_RD_LZMA is not set
> > +# CONFIG_RD_XZ is not set
> > +# CONFIG_RD_LZO is not set
> > +# CONFIG_RD_LZ4 is not set
> > +# CONFIG_SHMEM is not set
> > +CONFIG_EMBEDDED=y
> > +CONFIG_SLAB=y
> > +CONFIG_PROFILING=y
> > +# CONFIG_LBDAF is not set
> > +# CONFIG_BLK_DEV_BSG is not set
> > +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> > +# CONFIG_SUSPEND is not set
> > +CONFIG_NET=y
> > +CONFIG_PACKET=y
> > +CONFIG_UNIX=y
> > +CONFIG_INET=y
> > +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> > +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> > +# CONFIG_INET_XFRM_MODE_BEET is not set
> > +# CONFIG_INET_DIAG is not set
> > +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
> > +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
> > +CONFIG_NETFILTER=y
> > +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> > +CONFIG_IP_NF_IPTABLES=y
> > +CONFIG_IP_NF_FILTER=y
> > +CONFIG_IP6_NF_IPTABLES=y
> > +CONFIG_IP6_NF_FILTER=y
> > +# CONFIG_WIRELESS is not set
> > +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> > +CONFIG_DEVTMPFS=y
> > +CONFIG_DEVTMPFS_MOUNT=y
> > +CONFIG_MTD=y
> > +CONFIG_MTD_CMDLINE_PARTS=y
> > +CONFIG_MTD_BLOCK_RO=y
> > +CONFIG_MTD_NAND=y
> > +CONFIG_MTD_NAND_ECC_BCH=y
> > +CONFIG_MTD_NAND_GPIO=y
> > +CONFIG_MTD_UBI=y
> > +CONFIG_MTD_UBI_BLOCK=y
> > +CONFIG_NETDEVICES=y
> > +# CONFIG_NET_VENDOR_AMAZON is not set
> > +# CONFIG_NET_VENDOR_ARC is not set
> > +# CONFIG_NET_CADENCE is not set
> > +# CONFIG_NET_VENDOR_BROADCOM is not set
> > +# CONFIG_NET_VENDOR_EZCHIP is not set
> > +# CONFIG_NET_VENDOR_INTEL is not set
> > +# CONFIG_NET_VENDOR_MARVELL is not set
> > +# CONFIG_NET_VENDOR_MICREL is not set
> > +# CONFIG_NET_VENDOR_NATSEMI is not set
> > +# CONFIG_NET_VENDOR_NETRONOME is not set
> > +# CONFIG_NET_VENDOR_QUALCOMM is not set
> > +# CONFIG_NET_VENDOR_RENESAS is not set
> > +# CONFIG_NET_VENDOR_ROCKER is not set
> > +# CONFIG_NET_VENDOR_SAMSUNG is not set
> > +# CONFIG_NET_VENDOR_SEEQ is not set
> > +# CONFIG_NET_VENDOR_SMSC is not set
> > +# CONFIG_NET_VENDOR_STMICRO is not set
> > +CONFIG_SYNOPSYS_DWC_ETH_QOS=y
> > +# CONFIG_NET_VENDOR_VIA is not set
> > +# CONFIG_NET_VENDOR_WIZNET is not set
> > +# CONFIG_NET_VENDOR_XILINX is not set
> > +# CONFIG_WLAN is not set
> > +# CONFIG_INPUT_MOUSEDEV is not set
> > +# CONFIG_INPUT_KEYBOARD is not set
> > +# CONFIG_INPUT_MOUSE is not set
> > +# CONFIG_SERIO is not set
> > +# CONFIG_CONSOLE_TRANSLATIONS is not set
> > +CONFIG_VT_HW_CONSOLE_BINDING=y
> > +CONFIG_LEGACY_PTY_COUNT=32
> > +CONFIG_SERIAL_8250=y
> > +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
> > +CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_NR_UARTS=2
> > +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
> > +CONFIG_SERIAL_OF_PLATFORM=y
> > +# CONFIG_HW_RANDOM is not set
> > +CONFIG_GPIOLIB=y
> > +CONFIG_GPIO_SYSFS=y
> > +CONFIG_GPIO_GENERIC_PLATFORM=y
> > +# CONFIG_HWMON is not set
> > +# CONFIG_VGA_CONSOLE is not set
> > +# CONFIG_HID is not set
> > +# CONFIG_USB_SUPPORT is not set
> > +# CONFIG_MIPS_PLATFORM_DEVICES is not set
> > +# CONFIG_IOMMU_SUPPORT is not set
> > +CONFIG_UBIFS_FS=y
> > +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
> > +# CONFIG_UBIFS_FS_ZLIB is not set
> > +CONFIG_SQUASHFS=y
> > +# CONFIG_SQUASHFS_ZLIB is not set
> > +CONFIG_SQUASHFS_LZO=y
> > +CONFIG_SQUASHFS_XZ=y
> > +# CONFIG_NETWORK_FILESYSTEMS is not set
> > +# CONFIG_FTRACE is not set
> > +CONFIG_CRYPTO_CBC=y
> > +CONFIG_CRYPTO_ECB=y
> > +CONFIG_CRYPTO_CRC32C=y
> > +CONFIG_CRYPTO_ARC4=y
> > +# CONFIG_CRYPTO_HW is not set
> > +# CONFIG_XZ_DEC_X86 is not set
> > +# CONFIG_XZ_DEC_POWERPC is not set
> > +# CONFIG_XZ_DEC_IA64 is not set
> > +# CONFIG_XZ_DEC_ARM is not set
> > +# CONFIG_XZ_DEC_ARMTHUMB is not set
> > +# CONFIG_XZ_DEC_SPARC is not set
> > diff --git a/arch/mips/ni169445/169445-console.c
> > b/arch/mips/ni169445/169445-console.c new file mode 100644
> > index 0000000..f07e48b
> > --- /dev/null
> > +++ b/arch/mips/ni169445/169445-console.c
> > @@ -0,0 +1,38 @@
> > +/* Copyright 2016 National Instruments Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > Free + * Software Foundation; either version 2 of the License, or (at your
> > option) + * any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > WITHOUT + * ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License for + * more details.
> > + */
> > +#include <linux/init.h>
> > +#include <linux/console.h>
> > +#include <linux/serial_reg.h>
> > +#include <linux/io.h>
> > +
> > +#define NI_UART0_REGS_BASE ((unsigned char __iomem *)0xbf380000)
> > +
> > +static inline unsigned char serial_in(int offset)
> > +{
> > + return __raw_readb(NI_UART0_REGS_BASE + offset);
> > +}
> > +
> > +static inline void serial_out(int offset, char value)
> > +{
> > + __raw_writeb(value, NI_UART0_REGS_BASE + offset);
> > +}
> > +
> > +int prom_putchar(char c)
> > +{
> > + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
> > + ;
> > +
> > + serial_out(UART_TX, c);
> > +
> > + return 1;
> > +}
>
> Could you use the generic 16550 earlycon support? (see CONFIG_SERIAL_8250_CONSOLE)
>
> > diff --git a/arch/mips/ni169445/169445-init.c
> > b/arch/mips/ni169445/169445-init.c new file mode 100644
> > index 0000000..5c7ff5e
> > --- /dev/null
> > +++ b/arch/mips/ni169445/169445-init.c
> > @@ -0,0 +1,39 @@
> > +/* Copyright 2016 National Instruments Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > Free + * Software Foundation; either version 2 of the License, or (at your
> > option) + * any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > WITHOUT + * ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License for + * more details.
> > + */
> > +#include <linux/init.h>
> > +#include <linux/initrd.h>
> > +#include <linux/io.h>
> > +
> > +#include <asm/bootinfo.h>
> > +#include <asm/cacheflush.h>
> > +#include <asm/traps.h>
> > +#include <asm/mips-boards/generic.h>
> > +#include <asm/fw/fw.h>
> > +
> > +void __init prom_init(void)
> > +{
> > + fw_init_cmdline();
> > +
> > +#ifdef CONFIG_BLK_DEV_INITRD
> > + /* Read the initrd address from the firmware environment */
> > + initrd_start = fw_getenvl("initrd_start");
> > + if (initrd_start) {
> > + initrd_start = KSEG0ADDR(initrd_start);
> > + initrd_end = initrd_start + fw_getenvl("initrd_size");
> > + }
> > +#endif
> > +}
> > +
> > +void __init prom_free_prom_memory(void)
> > +{
> > +}
> > diff --git a/arch/mips/ni169445/169445-int.c
> > b/arch/mips/ni169445/169445-int.c new file mode 100644
> > index 0000000..83caf79
> > --- /dev/null
> > +++ b/arch/mips/ni169445/169445-int.c
> > @@ -0,0 +1,34 @@
> > +/* Copyright 2016 National Instruments Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > Free + * Software Foundation; either version 2 of the License, or (at your
> > option) + * any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > WITHOUT + * ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License for + * more details.
> > + */
> > +#include <linux/init.h>
> > +#include <linux/irq.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/irqchip/mips-gic.h>
> > +#include <linux/io.h>
> > +
> > +#include <asm/irq_cpu.h>
> > +#include <asm/setup.h>
> > +
> > +static const struct of_device_id of_irq_ids[] __initconst = {
> > + {
> > + .compatible = "mti,cpu-interrupt-controller",
> > + .data = mips_cpu_irq_of_init
> > + },
> > + {},
> > +};
> > +
> > +void __init arch_init_irq(void)
> > +{
> > + of_irq_init(of_irq_ids);
> > +}
>
> The CPU interrupt controller driver already does an IRQCHIP_DECLARE to
> provide its compatible string, so can you just use irqchip_init()?
>
> > +
> > diff --git a/arch/mips/ni169445/169445-setup.c
> > b/arch/mips/ni169445/169445-setup.c new file mode 100644
> > index 0000000..80a5c91
> > --- /dev/null
> > +++ b/arch/mips/ni169445/169445-setup.c
> > @@ -0,0 +1,58 @@
> > +/* Copyright 2016 National Instruments Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > Free + * Software Foundation; either version 2 of the License, or (at your
> > option) + * any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > WITHOUT + * ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License for + * more details.
> > + */
> > +#include <linux/init.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/libfdt.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_fdt.h>
> > +
> > +#include <asm/prom.h>
> > +#include <asm/fw/fw.h>
> > +
> > +#include <asm/mips-boards/generic.h>
> > +
> > +const char *get_system_type(void)
> > +{
> > + return "NI 169445 FPGA";
> > +}
> > +
> > +void __init plat_mem_setup(void)
> > +{
> > + /*
> > + * Load the builtin devicetree. This causes the chosen node to be
> > + * parsed resulting in our memory appearing
> > + */
> > + __dt_setup_arch(__dtb_start);
> > +}
> > +
> > +void __init device_tree_init(void)
> > +{
> > + if (!initial_boot_params)
> > + return;
> > +
> > + unflatten_and_copy_device_tree();
> > +}
> > +
> > +static int __init customize_machine(void)
> > +{
> > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> > + return 0;
> > +}
> > +arch_initcall(customize_machine);
> > +
> > +static int __init plat_dev_init(void)
> > +{
> > + of_clk_init(NULL);
> > + return 0;
> > +}
> > +device_initcall(plat_dev_init);
> > diff --git a/arch/mips/ni169445/169445-time.c
> > b/arch/mips/ni169445/169445-time.c new file mode 100644
> > index 0000000..3d2499e
> > --- /dev/null
> > +++ b/arch/mips/ni169445/169445-time.c
> > @@ -0,0 +1,35 @@
> > +/* Copyright 2016 National Instruments Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > Free + * Software Foundation; either version 2 of the License, or (at your
> > option) + * any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > WITHOUT + * ANY WARRANTY; without even the implied warranty of
> > MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > General Public License for + * more details.
> > + */
> > +
> > +#include <linux/init.h>
> > +#include <linux/of.h>
> > +
> > +#include <asm/time.h>
> > +
> > +void __init plat_time_init(void)
> > +{
> > + struct device_node *np;
> > + u32 freq;
> > +
> > + np = of_find_node_by_name(NULL, "cpus");
> > + if (!np)
> > + panic("missing 'cpus' DT node");
> > + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
> > + panic("missing 'mips-hpt-frequency' property");
>
> I think "clock-frequency" would be more standard, and the kernel would
> then just halve it to find the frequency at which the cop0 count register
> increments.
>
> > + of_node_put(np);
> > +
> > + mips_hpt_frequency = freq;
> > +
> > + /* IRQs will not work until the timer has been set at least once */
> > + write_c0_count(0);
>
> Really? Do you have any details of this, it sounds weird. Do you mean
> only the cop0 compare interrupt won't work until count is set? If so (and
> that sounds strange in itself) perhaps r4k_clockevent_init() ought to do
> this rather than some platform/board code.
>
Yes, the cop0 interrupt doesn't fire until you write count once. U-boot does
this in its MIPS timer code, and our hardware team confirmed this is the case.
I added this line before we started booting with U-boot, so it is probably fine
without it now.
> > +}
> > diff --git a/arch/mips/ni169445/Makefile b/arch/mips/ni169445/Makefile
> > new file mode 100644
> > index 0000000..f3a0c8c
> > --- /dev/null
> > +++ b/arch/mips/ni169445/Makefile
> > @@ -0,0 +1,9 @@
> > +#
> > +#
> > +obj-y := 169445-init.o \
> > + 169445-int.o 169445-setup.o \
> > + 169445-time.o
> > +
> > +obj-$(CONFIG_EARLY_PRINTK) += 169445-console.o
> > +
> > +CFLAGS_169445-setup.o = -I$(src)/../../../scripts/dtc/libfdt
> > diff --git a/arch/mips/ni169445/Platform b/arch/mips/ni169445/Platform
> > new file mode 100644
> > index 0000000..9380312
> > --- /dev/null
> > +++ b/arch/mips/ni169445/Platform
> > @@ -0,0 +1,6 @@
> > +#
> > +# National Instruments 169445 FPGA board
> > +#
> > +platform-$(CONFIG_NI_169445) += ni169445/
> > +load-$(CONFIG_NI_169445) += 0xffffffff80002000
> > +all-$(CONFIG_NI_169445) := $(COMPRESSION_FNAME).srec
>
> Could all this platform/board code be scrapped in favour of adding your
> system to the generic platform? There's some documentation over here
> which I hope to get in-tree soon:
>
> https://paulburton.eu/kernel-docs/mips/generic-platform.html
>
> You can also see some further examples of systems converted to the
> generic platform which I hope to get into mainline over the next few
> cycles over here:
>
> https://git.linux-mips.org/cgit/linux-mti.git/log/
>
> But the core of the generic platform is already there & ought to be
> usable for a system like this.
>
> Thanks,
> Paul
I think so, we aren't very different from the simpler MTI boards. I was under
the mistaken impression that MIPS didn't have a generic platform like ARM, but
I'll give this a try along with the other changes you suggested now that I
know about it.
Thanks,
Nathan
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^ permalink raw reply
* Re: [PATCH v2 1/7] ARM: dts: imx6qdl: Add VDOA compatible and clocks properties
From: Rob Herring @ 2016-12-13 18:52 UTC (permalink / raw)
To: Michael Tretter
Cc: linux-media, Philipp Zabel, devicetree, Hans Verkuil,
Mauro Carvalho Chehab, Philipp Zabel
In-Reply-To: <20161209165903.1293-2-m.tretter@pengutronix.de>
On Fri, Dec 09, 2016 at 05:58:57PM +0100, Michael Tretter wrote:
> From: Philipp Zabel <philipp.zabel@gmail.com>
>
> This adds a compatible property and the correct clock for the
> i.MX6Q Video Data Order Adapter.
This comment matches the dts change, but not the binding change.
> Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> .../devicetree/bindings/media/fsl-vdoa.txt | 21 +++++++++++++++++++++
> arch/arm/boot/dts/imx6qdl.dtsi | 2 ++
> 2 files changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/fsl-vdoa.txt
>
> diff --git a/Documentation/devicetree/bindings/media/fsl-vdoa.txt b/Documentation/devicetree/bindings/media/fsl-vdoa.txt
> new file mode 100644
> index 0000000..5e45f9b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/fsl-vdoa.txt
> @@ -0,0 +1,21 @@
> +Freescale Video Data Order Adapter
> +==================================
> +
> +The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
> +it to to reorder video data from the macroblock tiled order produced by the
s/it to/is/
> +CODA 960 VPU to the conventional raster-scan order for scanout.
> +
> +Required properties:
> +- compatible: must be "fsl,imx6q-vdoa"
> +- reg: the register base and size for the device registers
> +- interrupts: the VDOA interrupt
> +- clocks: the vdoa clock
> +
> +Example:
> +
> +vdoa@021e4000 {
Drop the leading 0.
> + compatible = "fsl,imx6q-vdoa";
> + reg = <0x021e4000 0x4000>;
> + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6QDL_CLK_VDOA>;
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index b13b0b2..69e3668 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1153,8 +1153,10 @@
> };
>
> vdoa@021e4000 {
> + compatible = "fsl,imx6q-vdoa";
> reg = <0x021e4000 0x4000>;
> interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6QDL_CLK_VDOA>;
> };
>
> uart2: serial@021e8000 {
> --
> 2.10.2
>
> --
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] MIPS: NI 169445 board support
From: Paul Burton @ 2016-12-13 18:40 UTC (permalink / raw)
To: Nathan Sullivan
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA,
mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1480693329-22265-1-git-send-email-nathan.sullivan-acOepvfBmUk@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 20385 bytes --]
Hi Nathan,
On Friday, 2 December 2016 09:42:09 GMT Nathan Sullivan wrote:
> Support the National Instruments 169445 board.
>
> Signed-off-by: Nathan Sullivan <nathan.sullivan-acOepvfBmUk@public.gmane.org>
> ---
> "gpio: mmio: add support for NI 169445 NAND GPIO" and
> "devicetree: add vendor prefix for National Instruments" are required for
> the NAND on this board to work.
>
> Documentation/devicetree/bindings/mips/ni.txt | 7 ++
> arch/mips/Kbuild.platforms | 1 +
> arch/mips/Kconfig | 26 ++++++
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/ni/169445.dts | 99 +++++++++++++++++++++
> arch/mips/boot/dts/ni/Makefile | 9 ++
> arch/mips/configs/ni169445_defconfig | 120 ++++++++++++++++++++++++++
> arch/mips/ni169445/169445-console.c | 38 ++++++++
> arch/mips/ni169445/169445-init.c | 39 +++++++++
> arch/mips/ni169445/169445-int.c | 34 ++++++++
> arch/mips/ni169445/169445-setup.c | 58 +++++++++++++
> arch/mips/ni169445/169445-time.c | 35 ++++++++
> arch/mips/ni169445/Makefile | 9 ++
> arch/mips/ni169445/Platform | 6 ++
> 14 files changed, 482 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
> create mode 100644 arch/mips/boot/dts/ni/169445.dts
> create mode 100644 arch/mips/boot/dts/ni/Makefile
> create mode 100644 arch/mips/configs/ni169445_defconfig
> create mode 100644 arch/mips/ni169445/169445-console.c
> create mode 100644 arch/mips/ni169445/169445-init.c
> create mode 100644 arch/mips/ni169445/169445-int.c
> create mode 100644 arch/mips/ni169445/169445-setup.c
> create mode 100644 arch/mips/ni169445/169445-time.c
> create mode 100644 arch/mips/ni169445/Makefile
> create mode 100644 arch/mips/ni169445/Platform
>
> diff --git a/Documentation/devicetree/bindings/mips/ni.txt
> b/Documentation/devicetree/bindings/mips/ni.txt new file mode 100644
> index 0000000..722bf2d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/ni.txt
> @@ -0,0 +1,7 @@
> +National Instruments MIPS platforms
> +
> +required root node properties:
> + - compatible: must be "ni,169445"
> +
> +CPU Nodes
> + - compatible: must be "mti,mips14KEc"
This doesn't describe anything else you rely on, like the
mips-hpt-frequency property which you panic without.
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index f5f1bdb..f2d7b5c 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -20,6 +20,7 @@ platforms += loongson32
> platforms += loongson64
> platforms += mti-malta
> platforms += netlogic
> +platforms += ni169445
> platforms += paravirt
> platforms += pic32
> platforms += pistachio
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index b3c5bde..d24d11f 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -574,6 +574,32 @@ config NXP_STB225
> help
> Support for NXP Semiconductors STB225 Development Board.
>
> +config NI_169445
> + bool "NI 169445 board"
> + select ARCH_WANT_OPTIONAL_GPIOLIB
> + select BOOT_ELF32
> + select BOOT_RAW
> + select BUILTIN_DTB
> + select CEVT_R4K
> + select CSRC_R4K
> + select CPU_MIPSR2_IRQ_VI
> + select CPU_MIPSR2_IRQ_EI
> + select DMA_NONCOHERENT
> + select IRQ_MIPS_CPU
> + select LIBFDT
> + select MIPS_MSC
> + select SYS_HAS_CPU_MIPS32_R1
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_HAS_EARLY_PRINTK
> + select SYS_SUPPORTS_32BIT_KERNEL
> + select SYS_SUPPORTS_LITTLE_ENDIAN
> + select USE_OF
> + select COMMON_CLK
> + help
> + This enables support for the National Instruments 169445A
> + board.
> +
> +
> config PMC_MSP
> bool "PMC-Sierra MSP chipsets"
> select CEVT_R4K
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index fc7a0a9..65a0ad8 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -3,6 +3,7 @@ dts-dirs += cavium-octeon
> dts-dirs += ingenic
> dts-dirs += lantiq
> dts-dirs += mti
> +dts-dirs += ni
> dts-dirs += netlogic
> dts-dirs += pic32
> dts-dirs += qca
> diff --git a/arch/mips/boot/dts/ni/169445.dts
> b/arch/mips/boot/dts/ni/169445.dts new file mode 100644
> index 0000000..a2b49f9
> --- /dev/null
> +++ b/arch/mips/boot/dts/ni/169445.dts
> @@ -0,0 +1,99 @@
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ni,169445";
> +
> + cpus {
> + mips-hpt-frequency = <25000000>;
> +
> + cpu@0 {
> + compatible = "mti,mips14KEc";
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x08000000>;
> + };
> +
> + clocks {
> + baseclk: baseclock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> + };
> +
> + cpu_intc: cpu_intc {
> + #address-cells = <0>;
> + compatible = "mti,cpu-interrupt-controller";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + ahb@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + gpio1: nand-gpio-out@1f300010 {
> + compatible = "ni,169445-nand-gpio";
> + reg = <0x1f300010 0x4>;
> + reg-names = "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <5>;
> + };
> +
> + gpio2: nand-gpio-in@1f300014 {
> + compatible = "ni,169445-nand-gpio";
> + reg = <0x1f300014 0x4>;
> + reg-names = "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <1>;
> + };
> +
> + nand@1f300000 {
> + compatible = "gpio-control-nand";
> + nand-on-flash-bbt;
> + nand-ecc-mode = "soft_bch";
> + nand-ecc-step-size = <512>;
> + nand-ecc-strength = <4>;
> + reg = <0x1f300000 4>;
> + gpios = <&gpio2 0 0>, /* rdy */
> + <&gpio1 1 0>, /* nce */
> + <&gpio1 2 0>, /* ale */
> + <&gpio1 3 0>, /* cle */
> + <&gpio1 4 0>; /* nwp */
> + };
> +
> + serial@1f380000 {
> + compatible = "ns16550a";
> + reg = <0x1f380000 0x1000>;
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <6>;
> + clocks = <&baseclk>;
> + reg-shift = <0>;
> + };
> +
> + ethernet@1f340000 {
> + compatible = "snps,dwc-qos-ethernet-4.10";
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <5>;
> + reg = <0x1f340000 0x2000>;
> + clock-names = "apb_pclk", "phy_ref_clk";
> + clocks = <&baseclk>, <&baseclk>;
> +
> + phy-mode = "rgmii";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
> new file mode 100644
> index 0000000..5291c18
> --- /dev/null
> +++ b/arch/mips/boot/dts/ni/Makefile
> @@ -0,0 +1,9 @@
> +dtb-$(CONFIG_NI_169445) += 169445.dtb
> +
> +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> +
> +# Force kbuild to make empty built-in.o if necessary
> +obj- += dummy.o
> +
> +always := $(dtb-y)
> +clean-files := *.dtb *.dtb.S
> diff --git a/arch/mips/configs/ni169445_defconfig
> b/arch/mips/configs/ni169445_defconfig new file mode 100644
> index 0000000..e5a34df
> --- /dev/null
> +++ b/arch/mips/configs/ni169445_defconfig
> @@ -0,0 +1,120 @@
> +CONFIG_NI_169445=y
> +CONFIG_CPU_MIPS32_R2=y
> +CONFIG_HZ_100=y
> +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
> +# CONFIG_SWAP is not set
> +CONFIG_SYSVIPC=y
> +CONFIG_HZ_PERIODIC=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_LOG_BUF_SHIFT=15
> +CONFIG_BLK_DEV_INITRD=y
> +# CONFIG_RD_GZIP is not set
> +# CONFIG_RD_LZMA is not set
> +# CONFIG_RD_XZ is not set
> +# CONFIG_RD_LZO is not set
> +# CONFIG_RD_LZ4 is not set
> +# CONFIG_SHMEM is not set
> +CONFIG_EMBEDDED=y
> +CONFIG_SLAB=y
> +CONFIG_PROFILING=y
> +# CONFIG_LBDAF is not set
> +# CONFIG_BLK_DEV_BSG is not set
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +# CONFIG_SUSPEND is not set
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_DIAG is not set
> +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
> +CONFIG_NETFILTER=y
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> +CONFIG_IP_NF_IPTABLES=y
> +CONFIG_IP_NF_FILTER=y
> +CONFIG_IP6_NF_IPTABLES=y
> +CONFIG_IP6_NF_FILTER=y
> +# CONFIG_WIRELESS is not set
> +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_MTD=y
> +CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_BLOCK_RO=y
> +CONFIG_MTD_NAND=y
> +CONFIG_MTD_NAND_ECC_BCH=y
> +CONFIG_MTD_NAND_GPIO=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_BLOCK=y
> +CONFIG_NETDEVICES=y
> +# CONFIG_NET_VENDOR_AMAZON is not set
> +# CONFIG_NET_VENDOR_ARC is not set
> +# CONFIG_NET_CADENCE is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_EZCHIP is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_NETRONOME is not set
> +# CONFIG_NET_VENDOR_QUALCOMM is not set
> +# CONFIG_NET_VENDOR_RENESAS is not set
> +# CONFIG_NET_VENDOR_ROCKER is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +# CONFIG_NET_VENDOR_STMICRO is not set
> +CONFIG_SYNOPSYS_DWC_ETH_QOS=y
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +# CONFIG_NET_VENDOR_XILINX is not set
> +# CONFIG_WLAN is not set
> +# CONFIG_INPUT_MOUSEDEV is not set
> +# CONFIG_INPUT_KEYBOARD is not set
> +# CONFIG_INPUT_MOUSE is not set
> +# CONFIG_SERIO is not set
> +# CONFIG_CONSOLE_TRANSLATIONS is not set
> +CONFIG_VT_HW_CONSOLE_BINDING=y
> +CONFIG_LEGACY_PTY_COUNT=32
> +CONFIG_SERIAL_8250=y
> +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_NR_UARTS=2
> +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
> +CONFIG_SERIAL_OF_PLATFORM=y
> +# CONFIG_HW_RANDOM is not set
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_GENERIC_PLATFORM=y
> +# CONFIG_HWMON is not set
> +# CONFIG_VGA_CONSOLE is not set
> +# CONFIG_HID is not set
> +# CONFIG_USB_SUPPORT is not set
> +# CONFIG_MIPS_PLATFORM_DEVICES is not set
> +# CONFIG_IOMMU_SUPPORT is not set
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
> +# CONFIG_UBIFS_FS_ZLIB is not set
> +CONFIG_SQUASHFS=y
> +# CONFIG_SQUASHFS_ZLIB is not set
> +CONFIG_SQUASHFS_LZO=y
> +CONFIG_SQUASHFS_XZ=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +# CONFIG_FTRACE is not set
> +CONFIG_CRYPTO_CBC=y
> +CONFIG_CRYPTO_ECB=y
> +CONFIG_CRYPTO_CRC32C=y
> +CONFIG_CRYPTO_ARC4=y
> +# CONFIG_CRYPTO_HW is not set
> +# CONFIG_XZ_DEC_X86 is not set
> +# CONFIG_XZ_DEC_POWERPC is not set
> +# CONFIG_XZ_DEC_IA64 is not set
> +# CONFIG_XZ_DEC_ARM is not set
> +# CONFIG_XZ_DEC_ARMTHUMB is not set
> +# CONFIG_XZ_DEC_SPARC is not set
> diff --git a/arch/mips/ni169445/169445-console.c
> b/arch/mips/ni169445/169445-console.c new file mode 100644
> index 0000000..f07e48b
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-console.c
> @@ -0,0 +1,38 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> Free + * Software Foundation; either version 2 of the License, or (at your
> option) + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License for + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/console.h>
> +#include <linux/serial_reg.h>
> +#include <linux/io.h>
> +
> +#define NI_UART0_REGS_BASE ((unsigned char __iomem *)0xbf380000)
> +
> +static inline unsigned char serial_in(int offset)
> +{
> + return __raw_readb(NI_UART0_REGS_BASE + offset);
> +}
> +
> +static inline void serial_out(int offset, char value)
> +{
> + __raw_writeb(value, NI_UART0_REGS_BASE + offset);
> +}
> +
> +int prom_putchar(char c)
> +{
> + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
> + ;
> +
> + serial_out(UART_TX, c);
> +
> + return 1;
> +}
Could you use the generic 16550 earlycon support? (see CONFIG_SERIAL_8250_CONSOLE)
> diff --git a/arch/mips/ni169445/169445-init.c
> b/arch/mips/ni169445/169445-init.c new file mode 100644
> index 0000000..5c7ff5e
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-init.c
> @@ -0,0 +1,39 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> Free + * Software Foundation; either version 2 of the License, or (at your
> option) + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License for + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/initrd.h>
> +#include <linux/io.h>
> +
> +#include <asm/bootinfo.h>
> +#include <asm/cacheflush.h>
> +#include <asm/traps.h>
> +#include <asm/mips-boards/generic.h>
> +#include <asm/fw/fw.h>
> +
> +void __init prom_init(void)
> +{
> + fw_init_cmdline();
> +
> +#ifdef CONFIG_BLK_DEV_INITRD
> + /* Read the initrd address from the firmware environment */
> + initrd_start = fw_getenvl("initrd_start");
> + if (initrd_start) {
> + initrd_start = KSEG0ADDR(initrd_start);
> + initrd_end = initrd_start + fw_getenvl("initrd_size");
> + }
> +#endif
> +}
> +
> +void __init prom_free_prom_memory(void)
> +{
> +}
> diff --git a/arch/mips/ni169445/169445-int.c
> b/arch/mips/ni169445/169445-int.c new file mode 100644
> index 0000000..83caf79
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-int.c
> @@ -0,0 +1,34 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> Free + * Software Foundation; either version 2 of the License, or (at your
> option) + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License for + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/of_irq.h>
> +#include <linux/irqchip/mips-gic.h>
> +#include <linux/io.h>
> +
> +#include <asm/irq_cpu.h>
> +#include <asm/setup.h>
> +
> +static const struct of_device_id of_irq_ids[] __initconst = {
> + {
> + .compatible = "mti,cpu-interrupt-controller",
> + .data = mips_cpu_irq_of_init
> + },
> + {},
> +};
> +
> +void __init arch_init_irq(void)
> +{
> + of_irq_init(of_irq_ids);
> +}
The CPU interrupt controller driver already does an IRQCHIP_DECLARE to
provide its compatible string, so can you just use irqchip_init()?
> +
> diff --git a/arch/mips/ni169445/169445-setup.c
> b/arch/mips/ni169445/169445-setup.c new file mode 100644
> index 0000000..80a5c91
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-setup.c
> @@ -0,0 +1,58 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> Free + * Software Foundation; either version 2 of the License, or (at your
> option) + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License for + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/clk-provider.h>
> +#include <linux/libfdt.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_fdt.h>
> +
> +#include <asm/prom.h>
> +#include <asm/fw/fw.h>
> +
> +#include <asm/mips-boards/generic.h>
> +
> +const char *get_system_type(void)
> +{
> + return "NI 169445 FPGA";
> +}
> +
> +void __init plat_mem_setup(void)
> +{
> + /*
> + * Load the builtin devicetree. This causes the chosen node to be
> + * parsed resulting in our memory appearing
> + */
> + __dt_setup_arch(__dtb_start);
> +}
> +
> +void __init device_tree_init(void)
> +{
> + if (!initial_boot_params)
> + return;
> +
> + unflatten_and_copy_device_tree();
> +}
> +
> +static int __init customize_machine(void)
> +{
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> + return 0;
> +}
> +arch_initcall(customize_machine);
> +
> +static int __init plat_dev_init(void)
> +{
> + of_clk_init(NULL);
> + return 0;
> +}
> +device_initcall(plat_dev_init);
> diff --git a/arch/mips/ni169445/169445-time.c
> b/arch/mips/ni169445/169445-time.c new file mode 100644
> index 0000000..3d2499e
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-time.c
> @@ -0,0 +1,35 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> Free + * Software Foundation; either version 2 of the License, or (at your
> option) + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> General Public License for + * more details.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/of.h>
> +
> +#include <asm/time.h>
> +
> +void __init plat_time_init(void)
> +{
> + struct device_node *np;
> + u32 freq;
> +
> + np = of_find_node_by_name(NULL, "cpus");
> + if (!np)
> + panic("missing 'cpus' DT node");
> + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
> + panic("missing 'mips-hpt-frequency' property");
I think "clock-frequency" would be more standard, and the kernel would
then just halve it to find the frequency at which the cop0 count register
increments.
> + of_node_put(np);
> +
> + mips_hpt_frequency = freq;
> +
> + /* IRQs will not work until the timer has been set at least once */
> + write_c0_count(0);
Really? Do you have any details of this, it sounds weird. Do you mean
only the cop0 compare interrupt won't work until count is set? If so (and
that sounds strange in itself) perhaps r4k_clockevent_init() ought to do
this rather than some platform/board code.
> +}
> diff --git a/arch/mips/ni169445/Makefile b/arch/mips/ni169445/Makefile
> new file mode 100644
> index 0000000..f3a0c8c
> --- /dev/null
> +++ b/arch/mips/ni169445/Makefile
> @@ -0,0 +1,9 @@
> +#
> +#
> +obj-y := 169445-init.o \
> + 169445-int.o 169445-setup.o \
> + 169445-time.o
> +
> +obj-$(CONFIG_EARLY_PRINTK) += 169445-console.o
> +
> +CFLAGS_169445-setup.o = -I$(src)/../../../scripts/dtc/libfdt
> diff --git a/arch/mips/ni169445/Platform b/arch/mips/ni169445/Platform
> new file mode 100644
> index 0000000..9380312
> --- /dev/null
> +++ b/arch/mips/ni169445/Platform
> @@ -0,0 +1,6 @@
> +#
> +# National Instruments 169445 FPGA board
> +#
> +platform-$(CONFIG_NI_169445) += ni169445/
> +load-$(CONFIG_NI_169445) += 0xffffffff80002000
> +all-$(CONFIG_NI_169445) := $(COMPRESSION_FNAME).srec
Could all this platform/board code be scrapped in favour of adding your
system to the generic platform? There's some documentation over here
which I hope to get in-tree soon:
https://paulburton.eu/kernel-docs/mips/generic-platform.html
You can also see some further examples of systems converted to the
generic platform which I hope to get into mainline over the next few
cycles over here:
https://git.linux-mips.org/cgit/linux-mti.git/log/
But the core of the generic platform is already there & ought to be
usable for a system like this.
Thanks,
Paul
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH] i2c: designware: Cleaning and comment style fixes.
From: Joe Perches @ 2016-12-13 18:34 UTC (permalink / raw)
To: Luis Oliveira, wsa-z923LK4zBo2bacvFa/9K2g,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
jarkko.nikula-VuQAYsv1563Yd54FQh9/CA,
andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA,
mika.westerberg-VuQAYsv1563Yd54FQh9/CA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Ramiro.Oliveira-HKixBCOQz3hWk0Htik3J/w,
Joao.Pinto-HKixBCOQz3hWk0Htik3J/w,
CARLOS.PALMINHA-HKixBCOQz3hWk0Htik3J/w
In-Reply-To: <32604e59cde19a8981681ad2f0ee447af847bf60.1481646098.git.lolivei-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
On Tue, 2016-12-13 at 16:34 +0000, Luis Oliveira wrote:
> - Misspelling of some words
> - Comment format fix
Most all adding periods to comments.
I think this is generally a value free change as these are
frequently sentence fragments, but, hey, it's not my code.
> /*
> - * Registers offset
> + * Registers offset.
> */
Like this.
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* [PATCH 7/7] ARM: dts: NSP: Add SD/MMC support
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
Add SD/MMC support to the Broadcom NSP SVK and XMC.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 9 +++
arch/arm/boot/dts/bcm958525xmc.dts | 6 +-
arch/arm/boot/dts/bcm958625k.dts | 118 ++++++++++++++++++++++++-------------
3 files changed, 90 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index ecffc16..6c58c78 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -209,6 +209,15 @@
#dma-cells = <1>;
};
+ sdio: sdhci@21000 {
+ compatible = "brcm,sdhci-iproc-cygnus";
+ reg = <0x21000 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ sdhci,auto-cmd12;
+ clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
+ status = "disabled";
+ };
+
amac0: ethernet@22000 {
compatible = "brcm,nsp-amac";
reg = <0x022000 0x1000>,
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 3912269..41e7fd3 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -59,7 +59,7 @@
};
};
-/* XHCI and SD/MMC support needed to be complete */
+/* XHCI support needed to be complete */
&amac0 {
status = "okay";
@@ -184,6 +184,10 @@
status = "okay";
};
+&sdio {
+ status = "ok";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 6e994f2..f8d47e5 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -117,58 +117,34 @@
&pinctrl {
pinctrl-names = "default";
- pinctrl-0 = <&nand_sel>;
+ pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
+
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
-};
-
-&srab {
- compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- label = "port0";
- reg = <0>;
- };
-
- port@1 {
- label = "port1";
- reg = <1>;
- };
-
- port@2 {
- label = "port2";
- reg = <2>;
- };
- port@3 {
- label = "port3";
- reg = <3>;
- };
+ gpiobs: gpiobs {
+ function = "gpio_b";
+ groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp",
+ "gpio_b_3_grp";
+ };
- port@4 {
- label = "port4";
- reg = <4>;
- };
+ pwmc: pwmc {
+ function = "pwm";
+ groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp";
+ };
- port@5 {
- ethernet = <&amac0>;
- label = "cpu";
- reg = <5>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
+ emmc_sel: emmc_sel {
+ function = "emmc";
+ groups = "emmc_grp";
};
};
+&pwm {
+ status = "okay";
+};
+
&qspi {
bspi-sel = <0>;
flash: m25p80@0 {
@@ -215,6 +191,64 @@
status = "okay";
};
+/*
+ * By default the sd slot is functional. For emmc to work add "<&emmc_sel>"
+ * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the
+ * bus-width property here and disable the nand node with status = "disabled";.
+ *
+ * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>;
+ */
+&sdio {
+ bus-width = <4>;
+ no-1-8-v;
+ status = "ok";
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ label = "port0";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "port1";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "port2";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "port3";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "port4";
+ reg = <4>;
+ };
+
+ port@5 {
+ ethernet = <&amac0>;
+ label = "cpu";
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 6/7] ARM: dts: NSP: Add Ethernet to NSP XMC
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
Enable the ethernet in the NSP XMC (bcm958525xmc) device tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm958525xmc.dts | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 89d9abc..3912269 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -59,7 +59,11 @@
};
};
-/* XHCI, MMC, and Ethernet support needed to be complete */
+/* XHCI and SD/MMC support needed to be complete */
+
+&amac0 {
+ status = "okay";
+};
&i2c0 {
temperature-sensor@4c {
--
2.7.4
^ permalink raw reply related
* [PATCH 5/7] ARM: dts: NSP: Add and enable amac2
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
Add and enable the third AMAC ethernet interface in the device trees for
the platforms where it is present. Also, enable amac1 on some of the
platforms where that was missing.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 9 +++++++++
arch/arm/boot/dts/bcm958622hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958623hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625hr.dts | 8 ++++++++
arch/arm/boot/dts/bcm958625k.dts | 4 ++++
arch/arm/boot/dts/bcm988312hr.dts | 8 ++++++++
6 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 9cd77ab..ecffc16 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -227,6 +227,15 @@
status = "disabled";
};
+ amac2: ethernet@24000 {
+ compatible = "brcm,nsp-amac";
+ reg = <0x024000 0x1000>,
+ <0x112000 0x1000>;
+ reg-names = "amac_base", "idm_base";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
nand: nand@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 18b8ffb..477c486 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -65,6 +65,14 @@
status = "okay";
};
+&amac1 {
+ status = "okay";
+};
+
+&amac2 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 61499ae..c0a499d 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -65,6 +65,14 @@
status = "okay";
};
+&amac1 {
+ status = "okay";
+};
+
+&amac2 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 94cce23..f7eb585 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -63,6 +63,14 @@
status = "okay";
};
+&amac1 {
+ status = "okay";
+};
+
+&amac2 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 7aa86c7..6e994f2 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -61,6 +61,10 @@
status = "okay";
};
+&amac2 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index c324c9f..16666324 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -65,6 +65,14 @@
status = "okay";
};
+&amac1 {
+ status = "okay";
+};
+
+&amac2 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] ARM: dts: NSP: Add BCM958625K switch ports
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Add the layout of the switch ports found on the BCM958625K reference
board. The CPU port is hooked up to the AMAC0 Ethernet controller
adapter.
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/bcm958625k.dts | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index dc24056..7aa86c7 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -120,6 +120,51 @@
};
};
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ label = "port0";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "port1";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "port2";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "port3";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "port4";
+ reg = <4>;
+ };
+
+ port@5 {
+ ethernet = <&amac0>;
+ label = "cpu";
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
&qspi {
bspi-sel = <0>;
flash: m25p80@0 {
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 3/7] ARM: dts: NSP: Add QSPI support to missing boards
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
QSPI device tree entries are present in bcm958625k, but missing from
bcm958522er, bcm958525er, bcm958525xmc, bcm958622hr, bcm958623hr,
bcm958625hr, and bcm988312hr. Duplicate the entry in bcm958625k for
all of those that are missing it (as they are identical).
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm958522er.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958525er.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958525xmc.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958622hr.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958623hr.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958625hr.dts | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm988312hr.dts | 34 ++++++++++++++++++++++++++++++++++
7 files changed, 238 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index 7afd845..3f04a40 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -124,6 +124,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index 9da18cd..9fd5422 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -124,6 +124,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&sata_phy0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 4492f55..89d9abc 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -134,6 +134,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&sata_phy0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index ad2aa87..18b8ffb 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -120,6 +120,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&srab {
compatible = "brcm,bcm58622-srab", "brcm,nsp-srab";
status = "okay";
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 32ea59a..61499ae 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -128,6 +128,40 @@
status = "okay";
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&srab {
compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
status = "okay";
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index e7a4cb1..94cce23 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -118,6 +118,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&sata_phy0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index 104afe9..c324c9f 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -120,6 +120,40 @@
};
};
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
+
&sata_phy0 {
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/7] ARM: dts: NSP: Correct NAND partition unit address
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
The NAND partition unit address does not match the other NSP device tree
files. This change makes them uniform.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm958625k.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 98337d6..dc24056 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -80,19 +80,19 @@
reg = <0x00000000 0x00200000>;
read-only;
};
- partition@1 {
+ partition@200000 {
label = "nenv";
reg = <0x00200000 0x00400000>;
};
- partition@2 {
+ partition@600000 {
label = "nsystem";
reg = <0x00600000 0x00a00000>;
};
- partition@3 {
+ partition@1000000 {
label = "nrootfs";
reg = <0x01000000 0x03000000>;
};
- partition@4 {
+ partition@4000000 {
label = "ncustfs";
reg = <0x04000000 0x3c000000>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH 1/7] ARM: dts: NSP: DT Clean-ups
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1481652831-2744-1-git-send-email-jon.mason@broadcom.com>
The QSPI entry was added out of the sequental order that the rest of the
DTSI file is in. Move it to make it fit in properly. Also, some other
entries have been added in a non-alphabetical order in the DTS files,
making them different from the other NSP DTS files. Move the relevant
peices to make it match. Finally, remove errant new lines.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 46 +++++++++++++--------------
arch/arm/boot/dts/bcm958522er.dts | 1 -
arch/arm/boot/dts/bcm958525er.dts | 1 -
arch/arm/boot/dts/bcm958525xmc.dts | 26 ++++++++--------
arch/arm/boot/dts/bcm958623hr.dts | 16 +++++-----
arch/arm/boot/dts/bcm958625hr.dts | 30 +++++++++---------
arch/arm/boot/dts/bcm958625k.dts | 64 +++++++++++++++++++-------------------
7 files changed, 91 insertions(+), 93 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b6142bd..9cd77ab 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -241,29 +241,6 @@
brcm,nand-has-wp;
};
- gpiob: gpio@30000 {
- compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
- reg = <0x30000 0x50>;
- #gpio-cells = <2>;
- gpio-controller;
- ngpios = <4>;
- interrupt-controller;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pwm: pwm@31000 {
- compatible = "brcm,iproc-pwm";
- reg = <0x31000 0x28>;
- clocks = <&osc>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- rng: rng@33000 {
- compatible = "brcm,bcm-nsp-rng";
- reg = <0x33000 0x14>;
- };
-
qspi: qspi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
reg = <0x027200 0x184>,
@@ -293,6 +270,29 @@
#size-cells = <0>;
};
+ gpiob: gpio@30000 {
+ compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
+ reg = <0x30000 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <4>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pwm: pwm@31000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x31000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ rng: rng@33000 {
+ compatible = "brcm,bcm-nsp-rng";
+ reg = <0x33000 0x14>;
+ };
+
ccbtimer0: timer@34000 {
compatible = "arm,sp804";
reg = <0x34000 0x1000>;
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index a21b0fd..7afd845 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -65,7 +65,6 @@
status = "okay";
};
-
&amac1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index be7f2f8..9da18cd 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -65,7 +65,6 @@
status = "okay";
};
-
&amac1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 959cde9..4492f55 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -59,6 +59,8 @@
};
};
+/* XHCI, MMC, and Ethernet support needed to be complete */
+
&i2c0 {
temperature-sensor@4c {
compatible = "adi,adt7461a";
@@ -115,12 +117,6 @@
};
};
-/* XHCI, MMC, and Ethernet support needed to be complete */
-
-&uart0 {
- status = "okay";
-};
-
&pcie0 {
status = "okay";
};
@@ -129,6 +125,15 @@
status = "okay";
};
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_sel>;
+ nand_sel: nand_sel {
+ function = "nand";
+ groups = "nand_grp";
+ };
+};
+
&sata_phy0 {
status = "okay";
};
@@ -141,11 +146,6 @@
status = "okay";
};
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&nand_sel>;
- nand_sel: nand_sel {
- function = "nand";
- groups = "nand_grp";
- };
+&uart0 {
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index 4ceb8fe..32ea59a 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -120,6 +120,14 @@
};
};
+&sata_phy0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
&srab {
compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
status = "okay";
@@ -165,14 +173,6 @@
};
};
-&sata_phy0 {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 4420025..e7a4cb1 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -1,7 +1,7 @@
/*
* BSD LICENSE
*
- * Copyright (c) 2016 Broadcom. All rights reserved.
+ * Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -59,6 +59,10 @@
};
};
+&amac0 {
+ status = "okay";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
@@ -97,10 +101,6 @@
};
};
-&uart0 {
- status = "okay";
-};
-
&pcie0 {
status = "okay";
};
@@ -118,7 +118,15 @@
};
};
-&amac0 {
+&sata_phy0 {
+ status = "okay";
+};
+
+&sata_phy1 {
+ status = "okay";
+};
+
+&sata {
status = "okay";
};
@@ -167,14 +175,6 @@
};
};
-&sata_phy0 {
- status = "okay";
-};
-
-&sata_phy1 {
- status = "okay";
-};
-
-&sata {
+&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 59d96fb..98337d6 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -53,14 +53,6 @@
};
};
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
&amac0 {
status = "okay";
};
@@ -69,30 +61,6 @@
status = "okay";
};
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&sata_phy0 {
- status = "okay";
-};
-
-&sata_phy1 {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
@@ -131,6 +99,18 @@
};
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
@@ -173,3 +153,23 @@
};
};
};
+
+&sata_phy0 {
+ status = "okay";
+};
+
+&sata_phy1 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 0/7] ARM: dts: NSP: DT Clean-ups and more
From: Jon Mason @ 2016-12-13 18:13 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
The Northstar Plus device tree files have gotten messy and out of sync.
The first 5 patches correct this, the next 2 add support for new things.
Jon Mason (7):
ARM: dts: NSP: DT Clean-ups
ARM: dts: NSP: Correct NAND partition unit address
ARM: dts: NSP: Add QSPI support to missing boards
ARM: dts: NSP: Add BCM958625K switch ports
ARM: dts: NSP: Add and enable amac2
ARM: dts: NSP: Add Ethernet to NSP XMC
ARM: dts: NSP: Add SD/MMC support
arch/arm/boot/dts/bcm-nsp.dtsi | 64 ++++++++++------
arch/arm/boot/dts/bcm958522er.dts | 35 ++++++++-
arch/arm/boot/dts/bcm958525er.dts | 35 ++++++++-
arch/arm/boot/dts/bcm958525xmc.dts | 68 +++++++++++++----
arch/arm/boot/dts/bcm958622hr.dts | 42 +++++++++++
arch/arm/boot/dts/bcm958623hr.dts | 58 ++++++++++++--
arch/arm/boot/dts/bcm958625hr.dts | 72 ++++++++++++++----
arch/arm/boot/dts/bcm958625k.dts | 151 ++++++++++++++++++++++++++++---------
arch/arm/boot/dts/bcm988312hr.dts | 42 +++++++++++
9 files changed, 472 insertions(+), 95 deletions(-)
--
2.7.4
--
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^ permalink raw reply
* Re: Re: [PATCH] i2c: designware: Cleaning and comment style fixes.
From: Luis Oliveira @ 2016-12-13 18:05 UTC (permalink / raw)
To: Andy Shevchenko, wsa-z923LK4zBo2bacvFa/9K2g,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
jarkko.nikula-VuQAYsv1563Yd54FQh9/CA,
mika.westerberg-VuQAYsv1563Yd54FQh9/CA,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Ramiro.Oliveira-HKixBCOQz3hWk0Htik3J/w,
Joao.Pinto-HKixBCOQz3hWk0Htik3J/w,
CARLOS.PALMINHA-HKixBCOQz3hWk0Htik3J/w
In-Reply-To: <1481648428.8991.4.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
On 13-Dec-16 17:00, Andy Shevchenko wrote:
> On Tue, 2016-12-13 at 16:34 +0000, Luis Oliveira wrote:
>> - Misspelling of some words
>
> So, do you use codespell tool for that? I would suggest to use that tool
> and propose any fix there first. At least that tool has a good history
> of changes back in forward until some native speaker(s) settle some
> cases.
>
I just fixed the words "acknowledgment" and "endianness" because checkpatch.pl
says it should be fixed.
>> - Comment format fix
>
> No need to use dot at the end of one-liner comments
>
> /* One line */
>
> /*
> * Multi-line comments. Might include several lines or
> * even paragraphs.
> */
>
> Also I would leave
> /*
> * One line
> */
>
> Without dots here. AFAIU they are used to better distinguish group of
> definitions inside headers (that's why 3 lines).
>
Ok thank you, I will go redo that.
>> - Minor fix in coding style
>>
>
> I'm almost fine with the change itself, but people may be concerned in:
>
> 1) what is the value of the change (would be nice to put this in commit
> message);
>
The value of this, besides the Linux kernel rules of coding style, is because I
will use this code after and it will make my future patch a lot bigger and
complicated to review if I have to do it all together.
> 2) how much additional work this change may bring for backported fixes
> if any;
>
I don't think there is any.
> 3) native speakers are the best who can re-read this and Ack.
>
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^ permalink raw reply
* [PATCH 2/2] iio: adc: hx711: Add IIO driver for AVIA HX711
From: Andreas Klinger @ 2016-12-13 18:02 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, ak-n176/SwNRljddJNmlsFzeA
This is the IIO driver for AVIA HX711 ADC which ist mostly used in weighting
cells.
The protocol is quite simple and using GPIO's:
One GPIO is used as clock (SCK) while another GPIO is read (DOUT)
Signed-off-by: Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
---
drivers/iio/adc/Kconfig | 13 +++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/hx711.c | 269 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 283 insertions(+)
create mode 100644 drivers/iio/adc/hx711.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 932de1f9d1e7..7902b50fcf32 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -205,6 +205,19 @@ config HI8435
This driver can also be built as a module. If so, the module will be
called hi8435.
+config HX711
+ tristate "AVIA HX711 ADC for weight cells"
+ depends on GPIOLIB
+ help
+ If you say yes here you get support for AVIA HX711 ADC which is used
+ for weight cells
+
+ This driver uses two GPIO's, one for setting the clock and the other
+ one for getting the data
+
+ This driver can also be built as a module. If so, the module will be
+ called hx711.
+
config INA2XX_ADC
tristate "Texas Instruments INA2xx Power Monitors IIO driver"
depends on I2C && !SENSORS_INA2XX
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index b1aa456e6af3..d46e289900ef 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
obj-$(CONFIG_HI8435) += hi8435.o
+obj-$(CONFIG_HX711) += hx711.o
obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
diff --git a/drivers/iio/adc/hx711.c b/drivers/iio/adc/hx711.c
new file mode 100644
index 000000000000..cbc89e467985
--- /dev/null
+++ b/drivers/iio/adc/hx711.c
@@ -0,0 +1,269 @@
+/*
+ * HX711: analog to digital converter for weight sensor module
+ *
+ * Copyright (c) Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/iio/iio.h>
+
+#define HX711_GAIN_32 2 /* gain = 32 for channel B */
+#define HX711_GAIN_64 3 /* gain = 64 for channel A */
+#define HX711_GAIN_128 1 /* gain = 128 for channel A */
+
+
+struct hx711_data {
+ struct device *dev;
+ dev_t devt;
+ struct gpio_desc *gpiod_sck;
+ struct gpio_desc *gpiod_dout;
+ int gain_pulse;
+ struct mutex lock;
+};
+
+static void hx711_reset(struct hx711_data *hx711_data)
+{
+ int val;
+ int i;
+
+ val = gpiod_get_value(hx711_data->gpiod_dout);
+ if (val) {
+ dev_warn(hx711_data->dev, "RESET-HX711\n");
+
+ gpiod_set_value(hx711_data->gpiod_sck, 1);
+ udelay(80);
+ gpiod_set_value(hx711_data->gpiod_sck, 0);
+
+ for (i = 0; i < 1000; i++) {
+ val = gpiod_get_value(hx711_data->gpiod_dout);
+ if (!val)
+ break;
+ /* sleep at least 1 ms*/
+ msleep(1);
+ }
+ }
+}
+
+static int hx711_cycle(struct hx711_data *hx711_data)
+{
+ int val;
+
+ /* if preempted for more then 60us while SCK is high:
+ * hx711 is going in reset
+ * ==> measuring is false
+ */
+ preempt_disable();
+ gpiod_set_value(hx711_data->gpiod_sck, 1);
+ val = gpiod_get_value(hx711_data->gpiod_dout);
+ gpiod_set_value(hx711_data->gpiod_sck, 0);
+ preempt_enable();
+
+ return val;
+}
+
+static unsigned int hx711_read(struct hx711_data *hx711_data)
+{
+ int i;
+ int ret;
+ int wert = 0;
+
+ hx711_reset(hx711_data);
+
+ for (i = 0; i < 24; i++) {
+ wert <<= 1;
+ ret = hx711_cycle(hx711_data);
+ if (ret)
+ wert++;
+ }
+
+ wert ^= 0x800000;
+
+ for (i = 0; i < hx711_data->gain_pulse; i++)
+ ret = hx711_cycle(hx711_data);
+
+ return wert;
+}
+
+
+static int hx711_read_raw(struct iio_dev *iio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct hx711_data *hx711_data = iio_priv(iio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ switch (chan->type) {
+ case IIO_VOLTAGE:
+ mutex_lock(&hx711_data->lock);
+ *val = (int)hx711_read(hx711_data);
+ mutex_unlock(&hx711_data->lock);
+ ret = IIO_VAL_INT;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return ret;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static const struct iio_info hx711_iio_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = hx711_read_raw,
+};
+
+static const struct iio_chan_spec hx711_chan_spec[] = {
+ { .type = IIO_VOLTAGE,
+ .channel = 0,
+ .info_mask_separate =
+ BIT(IIO_CHAN_INFO_RAW),
+ .scan_type = {
+ .sign = 'u',
+ .realbits = 24,
+ .storagebits = 32,
+ .shift = 0,
+ }
+ },
+};
+
+static int hx711_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct hx711_data *hx711_data = NULL;
+ struct iio_dev *iio;
+ int ret = 0, ival;
+
+ iio = devm_iio_device_alloc(dev, sizeof(struct hx711_data));
+ if (!iio) {
+ dev_err(dev, "failed to allocate IIO device\n");
+ return -ENOMEM;
+ }
+
+ hx711_data = iio_priv(iio);
+ hx711_data->dev = dev;
+
+ mutex_init(&hx711_data->lock);
+
+ hx711_data->gpiod_sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_HIGH);
+ if (IS_ERR(hx711_data->gpiod_sck)) {
+ ret = PTR_ERR(hx711_data->gpiod_sck);
+ goto err;
+ }
+
+ hx711_data->gpiod_dout = devm_gpiod_get(dev, "dout", GPIOD_OUT_HIGH);
+ if (IS_ERR(hx711_data->gpiod_dout)) {
+ ret = PTR_ERR(hx711_data->gpiod_dout);
+ goto err;
+ }
+
+ ret = of_property_read_u32 (node, "gain", &ival);
+ if (!ret) {
+ switch (ival) {
+ case 32:
+ hx711_data->gain_pulse = HX711_GAIN_32;
+ break;
+ case 64:
+ hx711_data->gain_pulse = HX711_GAIN_64;
+ break;
+ case 128:
+ hx711_data->gain_pulse = HX711_GAIN_128;
+ break;
+ default:
+ hx711_data->gain_pulse = HX711_GAIN_128;
+ }
+ } else
+ hx711_data->gain_pulse = HX711_GAIN_128;
+ dev_dbg(hx711_data->dev, "gain: %d\n", hx711_data->gain_pulse);
+
+ ret = gpiod_direction_input(hx711_data->gpiod_dout);
+ if (ret < 0) {
+ dev_err(hx711_data->dev, "gpiod_direction_input: %d\n", ret);
+ goto err;
+ }
+
+ ret = gpiod_direction_output(hx711_data->gpiod_sck, 0);
+ if (ret < 0) {
+ dev_err(hx711_data->dev, "gpiod_direction_output: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, iio);
+
+ iio->name = pdev->name;
+ iio->dev.parent = &pdev->dev;
+ iio->info = &hx711_iio_info;
+ iio->modes = INDIO_DIRECT_MODE;
+ iio->channels = hx711_chan_spec;
+ iio->num_channels = ARRAY_SIZE(hx711_chan_spec);
+
+ dev_err(hx711_data->dev, "initialized\n");
+
+ return devm_iio_device_register(dev, iio);
+
+err:
+ return ret;
+}
+
+
+static int hx711_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int hx711_resume(struct device *dev)
+{
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(hx711_pm_ops, hx711_suspend, hx711_resume);
+
+
+static const struct of_device_id of_hx711_match[] = {
+ { .compatible = "avia,hx711", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_hx711_match);
+
+static struct platform_driver hx711_driver = {
+ .probe = hx711_probe,
+ .driver = {
+ .name = "hx711-gpio",
+ .pm = &hx711_pm_ops,
+ .of_match_table = of_hx711_match,
+ },
+};
+
+module_platform_driver(hx711_driver);
+
+MODULE_AUTHOR("Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>");
+MODULE_DESCRIPTION("HX711 bitbanging driver - ADC for weight cells");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hx711-gpio");
+
--
2.1.4
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^ permalink raw reply related
* [PATCH 1/2] iio: adc: hx711: Add DT binding for avia,hx711
From: Andreas Klinger @ 2016-12-13 18:01 UTC (permalink / raw)
To: devicetree, linux-iio
Cc: linux-kernel, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
galak, jic23, knaack.h, lars, pmeerw, ak
Add DT bindings for avia,hx711
Add vendor avia to vendor list
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
---
.../devicetree/bindings/iio/adc/avia-hx711.txt | 23 ++++++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
2 files changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
new file mode 100644
index 000000000000..d56f95705fd2
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
@@ -0,0 +1,23 @@
+* AVIA HX711 ADC chip for weight cells
+ Bit-banging driver
+
+Required properties:
+ - compatible: Should be "avia,hx711"
+ - sck-gpios: Definition of the GPIO for the clock
+ - dout-gpios: Definition of the GPIO for Data-Out
+ See Documentation/devicetree/bindings/gpio/gpio.txt
+
+Recommended properties:
+ - gain: Gain select, can be 32, 64 or 128
+ default is 128
+
+Optional properties:
+
+Example:
+weight@0 {
+ compatible = "avia,hx711";
+ sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ gain = <32>
+};
+
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 44ddc980b085..4696bb5c2198 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -32,6 +32,7 @@ atlas Atlas Scientific LLC
atmel Atmel Corporation
auo AU Optronics Corporation
avago Avago Technologies
+avia avia semiconductor
avic Shanghai AVIC Optoelectronics Co., Ltd.
axis Axis Communications AB
boe BOE Technology Group Co., Ltd.
--
2.1.4
^ permalink raw reply related
* [PATCH 0/2] iio: adc: hx711: Add IIO driver for AVIA HX711 ADC
From: Andreas Klinger @ 2016-12-13 18:01 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, ak-n176/SwNRljddJNmlsFzeA
This series adds IIO driver support for the AVIA HX711 ADC which is
mostly used in weighting cells.
The first patch adds the new DT binding for which a new vendor avia
was also added.
The second patch is the simple IIO driver implemented as ADC.
The protocol is specific to this device and implemented using GPIO's.
Documentation of the chip can be found here:
https://cdn.sparkfun.com/datasheets/Sensors/ForceFlex/hx711_english.pdf
Andreas Klinger (2):
documented DT-binding avia,hx711
added avia,hx711 driver
.../devicetree/bindings/iio/adc/avia-hx711.txt | 23 ++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/hx711.c | 269 +++++++++++++++++++++
5 files changed, 307 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
create mode 100644 drivers/iio/adc/hx711.c
--
2.1.4
^ permalink raw reply
* Re: [PATCH 8/9] arm64: dts: rockchip: partially describe PWM regulators for Gru
From: Heiko Stuebner @ 2016-12-13 17:48 UTC (permalink / raw)
To: Brian Norris
Cc: linux-rockchip, linux-kernel, Caesar Wang, Doug Anderson,
devicetree, Rob Herring, Stephen Barber, linux-arm-kernel,
Chris Zhong
In-Reply-To: <20161207170916.GA84287@google.com>
Am Mittwoch, 7. Dezember 2016, 09:09:17 CET schrieb Brian Norris:
> Hi Heiko,
>
> On Wed, Dec 07, 2016 at 05:48:24PM +0100, Heiko Stuebner wrote:
> > Am Donnerstag, 1. Dezember 2016, 18:27:32 CET schrieb Brian Norris:
> > > We need to add regulators to the CPU nodes, so cpufreq doesn't think it
> > > can crank up the clock speed without changing the voltage. However, we
> > > don't yet have the DT bindings to fully describe the Over Voltage
> > > Protection (OVP) circuits on these boards. Without that description, we
> > > might end up changing the voltage too much, too fast.
> > >
> > > Add the pwm-regulator descriptions and associate the CPU OPPs, but leave
> > > them disabled.
> > >
> > > Signed-off-by: Brian Norris <briannorris@chromium.org>
> >
> > is there a specific reason for keeping this change separate?
>
> Maybe not a great one. I figured they were somewhat controversial, so I
> at least wanted to split the "cpufreq patches" (i.e., this and the
> previous) from the main DTS(I) additions. I also figured we typically
> like to keep the base SoC changes separate from the board DTS(I)
> changes.
I was scratching my head for a bit where this was affecting the evb, until I
found the include at the end of patch5 :-) .
> > While it is nice for documentation reasons, as it stands now the previous
> > patch introduces a regression (cpufreq trying to scale without regulators)
> > and immediately fixes it here.
>
> Right. Additionally, as noted on the previous patch, we might do the
> same with EVB. But I don't know what the regulators are like for EVB.
> This is probably a bigger deal, since EVB has been working (allegedly)
> upstream for a while now.
Yep, it was at least booting :-) . I guess I should wire it up again. My shiny
new Gru somehow did take up its space recently.
> There's no way to split these up without either breaking compilation or
> breaking bisectability. For Kevin/Gru, they don't function at all before
> this series, so I figured some "settle" time wasn't a huge deal.
>
> > So if you're ok with it, I'd like to merge this one back into the previous
> > patch when applying.
>
> That'd be OK with me, as long as we're also confident about EVB.
That somehow sounds unrelated, as this patch only touches gru stuff anyway. So
if the evb breaks, it would do so after patch5 already.
> Maybe at a minimum, I should just patch in some empty regulator nodes,
> so cpufreq doesn't think there's no need to handle voltage.
So I guess going forward we could do, describe the evb pwm regulators (in
disabled state), add general OPPs, add gru with pwm regulators?
I'll try to hook up my evb and check on the pwm-regulators in the schematics
this week.
Heiko
^ permalink raw reply
* [PATCH v3 2/2] ASoC: cs43130: Add devicetree bindings for CS43130
From: Li Xu @ 2016-12-13 17:47 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
In-Reply-To: <1481651227-15185-1-git-send-email-li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
Add devicetree bindings documentation file for Cirrus
Logic CS43130 codec.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
.../devicetree/bindings/sound/cs43130.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/cs43130.txt
diff --git a/Documentation/devicetree/bindings/sound/cs43130.txt b/Documentation/devicetree/bindings/sound/cs43130.txt
new file mode 100644
index 0000000..1af6b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs43130.txt
@@ -0,0 +1,41 @@
+CS43130 DAC
+
+Required properties:
+
+ - compatible : "cirrus,cs43130"
+
+ - reg : the I2C address of the device for I2C
+
+ - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
+ power supplies for the device, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+
+Optional properties:
+
+ - reset-gpios : Active low GPIO used to reset the device
+
+ - cirrus,xtal-ibias:
+ When external MCLK is generated by external crystal
+ oscillator, CS43130 can be used to provide bias current
+ for external crystal. Amount of bias current sent is
+ set as:
+ 1 = 7.5uA
+ 2 = 12.5uA
+ 3 = 15uA
+
+Example:
+
+cs43130: audio-codec@30 {
+ compatible = "cirrus,cs43130";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio 54 1>;
+ VA-supply = <&dummy_vreg>;
+ VP-supply = <&dummy_vreg>;
+ VL-supply = <&dummy_vreg>;
+ VCP-supply = <&dummy_vreg>;
+ VD-supply = <&dummy_vreg>;
+ cirrus,xtal-ibias = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <55 8>;
+};
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v3 1/2] ASoC: cs43130: Add support for CS43130 codec
From: Li Xu @ 2016-12-13 17:47 UTC (permalink / raw)
To: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA, Li Xu
Add support for Cirrus Logic CS43130 codec.
Support I2C control and I2S audio playback.
Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
---
sound/soc/codecs/Kconfig | 6 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/cs43130.c | 1153 ++++++++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/cs43130.h | 268 ++++++++++
4 files changed, 1429 insertions(+)
create mode 100644 sound/soc/codecs/cs43130.c
create mode 100644 sound/soc/codecs/cs43130.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 9e1718a..d6ede2b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS4271_I2C if I2C
select SND_SOC_CS4271_SPI if SPI_MASTER
select SND_SOC_CS42XX8_I2C if I2C
+ select SND_SOC_CS43130 if I2C
select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
@@ -473,6 +474,11 @@ config SND_SOC_CS42XX8_I2C
select SND_SOC_CS42XX8
select REGMAP_I2C
+# Cirrus Logic CS43130 HiFi DAC
+config SND_SOC_CS43130
+ tristate "Cirrus Logic CS43130 CODEC"
+ depends on I2C
+
# Cirrus Logic CS4349 HiFi DAC
config SND_SOC_CS4349
tristate "Cirrus Logic CS4349 CODEC"
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 7e1dad7..2f15228 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,6 +52,7 @@ snd-soc-cs4271-i2c-objs := cs4271-i2c.o
snd-soc-cs4271-spi-objs := cs4271-spi.o
snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
+snd-soc-cs43130-objs := cs43130.o
snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
@@ -281,6 +282,7 @@ obj-$(CONFIG_SND_SOC_CS4271_I2C) += snd-soc-cs4271-i2c.o
obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o
obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
+obj-$(CONFIG_SND_SOC_CS43130) += snd-soc-cs43130.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
diff --git a/sound/soc/codecs/cs43130.c b/sound/soc/codecs/cs43130.c
new file mode 100644
index 0000000..016d1b3
--- /dev/null
+++ b/sound/soc/codecs/cs43130.c
@@ -0,0 +1,1153 @@
+/*
+ * cs43130.c -- CS43130 ALSA Soc Audio driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Authors: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/of_irq.h>
+
+#include "cs43130.h"
+
+
+static const struct reg_default cs43130_reg_defaults[] = {
+ { CS43130_SYS_CLK_CTL_1, 0x06 },
+ { CS43130_SP_SRATE, 0x01 },
+ { CS43130_SP_BITSIZE, 0x05 },
+ { CS43130_PAD_INT_CFG, 0x03 },
+ { CS43130_PWDN_CTL, 0xFE },
+ { CS43130_CRYSTAL_SET, 0x04 },
+ { CS43130_PLL_SET_1, 0x00 },
+ { CS43130_PLL_SET_2, 0x00 },
+ { CS43130_PLL_SET_3, 0x00 },
+ { CS43130_PLL_SET_4, 0x00 },
+ { CS43130_PLL_SET_5, 0x40 },
+ { CS43130_PLL_SET_6, 0x10 },
+ { CS43130_PLL_SET_7, 0x80 },
+ { CS43130_PLL_SET_8, 0x03 },
+ { CS43130_PLL_SET_9, 0x02 },
+ { CS43130_PLL_SET_10, 0x02 },
+ { CS43130_CLKOUT_CTL, 0x00 },
+ { CS43130_ASP_NUM_1, 0x01 },
+ { CS43130_ASP_NUM_2, 0x00 },
+ { CS43130_ASP_DENOM_1, 0x08 },
+ { CS43130_ASP_DENOM_2, 0x00 },
+ { CS43130_ASP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_ASP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_ASP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_ASP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_ASP_CLOCK_CONF, 0x0C },
+ { CS43130_ASP_FRAME_CONF, 0x0A },
+ { CS43130_XSP_NUM_1, 0x01 },
+ { CS43130_XSP_NUM_2, 0x00 },
+ { CS43130_XSP_DENOM_1, 0x02 },
+ { CS43130_XSP_DENOM_2, 0x00 },
+ { CS43130_XSP_LRCK_HI_TIME_1, 0x1F },
+ { CS43130_XSP_LRCK_HI_TIME_2, 0x00 },
+ { CS43130_XSP_LRCK_PERIOD_1, 0x3F },
+ { CS43130_XSP_LRCK_PERIOD_2, 0x00 },
+ { CS43130_XSP_CLOCK_CONF, 0x0C },
+ { CS43130_XSP_FRAME_CONF, 0x0A },
+ { CS43130_ASP_CH_1_LOC, 0x00 },
+ { CS43130_ASP_CH_2_LOC, 0x00 },
+ { CS43130_ASP_CH_1_SZ_EN, 0x06 },
+ { CS43130_ASP_CH_2_SZ_EN, 0x0E },
+ { CS43130_XSP_CH_1_LOC, 0x00 },
+ { CS43130_XSP_CH_2_LOC, 0x00 },
+ { CS43130_XSP_CH_1_SZ_EN, 0x06 },
+ { CS43130_XSP_CH_2_SZ_EN, 0x0E },
+ { CS43130_DSD_VOL_B, 0x78 },
+ { CS43130_DSD_VOL_A, 0x78 },
+ { CS43130_DSD_PATH_CTL_1, 0xA8 },
+ { CS43130_DSD_INT_CFG, 0x00 },
+ { CS43130_DSD_PATH_CTL_2, 0x00 },
+ { CS43130_DSD_PCM_MIX_CTL, 0x00 },
+ { CS43130_DSD_PATH_CTL_3, 0x40 },
+ { CS43130_HP_OUT_CTL_1, 0x30 },
+ { CS43130_PCM_FILT_OPT, 0x02 },
+ { CS43130_PCM_VOL_B, 0x78 },
+ { CS43130_PCM_VOL_A, 0x78 },
+ { CS43130_PCM_PATH_CTL_1, 0xA8 },
+ { CS43130_PCM_PATH_CTL_2, 0x00 },
+ { CS43130_CLASS_H_CTL, 0x1E },
+ { CS43130_HP_DETECT, 0x04 },
+ { CS43130_HP_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_1, 0x00 },
+ { CS43130_HP_MEAS_LOAD_2, 0x00 },
+ { CS43130_INT_MASK_1, 0xFF },
+ { CS43130_INT_MASK_2, 0xFF },
+ { CS43130_INT_MASK_3, 0xFF },
+ { CS43130_INT_MASK_4, 0xFF },
+ { CS43130_INT_MASK_5, 0xFF },
+};
+
+static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
+ case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
+ case CS43130_DXD1:
+ case CS43130_PWDN_CTL:
+ case CS43130_DXD2:
+ case CS43130_CRYSTAL_SET:
+ case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
+ case CS43130_PLL_SET_6:
+ case CS43130_PLL_SET_7:
+ case CS43130_PLL_SET_8:
+ case CS43130_PLL_SET_9:
+ case CS43130_PLL_SET_10:
+ case CS43130_CLKOUT_CTL:
+ case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
+ case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
+ case CS43130_ASP_CH_1_LOC:
+ case CS43130_ASP_CH_2_LOC:
+ case CS43130_ASP_CH_1_SZ_EN:
+ case CS43130_ASP_CH_2_SZ_EN:
+ case CS43130_XSP_CH_1_LOC:
+ case CS43130_XSP_CH_2_LOC:
+ case CS43130_XSP_CH_1_SZ_EN:
+ case CS43130_XSP_CH_2_SZ_EN:
+ case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
+ case CS43130_HP_OUT_CTL_1:
+ case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
+ case CS43130_CLASS_H_CTL:
+ case CS43130_HP_DETECT:
+ case CS43130_HP_STATUS:
+ case CS43130_HP_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_1:
+ case CS43130_HP_MEAS_LOAD_2:
+ case CS43130_HP_DC_STAT_1:
+ case CS43130_HP_DC_STAT_2:
+ case CS43130_HP_AC_STAT_1:
+ case CS43130_HP_AC_STAT_2:
+ case CS43130_HP_LOAD_STAT:
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool cs43130_precious_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
+ return true;
+ default:
+ return false;
+ }
+}
+
+struct cs43130_pll_params {
+ u32 pll_in;
+ u8 mclk_int;
+ u8 sclk_prediv;
+ u8 pll_div_int;
+ u32 pll_div_frac;
+ u8 pll_mode;
+ u8 pll_divout;
+ u32 pll_out;
+ u8 pll_cal_ratio;
+};
+
+static const struct cs43130_pll_params pll_ratio_table[] = {
+ { 9600000, 1, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151 },
+ { 9600000, 0, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164 },
+
+ { 11289600, 1, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128 },
+ { 11289600, 0, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139 },
+
+ { 12000000, 1, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 12000000, 0, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 12288000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 12288000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 13000000, 1, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118 },
+ { 13000000, 0, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128 },
+
+ { 19200000, 1, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 19200000, 0, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+
+ { 22579200, 1, 0, 0, 0, 0, 0, 22579200, 0 },
+ { 22579200, 0, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139 },
+
+ { 24000000, 1, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120 },
+ { 24000000, 0, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131 },
+
+ { 24576000, 1, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 128 },
+ { 24576000, 0, 0, 0, 0, 0, 0, 24576000, 0 },
+
+ { 26000000, 1, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111 },
+ { 26000000, 0, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121 },
+};
+
+static int cs43130_pll_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int i;
+
+ dev_dbg(codec->dev, "%s: cs43130->mclk = %d, cs43130->pll_out = %d",
+ __func__, cs43130->mclk, cs43130->pll_out);
+ for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
+ if (pll_ratio_table[i].pll_in == cs43130->mclk &&
+ pll_ratio_table[i].pll_out == cs43130->pll_out) {
+
+ cs43130->mclk_int = pll_ratio_table[i].mclk_int;
+
+ if (pll_ratio_table[i].pll_cal_ratio == 0) {
+ if (cs43130->xtal_ibias > 0) {
+ usleep_range(1000, 1050);
+ /*PDN_XTAL = 0,enable*/
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK,
+ 0 << CS43130_PDN_XTAL_SHIFT);
+ }
+
+ /* PLL_START = 0, disable PLL_START */
+ regmap_update_bits(cs43130->regmap,
+ CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK,
+ 0 << CS43130_PLL_START_MASK);
+
+ cs43130->pll_bypass = true;
+ return 0;
+ }
+
+ /* PDN_PLL= 0,enable */
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK,
+ 0 << CS43130_PDN_PLL_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_9,
+ CS43130_PLL_REF_PREDIV_MASK,
+ pll_ratio_table[i].sclk_prediv);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
+ pll_ratio_table[i].pll_div_int);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_2,
+ pll_ratio_table[i].pll_div_frac &
+ CS43130_7_0_MASK);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_3,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_15_8_MASK) >> 8);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_4,
+ (pll_ratio_table[i].pll_div_frac &
+ CS43130_23_16_MASK) >> 16);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
+ CS43130_PLL_MODE_MASK,
+ pll_ratio_table[i].pll_mode
+ << CS43130_PLL_MODE_SHIFT);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_6,
+ pll_ratio_table[i].pll_divout);
+
+ regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
+ pll_ratio_table[i].pll_cal_ratio);
+
+ /* PLL_START = 1, enable PLL_START */
+ regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
+ CS43130_PLL_START_MASK, CS43130_PLL_START_MASK);
+ cs43130->pll_bypass = false;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int cs43130_format_config(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ int period_size = 0;
+ int pulse_width = 0;
+ int asp_fsd;
+ int asp_stp;
+ int bick_inv;
+ int asp_m = 0;
+ int asp_sprate = 0;
+ int ret = 0;
+ unsigned int bitwidth_sclk = (cs43130->sclk / cs43130->fs) / 2;
+ unsigned int bitwidth_dai = (cs43130->dai_bit + 1) * 8;
+
+ if (cs43130->fs) {
+ if (bitwidth_sclk < bitwidth_dai) {
+ dev_err(codec->dev, "Format not supported\n");
+ return -EINVAL;
+ }
+ period_size = cs43130->sclk / cs43130->fs;
+ pulse_width = period_size/2;
+
+ if (cs43130->sclk != 0)
+ asp_m = cs43130->pll_out / cs43130->sclk;
+ }
+ dev_dbg(codec->dev, "%s: cs43130->sclk = %d, cs43130->fs = %d, cs43130->dai_bit = %d",
+ __func__, cs43130->sclk, cs43130->fs, cs43130->dai_bit);
+ dev_dbg(codec->dev, "%s: period_size = %d, pulse_width = %d, asp_m = %d",
+ __func__, period_size, pulse_width, asp_m);
+
+ if (cs43130->dai_format) {
+ /*MSB*/
+ bick_inv = 0;
+ asp_fsd = 0;
+ asp_stp = 1;
+
+ } else {
+ /*I2S*/
+ bick_inv = 1;
+ asp_fsd = 2; /* one bick delay */
+ asp_stp = 0;
+ }
+ dev_dbg(codec->dev,
+ "%s: cs43130->dai_format = %d, bick_inv = %d, asp_fsd = %d, asp_stp = %d",
+ __func__, cs43130->dai_format, bick_inv, asp_fsd, asp_stp);
+
+ switch (cs43130->fs) {
+ case 32000:
+ asp_sprate = CS43130_ASP_SPRATE_32K;
+ break;
+ case 44100:
+ asp_sprate = CS43130_ASP_SPRATE_44_1K;
+ break;
+ case 48000:
+ asp_sprate = CS43130_ASP_SPRATE_48K;
+ break;
+ case 88200:
+ asp_sprate = CS43130_ASP_SPRATE_88_2K;
+ break;
+ case 96000:
+ asp_sprate = CS43130_ASP_SPRATE_96K;
+ break;
+ case 176400:
+ asp_sprate = CS43130_ASP_SPRATE_176_4K;
+ break;
+ case 192000:
+ asp_sprate = CS43130_ASP_SPRATE_192K;
+ break;
+ case 352800:
+ asp_sprate = CS43130_ASP_SPRATE_352_8K;
+ break;
+ case 384000:
+ asp_sprate = CS43130_ASP_SPRATE_384K;
+ break;
+ default:
+ dev_err(codec->dev, "sample rate(%d) not supported\n",
+ cs43130->fs);
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: asp_sprate = %d, cs43130->asp_size = %d",
+ __func__, asp_sprate, cs43130->asp_size);
+
+ /* ASP_SPRATE = fs*/
+ regmap_write(cs43130->regmap, CS43130_SP_SRATE, asp_sprate);
+ /*ASP_SPSIZE*/
+ regmap_update_bits(cs43130->regmap, CS43130_SP_BITSIZE,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->asp_size);
+
+
+ /* Set up slave mode */
+ /*BICK = ASP_N/ASP_M * PLL_OUT */
+ /* ASP_N = 1 */
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, 1);
+ regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, 0);
+
+ /*ASP_M*/
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_1, asp_m & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_DENOM_2, (asp_m >> 8) & 0x3f);
+
+
+ /* H / L ratio of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
+ (pulse_width-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
+ ((pulse_width-1) >> 8) & 0xff);
+
+ /* the period of LRCK*/
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
+ (period_size-1) & 0xff);
+ regmap_write(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
+ ((period_size-1) >> 8) & 0xff);
+
+ /*resolution*/
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
+ CS43130_SP_BITSIZE_ASP_MASK, cs43130->dai_bit);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_FSD_MASK, asp_fsd << CS43130_ASP_FSD_SHIFT);
+
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_FRAME_CONF,
+ CS43130_ASP_STP_MASK, asp_stp << CS43130_ASP_STP_SHIFT);
+
+ /* set clk master/slave */
+ dev_dbg(codec->dev, "%s: cs43130->dai_mode = %d",
+ __func__, cs43130->dai_mode);
+ regmap_update_bits(cs43130->regmap, CS43130_ASP_CLOCK_CONF,
+ CS43130_ASP_MODE_MASK, cs43130->dai_mode << CS43130_ASP_MODE_SHIFT);
+
+ return ret;
+}
+
+static int cs43130_change_clksrc(struct snd_soc_codec *codec,
+ enum cs43130_mclk_src_sel src)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_SRC_SEL_MASK, src << CS43130_MCLK_SRC_SEL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
+ CS43130_MCLK_INT_MASK, cs43130->mclk_int << CS43130_MCLK_INT_SHIFT);
+
+ usleep_range(150, 200);
+
+ return ret;
+}
+
+static int cs43130_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ unsigned int bitwidth;
+ int ret = 0;
+
+ cs43130->fs = params_rate(params);
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_8;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_32;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_16;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_24;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_24;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_16;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ cs43130->dai_bit = CS43130_SP_BIT_SIZE_32;
+ cs43130->asp_size = CS43130_SP_BIT_SIZE_8;
+ break;
+ default:
+ dev_err(codec->dev, "Format(%d) not supported",
+ params_format(params));
+ return -EINVAL;
+ }
+
+ bitwidth = (cs43130->dai_bit+1)*8;
+ dev_dbg(codec->dev, "(data bit)%d: (rate)%d",
+ bitwidth, cs43130->fs);
+
+ ret = cs43130_format_config(codec);
+ return ret;
+}
+
+static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
+
+static const struct snd_kcontrol_new cs43130_snd_controls[] = {
+ SOC_DOUBLE_R_TLV("Master Playback Volume",
+ CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
+ pcm_vol_tlv),
+ SOC_SINGLE("Swap L/R", CS43130_PCM_PATH_CTL_2, 1, 1, 0),
+ SOC_SINGLE("Copy L/R", CS43130_PCM_PATH_CTL_2, 0, 1, 0),
+};
+
+static int cs43130_aspin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (cs43130->pll_bypass)
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_XTAL);
+ else
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL);
+
+ usleep_range(10000, 10050);
+ /* ASP_3ST = 0 in master mode */
+ if (cs43130->dai_mode)
+ regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
+ 0x01, 0x00);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_CLKOUT_MASK, 0
+ << CS43130_PDN_CLKOUT_SHIFT);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ break;
+ default:
+ dev_err(codec->dev, "Invalid ASPOUT event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ cs43130_change_clksrc(codec, CS43130_MCLK_SRC_RCO);
+
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_XTAL_MASK, 1
+ << CS43130_PDN_XTAL_SHIFT);
+ regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
+ CS43130_PDN_PLL_MASK, 1
+ << CS43130_PDN_PLL_SHIFT);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid DAC event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMD:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 0 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x00);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
+ regmap_write(cs43130->regmap, CS43130_DXD2, 0x01);
+ regmap_update_bits(cs43130->regmap, CS43130_HP_OUT_CTL_1,
+ CS43130_HP_IN_EN_MASK, 1 << CS43130_HP_IN_EN_SHIFT);
+ regmap_write(cs43130->regmap, CS43130_DXD1, 0x00);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid HPIN event = 0x%x\n", event);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget cs43130_dapm_widgets[] = {
+
+ SND_SOC_DAPM_OUTPUT("HPOUTA"),
+ SND_SOC_DAPM_OUTPUT("HPOUTB"),
+
+ SND_SOC_DAPM_AIF_IN_E("ASPIN", NULL, 0, CS43130_PWDN_CTL,
+ CS43130_PDN_ASP_SHIFT, 1, cs43130_aspin_event,
+ (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
+
+ SND_SOC_DAPM_DAC_E("HiFi DAC",
+ NULL, CS43130_PWDN_CTL, CS43130_PDN_HP_SHIFT, 1,
+ cs43130_dac_event,
+ (SND_SOC_DAPM_PRE_PMD)
+ ),
+
+ SND_SOC_DAPM_LINE("Analog Playback", cs43130_hpin_event),
+};
+
+static const struct snd_soc_dapm_route cs43130_routes[] = {
+ {"ASPIN", NULL, "DAC Playback"},
+ {"HiFi DAC", NULL, "ASPIN"},
+
+ {"HPOUTA", NULL, "HiFi DAC"},
+ {"HPOUTB", NULL, "HiFi DAC"},
+ {"HPOUTA", NULL, "Analog Playback"},
+ {"HPOUTB", NULL, "Analog Playback"},
+};
+
+static const unsigned int cs43130_src_rates[] = {
+ 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
+};
+
+static const struct snd_pcm_hw_constraint_list cs43130_constraints = {
+ .count = ARRAY_SIZE(cs43130_src_rates),
+ .list = cs43130_src_rates,
+};
+
+static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, &cs43130_constraints);
+ return 0;
+}
+
+static int cs43130_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ cs43130->dai_mode = CS43130_SLAVE_MODE;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ cs43130->dai_mode = CS43130_MASTER_MODE;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported i2s master mode\n");
+ return -EINVAL;
+ }
+
+ /* interface format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ cs43130->dai_format = 0;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ cs43130->dai_format = 1;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio format except I2S and MSB\n");
+ return -EINVAL;
+ }
+
+ /* BICK/LRCK pority */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = false;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ cs43130->bick_invert = false;
+ cs43130->lrck_invert = true;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ cs43130->bick_invert = true;
+ cs43130->lrck_invert = true;
+ break;
+ default:
+ dev_err(codec->dev, "unsupported audio polarity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+static int cs43130_set_mute(struct snd_soc_dai *dai, int mute)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+ int ret = 0;
+ unsigned int reg;
+ u8 mute_reg;
+
+ regmap_read(cs43130->regmap, CS43130_PCM_PATH_CTL_1, ®);
+ mute_reg = reg & 0xfc;
+ if (mute)
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
+ mute_reg | 0x03);
+ else
+ regmap_write(cs43130->regmap, CS43130_PCM_PATH_CTL_1, mute_reg);
+
+ return ret;
+}
+
+static int cs43130_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+
+ switch (div_id) {
+ case CS43130_AIF_BICK_RATE:
+ cs43130->bick = div;
+ break;
+ default:
+ dev_err(codec->dev,
+ "Unsupported divide value: div_id = %d", div_id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int cs43130_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
+ unsigned int freq_in, unsigned int freq_out)
+{
+ int ret = 0;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ if (freq_in < 9600000 || freq_in > 26000000) {
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_in) {
+ case 9600000:
+ case 11289600:
+ case 12000000:
+ case 12288000:
+ case 13000000:
+ case 19200000:
+ case 22579200:
+ case 24000000:
+ case 24576000:
+ case 26000000:
+ cs43130->mclk = freq_in;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll input reference clock:%d\n", freq_in);
+ return -EINVAL;
+ }
+
+ switch (freq_out) {
+ case 22579200:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 1;
+ break;
+ case 24576000:
+ cs43130->pll_out = freq_out;
+ cs43130->mclk_int = 0;
+ break;
+ default:
+ dev_err(codec->dev,
+ "unsupported pll output reference clock:%d\n",
+ freq_out);
+ return -EINVAL;
+ }
+
+ ret = cs43130_pll_config(codec);
+ dev_dbg(codec->dev, "%s: cs43130->pll_bypass = %d",
+ __func__, cs43130->pll_bypass);
+ return ret;
+}
+
+static int cs43130_dai_set_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, freq = %d, dir = %d",
+ __func__, clk_id, freq, dir);
+ cs43130->sclk = freq;
+ return 0;
+}
+
+static const struct snd_soc_dai_ops cs43130_dai_ops = {
+ .startup = cs43130_pcm_startup,
+ .hw_params = cs43130_pcm_hw_params,
+ .set_sysclk = cs43130_dai_set_sysclk,
+ .set_fmt = cs43130_set_dai_fmt,
+ .digital_mute = cs43130_set_mute,
+ .set_clkdiv = cs43130_set_clkdiv,
+};
+
+static struct snd_soc_dai_driver cs43130_dai[] = {
+ {
+ .name = "cs43130_hifi",
+ .id = 0,
+ .playback = {
+ .stream_name = "DAC Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_ASP_FORMATS,
+ },
+ .ops = &cs43130_dai_ops,
+ .symmetric_rates = 1,
+ },
+ {
+ .name = "cs43130-xsp",
+ .id = 1,
+ .playback = {
+ .stream_name = "XSP Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_KNOT,
+ .formats = CS43130_XSP_FORMATS,
+ },
+ .symmetric_rates = 1,
+ },
+};
+
+static int cs43130_codec_set_sysclk(struct snd_soc_codec *codec,
+ int clk_id, int source, unsigned int freq, int dir)
+{
+ /* 24576000 is not supported */
+ unsigned int mclk_int_freq = 22579200;
+
+ dev_dbg(codec->dev, "%s: clk_id = %d, source = %d, freq = %d, dir = %d\n",
+ __func__, clk_id, source, freq, dir);
+ /*
+ * freq is external mclk freq
+ * if freq == mclk_int_freq, pll is bypassed
+ * modify mclk_int_freq as needed for application
+ */
+ cs43130_set_pll(codec, 0, 0, freq, mclk_int_freq);
+ return 0;
+}
+
+static irqreturn_t cs43130_irq_thread(int irq, void *data)
+{
+ struct cs43130_private *cs43130 =
+ (struct cs43130_private *)data;
+ struct snd_soc_codec *codec = cs43130->codec;
+ unsigned int stickies[CS43130_NUM_INT];
+ unsigned int masks[CS43130_NUM_INT];
+ unsigned int i;
+
+ /* Read all INT status and mask reg */
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_STATUS_1,
+ stickies, CS43130_NUM_INT * sizeof(unsigned int));
+ regmap_bulk_read(cs43130->regmap, CS43130_INT_MASK_1,
+ masks, CS43130_NUM_INT * sizeof(unsigned int));
+
+ for (i = 0; i < ARRAY_SIZE(stickies); i++)
+ stickies[i] = stickies[i] & (~masks[i]);
+
+ if (stickies[0] & CS43130_XTAL_RDY_INT)
+ dev_dbg(codec->dev, "%s: Crystal ready", __func__);
+
+ if (stickies[0] & CS43130_XTAL_ERR_INT)
+ dev_err(codec->dev, "%s: Crystal err", __func__);
+
+ return IRQ_HANDLED;
+}
+
+static int cs43130_probe(struct snd_soc_codec *codec)
+{
+ struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec);
+
+ cs43130->codec = codec;
+
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_cs43130 = {
+ .probe = cs43130_probe,
+ .component_driver = {
+ .controls = cs43130_snd_controls,
+ .num_controls = ARRAY_SIZE(cs43130_snd_controls),
+ .dapm_widgets = cs43130_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(cs43130_dapm_widgets),
+ .dapm_routes = cs43130_routes,
+ .num_dapm_routes = ARRAY_SIZE(cs43130_routes),
+ },
+ .set_sysclk = cs43130_codec_set_sysclk,
+ .set_pll = cs43130_set_pll,
+};
+
+static const struct regmap_config cs43130_regmap = {
+ .reg_bits = 24,
+ .pad_bits = 8,
+ .val_bits = 8,
+
+ .max_register = CS43130_LASTREG,
+ .reg_defaults = cs43130_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults),
+ .readable_reg = cs43130_readable_register,
+ .precious_reg = cs43130_precious_register,
+ .volatile_reg = cs43130_volatile_register,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static int cs43130_handle_device_data(
+ struct i2c_client *i2c_client, struct cs43130_private *cs43130)
+{
+ struct device_node *np = i2c_client->dev.of_node;
+ unsigned int val;
+ int ret = 0;
+
+ of_property_read_u32(np, "cirrus,xtal-ibias", &val);
+ switch (val) {
+ case 1:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
+ break;
+ case 2:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
+ break;
+ case 3:
+ cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
+ break;
+ default:
+ dev_info(&i2c_client->dev,
+ "cirrus,xtal-ibias value or xtal unused %d",
+ val);
+ }
+ return ret;
+}
+
+static int cs43130_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct cs43130_private *cs43130;
+ int ret;
+ unsigned int devid = 0;
+ unsigned int reg;
+ int i;
+
+ cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
+ if (cs43130 == NULL)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, cs43130);
+
+ cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
+ if (IS_ERR(cs43130->regmap)) {
+ ret = PTR_ERR(cs43130->regmap);
+ return ret;
+ }
+
+ if (client->dev.of_node) {
+ ret = cs43130_handle_device_data(client, cs43130);
+ if (ret != 0)
+ return ret;
+ }
+ for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
+ cs43130->supplies[i].supply = cs43130_supply_names[i];
+
+ ret = devm_regulator_bulk_get(&client->dev,
+ ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to request supplies: %d\n", ret);
+ return ret;
+ }
+ ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(&client->dev,
+ "Failed to enable supplies: %d\n", ret);
+ return ret;
+ }
+
+ cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
+ "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(cs43130->reset_gpio))
+ return PTR_ERR(cs43130->reset_gpio);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ /* initialize codec */
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®);
+
+ devid = (reg & 0xFF) << 12;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®);
+ devid |= (reg & 0xFF) << 4;
+ ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®);
+ devid |= (reg & 0xF0) >> 4;
+
+ switch (devid) {
+ case CS43130_CHIP_ID:
+ break;
+ case CS4399_CHIP_ID:
+ break;
+ default:
+ dev_err(&client->dev,
+ "CS43130 Device ID (%X). Expected ID %X or %X\n",
+ devid, CS43130_CHIP_ID, CS4399_CHIP_ID);
+ ret = -ENODEV;
+ goto err;
+ }
+
+ cs43130->dev_id = devid;
+ ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
+ if (ret < 0) {
+ dev_err(&client->dev, "Get Revision ID failed\n");
+ goto err;
+ }
+
+ dev_info(&client->dev,
+ "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
+ reg & 0xFF);
+
+ /* Enable interrupt handler */
+ ret = devm_request_threaded_irq(&client->dev,
+ client->irq,
+ NULL, cs43130_irq_thread,
+ IRQF_ONESHOT | IRQF_TRIGGER_LOW,
+ "cs43130", cs43130);
+ if (ret != 0) {
+ dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
+ return ret;
+ }
+
+ /* Unmask INT */
+ regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
+ CS43130_XTAL_RDY_INT | CS43130_XTAL_ERR_INT, 0);
+
+ regmap_write(cs43130->regmap,
+ CS43130_CRYSTAL_SET, cs43130->xtal_ibias);
+ ret = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_cs43130, cs43130_dai,
+ ARRAY_SIZE(cs43130_dai));
+
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "%s: snd_soc_register_codec failed with ret = %d\n",
+ __func__, ret);
+ goto err;
+ }
+ return 0;
+err:
+ return ret;
+
+}
+
+static int cs43130_i2c_remove(struct i2c_client *client)
+{
+ struct cs43130_private *cs43130 = i2c_get_clientdata(client);
+
+ snd_soc_unregister_codec(&client->dev);
+
+ if (cs43130->reset_gpio)
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ pm_runtime_disable(&client->dev);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int cs43130_runtime_suspend(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+
+ regcache_cache_only(cs43130->regmap, true);
+ regcache_mark_dirty(cs43130->regmap);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
+
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ return 0;
+}
+
+static int cs43130_runtime_resume(struct device *dev)
+{
+ struct cs43130_private *cs43130 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+ if (ret != 0) {
+ dev_err(dev, "Failed to enable supplies: %d\n",
+ ret);
+ return ret;
+ }
+
+ regcache_cache_only(cs43130->regmap, false);
+
+ gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
+
+ usleep_range(2000, 2050);
+
+ ret = regcache_sync(cs43130->regmap);
+ if (ret != 0) {
+ dev_err(dev, "Failed to restore register cache\n");
+ goto err;
+ }
+ return 0;
+err:
+ regcache_cache_only(cs43130->regmap, true);
+ regulator_bulk_disable(CS43130_NUM_SUPPLIES,
+ cs43130->supplies);
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops cs43130_runtime_pm = {
+ SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id cs43130_of_match[] = {
+ { .compatible = "cirrus,cs43130", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, cs43130_of_match);
+
+static const struct i2c_device_id cs43130_i2c_id[] = {
+ {"cs43130", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
+
+static struct i2c_driver cs43130_i2c_driver = {
+ .driver = {
+ .name = "cs43130",
+ .of_match_table = cs43130_of_match,
+ },
+ .id_table = cs43130_i2c_id,
+ .probe = cs43130_i2c_probe,
+ .remove = cs43130_i2c_remove,
+};
+
+module_i2c_driver(cs43130_i2c_driver);
+
+MODULE_AUTHOR("Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs43130.h b/sound/soc/codecs/cs43130.h
new file mode 100644
index 0000000..bceae76
--- /dev/null
+++ b/sound/soc/codecs/cs43130.h
@@ -0,0 +1,268 @@
+/*
+ * ALSA SoC CS43130 codec driver
+ *
+ * Copyright 2016 Cirrus Logic, Inc.
+ *
+ * Author: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#ifndef __CS43130_H__
+#define __CS43130_H__
+
+/* CS43130 registers addresses */
+/* all reg address is shifted by a byte for control byte to be LSB */
+#define CS43130_FIRSTREG 0x010000
+#define CS43130_LASTREG 0x0F0014
+#define CS43130_CHIP_ID 0x00043130
+#define CS4399_CHIP_ID 0x00043990
+#define CS43130_DEVID_AB 0x010000 /*Device ID A & B [RO]*/
+#define CS43130_DEVID_CD 0x010001 /*Device ID C & D [RO]*/
+#define CS43130_DEVID_E 0x010002 /*Device ID E [RO]*/
+#define CS43130_FAB_ID 0x010003 /*Fab ID [RO]*/
+#define CS43130_REV_ID 0x010004 /*Revision ID [RO]*/
+#define CS43130_SUBREV_ID 0x010005 /*Subrevision ID*/
+#define CS43130_SYS_CLK_CTL_1 0x010006 /*System Clocking Ctl 1*/
+#define CS43130_SP_SRATE 0x01000B /*Serial Port Sample Rate*/
+#define CS43130_SP_BITSIZE 0x01000C /*Serial Port Bit Size*/
+#define CS43130_PAD_INT_CFG 0x01000D /*Pad Interface Config*/
+#define CS43130_DXD1 0x010010 /*DXD1*/
+#define CS43130_PWDN_CTL 0x020000 /*Power Down Ctl*/
+#define CS43130_DXD2 0x020019 /*DXD2*/
+#define CS43130_CRYSTAL_SET 0x020052 /*Crystal Setting*/
+#define CS43130_PLL_SET_1 0x030001 /*PLL Setting 1*/
+#define CS43130_PLL_SET_2 0x030002 /*PLL Setting 2*/
+#define CS43130_PLL_SET_3 0x030003 /*PLL Setting 3*/
+#define CS43130_PLL_SET_4 0x030004 /*PLL Setting 4*/
+#define CS43130_PLL_SET_5 0x030005 /*PLL Setting 5*/
+#define CS43130_PLL_SET_6 0x030008 /*PLL Setting 6*/
+#define CS43130_PLL_SET_7 0x03000A /*PLL Setting 7*/
+#define CS43130_PLL_SET_8 0x03001B /*PLL Setting 8*/
+#define CS43130_PLL_SET_9 0x040002 /*PLL Setting 9*/
+#define CS43130_PLL_SET_10 0x040003 /*PLL Setting 10*/
+#define CS43130_CLKOUT_CTL 0x040004 /*CLKOUT Ctl*/
+#define CS43130_ASP_NUM_1 0x040010 /*ASP Numerator 1*/
+#define CS43130_ASP_NUM_2 0x040011 /*ASP Numerator 2*/
+#define CS43130_ASP_DENOM_1 0x040012 /*ASP Denominator 1*/
+#define CS43130_ASP_DENOM_2 0x040013 /*ASP Denominator 2*/
+#define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /*ASP LRCK High Time 1*/
+#define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /*ASP LRCK High Time 2*/
+#define CS43130_ASP_LRCK_PERIOD_1 0x040016 /*ASP LRCK Period 1*/
+#define CS43130_ASP_LRCK_PERIOD_2 0x040017 /*ASP LRCK Period 2*/
+#define CS43130_ASP_CLOCK_CONF 0x040018 /*ASP Clock Config*/
+#define CS43130_ASP_FRAME_CONF 0x040019 /*ASP Frame Config*/
+#define CS43130_XSP_NUM_1 0x040020 /*XSP Numerator 1*/
+#define CS43130_XSP_NUM_2 0x040021 /*XSP Numerator 2*/
+#define CS43130_XSP_DENOM_1 0x040022 /*XSP Denominator 1*/
+#define CS43130_XSP_DENOM_2 0x040023 /*XSP Denominator 2*/
+#define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /*XSP LRCK High Time 1*/
+#define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /*XSP LRCK High Time 2*/
+#define CS43130_XSP_LRCK_PERIOD_1 0x040026 /*XSP LRCK Period 1*/
+#define CS43130_XSP_LRCK_PERIOD_2 0x040027 /*XSP LRCK Period 2*/
+#define CS43130_XSP_CLOCK_CONF 0x040028 /*XSP Clock Config*/
+#define CS43130_XSP_FRAME_CONF 0x040029 /*XSP Frame Config*/
+#define CS43130_ASP_CH_1_LOC 0x050000 /*ASP Chan 1 Location*/
+#define CS43130_ASP_CH_2_LOC 0x050001 /*ASP Chan 2 Location*/
+#define CS43130_ASP_CH_1_SZ_EN 0x05000A /*ASP Chan 1 Size, Enable*/
+#define CS43130_ASP_CH_2_SZ_EN 0x05000B /*ASP Chan 2 Size, Enable*/
+#define CS43130_XSP_CH_1_LOC 0x060000 /*XSP Chan 1 Location*/
+#define CS43130_XSP_CH_2_LOC 0x060001 /*XSP Chan 2 Location*/
+#define CS43130_XSP_CH_1_SZ_EN 0x06000A /*XSP Chan 1 Size, Enable*/
+#define CS43130_XSP_CH_2_SZ_EN 0x06000B /*XSP Chan 2 Size, Enable*/
+#define CS43130_DSD_VOL_B 0x070000 /*DSD Volume B*/
+#define CS43130_DSD_VOL_A 0x070001 /*DSD Volume A*/
+#define CS43130_DSD_PATH_CTL_1 0x070002 /*DSD Proc Path Sig Ctl 1*/
+#define CS43130_DSD_INT_CFG 0x070003 /*DSD Interface Config*/
+#define CS43130_DSD_PATH_CTL_2 0x070004 /*DSD Proc Path Sig Ctl 2*/
+#define CS43130_DSD_PCM_MIX_CTL 0x070005 /*DSD and PCM Mixing Ctl*/
+#define CS43130_DSD_PATH_CTL_3 0x070006 /*DSD Proc Path Sig Ctl 3*/
+#define CS43130_HP_OUT_CTL_1 0x080000 /*HP Output Ctl 1*/
+#define CS43130_PCM_FILT_OPT 0x090000 /*PCM Filter Option*/
+#define CS43130_PCM_VOL_B 0x090001 /*PCM Volume B*/
+#define CS43130_PCM_VOL_A 0x090002 /*PCM Volume A*/
+#define CS43130_PCM_PATH_CTL_1 0x090003 /*PCM Path Signal Ctl 1*/
+#define CS43130_PCM_PATH_CTL_2 0x090004 /*PCM Path Signal Ctl 2*/
+#define CS43130_CLASS_H_CTL 0x0B0000 /*Class H Ctl*/
+#define CS43130_HP_DETECT 0x0D0000 /*HP Detect*/
+#define CS43130_HP_STATUS 0x0D0001 /*HP Status [RO]*/
+#define CS43130_HP_LOAD_1 0x0E0000 /*HP Load 1*/
+#define CS43130_HP_MEAS_LOAD_1 0x0E0003 /*HP Load Measurement 1*/
+#define CS43130_HP_MEAS_LOAD_2 0x0E0004 /*HP Load Measurement 2*/
+#define CS43130_HP_DC_STAT_1 0x0E000D /*HP DC Load Status 0 [RO]*/
+#define CS43130_HP_DC_STAT_2 0x0E000E /*HP DC Load Status 1 [RO]*/
+#define CS43130_HP_AC_STAT_1 0x0E0010 /*HP AC Load Status 0 [RO]*/
+#define CS43130_HP_AC_STAT_2 0x0E0011 /*HP AC Load Status 1 [RO]*/
+#define CS43130_HP_LOAD_STAT 0x0E001A /*HP Load Status [RO]*/
+#define CS43130_INT_STATUS_1 0x0F0000 /*Interrupt Status 1*/
+#define CS43130_INT_STATUS_2 0x0F0001 /*Interrupt Status 2*/
+#define CS43130_INT_STATUS_3 0x0F0002 /*Interrupt Status 3*/
+#define CS43130_INT_STATUS_4 0x0F0003 /*Interrupt Status 4*/
+#define CS43130_INT_STATUS_5 0x0F0004 /*Interrupt Status 5*/
+#define CS43130_INT_MASK_1 0x0F0010 /*Interrupt Mask 1*/
+#define CS43130_INT_MASK_2 0x0F0011 /*Interrupt Mask 2*/
+#define CS43130_INT_MASK_3 0x0F0012 /*Interrupt Mask 3*/
+#define CS43130_INT_MASK_4 0x0F0013 /*Interrupt Mask 4*/
+#define CS43130_INT_MASK_5 0x0F0014 /*Interrupt Mask 5*/
+
+#define CS43130_MCLK_SRC_SEL_MASK 0x03
+#define CS43130_MCLK_SRC_SEL_SHIFT 0
+#define CS43130_MCLK_INT_MASK 0x04
+#define CS43130_MCLK_INT_SHIFT 2
+#define CS43130_SP_SRATE_MASK 0x0F
+#define CS43130_SP_SRATE_SHIFT 0
+#define CS43130_SP_BITSIZE_ASP_MASK 0x03
+#define CS43130_SP_BITSIZE_ASP_SHIFT 0
+#define CS43130_HP_DETECT_CTRL_SHIFT 6
+#define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
+#define CS43130_HP_DETECT_INV_SHIFT 5
+#define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)
+
+/* CS43130_INT_MASK_1 */
+#define CS43130_HP_PLUG_INT_SHIFT 6
+#define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)
+#define CS43130_HP_UNPLUG_INT_SHIFT 5
+#define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)
+#define CS43130_XTAL_RDY_INT_SHIFT 4
+#define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)
+#define CS43130_XTAL_ERR_INT_SHIFT 3
+#define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)
+
+/*Reg CS43130_SP_BITSIZE*/
+#define CS43130_SP_BIT_SIZE_8 0x00
+#define CS43130_SP_BIT_SIZE_16 0x01
+#define CS43130_SP_BIT_SIZE_24 0x02
+#define CS43130_SP_BIT_SIZE_32 0x03
+
+/*PLL*/
+#define CS43130_PLL_START_MASK (0x1<<0)
+#define CS43130_PLL_MODE_MASK 0x02
+#define CS43130_PLL_MODE_SHIFT 1
+
+#define CS43130_PLL_REF_PREDIV_MASK 0x3
+
+#define CS43130_ASP_STP_MASK 0x10
+#define CS43130_ASP_STP_SHIFT 4
+#define CS43130_ASP_5050_MASK 0x08
+#define CS43130_ASP_5050_SHIFT 3
+#define CS43130_ASP_FSD_MASK 0x07
+#define CS43130_ASP_FSD_SHIFT 0
+
+#define CS43130_ASP_MODE_MASK 0x10
+#define CS43130_ASP_MODE_SHIFT 4
+#define CS43130_ASP_SCPOL_OUT_MASK 0x08
+#define CS43130_ASP_SCPOL_OUT_SHIFT 3
+#define CS43130_ASP_SCPOL_IN_MASK 0x04
+#define CS43130_ASP_SCPOL_IN_SHIFT 2
+#define CS43130_ASP_LCPOL_OUT_MASK 0x02
+#define CS43130_ASP_LCPOL_OUT_SHIFT 1
+#define CS43130_ASP_LCPOL_IN_MASK 0x01
+#define CS43130_ASP_LCPOL_IN_SHIFT 0
+
+/*Reg CS43130_PWDN_CTL*/
+#define CS43130_PDN_XSP_MASK 0x80
+#define CS43130_PDN_XSP_SHIFT 7
+#define CS43130_PDN_ASP_MASK 0x40
+#define CS43130_PDN_ASP_SHIFT 6
+#define CS43130_PDN_DSPIF_MASK 0x20
+#define CS43130_PDN_DSDIF_SHIFT 5
+#define CS43130_PDN_HP_MASK 0x10
+#define CS43130_PDN_HP_SHIFT 4
+#define CS43130_PDN_XTAL_MASK 0x08
+#define CS43130_PDN_XTAL_SHIFT 3
+#define CS43130_PDN_PLL_MASK 0x04
+#define CS43130_PDN_PLL_SHIFT 2
+#define CS43130_PDN_CLKOUT_MASK 0x02
+#define CS43130_PDN_CLKOUT_SHIFT 1
+
+#define CS43130_7_0_MASK 0xFF
+#define CS43130_15_8_MASK 0xFF00
+#define CS43130_23_16_MASK 0xFF0000
+
+/* Reg CS43130_HP_OUT_CTL_1 */
+#define CS43130_HP_IN_EN_SHIFT 3
+#define CS43130_HP_IN_EN_MASK 0x08
+
+#define CS43130_ASP_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
+ SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#define CS43130_XSP_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+enum cs43130_asp_rate {
+ CS43130_ASP_SPRATE_32K = 0,
+ CS43130_ASP_SPRATE_44_1K,
+ CS43130_ASP_SPRATE_48K,
+ CS43130_ASP_SPRATE_88_2K,
+ CS43130_ASP_SPRATE_96K,
+ CS43130_ASP_SPRATE_176_4K,
+ CS43130_ASP_SPRATE_192K,
+ CS43130_ASP_SPRATE_352_8K,
+ CS43130_ASP_SPRATE_384K,
+};
+
+enum cs43130_mclk_src_sel {
+ CS43130_MCLK_SRC_XTAL = 0,
+ CS43130_MCLK_SRC_PLL,
+ CS43130_MCLK_SRC_RCO
+};
+
+enum cs43130_mode {
+ CS43130_SLAVE_MODE = 0,
+ CS43130_MASTER_MODE
+};
+
+enum cs43130_xtal_ibias {
+ CS43130_XTAL_IBIAS_15UA = 2,
+ CS43130_XTAL_IBIAS_12_5UA = 4,
+ CS43130_XTAL_IBIAS_7_5UA = 6,
+};
+
+#define CS43130_AIF_BICK_RATE 1
+#define CS43130_SYSCLK_MCLK 1
+#define CS43130_NUM_SUPPLIES 5
+static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
+ "VA",
+ "VP",
+ "VCP",
+ "VD",
+ "VL",
+};
+
+#define CS43130_NUM_INT 5 /* number of interrupt status reg */
+
+struct cs43130_private {
+ struct snd_soc_codec *codec;
+ struct regmap *regmap;
+ struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];
+ /* codec device ID */
+ unsigned int dev_id;
+ int mclk;
+ int sclk;
+ int xtal_ibias;
+
+ bool pll_bypass;
+ int pll_out;
+ int mclk_int;
+ int dai_format;
+ int dai_mode;
+ int dai_bit;
+ int asp_size;
+ int fs;
+ bool bick_invert;
+ bool lrck_invert;
+ int bick;
+ struct gpio_desc *reset_gpio;
+};
+
+#endif /* __CS43130_H__ */
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH 9/9] arm64: dts: rockchip: add regulator info for Kevin digitizer
From: Heiko Stuebner @ 2016-12-13 17:36 UTC (permalink / raw)
To: Brian Norris
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Doug Anderson,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Chris Zhong, Stephen Barber,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Caesar Wang
In-Reply-To: <1480645653-36943-10-git-send-email-briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Am Donnerstag, 1. Dezember 2016, 18:27:33 CET schrieb Brian Norris:
> We need to enable this regulator before the digitizer can be used. Wacom
> recommended waiting for 100 ms before talking to the HID.
>
> Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> Uses WIP bindings:
>
> [PATCH v3 1/2] devicetree: i2c-hid: Add regulator support
> https://patchwork.kernel.org/patch/9457493/
if you notice the bindings being accepted before me, could you notify here
please?
Thanks
Heiko
^ permalink raw reply
* Re: [PATCH v4 4/4] regulator: Prevent falling too fast
From: Mark Brown @ 2016-12-13 17:19 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Doug Anderson, Liam Girdwood, Brian Norris,
Javier Martinez Canillas, Rob Herring, Mark Rutland,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161212211502.GA96889-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
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On Mon, Dec 12, 2016 at 01:15:02PM -0800, Matthias Kaehlcke wrote:
> El Fri, Oct 28, 2016 at 07:15:21PM +0100 Mark Brown ha dit:
> > On Mon, Sep 26, 2016 at 10:41:59AM -0700, Doug Anderson wrote:
> > What you're describing to me is a discrete DCDC that has an input
> > voltage that sets the output voltage which happens to be set with a PWM.
> I experimented a bit with this. Besides the question of how to model
> the passives I wonder how the two regulators would interact. The
> correct thing seems to be to specify the input regulator as a supply
> of the DCDC. dcdc->set_voltage breaks down a voltage transition into
No, not unless the prior descriptions of the hardware have been wildly
inaccurate - my understanding had been that the DCDC was a normal DCDC
with an analogue input intended to be biased to set the output voltage
(presumably in terms of a full rail supply) and that the PWM had been
connected to this analogue input. If the PWM is supplying the DCDC then
the hardware design just seems bizzare, I can't see how this would even
work.
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^ permalink raw reply
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