* Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers
From: Linus Walleij @ 2016-12-27 22:16 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Rob Herring, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20161220073551.28522-3-andrew@aj.id.au>
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
>
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
Patch applied, adding Rob's ack in the process.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v4 3/5] pinctrl: aspeed-g4: Add mux configuration for all pins
From: Linus Walleij @ 2016-12-27 22:18 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Rob Herring, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Timothy Pearson
In-Reply-To: <20161220073551.28522-4-andrew@aj.id.au>
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The patch introducing the g4 pinctrl driver implemented a smattering of
> pins to flesh out the implementation of the core and provide bare-bones
> support for some OpenPOWER platforms. Now, update the bindings document
> to reflect the complete functionality and implement the necessary pin
> configuration tables in the driver.
>
> Cc: Timothy Pearson <tpearson@raptorengineering.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Acked-by: Joel Stanley <joel@jms.id.au>
> Acked-by: Rob Herring <robh@kernel.org>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [RFC PATCH 3/6] ARM64: dts: exynos5433: add the pcie_phy node for PCIe
From: Jaehoon Chung @ 2016-12-27 22:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-pci, devicetree, linux-kernel, linux-samsung-soc, bhelgaas,
robh+dt, mark.rutland, kgene, javier, kishon, will.deacon,
catalin.marinas, cpgs
In-Reply-To: <20161227161134.ds67t5byucphwkjg@kozik-lap>
On 12/28/2016 01:11 AM, Krzysztof Kozlowski wrote:
> On Mon, Dec 26, 2016 at 02:20:26PM +0900, Jaehoon Chung wrote:
>> To use the generic PHY framework, adds the pcie_phy node.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 64226d5..2a15f18 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -805,6 +805,11 @@
>> reg = <0x145f0000 0x1038>;
>> };
>>
>> + syscon_fsys: syscon@156f0000 {
>> + compatible = "syscon";
>> + reg = <0x156f0000 0x1044>;
>> + };
>> +
>> gsc_0: video-scaler@13C00000 {
>> compatible = "samsung,exynos5433-gsc";
>> reg = <0x13c00000 0x1000>;
>> @@ -1443,6 +1448,15 @@
>> status = "disabled";
>> };
>> };
>> +
>> + pcie_phy: pcie-phy@15680000 {
>> + #phy-cells = <0>;
>> + compatible = "samsung,exynos5433-pcie-phy";
>
> Mostly we use the convention of compatible being first property.
>
>> + reg = <0x15680000 0x1000>;
>> + samsung,pmureg-phandle = <&pmu_system_controller>;
>> + samsung,fsys-sysreg = <&syscon_fsys>;
>> + status = "okay";
>
> Why do you need to put status=okay here?
Not need. Will remove.
Best Regards,
Jaehoon Chung
>
> Best regards,
> Krzysztof
>
>> + };
>> };
>>
>> timer: timer {
>> --
>> 2.10.2
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply
* Re: [RFC PATCH 5/6] Documentation: pci: add the exynos5433-pcie binding
From: Jaehoon Chung @ 2016-12-27 23:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-pci, devicetree, linux-kernel, linux-samsung-soc, bhelgaas,
robh+dt, mark.rutland, kgene, javier, kishon, will.deacon,
catalin.marinas, cpgs
In-Reply-To: <20161227161916.nb6yf3n2kmkzkeg2@kozik-lap>
On 12/28/2016 01:19 AM, Krzysztof Kozlowski wrote:
> On Mon, Dec 26, 2016 at 02:20:28PM +0900, Jaehoon Chung wrote:
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> .../devicetree/bindings/pci/exynos5433-pcie.txt | 36 ++++++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>> new file mode 100644
>> index 0000000..932a847
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>> @@ -0,0 +1,36 @@
>> +* Samsung Exynos5433 PCIe interface
>> +
>> +This PCIe host controller is based on the Synopsis Designware PCIe IP
>
> Synopsys.
Will fix.
>
>> +and thus inherits all the common properties defined in designware-pcie.txt.
>> +
>> +Required properties:
>> +- compatible: "samsung,exynos5433-pcie"
>> +- reg: base addresses and lengths of the pcie controller,
>> + the phy controller, additional register for the phy controller.
>
> You mentioned three regs but the example contains four of them. Is the
> config comming from snps,dw-pcie?
Oops..It's my mistake. Just needs to put three reg.
Elbi : External local Bus interface register.
Dbi : Data bus interface register.(Control register.)
Config : for configuration space.
"config" can be removed. Because it's not Exynos specific, synopsys's Required property.
>
>> +- reg-names: Must be "elbi", "phy" and "dbi" for each regs
>
> Again, three here, four in example.
Will fix.
>
>> +- interrupt-names: Must be "intr" for legacy interrupt pin.
>> +
>> +Other common properites refer to
>> + Documentation/devicetree/binding/pci/designware-pcie.txt
>> +
>> +Example:
>> +
>> + pcie: pcie@15700000 {
>> + compatible ="samsung,exynos5433-pcie", "snps,dw-pcie";
> ^
> space needed
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "intr";
>> + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
>> + clock-names = "pcie", "pcie_bus";
>> + num-lanes = <1>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pcie_bus>;
>> + reg = <0x156b0000 0x1000>, <0x15680000 0x1000>,
>> + <0x15700000 0x1000>, <0x0c000000 0x1000>;
>
> Indentation here looks wrong. You indented it with spaces after tabs...
> but not to align with line before.
Will fix.
Best Regards,
Jaehoon Chung
>
> Beside that, fine with me:
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> Best regards,
> Krzysztof
>
>
>> + reg-names = "elbi", "phy", "dbi", "config";
>> + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000
>> + 0x82000000 0 0x0c011000 0x0c011000 0 0x3feefff>;
>> + status = "disabled";
>> + };
>> --
>> 2.10.2
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply
* Re: [RFC PATCH 6/6] ARM64: exynos: add the pcie node for TM2
From: Jaehoon Chung @ 2016-12-27 23:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-pci, devicetree, linux-kernel, linux-samsung-soc, bhelgaas,
robh+dt, mark.rutland, kgene, javier, kishon, will.deacon,
catalin.marinas, cpgs
In-Reply-To: <20161227163200.6noed454fmtgozrv@kozik-lap>
On 12/28/2016 01:32 AM, Krzysztof Kozlowski wrote:
> On Mon, Dec 26, 2016 at 02:20:29PM +0900, Jaehoon Chung wrote:
>> Add the Exxynos5433 pcie node for TM2.
>> This pcie device is used for supporting WiFi.
>>
>> And some gpios are already requested from pinctrl. so it doesn't need to
>> initialize.
>> GPJ2-0 is used for supplying to WiFi PCIe chip.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 7 +++++++
>> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 11 +++++++++--
>> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 23 ++++++++++++++++++++++
>> 3 files changed, 39 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
>> index ad71247..3e8b728 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
>> @@ -183,6 +183,13 @@
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> };
>> +
>> + pcie_wlanen: pcie-wlanen {
>> + samsung,pins = "gpj2-0";
>> + samsung,pin-function = <0>;
>> + samsung,pin-pud = <3>;
>> + samsung,pin-drv = <3>;
>> + };
>> };
>>
>> &pinctrl_finger {
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index f21bdc2..c84a2ad 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -737,6 +737,15 @@
>> bus-width = <4>;
>> };
>>
>> +&pcie {
>> + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
>> + <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
>> + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
>> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
>> + assigned-clock-rates = <0>, <100000000>;
>> + status = "okay";
>> +};
>> +
>> &pinctrl_alive {
>> pinctrl-names = "default";
>> pinctrl-0 = <&initial_alive>;
>> @@ -836,7 +845,6 @@
>> pinctrl-0 = <&initial_ese>;
>>
>> initial_ese: initial-state {
>> - PIN(IN, gpj2-0, DOWN, LV1);
>> PIN(IN, gpj2-1, DOWN, LV1);
>> PIN(IN, gpj2-2, DOWN, LV1);
>> };
>> @@ -851,7 +859,6 @@
>> PIN(IN, gpr3-1, DOWN, LV1);
>> PIN(IN, gpr3-2, DOWN, LV1);
>> PIN(IN, gpr3-3, DOWN, LV1);
>> - PIN(IN, gpr3-7, NONE, LV1);
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 2a15f18..da287f4 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -1457,6 +1457,29 @@
>> samsung,fsys-sysreg = <&syscon_fsys>;
>> status = "okay";
>> };
>> +
>> + pcie: pcie@15700000 {
>> + compatible = "samsung,exynos5433-pcie", "snps,dw-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "intr";
>> + clocks = <&cmu_fsys CLK_PCIE>,
>> + <&cmu_fsys CLK_PCLK_PCIE_PHY>;
>
> Here and in the 'reg' property - indentation looks weird. Tabs+spaces
> but not aligned. Either you use spaces to align... or just don't care
> and use tabs. I prefer consistency and below the 'ranges' property is
> aligned.
Will fix.
>
>> + clock-names = "pcie", "pcie_bus";
>> + num-lanes = <1>;
>> + pinctrl-names = "default";
>> + phys = <&pcie_phy>;
>> + phy-names = "pcie-phy";
>> + pinctrl-0 = <&pcie_bus &pcie_wlanen>;
>> + reg = <0x156b0000 0x1000>, <0x15700000 0x1000>,
>> + <0x0c000000 0x1000>;
>> + reg-names = "elbi", "dbi", "config";
>
> This does not match the bindings documentation.
This is right. Bindings documentation is wrong. :)
And I will put the prefix as "dts" on subject, according to your other comment.
Best Regards,
Jaehoon Chung
>
> Best regards,
> Krzysztof
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply
* Re: [PATCH v4 4/5] pinctrl: aspeed-g5: Add mux configuration for all pins
From: Linus Walleij @ 2016-12-28 0:22 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Rob Herring, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161220073551.28522-5-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> wrote:
> The patch introducing the g5 pinctrl driver implemented a smattering of
> pins to flesh out the implementation of the core and provide bare-bones
> support for some OpenPOWER platforms and the AST2500 evaluation board.
> Now, update the bindings document to reflect the complete functionality
> and implement the necessary pin configuration tables in the driver.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> Acked-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Patch applied.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* Re: [PATCH v4 5/5] pinctrl: aspeed: Fix kerneldoc return descriptions
From: Linus Walleij @ 2016-12-28 0:23 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Rob Herring, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20161220073551.28522-6-andrew@aj.id.au>
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Acked-by: Joel Stanley <joel@jms.id.au>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [RESEND PATCH V3 4/4] gpio: pv88080: Add GPIO function support
From: Linus Walleij @ 2016-12-28 0:28 UTC (permalink / raw)
To: Eric Jeong
Cc: Alexandre Courbot, LINUX-GPIO, LINUX-KERNEL, DEVICETREE,
Lee Jones, Liam Girdwood, Mark Brown, Mark Rutland, Rob Herring,
Support Opensource
In-Reply-To: <3e5d9f938494bf7420577ca2f55fd243705d9415.1481002393.git.eric.jeong@diasemi.com>
On Tue, Dec 6, 2016 at 6:33 AM, Eric Jeong
<eric.jeong.opensource@diasemi.com> wrote:
> From: Eric Jeong <eric.jeong.opensource@diasemi.com>
>
> This patch adds support for PV88080 PMIC GPIOs.
> PV88080 has two configurable GPIOs.
>
> Kconfig and Makefile are updated to reflect support
> for PV88080 PMIC GPIO.
>
> Signed-off-by: Eric Jeong <eric.jeong.opensource@diasemi.com>
> +#include <linux/gpio.h>
Use
#include <linux/gpio/driver.h>
only.
> +#include <linux/mfd/pv88080.h>
I see this header is not yet upstream so I can't merge
this driver (else I would just correct the above and merge it).
With the oneliner change:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
I guess Lee needs to merge this with the MFD bits.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy
From: Stephen Boyd @ 2016-12-28 1:13 UTC (permalink / raw)
To: Vivek Gautam, Rob Herring
Cc: kishon, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Mark Rutland, Srinivas Kandagatla, linux-arm-msm
In-Reply-To: <CAFp+6iESYfFrLpidhAXrPm7LQtYa6dV1xOL=AjdMfLXgL8Fv8g@mail.gmail.com>
On 12/22/2016 08:52 PM, Vivek Gautam wrote:
>
>>> +
>>> +Optional properties:
>>> + - nvmem-cells: a list of phandles to nvmem cells that contain fused
>>> + tuning parameters for qusb2 phy, one for each entry
>>> + in nvmem-cell-names.
>>> + - nvmem-cell-names: must be "tune2_hstx_trim" for cell containing
>>> + HS Tx trim value.
>> ditto.
> nvmem doesn't allow, at this point, to get the cells by index.
> Its APIs take 'const char' cell id and get the cell.
>
> We should add this support to get the cell by index.
> Will create a patch for that, and drop the '-names' property from bindings.
>
If we introduce a cells based API just for this case of one phandle it
may make sense to allow the cell id to be NULL and default to whatever
cell is there without a names property. We do something similar with
clks where a NULL connection id defaults to the first phandle in the
list. Then we can avoid having a new set of DT specific APIs here. Of
course, documentation should be updated to indicate that a NULL cell_id
means use index 0 with DT.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 1/2] spi: bcm-qspi: Enable the driver on BMIPS_GENERIC
From: Florian Fainelli @ 2016-12-28 1:15 UTC (permalink / raw)
To: Jaedon Shin, Ralf Baechle
Cc: Kevin Cernekee, Rob Herring, linux-mips, devicetree
In-Reply-To: <20161227015923.882-2-jaedon.shin@gmail.com>
On 12/26/2016 05:59 PM, Jaedon Shin wrote:
> The Broadcom BCM7XXX ARM and MIPS based SoCs share a similar hardware
> block for SPI.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Jaehoon Chung @ 2016-12-28 2:49 UTC (permalink / raw)
To: Vivek Gautam
Cc: linux-pci, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
Bjorn Helgaas, robh+dt, Mark Rutland, Kukjin Kim, krzk, javier,
kishon, Will Deacon, catalin.marinas, CPGS
In-Reply-To: <CAFp+6iH0q9TNvPgv3_Nexm-vE6TBB_eQHXCwniO-Yn=fq+WWMg@mail.gmail.com>
Hi Vivek,
On 12/27/2016 02:53 PM, Vivek Gautam wrote:
> Hi Jaehoon,
>
>
> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> drivers/phy/Kconfig | 9 ++
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 237 insertions(+)
>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index fe00f91..94b0433 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>> This driver provides PHY interface for USB 3.0 DRD controller
>> present on Exynos5 SoC series.
>>
>> +config PHY_EXYNOS_PCIE
>> + bool "Exynos PCIe PHY driver"
>
> Is there a reason for this not being 'tristate' ?
Will change.
>
>> + depends on ARCH_EXYNOS && OF
>> + depends on PCI_EXYNOS5433
>> + select GENERIC_PHY
>> + help
>> + Enable PCIe PHY support for Exynos SoC series.
>
> If this driver is for Exynos5433, then same should come in this help
> text as well.
will support the other exynos series.
I'm working on refactoring exynos5440 with PHY generic Framework.
Then this drive is not for only Exnyos5433. how about?
>
>> + This driver provides PHY interface for Exynos PCIe controller.
>> +
>> config PHY_PISTACHIO_USB
>> tristate "IMG Pistachio USB2.0 PHY driver"
>> depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a534cf5..586344d 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -38,6 +38,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
>> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
>> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
>> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 0000000..0f5eefd
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,227 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
>> + * Jaehoon Chung <jh80.chung@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>
> nit: It's good to have these includes in alphabetical order.
Will fix.
>
>> +
>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>> +
>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>> +#define PCIE_PHY_MAC_RESET 0x208
>> +#define PCIE_MAC_RESET_MASK 0xFF
>> +#define PCIE_MAC_RESET BIT(4)
>> +#define PCIE_L1SUB_CM_CON 0x1010
>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>> +#define PCIE_PHY_COMMON_RESET 0x1020
>> +#define PCIE_PHY_RESET BIT(0)
>> +#define PCIE_PHY_GLOBAL_RESET 0x1040
>> +#define PCIE_GLOBAL_RESET BIT(0)
>> +#define PCIE_REFCLK BIT(1)
>> +#define PCIE_REFCLK_MASK 0x16
>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
>> +
>> +enum exynos_pcie_phy_data_type {
>> + PCIE_PHY_TYPE_EXYNOS5433,
>> +};
>> +
>> +struct exynos_pcie_phy_data {
>> + enum exynos_pcie_phy_data_type ctrl_type;
>
> Why do we need this controller type ?
> If there are changes in the IP between different version,
> then you can as well use different compatibles.
Do you mean is the using "of_device_is_compatible()"?
>
>> + u32 pmureg_offset; /* PMU_REG offset */
>
> Please use top comments.
>
>> + struct phy_ops *ops;
>> +};
>> +
>> +/* for Exynos pcie phy */
>> +struct exynos_pcie_phy {
>> + const struct exynos_pcie_phy_data *drv_data;
>> + struct regmap *pmureg;
>> + struct regmap *fsysreg;
>> + void __iomem *phy_base;
>
> just 'base' ?
Will change
>
>> +};
>> +
>> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
>> +{
>> + writel(val, base + offset);
>> +}
>> +
>> +static int exynos_pcie_phy_init(struct phy *phy)
>> +{
>> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> + if (ep->fsysreg) {
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_COMMON_RESET,
>> + PCIE_PHY_RESET, 1);
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_MAC_RESET,
>> + PCIE_MAC_RESET, 0);
>> + /* PHY refclk 24MHz */
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_GLOBAL_RESET,
>> + PCIE_REFCLK_MASK, PCIE_REFCLK);
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_GLOBAL_RESET,
>> + PCIE_GLOBAL_RESET, 0);
>> + }
>> +
>> + exynos_pcie_phy_writel(ep->phy_base, 0x11, PCIE_PHY_OFFSET(0x3));
>> +
>> + /* band gap reference on */
>> + exynos_pcie_phy_writel(ep->phy_base, 0, PCIE_PHY_OFFSET(0x20));
>> + exynos_pcie_phy_writel(ep->phy_base, 0, PCIE_PHY_OFFSET(0x4b));
>> +
>> + /* jitter tunning */
>> + exynos_pcie_phy_writel(ep->phy_base, 0x34, PCIE_PHY_OFFSET(0x4));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x02, PCIE_PHY_OFFSET(0x7));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x41, PCIE_PHY_OFFSET(0x21));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x7F, PCIE_PHY_OFFSET(0x14));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xC0, PCIE_PHY_OFFSET(0x15));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x61, PCIE_PHY_OFFSET(0x36));
>> +
>> + /* D0 uninit.. */
>> + exynos_pcie_phy_writel(ep->phy_base, 0x44, PCIE_PHY_OFFSET(0x3D));
>> +
>> + /* 24MHz */
>> + exynos_pcie_phy_writel(ep->phy_base, 0x94, PCIE_PHY_OFFSET(0x8));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xA7, PCIE_PHY_OFFSET(0x9));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x93, PCIE_PHY_OFFSET(0xA));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x6B, PCIE_PHY_OFFSET(0xC));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xA5, PCIE_PHY_OFFSET(0xF));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x34, PCIE_PHY_OFFSET(0x16));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xA3, PCIE_PHY_OFFSET(0x17));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xA7, PCIE_PHY_OFFSET(0x1A));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x71, PCIE_PHY_OFFSET(0x23));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x4C, PCIE_PHY_OFFSET(0x24));
>> +
>> + exynos_pcie_phy_writel(ep->phy_base, 0x0E, PCIE_PHY_OFFSET(0x26));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_OFFSET(0x7));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x48, PCIE_PHY_OFFSET(0x43));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x44, PCIE_PHY_OFFSET(0x44));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x03, PCIE_PHY_OFFSET(0x45));
>> + exynos_pcie_phy_writel(ep->phy_base, 0xA7, PCIE_PHY_OFFSET(0x48));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x13, PCIE_PHY_OFFSET(0x54));
>> + exynos_pcie_phy_writel(ep->phy_base, 0x04, PCIE_PHY_OFFSET(0x31));
>> + exynos_pcie_phy_writel(ep->phy_base, 0, PCIE_PHY_OFFSET(0x32));
>> +
>> + if (ep->fsysreg) {
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_COMMON_RESET,
>> + PCIE_PHY_RESET, 0);
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_MAC_RESET,
>> + PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int exynos_pcie_phy_power_on(struct phy *phy)
>> +{
>> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> + if (ep->pmureg) {
>> + if (regmap_update_bits(ep->pmureg, ep->drv_data->pmureg_offset,
>> + BIT(0), 1))
>> + dev_warn(&phy->dev, "Failed to update regmap bit.\n");
>> + }
>> +
>> + if (ep->fsysreg) {
>> + regmap_update_bits(ep->fsysreg, PCIE_PHY_GLOBAL_RESET,
>> + PCIE_APP_REQ_EXIT_L1_MODE, 0);
>> + regmap_update_bits(ep->fsysreg, PCIE_L1SUB_CM_CON,
>> + PCIE_REFCLK_GATING_EN, 0);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static struct phy_ops exynos_phy_ops = {
>
> const ?
Yep.
>
>> + .init = exynos_pcie_phy_init,
>> + .power_on = exynos_pcie_phy_power_on,
>> +};
>> +
>> +static const struct exynos_pcie_phy_data exynos5433_pcie_phy_data = {
>> + .ctrl_type = PCIE_PHY_TYPE_EXYNOS5433,
>> + .pmureg_offset = PCIE_EXYNOS5433_PMU_PHY_OFFSET,
>> + .ops = &exynos_phy_ops,
>> +};
>> +
>> +static const struct of_device_id exynos_pcie_phy_match[] = {
>> + {
>> + .compatible = "samsung,exynos5433-pcie-phy",
>> + .data = &exynos5433_pcie_phy_data,
>> + },
>> + {}
>
> missing comma after braces.
Will fix.
>
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
>> +
>> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct exynos_pcie_phy *exynos_phy;
>> + struct phy *generic_phy;
>> + struct phy_provider *phy_provider;
>> + struct resource *res;
>> + const struct exynos_pcie_phy_data *drv_data;
>> + const struct of_device_id *match;
>> +
>> + exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
>> + if (!exynos_phy)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + exynos_phy->phy_base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(exynos_phy->phy_base))
>> + return PTR_ERR(exynos_phy->phy_base);
>> +
>> + exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(np,
>> + "samsung,pmureg-phandle");
>> + if (IS_ERR(exynos_phy->pmureg)) {
>> + dev_warn(&pdev->dev, "pmureg syscon regmap lookup failed.\n");
>> + exynos_phy->pmureg = NULL;
>> + }
>
> Is this really optional ? There should be a failure path for IP versions that
> require this compulsorily.
Agreed. Will fix.
>
>> +
>> + match = of_match_node(exynos_pcie_phy_match, pdev->dev.of_node);
>> + drv_data = match->data;
>
> Please use of_device_get_match_data().
Ok.
>
>> + exynos_phy->drv_data = drv_data;
>> +
>> + exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(np,
>> + "samsung,fsys-sysreg");
>> + if (IS_ERR(exynos_phy->fsysreg)) {
>> + dev_warn(&pdev->dev, "Fsysreg syscon regmap lookup failed.\n");
>> + exynos_phy->fsysreg = NULL;
>> + }
>
> Same here, is this optional ?
Will fix.
Thanks for reviewing.
Best Regards,
Jaehoon Chung
>
>> +
>> + generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
>> + if (IS_ERR(generic_phy)) {
>> + dev_err(dev, "failed to create PHY\n");
>> + return PTR_ERR(generic_phy);
>> + }
>> +
>> + phy_set_drvdata(generic_phy, exynos_phy);
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static struct platform_driver exynos_pcie_phy_driver = {
>> + .probe = exynos_pcie_phy_probe,
>> + .driver = {
>> + .of_match_table = exynos_pcie_phy_match,
>> + .name = "exynos_pcie_phy",
>> + }
>> +};
>> +module_platform_driver(exynos_pcie_phy_driver);
>> --
>> 2.10.2
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
> Thanks
> Vivek
>
^ permalink raw reply
* [PATCH v29 9/9] Documentation: dt: chosen properties for arm64 kdump
From: AKASHI Takahiro @ 2016-12-28 4:37 UTC (permalink / raw)
To: catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: james.morse-5wv7dgnIgG8, geoff-wEGCiKHe2LqWVfeAwA7xHQ,
bauerman-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
dyoung-H+wXaHxf7aLQT0dZR+AlfA,
kexec-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, AKASHI Takahiro
In-Reply-To: <20161228043347.27358-1-takahiro.akashi-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
From: James Morse <james.morse-5wv7dgnIgG8@public.gmane.org>
Add documentation for
linux,crashkernel-base and crashkernel-size,
linux,usable-memory-range
linux,elfcorehdr
used by arm64 kdump to decribe the kdump reserved area, and
the elfcorehdr's location within it.
Signed-off-by: James Morse <james.morse-5wv7dgnIgG8@public.gmane.org>
[takahiro.akashi-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org: added "linux,crashkernel-base" and "-size" ]
Signed-off-by: AKASHI Takahiro <takahiro.akashi-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
---
Documentation/devicetree/bindings/chosen.txt | 50 ++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt
index 6ae9d82d4c37..7b115165e9ec 100644
--- a/Documentation/devicetree/bindings/chosen.txt
+++ b/Documentation/devicetree/bindings/chosen.txt
@@ -52,3 +52,53 @@ This property is set (currently only on PowerPC, and only needed on
book3e) by some versions of kexec-tools to tell the new kernel that it
is being booted by kexec, as the booting environment may differ (e.g.
a different secondary CPU release mechanism)
+
+linux,crashkernel-base
+linux,crashkernel-size
+----------------------
+
+These properties (currently used on PowerPC and arm64) indicates
+the base address and the size, respectively, of the reserved memory
+range for crash dump kernel.
+e.g.
+
+/ {
+ chosen {
+ linux,crashkernel-base = <0x9 0xf0000000>;
+ linux,crashkernel-size = <0x0 0x10000000>;
+ };
+};
+
+linux,usable-memory-range
+-------------------------
+
+This property (currently used only on arm64) holds the memory range,
+the base address and the size, which can be used as system ram on
+the *current* kernel. Note that, if this property is present, any memory
+regions under "memory" nodes in DT blob or ones marked as "conventional
+memory" in EFI memory map should be ignored.
+e.g.
+
+/ {
+ chosen {
+ linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>;
+ };
+};
+
+The main usage is for crash dump kernel to identify its own usable
+memory and exclude, at its boot time, any other memory areas that are
+part of the panicked kernel's memory.
+
+linux,elfcorehdr
+----------------
+
+This property (currently used only on arm64) holds the memory range,
+the address and the size, of the elf core header which mainly describes
+the panicked kernel's memory layout as PT_LOAD segments of elf format.
+e.g.
+
+/ {
+ chosen {
+ linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>;
+ };
+};
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy
From: Vivek Gautam @ 2016-12-28 5:40 UTC (permalink / raw)
To: Stephen Boyd
Cc: Rob Herring, kishon, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Mark Rutland, Srinivas Kandagatla,
linux-arm-msm
In-Reply-To: <a4fc38f0-425d-5d4f-7fe9-8245b5b9c3af@codeaurora.org>
On Wed, Dec 28, 2016 at 6:43 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 12/22/2016 08:52 PM, Vivek Gautam wrote:
>>
>>>> +
>>>> +Optional properties:
>>>> + - nvmem-cells: a list of phandles to nvmem cells that contain fused
>>>> + tuning parameters for qusb2 phy, one for each entry
>>>> + in nvmem-cell-names.
>>>> + - nvmem-cell-names: must be "tune2_hstx_trim" for cell containing
>>>> + HS Tx trim value.
>>> ditto.
>> nvmem doesn't allow, at this point, to get the cells by index.
>> Its APIs take 'const char' cell id and get the cell.
>>
>> We should add this support to get the cell by index.
>> Will create a patch for that, and drop the '-names' property from bindings.
>>
>
> If we introduce a cells based API just for this case of one phandle it
> may make sense to allow the cell id to be NULL and default to whatever
> cell is there without a names property. We do something similar with
> clks where a NULL connection id defaults to the first phandle in the
> list. Then we can avoid having a new set of DT specific APIs here. Of
> course, documentation should be updated to indicate that a NULL cell_id
> means use index 0 with DT.
Right. This makes sense. I didn't notice that we do something
similar in clocks.
I will post a new change for this (which should be pretty small
in comparison to earlier patchset that introduced new dt based APIs).
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 0/3] Add clock and power domain DT nodes for Mediatek MT2701
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch series base on v4.10-rc1, include MT2701 power domain and clock
DT nodes.
An early patch [1] which was not applied in v4.10-rc1 also included in this
patch series.
[1] https://patchwork.kernel.org/patch/9457625/
James Liao (3):
arm: dts: mt2701: Sort DT nodes by register address
arm: dts: mt2701: Add subsystem clock controller device nodes
arm: dts: mt2701: Add power domain controller device node
arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++----------
1 file changed, 66 insertions(+), 18 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 1/3] arm: dts: mt2701: Sort DT nodes by register address
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao@mediatek.com>
This patch rearrange MT2701 DT nodes to keep them in ascending order.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- pio: pinctrl@10005000 {
- compatible = "mediatek,mt2701-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- syscfg_pctl_a: syscfg@10005000 {
- compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
topckgen: syscon@10000000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2701-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ syscfg_pctl_a: syscfg@10005000 {
+ compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] arm: dts: mt2701: Add subsystem clock controller device nodes
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao@mediatek.com>
Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys,
vdecsys, hifsys, ethsys and bdpsys.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 73f4b7c..150c48d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -214,4 +214,40 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt2701-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt2701-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt2701-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt2701-hifsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt2701-ethsys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ bdpsys: syscon@1c000000 {
+ compatible = "mediatek,mt2701-bdpsys", "syscon";
+ reg = <0 0x1c000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] arm: dts: mt2701: Add power domain controller device node
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Add power domain controller node (scpsys) for MT2701.
Signed-off-by: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/mt2701.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 150c48d..bdf8954 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -13,6 +13,7 @@
*/
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt2701-resets.h>
@@ -134,6 +135,17 @@
reg = <0 0x10005000 0 0x1000>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt2701-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "mm", "mfg", "ethif";
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
--
1.9.1
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC PATCH 0/5] overlay: tool to convert old overlay style dts to new style
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
In response to "Subject: Re: [PATCH v11 5/7] overlay: Documentation for the
overlay sugar syntax" I suggested a tool to convert the old style of dts
overlay files to use the new syntactic sugar [1]:
>>> I can imagine some reasons to support the fully written out version,
>>> but can we document what those reasons are?
>>
>> I believe the main one is the dts files in this format out in the
>> field. Mind you, I guess we're already requiring them to tweak how
>> they declare the /plugin/ option.
>
> It might be easy to write a program that transforms the expanded
> format to the simple format. I'll try to make some time to see
> how difficult it is. The transformation is relatively easy to
> do manually, but I don't know how many dts files would need to
> be converted.
My goal is to minimize legacy issues of dts files that expose the
internal implementation of overlays, such as the fragment and
__overlay__ nodes. Pantelis has submitted the dtc patches to add
the necessary syntactic sugar, and these appear to be moving toward
acceptance.
I have created a perl script to create a new style dts overlay file
from an old style dts overlay file. I have also created a shell
script to provide some error checking and to validate that the
new dts file compiles to the same result as the old dts file.
I treat the issue as a simplistic text processing exercise instead
of using a more complex approach with the hope that this is
sufficient to process the bulk of the existing in the wild overlay
dts files.
I do not think it is worth cluttering the dtc git repo with these
tools, but have no objection to them being hosted there if David
prefers. I can host them on github, elinux.org, or anywhere else
that makes sense for a (hopefully) short lived tool.
Patches 3, 4, and 5 are sample old style dts overlay files and
are not intended to be committed.
Following are several examples of use. One example that converts
properly and two that show how convsersion a malformed old style
dts is reported.
----- example 1
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new a.dts b.dts
$ cat a.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&am3353x_pinmux>;
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
target = <&i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
$ cat b.dts
/dts-v1/;
/plugin/;
&am3353x_pinmux {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
$ diff -u a.dts b.dts
--- a.dts 2016-12-27 15:51:36.433101164 -0800
+++ b.dts 2016-12-27 22:01:28.541530464 -0800
@@ -1,11 +1,7 @@
/dts-v1/;
/plugin/;
-/ {
- fragment@0 {
- target = <&am3353x_pinmux>;
-
- __overlay__ {
+ &am3353x_pinmux {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
@@ -14,12 +10,8 @@
>;
};
};
- };
-
- fragment@1 {
- target = <&i2c1>;
- __overlay__ {
+ &i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -33,5 +25,3 @@
reg = <0x50>;
};
};
- };
-};
----- example 2
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new bad_a_1.dts bad_b_1.dts
No 'target' property in node fragment@0
ERROR: unable to convert bad_a_1.dts
$ cat bad_a_1.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
target = <&i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
----- example 3
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new bad_a_2.dts bad_b_2.dts
No 'target' property in node fragment@1
ERROR: unable to convert bad_a_2.dts
$ cat bad_a_2.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&am3353x_pinmux>;
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
[1] http://www.spinics.net/lists/devicetree/msg152891.html
Frank Rowand (5):
perl script to convert dts from old overlay style to new overlay style
shell script to make overlay_convert easier to use
a.dts: example of an old style dts file to be converted
bad_a_1.dts: example of an old style dts file unable to be converted
bad_a_2.dts: example of an old style dts file to be converted
^ permalink raw reply
* [RFC PATCH 1/5] overlay: perl script to convert dts from old overlay style to new overlay style
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Convert overlay dts file from hand-coded expanded form to new syntactic
sugar form.
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
overlay_convert | 158 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
create mode 100755 overlay_convert
diff --git a/overlay_convert b/overlay_convert
new file mode 100755
index 000000000000..fede0103fb4e
--- /dev/null
+++ b/overlay_convert
@@ -0,0 +1,158 @@
+#!/usr/bin/perl
+
+# Copyright 2016 Frank Rowand frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org
+# license: GPL V2
+# This file is subject to the terms and conditions of the GNU General Public
+# License v2.
+#
+# Convert overlay dts file from hand-coded expanded form to new syntactic
+# sugar form.
+
+# zzz TODO:
+# - May need to update the "/plugin/" declaration if dtc has changed.
+
+
+use strict 'refs';
+use strict subs;
+
+use Getopt::Long;
+
+$VUFX = "161227a";
+
+$script_name = $0;
+$script_name =~ s|^.*/||;
+
+
+sub usage()
+{
+ print STDERR
+"
+Usage: $script_name [options] DTS
+
+ Convert overlay dts file from hand-coded expanded form to new syntactic
+ sugar form.
+
+ Node names __symbols__, __fixups__, and __local_fixups__ are not allowed.
+ Their presence suggests that DTS has been compiled into a .dtbo and then
+ de-compiled. This is not the preferred form of source since phandle
+ references are not of the form: &label.
+
+Valid options:
+
+ -h Synonym for --help
+ --help Display this message
+ --version Display program version and exit
+
+
+ Return value:
+ 0 no error
+ 1 error processing command line
+ 2 unable to open or read DTS
+ 10 DTS contains a node name other than __overlay__, with leading '_'
+ 11 DTS contains a fragment node with no target property
+
+";
+}
+
+
+# -----------------------------------------------------------------------------
+# program entry point
+
+Getopt::Long::Configure("no_ignore_case", "bundling");
+
+if (!GetOptions(
+ "h" => \$help,
+ "help" => \$help,
+ "version" => \$version,
+ )) {
+
+ exit 1;
+}
+
+if ($version) {
+ print STDERR "\n$script_name $VUFX\n";
+ exit 0;
+}
+
+if ($help) {
+ &usage;
+ exit 0;
+}
+
+
+# ----- scan DTS
+
+$node_depth = 0;
+
+LINE:
+while ($line = <ARGV>) {
+
+ # ----- start of node
+
+ if ($line =~ /{/) {
+ $node_depth++;
+ $node_name = $line;
+ chomp $node_name;
+ $indent = $node_name;
+ $indent =~ s/\S.*//;
+ $node_name =~ s/^\s*//;
+ $node_name =~ s/\s*{.*//;
+
+ $in_fragment = 0;
+ if (($node_depth == 2) && ($node_name =~ /^fragment@\d*$/)) {
+ $in_fragment = 1;
+ $fragment_name = $node_name;
+ push @fragment_depth, $node_depth;
+ } elsif ($node_name =~ /^__overlay__$/) {
+ if (!$save_target) {
+ print STDERR "No 'target' property in node ${fragment_name}\n";
+ exit 11
+ }
+ print "$indent$save_target {\n";
+ undef $save_target;
+ } elsif ($node_name =~ /^_/) {
+ # might be __symbols__, __fixups__, or __local_fixups__
+ print STDERR "\nIllegal node name: $node_name\n\n";
+ exit 10;
+ } elsif ($node_depth > 1) {
+ print "$indent$node_name {\n";
+ }
+
+ next LINE;
+ }
+
+
+ # ----- end of node
+
+ if ($line =~ /}/) {
+
+ $indent = $line;
+ chomp $indent;
+ $indent =~ s/\S.*//;
+
+ $fragment_depth = pop @fragment_depth;
+ if (($node_depth > 2) && ($fragment_depth != $node_depth)) {
+ push @fragment_depth, $fragment_depth;
+ print "$line";
+ }
+
+ $node_depth--;
+
+ next LINE;
+ }
+
+
+ # ----- anything else
+
+ if ($in_fragment && ($line =~ /target = </)) {
+ $save_target = $line;
+ chomp $save_target;
+ $save_target =~ s/.*<\s*//;
+ $save_target =~ s/\s*>.*//;
+ } elsif (!$in_fragment) {
+ print "$line";
+ }
+
+ next LINE;
+
+}
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 2/5] overlay: shell script to make overlay_convert easier to use
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
A slightly paranoid wrapper around overlay_convert. Verifies that
converted dts file is equivalent to original dts file.
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
overlay_convert_old_to_new | 144 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100755 overlay_convert_old_to_new
diff --git a/overlay_convert_old_to_new b/overlay_convert_old_to_new
new file mode 100755
index 000000000000..bc26c57d4dc1
--- /dev/null
+++ b/overlay_convert_old_to_new
@@ -0,0 +1,144 @@
+#! /bin/bash
+
+#_______________________________________________________________________________
+
+
+function usage
+{
+echo "" >&2
+echo "usage:" >&2
+echo " `basename $0` -h | -help | --help" >&2
+echo " `basename $0` [options] OLD_DTS NEW_DTS" >&2
+echo "" >&2
+echo " Convert OLD_DTS from old overlay style to new overlay style" >&2
+echo " using syntactic sugar." >&2
+echo "" >&2
+echo " Options:" >&2
+echo " -h synonym for --help" >&2
+echo " --help print this message" >&2
+echo " -o synonym for --overwrite" >&2
+echo " --overwrite overwrite NEW_DTS if it already exists" >&2
+echo "" >&2
+echo " The early patches to dtc to support overlays required 'fragment'" >&2
+echo " and '__overlay__' nodes in the .dts source. Later patches to dtc" >&2
+echo " will not require these nodes (and may possibly disallow them)." >&2
+echo " The new overlay style is expected to be the preferrred form." >&2
+echo "" >&2
+echo " Will not overwrite NEW_DTS if it already exists." >&2
+echo "" >&2
+echo " Exit status is:" >&2
+echo " 0 success" >&2
+echo " 1 general error" >&2
+echo " 2 NEW_DTS already exists" >&2
+echo " 3 conversion problem" >&2
+echo " 4 'dtc -@ -O dts OLD_DTS' is different than 'dtc -@ -O dts NEW_DTS'" >&2
+echo "" >&2
+}
+
+
+unset new_dts
+unset old_dts
+unset overwrite
+
+while [[ ($# -gt 0) ]] ; do
+
+ case $1 in
+
+ -o | --overwrite )
+ shift
+ overwrite=1
+ ;;
+
+ -h | -help | --help )
+ shift
+ help=1
+ ;;
+
+ * )
+ if [[ "${old_dts}" != "" ]] ; then
+
+ if [[ "${new_dts}" != "" ]] ; then
+ echo "" >&2
+ echo "ERROR: too many arguments" >&2
+ echo "" >&2
+ exit 1
+ fi
+
+ new_dts=$1
+ shift
+ else
+ old_dts=$1
+ shift
+ fi
+ ;;
+
+ esac
+done
+
+
+if [[ (${help} == 1) ]] ; then
+ usage
+ exit 1
+fi
+
+
+#_______________________________________________________________________________
+
+if [[ -f ${new_dts} && overwrite -eq 0 ]] ; then
+
+ echo "" >&2
+ echo "ERROR: file '${new_dts}' already exists" >&2
+ echo "" >&2
+
+ exit 2
+fi
+
+
+#_______________________________________________________________________________
+
+
+if which overlay_convert >/dev/null ; then
+ OVERLAY_CONVERT=overlay_convert
+elif which ./overlay_convert >/dev/null ; then
+ OVERLAY_CONVERT=./overlay_convert
+else
+ echo "" >&2
+ echo "ERROR: overlay_convert not found or not executable" >&2
+ echo "" >&2
+
+ exit 1
+fi
+
+if ! ${OVERLAY_CONVERT} ${old_dts} > ${new_dts} ; then
+
+ echo "" >&2
+ echo "ERROR: unable to convert ${old_dts}" >&2
+ echo "" >&2
+
+ rm ${new_dts}
+
+ exit 3
+fi
+
+
+if ! which dtc >/dev/null ; then
+
+ echo "" >&2
+ echo "ERROR: dtc not found or not executable" >&2
+ echo " add the location of dtc to \$PATH" >&2
+ echo "" >&2
+
+ exit 1
+fi
+
+if ! diff -q \
+ <(dtc -@ -O dts ${old_dts} 2>/dev/null) \
+ <(dtc -@ -O dts ${new_dts} 2>/dev/null) ; then
+
+ echo "" >&2
+ echo "ERROR: ${new_dts} is not equivalent to ${old_dts}" >&2
+ echo "" >&2
+
+ exit 4
+fi
+
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 3/5] overlay: a.dts, example of an old style dts file to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new a.dts b.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
a.dts | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 a.dts
diff --git a/a.dts b/a.dts
new file mode 100644
index 000000000000..ec21206a081f
--- /dev/null
+++ b/a.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&am3353x_pinmux>;
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC PATCH 4/5] overlay: bad_a_1.dts, example of an old style dts file unable to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new bad_a_1.dts bad_b_1.dts
No 'target' property in node fragment@0
ERROR: unable to convert bad_a_1.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
bad_a_1.dts | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 bad_a_1.dts
diff --git a/bad_a_1.dts b/bad_a_1.dts
new file mode 100644
index 000000000000..b4e26fc8d945
--- /dev/null
+++ b/bad_a_1.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 5/5] overlay: bad_a_2.dts, example of an old style dts file to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new bad_a_2.dts bad_b_2.dts
No 'target' property in node fragment@1
ERROR: unable to convert bad_a_2.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
bad_a_2.dts | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 bad_a_2.dts
diff --git a/bad_a_2.dts b/bad_a_2.dts
new file mode 100644
index 000000000000..68ac978f516c
--- /dev/null
+++ b/bad_a_2.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&am3353x_pinmux>;
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 2/2] MIPS: BMIPS: Add support SPI device nodes
From: Jaedon Shin @ 2016-12-28 7:39 UTC (permalink / raw)
To: Florian Fainelli
Cc: Ralf Baechle, Kevin Cernekee, Rob Herring,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <0dffeca2-68bf-bacd-7eff-8b966c721dde-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> On 28 Dec 2016, at 7:12 AM, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> On 12/26/2016 05:59 PM, Jaedon Shin wrote:
>> Adds SPI device nodes to BCM7xxx MIPS based SoCs.
>>
>> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> arch/mips/boot/dts/brcm/bcm7125.dtsi | 55 +++++++++++++++++++++++++++++--
>> arch/mips/boot/dts/brcm/bcm7346.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7358.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7360.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7362.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7420.dtsi | 55 +++++++++++++++++++++++++++++--
>> arch/mips/boot/dts/brcm/bcm7425.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7435.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97358svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97360svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97362svmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97420c.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97425svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97435svmb.dts | 4 +++
>> 16 files changed, 526 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> index bbd00f65ce39..c1e19e57f64a 100644
>> --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> @@ -46,6 +46,12 @@
>> #clock-cells = <0>;
>> clock-frequency = <27000000>;
>> };
>> +
>> + spi_clk: spi_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <27000000>;
>> + };
>
> Nit, this should actually be upg_clk, since this is the clock that the
> SPI controller uses, and it is a fixed-clock with a 27Mhz frequency.
>
> Other than that, the rest looks good to me, thanks!
> --
> Florian
I will change the qspi uses upg_clk in v2.
Thanks,
Jaedon
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^ permalink raw reply
* Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Vivek Gautam @ 2016-12-28 8:58 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-pci, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
Bjorn Helgaas, robh+dt, Mark Rutland, Kukjin Kim, krzk, javier,
kishon, Will Deacon, catalin.marinas, CPGS
In-Reply-To: <21de9ca7-e586-e5c8-ecda-d30c18bb6e40@samsung.com>
Hi Jaehoon,
On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi Vivek,
>
> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>>
>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>> When Exynos that supported the pcie want to use the PCIe,
>>> it needs to control the phy resgister.
>>> But it should be more complex to control in their own PCIe device drivers.
>>>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> ---
>>> drivers/phy/Kconfig | 9 ++
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 237 insertions(+)
>>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index fe00f91..94b0433 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>> This driver provides PHY interface for USB 3.0 DRD controller
>>> present on Exynos5 SoC series.
>>>
>>> +config PHY_EXYNOS_PCIE
>>> + bool "Exynos PCIe PHY driver"
>>
>> Is there a reason for this not being 'tristate' ?
>
> Will change.
I notice that PCI_EXYNOS5433 is bool as well.
If the host has to be 'bool' then it makes sense to have phy
also bool as well. But if PCI_EXYNOS5433 can be made
tristate, then this also changes to tristate.
>
>>
>>> + depends on ARCH_EXYNOS && OF
>>> + depends on PCI_EXYNOS5433
>>> + select GENERIC_PHY
>>> + help
>>> + Enable PCIe PHY support for Exynos SoC series.
>>
>> If this driver is for Exynos5433, then same should come in this help
>> text as well.
>
> will support the other exynos series.
> I'm working on refactoring exynos5440 with PHY generic Framework.
> Then this drive is not for only Exnyos5433. how about?
Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
makes it look like it is for EXYNOS5433. I am fine if that changes as well.
[...]
>>> +
>>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>>> +
>>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>>> +#define PCIE_PHY_MAC_RESET 0x208
>>> +#define PCIE_MAC_RESET_MASK 0xFF
>>> +#define PCIE_MAC_RESET BIT(4)
>>> +#define PCIE_L1SUB_CM_CON 0x1010
>>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>>> +#define PCIE_PHY_COMMON_RESET 0x1020
>>> +#define PCIE_PHY_RESET BIT(0)
>>> +#define PCIE_PHY_GLOBAL_RESET 0x1040
>>> +#define PCIE_GLOBAL_RESET BIT(0)
>>> +#define PCIE_REFCLK BIT(1)
>>> +#define PCIE_REFCLK_MASK 0x16
>>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
>>> +
>>> +enum exynos_pcie_phy_data_type {
>>> + PCIE_PHY_TYPE_EXYNOS5433,
>>> +};
>>> +
>>> +struct exynos_pcie_phy_data {
>>> + enum exynos_pcie_phy_data_type ctrl_type;
>>
>> Why do we need this controller type ?
>> If there are changes in the IP between different version,
>> then you can as well use different compatibles.
>
> Do you mean is the using "of_device_is_compatible()"?
I meant that multiple compatible strings can be added based on the
IP versions. And any IP specific data can be put in the .data field
of 'of_device_id' structure.
If there's more to differentiate between the IP versions at runtime,
you can use of_device_is_compatible().
[...]
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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