* Re: [PATCH v3 1/4] devicetree: hwmon: Add bindings for ADC128D818
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Alexander Koch
Cc: linux-kernel, linux-hwmon, Mark Rutland, Jean Delvare,
Guenter Roeck, Michael Hornung, devicetree
In-Reply-To: <20170106103817.11588-2-mail@alexanderkoch.net>
On Fri, Jan 06, 2017 at 11:38:14AM +0100, Alexander Koch wrote:
> Add bindings documentation for the ADC128D818 driver, featuring default I2C
> properties along with the optional 'mode' property for chip operation mode
> selection (see datasheet, sec. 8.4.1).
>
> Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
> Acked-by: Michael Hornung <mhornung.linux@gmail.com>
> ---
> .../devicetree/bindings/hwmon/adc128d818.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/adc128d818.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v7 1/5] dt-bindings: zte: add bindings document for zx2967 power domain controller
From: Rob Herring @ 2017-01-10 5:35 UTC (permalink / raw)
To: Baoyou Xie
Cc: jun.nie-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
davem-fT/PcQaiUtIeIZ0/mPfg9Q,
geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ,
akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b,
mchehab-DgEjT+Ai2ygdnm+yROfE0A, krzk-DgEjT+Ai2ygdnm+yROfE0A,
arnd-r2nGTMty4D4, claudiu.manoil-3arQi8VN3Tc,
amitdanielk-Re5JQEeQqe8AvxtiuMwx3w,
pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ, yangbo.lu-3arQi8VN3Tc,
scott.branden-dY08KVG/lbpWk0Htik3J/w,
simon.horman-wFxRvT7yatFl57MIdRCFDg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1483694164-7668-1-git-send-email-baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Fri, Jan 06, 2017 at 05:16:00PM +0800, Baoyou Xie wrote:
> This patch adds device tree bindings document for ZTE zx2967
> family power domain controller.
>
> Signed-off-by: Baoyou Xie <baoyou.xie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../devicetree/bindings/soc/zte/pd-2967xx.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH RESEND] dmaengine: stm32-dma: Add error messages if xlate fails
From: Vinod Koul @ 2017-01-10 5:21 UTC (permalink / raw)
To: M'boumba Cedric Madianga
Cc: robh+dt, mark.rutland, mcoquelin.stm32, alexandre.torgue,
dan.j.williams, dmaengine, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <1483603780-3368-1-git-send-email-cedric.madianga@gmail.com>
On Thu, Jan 05, 2017 at 09:09:40AM +0100, M'boumba Cedric Madianga wrote:
> This patch adds some error messages when a slave device fails to request a
> channel.
Applied now
--
~Vinod
^ permalink raw reply
* Re: [PATCH resend v4 2/3] ARM: dts: imx6: Support Savageboard dual
From: Milo Kim @ 2017-01-10 4:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Sascha Hauer, Fabio Estevam, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20170110032736.GX20956@dragon>
On 01/10/2017 12:27 PM, Shawn Guo wrote:
> On Wed, Jan 04, 2017 at 04:04:36PM +0900, Milo Kim wrote:
>> Common savageboard DT file is used for board support.
>> Add the vendor name and specify the dtb file for i.MX6Q build.
>>
>> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
>> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
>> ---
>> .../devicetree/bindings/vendor-prefixes.txt | 1 +
> The bindings change should be ideally a separate patch. But since Rob
> seems to be fine with it this time, I just applied the whole series.
Got it. Thanks for taking this.
Best regards,
Milo
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU
From: Xing Zheng @ 2017-01-10 3:31 UTC (permalink / raw)
To: Doug Anderson
Cc: Heiko Stübner, open list:ARM/Rockchip SoC...,
Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Caesar Wang, Shawn Lin,
Brian Norris, Jianqun Xu, Elaine Zhang, David Wu, linux-clk,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAD=FV=UsMR=HD5799N7ny_Ce8XXCkcd3R3tpX34AEC6UmGkXtA@mail.gmail.com>
Hi, Doug
On 2017年01月10日 11:06, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng <zhengxing@rock-chips.com> wrote:
>> The structure rockchip_clk_provider needs to refer the GRF regmap
>> in somewhere, if the CRU node has not "rockchip,grf" property,
>> calling syscon_regmap_lookup_by_phandle will return an invalid GRF
>> regmap, and the MUXGRF type clock will be not supported.
>>
>> Therefore, we need to add them.
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> ---
>>
>> Changes in v3:
>> - add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
>>
>> Changes in v2:
>> - referring pmugrf for PMUGRU
>> - fix the typo "invaild" in COMMIT message
>>
>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +++++
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
> "dts" and bindings shouldn't change in the same patch since they go
> through different trees. This is why I said:
>
>> This looks sane to me, but before you land it you need to first send
>> up a (separate) patch that adjusts:
>> --------
> AKA: you need a two patch series here.
>
> Sometimes it's OK to include bindings together with code changes
> (depends on the maintainer), but never with dts changes.
>
> -Doug
For little lazy, I did refer other SoC platform to using "dts" and
bindings in the same patch...
OK, I will use a two patch series.
Thanks
>
>
--
- Xing Zheng
^ permalink raw reply
* Re: [PATCH resend v4 2/3] ARM: dts: imx6: Support Savageboard dual
From: Shawn Guo @ 2017-01-10 3:27 UTC (permalink / raw)
To: Milo Kim
Cc: Sascha Hauer, Fabio Estevam, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170104070436.3425-1-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Wed, Jan 04, 2017 at 04:04:36PM +0900, Milo Kim wrote:
> Common savageboard DT file is used for board support.
> Add the vendor name and specify the dtb file for i.MX6Q build.
>
> Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
> Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> .../devicetree/bindings/vendor-prefixes.txt | 1 +
The bindings change should be ideally a separate patch. But since Rob
seems to be fine with it this time, I just applied the whole series.
Shawn
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6dl-savageboard.dts | 51 ++++++++++++++++++++++
> 3 files changed, 53 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-savageboard.dts
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* RE: [PATCH v2 04/12] driver: clk: imx: Add clock driver for imx6sll
From: Jacky Bai @ 2017-01-10 3:18 UTC (permalink / raw)
To: Stephen Boyd
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org, Fabio Estevam,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
jacky.baip-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
In-Reply-To: <20170110003753.GM17126-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> > +#include <dt-bindings/clock/imx6sll-clock.h>
> > +#include <linux/clk.h>
> > +#include <linux/clkdev.h>
>
> Is this used?
Sorry, this should be removed.
>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
>
> Is this used?
I will remove it.
>
> > +#include <linux/types.h>
> > +
> > +#include "clk.h"
> > +
> > +#define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
> > +#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
> > +#define CCDR 0x4
> > +#define xPLL_CLR(offset) (offset + 0x8)
> > +
> > +static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
>
> All these should be const char * const unless something is wrong.
If changed to 'const char * const', it vill has argument type mismatch error, as imx_clk_* wrapper function
has argument type 'const char *'.
>
> > +static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src",
> > +}; static const char *pll2_bypass_sels[] = { "pll2",
> > +"pll2_bypass_src", }; static const char *pll3_bypass_sels[] = {
> > +"pll3", "pll3_bypass_src", }; static const char *pll4_bypass_sels[] =
> > +{ "pll4", "pll4_bypass_src", }; static const char *pll5_bypass_sels[]
> > += { "pll5", "pll5_bypass_src", }; static const char
> > +*pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
> [...]
> > + clks[IMX6SLL_CLK_USDHC3] = imx_clk_gate2("usdhc3",
> "usdhc3_podf", base + 0x80, 6);
> > +
> > + /* mask handshake of mmdc */
> > + writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
> > +
> > + for (i = 0; i < ARRAY_SIZE(clks); i++)
> > + if (IS_ERR(clks[i]))
> > + pr_err("i.MX6SLL clk %d: register failed with %ld\n", i,
> > +PTR_ERR(clks[i]));
> > +
> > + clk_data.clks = clks;
> > + clk_data.clk_num = ARRAY_SIZE(clks);
> > + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> > +
> > + /* set perclk to from OSC */
> > + clk_set_parent(clks[IMX6SLL_CLK_PERCLK_SEL],
> clks[IMX6SLL_CLK_OSC]);
>
> Can this be done with assigned-clocks in DT?
Ok, I will move it to assigned-clocks in DT.
>
> > +
> > + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
> > + clk_prepare_enable(clks[clks_init_on[i]]);
>
> Critical clocks?
Yes, these clocks must be always on.
>
> > +
> > + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
> > + clk_prepare_enable(clks[IMX6SLL_CLK_USBPHY1_GATE]);
> > + clk_prepare_enable(clks[IMX6SLL_CLK_USBPHY2_GATE]);
>
> The phy driver can't enable these?
The reason why we enable these two clks here is in below commit
commit a5120e89e7e187a91852896f586876c7a2030804
Author: Peter Chen <peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Date: Fri Jan 18 10:38:05 2013 +0800
ARM i.MX6: change mxs usbphy clock usage
>
> > + }
> > +
> > + /* Lower the AHB clock rate before changing the clock source. */
> > + clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
> > +
> > + /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
> > + clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL],
> clks[IMX6SLL_CLK_PLL3_USB_OTG]);
> > + clk_set_parent(clks[IMX6SLL_CLK_PERIPH],
> clks[IMX6SLL_CLK_PERIPH_CLK2]);
> > + clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE],
> clks[IMX6SLL_CLK_PLL2_BUS]);
> > + clk_set_parent(clks[IMX6SLL_CLK_PERIPH],
> > +clks[IMX6SLL_CLK_PERIPH_PRE]);
> > +
> > + clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
>
> assigned-clocks for rates now? Or perhaps we shouldn't be exposing these as
> clks if they have some sort of complicated rate sequence switch that we can't
> guarantee with the clk_ops we have today.
These clks will be used by some peripherals, so we need to expose these clocks.
And the above parent and rate swith sequence is not very easy to be handled in assigned-clocks,
So we leave it in this place.
>
> > +}
> > +
> > +CLK_OF_DECLARE(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);
> > +
>
> Please drop this extra newline.
>
Thanks, will remove in V3.
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
> Foundation Collaborative Project
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^ permalink raw reply
* Re: [PATCH V3] arm64: dts: ls1046a: Add TMU device tree support
From: Shawn Guo @ 2017-01-10 3:12 UTC (permalink / raw)
To: Jia Hongtao
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w, yuantian.tang-3arQi8VN3Tc,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, scott.wood-3arQi8VN3Tc,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1483497385-22121-1-git-send-email-hongtao.jia-3arQi8VN3Tc@public.gmane.org>
On Wed, Jan 04, 2017 at 10:36:25AM +0800, Jia Hongtao wrote:
> Also add nodes and properties for thermal management support.
>
> Signed-off-by: Jia Hongtao <hongtao.jia-3arQi8VN3Tc@public.gmane.org>
Applied, thanks.
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^ permalink raw reply
* Re: [PATCH] ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 3
From: Olof Johansson @ 2017-01-10 3:11 UTC (permalink / raw)
To: Masahiro Yamada
Cc: arm, Arnd Bergmann, Rob Herring, devicetree, Krzysztof Kozlowski,
Kukjin Kim, linux-arm-msm, linux-kernel, Andy Gross, Russell King,
Javier Martinez Canillas, linux-samsung-soc, Rob Herring,
David Brown, Will Deacon, Mark Rutland, linux-soc,
Catalin Marinas, linux-arm-kernel
In-Reply-To: <1482853886-7932-1-git-send-email-yamada.masahiro@socionext.com>
On Wed, Dec 28, 2016 at 12:51:26AM +0900, Masahiro Yamada wrote:
> Tree-wide replacement was done by commit 2ef7d5f342c1 ("ARM, ARM64:
> dts: drop "arm,amba-bus" in favor of "simple-bus"), then the 2nd
> round by commit 15b7cc78f095 ("arm64: dts: drop "arm,amba-bus" in
> favor of "simple-bus" part 2").
>
> Here, some new users have appeared for Linux v4.10-rc1. Eliminate
> them now.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> Hi Arnd, Olof,
>
> Can you pick this up for v4.10 fixes?
>
> If we carry arm,amba-bus until the release, we will need to
> take more time to deprecate it.
Applied to fixes for 4.10.
Thanks,
-Olof
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU
From: Doug Anderson @ 2017-01-10 3:08 UTC (permalink / raw)
To: Xing Zheng
Cc: Heiko Stübner, open list:ARM/Rockchip SoC...,
Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Caesar Wang, Shawn Lin,
Brian Norris, Jianqun Xu, Elaine Zhang, David Wu, linux-clk,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <1484011661-13474-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Hi,
On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing pll rates are not changable, due to the missing pll lock status.
On rk3399 the GRF isn't used for pll lock status. It's used for PLL muxes.
...so technically if you don't include it then the PLL muxes won't be
changeable. Hopefully the code handles this if the property is listed
as "Optional". ...and unless Heiko says otherwise, you probably need
to list it as "Optional" since (presumably) there might be backward
compatibility issues.
-Doug
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^ permalink raw reply
* Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU
From: Doug Anderson @ 2017-01-10 3:06 UTC (permalink / raw)
To: Xing Zheng
Cc: Heiko Stübner, open list:ARM/Rockchip SoC...,
Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Caesar Wang, Shawn Lin,
Brian Norris, Jianqun Xu, Elaine Zhang, David Wu, linux-clk,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <1484011661-13474-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Hi,
On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> The structure rockchip_clk_provider needs to refer the GRF regmap
> in somewhere, if the CRU node has not "rockchip,grf" property,
> calling syscon_regmap_lookup_by_phandle will return an invalid GRF
> regmap, and the MUXGRF type clock will be not supported.
>
> Therefore, we need to add them.
>
> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>
> Changes in v3:
> - add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
>
> Changes in v2:
> - referring pmugrf for PMUGRU
> - fix the typo "invaild" in COMMIT message
>
> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +++++
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
"dts" and bindings shouldn't change in the same patch since they go
through different trees. This is why I said:
> This looks sane to me, but before you land it you need to first send
> up a (separate) patch that adjusts:
> --------
AKA: you need a two patch series here.
Sometimes it's OK to include bindings together with code changes
(depends on the maintainer), but never with dts changes.
-Doug
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^ permalink raw reply
* Re: [PATCH 0/2] ARM: dts: boundary: fix sgtl5000 pinctrl init
From: Shawn Guo @ 2017-01-10 2:59 UTC (permalink / raw)
To: Gary Bisson
Cc: fabio.estevam-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170103112247.4563-1-gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
On Tue, Jan 03, 2017 at 12:22:45PM +0100, Gary Bisson wrote:
> Gary Bisson (2):
> ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
> ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init
Applied both, thanks.
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^ permalink raw reply
* Re: [PATCH v3 1/2] Doc: devicetree: bindings: Add vendor prefix entry - lwn
From: Shawn Guo @ 2017-01-10 2:48 UTC (permalink / raw)
To: Lukasz Majewski
Cc: Rob Herring, Mark Rutland, Russell King, Fabio Estevam,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Vladimir Zapolskiy, Sascha Hauer, Zerlauth Karl (LWN),
Lukasz Majewski
In-Reply-To: <1483440381-24268-1-git-send-email-lukma-ynQEQJNshbs@public.gmane.org>
On Tue, Jan 03, 2017 at 11:46:20AM +0100, Lukasz Majewski wrote:
> This patch adds entry for LWN - the Liebherr-Werk Nenzing GmbH company to
> vendor-prefixes.txt file.
>
> Signed-off-by: Lukasz Majewski <lukma-ynQEQJNshbs@public.gmane.org>
Applied both, thanks.
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^ permalink raw reply
* Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU
From: Shawn Lin @ 2017-01-10 2:37 UTC (permalink / raw)
To: Xing Zheng, heiko
Cc: shawn.lin, Mark Rutland, devicetree, Elaine Zhang, linux-kernel,
Catalin Marinas, Michael Turquette, Brian Norris, Stephen Boyd,
Douglas Anderson, Will Deacon, dianders, linux-clk,
linux-rockchip, Rob Herring, David Wu, Jianqun Xu,
linux-arm-kernel, Caesar Wang
In-Reply-To: <1484011661-13474-1-git-send-email-zhengxing@rock-chips.com>
On 2017/1/10 9:27, Xing Zheng wrote:
> The structure rockchip_clk_provider needs to refer the GRF regmap
> in somewhere, if the CRU node has not "rockchip,grf" property,
> calling syscon_regmap_lookup_by_phandle will return an invalid GRF
> regmap, and the MUXGRF type clock will be not supported.
>
> Therefore, we need to add them.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---
>
> Changes in v3:
> - add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
>
> Changes in v2:
> - referring pmugrf for PMUGRU
> - fix the typo "invaild" in COMMIT message
>
> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +++++
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> index 3888dd3..f476b3d 100644
> --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> @@ -13,6 +13,11 @@ Required Properties:
> - #clock-cells: should be 1.
> - #reset-cells: should be 1.
>
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing pll rates are not changable, due to the missing pll lock status.
> +
It twists my tongue w/o proper punctuation:)
- rockchip,grf: phandle to the syscon managing the "general register
files". If missing, pll rates are not changable due to the missing pll
lock status.
> Each clock is assigned an identifier and client nodes can use this identifier
> to specify the clock which they consume. All available clocks are defined as
> preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index c928015..081621b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1077,6 +1077,7 @@
> pmucru: pmu-clock-controller@ff750000 {
> compatible = "rockchip,rk3399-pmucru";
> reg = <0x0 0xff750000 0x0 0x1000>;
> + rockchip,grf = <&pmugrf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> assigned-clocks = <&pmucru PLL_PPLL>;
> @@ -1086,6 +1087,7 @@
> cru: clock-controller@ff760000 {
> compatible = "rockchip,rk3399-cru";
> reg = <0x0 0xff760000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> assigned-clocks =
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* Re: [PATCH 1/2] Documentation: devicetree: Add document bindings for mtk-cir
From: Sean Wang @ 2017-01-10 2:35 UTC (permalink / raw)
To: Rob Herring
Cc: mchehab-JPH+aEBZ4P+UEJcrhfAQsw, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
hkallweit1-Re5JQEeQqe8AvxtiuMwx3w, mark.rutland-5wv7dgnIgG8,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sean-hENCXIMQXOg,
ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170109183214.xonv52sn3fo4exqp@rob-hp-laptop>
Hi Rob,
thanks for your effort for reviewing. I added comments inline.
On Mon, 2017-01-09 at 12:32 -0600, Rob Herring wrote:
> On Fri, Jan 06, 2017 at 12:06:23AM +0800, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> > From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >
> > This patch adds documentation for devicetree bindings for
> > Mediatek IR controller.
> >
> > Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > .../devicetree/bindings/media/mtk-cir.txt | 23 ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> > create mode 100644 linux-4.8.rc1_p0/Documentation/devicetree/bindings/media/mtk-cir.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/mtk-cir.txt b/Documentation/devicetree/bindings/media/mtk-cir.txt
> > new file mode 100644
> > index 0000000..bbedd71
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mtk-cir.txt
> > @@ -0,0 +1,23 @@
> > +Device-Tree bindings for Mediatek IR controller found in Mediatek SoC family
> > +
> > +Required properties:
> > +- compatible : "mediatek,mt7623-ir"
> > +- clocks : list of clock specifiers, corresponding to
> > + entries in clock-names property;
> > +- clock-names : should contain "clk" entries;
> > +- interrupts : should contain IR IRQ number;
> > +- reg : should contain IO map address for IR.
> > +
> > +Optional properties:
> > +- linux,rc-map-name : Remote control map name.
>
> Would 'label' be appropriate here instead? If not, this needs to be
> documented in a common location and explained better.
>
I checked with how the way applied in other IR drivers is and found that
most IR driver also use the same label to identify the scan/key table
they prefer to use such as gpio-ir-recv, ir-hix5hd2, meson-ir and
sunxi-cir or use hard coding inside the driver. So I thought it should
be appropriate here currently.
> > +
> > +Example:
> > +
> > +cir: cir@0x10013000 {
>
> Drop the '0x'.
>
okay, I will.
> > + compatible = "mediatek,mt7623-ir";
> > + reg = <0 0x10013000 0 0x1000>;
> > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg CLK_INFRA_IRRX>;
> > + clock-names = "clk";
> > + linux,rc-map-name = "rc-rc6-mce";
> > +};
> > --
> > 1.9.1
> >
--
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^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: exynos5433-tm2: enable HDMI/TV path
From: hoegeun kwon @ 2017-01-10 2:32 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc, Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas, devicetree,
Andi Shyti, Chanwoo Choi, Hoegeun Kwon
In-Reply-To: <1483958437-6572-3-git-send-email-a.hajda@samsung.com>
Hi Andrzej,
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Hoegeun
On 01/09/2017 07:40 PM, Andrzej Hajda wrote:
> TV path consist of following interconnected components:
> - DECON_TV - display controller,
> - HDMI - video signal converter RGB / HDMI,
> - MHL - video signal converter HDMI / MHL,
> - DDC - i2c slave device for EDID reading (on hsi2c_11 bus).
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> v2:
> - replaced magic numbers with macros,
> - removed assigned-clock properties from sii8620 -
> PMU clock is already confgured in PMU node
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 669bb1f..ca90e6a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -281,6 +281,22 @@
> };
> };
>
> +&decon_tv {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + tv_to_hdmi: endpoint {
> + remote-endpoint = <&hdmi_to_tv>;
> + };
> + };
> + };
> +};
> +
> &dsi {
> status = "okay";
> vddcore-supply = <&ldo6_reg>;
> @@ -304,6 +320,33 @@
> };
> };
>
> +&hdmi {
> + hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> + vdd-supply = <&ldo6_reg>;
> + vdd_osc-supply = <&ldo7_reg>;
> + vdd_pll-supply = <&ldo6_reg>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + hdmi_to_tv: endpoint {
> + remote-endpoint = <&tv_to_hdmi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + hdmi_to_mhl: endpoint {
> + remote-endpoint = <&mhl_to_hdmi>;
> + };
> + };
> + };
> +};
> +
> &hsi2c_0 {
> status = "okay";
> clock-frequency = <2500000>;
> @@ -692,6 +735,28 @@
> };
> };
>
> +&hsi2c_7 {
> + status = "okay";
> +
> + sii8620@39 {
> + reg = <0x39>;
> + compatible = "sil,sii8620";
> + cvcc10-supply = <&ldo36_reg>;
> + iovcc18-supply = <&ldo34_reg>;
> + interrupt-parent = <&gpf0>;
> + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> + reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
> + clocks = <&pmu_system_controller 0>;
> + clock-names = "xtal";
> +
> + port {
> + mhl_to_hdmi: endpoint {
> + remote-endpoint = <&hdmi_to_mhl>;
> + };
> + };
> + };
> +};
> +
> &hsi2c_8 {
> status = "okay";
>
> @@ -735,6 +800,10 @@
> };
> };
>
> +&hsi2c_11 {
> + status = "okay";
> +};
> +
> &i2s0 {
> status = "okay";
> };
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: exynos5433: add HDMI node
From: hoegeun kwon @ 2017-01-10 2:31 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti, Chanwoo Choi,
Hoegeun Kwon
In-Reply-To: <1483958437-6572-2-git-send-email-a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi Andrzej,
Tested-by: Hoegeun Kwon <hoegeun.kwon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hoegeun
On 01/09/2017 07:40 PM, Andrzej Hajda wrote:
> HDMI converts RGB/I80 signal from DECON_TV to HDMI/TMDS video stream.
>
> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> ---
> v2:
> - replaced magic numbers with macros,
> - removed power domains
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 5552f77..f82d26e 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -837,6 +837,35 @@
> iommu-names = "m0", "m1";
> };
>
> + hdmi: hdmi@13970000 {
> + compatible = "samsung,exynos5433-hdmi";
> + reg = <0x13970000 0x70000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_disp CLK_PCLK_HDMI>,
> + <&cmu_disp CLK_PCLK_HDMIPHY>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
> + <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
> + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
> + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
> + <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
> + clock-names = "hdmi_pclk", "hdmi_i_pclk",
> + "i_tmds_clk", "i_pixel_clk",
> + "tmds_clko", "tmds_clko_user",
> + "pixel_clko", "pixel_clko_user",
> + "oscclk", "i_spdif_clk";
> + phy = <&hdmiphy>;
> + ddc = <&hsi2c_11>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,sysreg-phandle = <&syscon_disp>;
> + status = "disabled";
> + };
> +
> + hdmiphy: hdmiphy@13af0000 {
> + reg = <0x13af0000 0x80>;
> + };
> +
> syscon_disp: syscon@13b80000 {
> compatible = "syscon";
> reg = <0x13b80000 0x1010>;
--
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^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: dts: exynos5433: add DECON_TV node
From: hoegeun kwon @ 2017-01-10 2:31 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc, Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas, devicetree,
Andi Shyti, Chanwoo Choi, Hoegeun Kwon
In-Reply-To: <1483958437-6572-1-git-send-email-a.hajda@samsung.com>
Hi Andrzej,
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Hoegeun
On 01/09/2017 07:40 PM, Andrzej Hajda wrote:
> DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
> or 2nd DSI path.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
>
> Hi Krzysztof,
>
> These patches are based on latest patches separating tm2 and tm2e and
> touchscreen patches. I hope this is good base.
> Thanks all for quick response/review.
>
> Regards
> Andrzej
>
> v2:
> - replaced magic numbers with macros,
> - removed power domains,
> - removed 0x prefixes from node names
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 43 ++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 68f764e..5552f77 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -814,6 +814,29 @@
> };
> };
>
> + decon_tv: decon@13880000 {
> + compatible = "samsung,exynos5433-decon-tv";
> + reg = <0x13880000 0x20b8>;
> + clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
> + <&cmu_disp CLK_ACLK_DECON_TV>,
> + <&cmu_disp CLK_ACLK_SMMU_TV0X>,
> + <&cmu_disp CLK_ACLK_XIU_TV0X>,
> + <&cmu_disp CLK_PCLK_SMMU_TV0X>,
> + <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
> + <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
> + clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
> + "aclk_xiu_decon0x", "pclk_smmu_decon0x",
> + "sclk_decon_vclk", "sclk_decon_eclk";
> + samsung,disp-sysreg = <&syscon_disp>;
> + interrupt-names = "fifo", "vsync", "lcd_sys";
> + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
> + iommu-names = "m0", "m1";
> + };
> +
> syscon_disp: syscon@13b80000 {
> compatible = "syscon";
> reg = <0x13b80000 0x1010>;
> @@ -912,6 +935,26 @@
> #iommu-cells = <0>;
> };
>
> + sysmmu_tv0x: sysmmu@13a20000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a20000 0x1000>;
> + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
> + <&cmu_disp CLK_ACLK_SMMU_TV0X>;
> + #iommu-cells = <0>;
> + };
> +
> + sysmmu_tv1x: sysmmu@13a30000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a30000 0x1000>;
> + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
> + <&cmu_disp CLK_ACLK_SMMU_TV1X>;
> + #iommu-cells = <0>;
> + };
> +
> sysmmu_gscl0: sysmmu@0x13C80000 {
> compatible = "samsung,exynos-sysmmu";
> reg = <0x13C80000 0x1000>;
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: exynos5433-tm2: enable HDMI/TV path
From: Chanwoo Choi @ 2017-01-10 2:20 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti
In-Reply-To: <1483958437-6572-3-git-send-email-a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi,
Looks good to me. I tested this patch on TM2 board
with Hoegeun Kwon (hoeguen.kwon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org). It is well working.
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
On 2017년 01월 09일 19:40, Andrzej Hajda wrote:
> TV path consist of following interconnected components:
> - DECON_TV - display controller,
> - HDMI - video signal converter RGB / HDMI,
> - MHL - video signal converter HDMI / MHL,
> - DDC - i2c slave device for EDID reading (on hsi2c_11 bus).
>
> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> ---
> v2:
> - replaced magic numbers with macros,
> - removed assigned-clock properties from sii8620 -
> PMU clock is already confgured in PMU node
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 669bb1f..ca90e6a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -281,6 +281,22 @@
> };
> };
>
> +&decon_tv {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + tv_to_hdmi: endpoint {
> + remote-endpoint = <&hdmi_to_tv>;
> + };
> + };
> + };
> +};
> +
> &dsi {
> status = "okay";
> vddcore-supply = <&ldo6_reg>;
> @@ -304,6 +320,33 @@
> };
> };
>
> +&hdmi {
> + hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> + vdd-supply = <&ldo6_reg>;
> + vdd_osc-supply = <&ldo7_reg>;
> + vdd_pll-supply = <&ldo6_reg>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + hdmi_to_tv: endpoint {
> + remote-endpoint = <&tv_to_hdmi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + hdmi_to_mhl: endpoint {
> + remote-endpoint = <&mhl_to_hdmi>;
> + };
> + };
> + };
> +};
> +
> &hsi2c_0 {
> status = "okay";
> clock-frequency = <2500000>;
> @@ -692,6 +735,28 @@
> };
> };
>
> +&hsi2c_7 {
> + status = "okay";
> +
> + sii8620@39 {
> + reg = <0x39>;
> + compatible = "sil,sii8620";
> + cvcc10-supply = <&ldo36_reg>;
> + iovcc18-supply = <&ldo34_reg>;
> + interrupt-parent = <&gpf0>;
> + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> + reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
> + clocks = <&pmu_system_controller 0>;
> + clock-names = "xtal";
> +
> + port {
> + mhl_to_hdmi: endpoint {
> + remote-endpoint = <&hdmi_to_mhl>;
> + };
> + };
> + };
> +};
> +
> &hsi2c_8 {
> status = "okay";
>
> @@ -735,6 +800,10 @@
> };
> };
>
> +&hsi2c_11 {
> + status = "okay";
> +};
> +
> &i2s0 {
> status = "okay";
> };
>
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
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^ permalink raw reply
* RE: [PATCH v4] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2017-01-10 2:19 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org, Bhaskar U,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20170110021717.GR20956@dragon>
>
> I changed subject a bit as below and applied patch.
>
> arm64: dts: Add support for FSL's LS1012A SoC
Thanks Shawn
Regards
Harry++
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* Re: [PATCH v2 2/3] arm64: dts: exynos5433: add HDMI node
From: Chanwoo Choi @ 2017-01-10 2:19 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti
In-Reply-To: <1483958437-6572-2-git-send-email-a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi,
Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
On 2017년 01월 09일 19:40, Andrzej Hajda wrote:
> HDMI converts RGB/I80 signal from DECON_TV to HDMI/TMDS video stream.
>
> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> ---
> v2:
> - replaced magic numbers with macros,
> - removed power domains
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 5552f77..f82d26e 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -837,6 +837,35 @@
> iommu-names = "m0", "m1";
> };
>
> + hdmi: hdmi@13970000 {
> + compatible = "samsung,exynos5433-hdmi";
> + reg = <0x13970000 0x70000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_disp CLK_PCLK_HDMI>,
> + <&cmu_disp CLK_PCLK_HDMIPHY>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
> + <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
> + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
> + <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
> + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
> + <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
> + clock-names = "hdmi_pclk", "hdmi_i_pclk",
> + "i_tmds_clk", "i_pixel_clk",
> + "tmds_clko", "tmds_clko_user",
> + "pixel_clko", "pixel_clko_user",
> + "oscclk", "i_spdif_clk";
> + phy = <&hdmiphy>;
> + ddc = <&hsi2c_11>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,sysreg-phandle = <&syscon_disp>;
> + status = "disabled";
> + };
> +
> + hdmiphy: hdmiphy@13af0000 {
> + reg = <0x13af0000 0x80>;
> + };
> +
> syscon_disp: syscon@13b80000 {
> compatible = "syscon";
> reg = <0x13b80000 0x1010>;
>
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
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^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: dts: exynos5433: add DECON_TV node
From: Chanwoo Choi @ 2017-01-10 2:18 UTC (permalink / raw)
To: Andrzej Hajda, linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
Krzysztof Kozlowski
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Inki Dae,
Rob Herring, Mark Rutland, Javier Martinez Canillas,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andi Shyti
In-Reply-To: <1483958437-6572-1-git-send-email-a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi,
On 2017년 01월 09일 19:40, Andrzej Hajda wrote:
> DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
> or 2nd DSI path.
>
> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> ---
>
> Hi Krzysztof,
>
> These patches are based on latest patches separating tm2 and tm2e and
> touchscreen patches. I hope this is good base.
> Thanks all for quick response/review.
>
> Regards
> Andrzej
>
> v2:
> - replaced magic numbers with macros,
> - removed power domains,
> - removed 0x prefixes from node names
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 43 ++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 68f764e..5552f77 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -814,6 +814,29 @@
> };
> };
>
> + decon_tv: decon@13880000 {
The 'decon_tv' node better to be located under the 'decon' node
because of base address ordering. (decon@13800000, decon_tv@13880000)
> + compatible = "samsung,exynos5433-decon-tv";
> + reg = <0x13880000 0x20b8>;
> + clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
> + <&cmu_disp CLK_ACLK_DECON_TV>,
> + <&cmu_disp CLK_ACLK_SMMU_TV0X>,
> + <&cmu_disp CLK_ACLK_XIU_TV0X>,
> + <&cmu_disp CLK_PCLK_SMMU_TV0X>,
> + <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
> + <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
> + clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
> + "aclk_xiu_decon0x", "pclk_smmu_decon0x",
> + "sclk_decon_vclk", "sclk_decon_eclk";
> + samsung,disp-sysreg = <&syscon_disp>;
> + interrupt-names = "fifo", "vsync", "lcd_sys";
> + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
> + iommu-names = "m0", "m1";
> + };
> +
[snip]
Except for ordering of 'decon_tv' node, looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Also, I tested these patches on TM2 board
with Hoegeun Kwon (hoeguen.kwon-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org). It is well working.
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
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^ permalink raw reply
* Re: [PATCH v4] arm64: Add DTS support for FSL's LS1012A SoC
From: Shawn Guo @ 2017-01-10 2:17 UTC (permalink / raw)
To: Harninder Rai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, oss-fOR+EgIDQEHk1uMJSBkQmQ,
Bhaskar Upadhaya,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1483437451-20971-1-git-send-email-harninder.rai-3arQi8VN3Tc@public.gmane.org>
On Tue, Jan 03, 2017 at 03:27:31PM +0530, Harninder Rai wrote:
> LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
> with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
> L1-D cache, as well as 256 KB of ECC protected L2 cache.
>
> Features summary
> One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
> - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
> protection
> - Speed up to 800 MHz
> - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
> - Neon SIMD engine
> - ARM v8 cryptography extensions
> One 16-bit DDR3L SDRAM memory controller
> ARM core-link CCI-400 cache coherent interconnect
> Cryptography acceleration (SEC)
> One Configurable x3 SerDes
> One PCI Express Gen2 controller, supporting x1 operation
> One serial ATA (SATA Gen 3.0) controller
> One USB 3.0/2.0 controller with integrated PHY
>
> Following levels of DTSI/DTS files have been created for the LS1012A
> SoC family:
>
> - fsl-ls1012a.dtsi:
> DTS-Include file for FSL LS1012A SoC.
>
> - fsl-ls1012a-frdm.dts:
> DTS file for FSL LS1012A FRDM board.
>
> - fsl-ls1012a-qds.dts:
> DTS file for FSL LS1012A QDS board.
>
> - fsl-ls1012a-rdb.dts:
> DTS file for FSL LS1012A RDB board.
>
> Signed-off-by: Harninder Rai <harninder.rai-3arQi8VN3Tc@public.gmane.org>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
I changed subject a bit as below and applied patch.
arm64: dts: Add support for FSL's LS1012A SoC
Shawn
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* [v3] MIPS: BMIPS: Add support SPI device nodes
From: Jaedon Shin @ 2017-01-10 2:00 UTC (permalink / raw)
To: Ralf Baechle, Florian Fainelli
Cc: Kevin Cernekee, Rob Herring, linux-mips-6z/3iImG2C8G8FEW9MqTrA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Jaedon Shin
Adds SPI device nodes to BCM7xxx MIPS based SoCs.
Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Hi all,
This series adds dependency with BMIPS_GENERIC for Broadcom MIPS based SoCs
and device nodes.
As far as I know the boards are booting from NAND by default except BCM97358,
BCM97360 and BCM97425, and therefore the SPI nodes for boot (qspi) of the boards
are disabled.
Changes in v3:
- Use decimal property instead of hexadecimal.
Changes in v2:
- Use upg_clk instead of new spi_clk.
arch/mips/boot/dts/brcm/bcm7125.dtsi | 49 +++++++++++++++++++++++++++++--
arch/mips/boot/dts/brcm/bcm7346.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7358.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7360.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7362.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7420.dtsi | 49 +++++++++++++++++++++++++++++--
arch/mips/boot/dts/brcm/bcm7425.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 43 +++++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 4 +++
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 4 +++
arch/mips/boot/dts/brcm/bcm97358svmb.dts | 36 +++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97360svmb.dts | 36 +++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97362svmb.dts | 4 +++
arch/mips/boot/dts/brcm/bcm97420c.dts | 4 +++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 36 +++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97435svmb.dts | 4 +++
16 files changed, 478 insertions(+), 6 deletions(-)
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
index bbd00f65ce39..79f838ed96c5 100644
--- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -91,15 +91,15 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
- brcm,int-map-mask = <0x44>, <0xf000000>;
+ brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
- interrupts = <18>, <19>;
- interrupt-names = "upg_main", "upg_bsc";
+ interrupts = <18>, <19>, <20>;
+ interrupt-names = "upg_main", "upg_bsc", "upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -226,5 +226,48 @@
interrupts = <61>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <79>;
+ };
+
+ qspi: spi@443000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@406400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x406400 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index 4bbcc95f1c15..da7bfa45a57d 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -439,5 +439,48 @@
interrupts = <85>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <31>;
+ };
+
+ qspi: spi@413000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@408a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x408a00 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
index 3e42535c8d29..9b05760453f0 100644
--- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -318,5 +318,48 @@
interrupts = <24>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <31>;
+ };
+
+ qspi: spi@413000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@408a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x408a00 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 112a5571c596..57b613c6acf2 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -358,5 +358,48 @@
interrupts = <82>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <31>;
+ };
+
+ qspi: spi@413000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@408a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x408a00 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index 34abfb0b07e7..c2a2843aaa9a 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -354,5 +354,48 @@
interrupts = <82>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <31>;
+ };
+
+ qspi: spi@413000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@408a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x408a00 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
index b143723c674e..532fc8a15796 100644
--- a/arch/mips/boot/dts/brcm/bcm7420.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -92,15 +92,15 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
- brcm,int-map-mask = <0x44>, <0x1f000000>;
+ brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
- interrupts = <18>, <19>;
- interrupt-names = "upg_main", "upg_bsc";
+ interrupts = <18>, <19>, <20>;
+ interrupt-names = "upg_main", "upg_bsc", "upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -287,5 +287,48 @@
interrupts = <62>;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@411d00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411d00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <78>;
+ };
+
+ qspi: spi@443000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@406400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x406400 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 2488d2f61f60..f56fb25f2e6b 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -450,5 +450,48 @@
mmc-hs200-1_8v;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@41ad00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x41ad00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <25>;
+ };
+
+ qspi: spi@41c000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@409200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x409200 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 19fa259b968b..f2cead2eae5c 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -465,5 +465,48 @@
mmc-hs200-1_8v;
status = "disabled";
};
+
+ spi_l2_intc: interrupt-controller@41bd00 {
+ compatible = "brcm,l2-intc";
+ reg = <0x41bd00 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <25>;
+ };
+
+ qspi: spi@41d200 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-qspi";
+ clocks = <&upg_clk>;
+ reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
+ reg-names = "cs_reg", "hif_mspi", "bspi";
+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+ interrupt-parent = <&spi_l2_intc>;
+ interrupt-names = "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread",
+ "mspi_done",
+ "mspi_halted";
+ status = "disabled";
+ };
+
+ mspi: spi@409200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,spi-bcm-qspi",
+ "brcm,spi-brcmstb-mspi";
+ clocks = <&upg_clk>;
+ reg = <0x409200 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&upg_aon_irq0_intc>;
+ interrupt-names = "mspi_done";
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
index 5c24eacd72dd..d72bc423ceaa 100644
--- a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
@@ -57,3 +57,7 @@
&ohci0 {
status = "disabled";
};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
index e67eaf30de3d..ea52d7b5772f 100644
--- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -109,3 +109,7 @@
&sdhci0 {
status = "okay";
};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
index ee4607fae47a..71357fdc19af 100644
--- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -69,3 +69,39 @@
&nand {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "m25p80";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-cpol;
+ spi-cpha;
+ use-bspi;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0.cfe@0 {
+ reg = <0x0 0x200000>;
+ };
+
+ flash0.mac@200000 {
+ reg = <0x200000 0x40000>;
+ };
+
+ flash0.nvram@240000 {
+ reg = <0x240000 0x10000>;
+ };
+ };
+ };
+};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
index bed821b03013..e2fed406c6ee 100644
--- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -72,3 +72,39 @@
&sdhci0 {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "m25p80";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-cpol;
+ spi-cpha;
+ use-bspi;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0.cfe@0 {
+ reg = <0x0 0x200000>;
+ };
+
+ flash0.mac@200000 {
+ reg = <0x200000 0x40000>;
+ };
+
+ flash0.nvram@240000 {
+ reg = <0x240000 0x10000>;
+ };
+ };
+ };
+};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
index 68fd823868e0..78bffdf11872 100644
--- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -73,3 +73,7 @@
&sdhci0 {
status = "okay";
};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts
index e66271af055e..d62b448a152d 100644
--- a/arch/mips/boot/dts/brcm/bcm97420c.dts
+++ b/arch/mips/boot/dts/brcm/bcm97420c.dts
@@ -79,3 +79,7 @@
&ohci1 {
status = "okay";
};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index f95ba1bf3e58..73aa006bd9ce 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -107,3 +107,39 @@
&sdhci1 {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "m25p80";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-cpol;
+ spi-cpha;
+ use-bspi;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0.cfe@0 {
+ reg = <0x0 0x200000>;
+ };
+
+ flash0.mac@200000 {
+ reg = <0x200000 0x40000>;
+ };
+
+ flash0.nvram@240000 {
+ reg = <0x240000 0x10000>;
+ };
+ };
+ };
+};
+
+&mspi {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index fb37b7111bf4..0a915f3feab6 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -115,3 +115,7 @@
&sdhci1 {
status = "okay";
};
+
+&mspi {
+ status = "okay";
+};
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH v2 3/3] ARM: dts: imx: Add ocotp node for imx6ul
From: Shawn Guo @ 2017-01-10 1:35 UTC (permalink / raw)
To: Bai Ping
Cc: robh-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, fabio.estevam-3arQi8VN3Tc,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1479344899-3141-3-git-send-email-ping.bai-3arQi8VN3Tc@public.gmane.org>
On Thu, Nov 17, 2016 at 09:08:19AM +0800, Bai Ping wrote:
> Add ocotp node for i.MX6UL SOC.
>
> Signed-off-by: Bai Ping <ping.bai-3arQi8VN3Tc@public.gmane.org>
Applied, thanks.
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^ permalink raw reply
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